1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/string_helpers.h> 29 30 #include <drm/display/drm_scdc_helper.h> 31 #include <drm/drm_privacy_screen_consumer.h> 32 33 #include "i915_drv.h" 34 #include "i915_reg.h" 35 #include "intel_audio.h" 36 #include "intel_audio_regs.h" 37 #include "intel_backlight.h" 38 #include "intel_combo_phy.h" 39 #include "intel_combo_phy_regs.h" 40 #include "intel_connector.h" 41 #include "intel_crtc.h" 42 #include "intel_cx0_phy.h" 43 #include "intel_cx0_phy_regs.h" 44 #include "intel_ddi.h" 45 #include "intel_ddi_buf_trans.h" 46 #include "intel_de.h" 47 #include "intel_display_power.h" 48 #include "intel_display_types.h" 49 #include "intel_dkl_phy.h" 50 #include "intel_dkl_phy_regs.h" 51 #include "intel_dp.h" 52 #include "intel_dp_aux.h" 53 #include "intel_dp_link_training.h" 54 #include "intel_dp_mst.h" 55 #include "intel_dpio_phy.h" 56 #include "intel_dsi.h" 57 #include "intel_fdi.h" 58 #include "intel_fifo_underrun.h" 59 #include "intel_gmbus.h" 60 #include "intel_hdcp.h" 61 #include "intel_hdmi.h" 62 #include "intel_hotplug.h" 63 #include "intel_hti.h" 64 #include "intel_lspcon.h" 65 #include "intel_mg_phy_regs.h" 66 #include "intel_modeset_lock.h" 67 #include "intel_pps.h" 68 #include "intel_psr.h" 69 #include "intel_quirks.h" 70 #include "intel_snps_phy.h" 71 #include "intel_tc.h" 72 #include "intel_vdsc.h" 73 #include "intel_vdsc_regs.h" 74 #include "skl_scaler.h" 75 #include "skl_universal_plane.h" 76 77 static const u8 index_to_dp_signal_levels[] = { 78 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 79 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 80 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 81 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 82 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 83 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 84 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 85 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 86 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 87 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 88 }; 89 90 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 91 const struct intel_ddi_buf_trans *trans) 92 { 93 int level; 94 95 level = intel_bios_hdmi_level_shift(encoder->devdata); 96 if (level < 0) 97 level = trans->hdmi_default_entry; 98 99 return level; 100 } 101 102 static bool has_buf_trans_select(struct drm_i915_private *i915) 103 { 104 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); 105 } 106 107 static bool has_iboost(struct drm_i915_private *i915) 108 { 109 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); 110 } 111 112 /* 113 * Starting with Haswell, DDI port buffers must be programmed with correct 114 * values in advance. This function programs the correct values for 115 * DP/eDP/FDI use cases. 116 */ 117 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 118 const struct intel_crtc_state *crtc_state) 119 { 120 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 121 u32 iboost_bit = 0; 122 int i, n_entries; 123 enum port port = encoder->port; 124 const struct intel_ddi_buf_trans *trans; 125 126 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 127 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 128 return; 129 130 /* If we're boosting the current, set bit 31 of trans1 */ 131 if (has_iboost(dev_priv) && 132 intel_bios_dp_boost_level(encoder->devdata)) 133 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 134 135 for (i = 0; i < n_entries; i++) { 136 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 137 trans->entries[i].hsw.trans1 | iboost_bit); 138 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 139 trans->entries[i].hsw.trans2); 140 } 141 } 142 143 /* 144 * Starting with Haswell, DDI port buffers must be programmed with correct 145 * values in advance. This function programs the correct values for 146 * HDMI/DVI use cases. 147 */ 148 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 149 const struct intel_crtc_state *crtc_state) 150 { 151 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 152 int level = intel_ddi_level(encoder, crtc_state, 0); 153 u32 iboost_bit = 0; 154 int n_entries; 155 enum port port = encoder->port; 156 const struct intel_ddi_buf_trans *trans; 157 158 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 159 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 160 return; 161 162 /* If we're boosting the current, set bit 31 of trans1 */ 163 if (has_iboost(dev_priv) && 164 intel_bios_hdmi_boost_level(encoder->devdata)) 165 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 166 167 /* Entry 9 is for HDMI: */ 168 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 169 trans->entries[level].hsw.trans1 | iboost_bit); 170 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 171 trans->entries[level].hsw.trans2); 172 } 173 174 static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port) 175 { 176 int ret; 177 178 /* FIXME: find out why Bspec's 100us timeout is too short */ 179 ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) & 180 XELPDP_PORT_BUF_PHY_IDLE), 10000); 181 if (ret) 182 drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n", 183 port_name(port)); 184 } 185 186 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 187 enum port port) 188 { 189 if (IS_BROXTON(dev_priv)) { 190 udelay(16); 191 return; 192 } 193 194 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 195 DDI_BUF_IS_IDLE), 8)) 196 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 197 port_name(port)); 198 } 199 200 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, 201 enum port port) 202 { 203 enum phy phy = intel_port_to_phy(dev_priv, port); 204 int timeout_us; 205 int ret; 206 207 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 208 if (DISPLAY_VER(dev_priv) < 10) { 209 usleep_range(518, 1000); 210 return; 211 } 212 213 if (DISPLAY_VER(dev_priv) >= 14) { 214 timeout_us = 10000; 215 } else if (IS_DG2(dev_priv)) { 216 timeout_us = 1200; 217 } else if (DISPLAY_VER(dev_priv) >= 12) { 218 if (intel_phy_is_tc(dev_priv, phy)) 219 timeout_us = 3000; 220 else 221 timeout_us = 1000; 222 } else { 223 timeout_us = 500; 224 } 225 226 if (DISPLAY_VER(dev_priv) >= 14) 227 ret = _wait_for(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_PORT_BUF_PHY_IDLE), 228 timeout_us, 10, 10); 229 else 230 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE), 231 timeout_us, 10, 10); 232 233 if (ret) 234 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 235 port_name(port)); 236 } 237 238 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 239 { 240 switch (pll->info->id) { 241 case DPLL_ID_WRPLL1: 242 return PORT_CLK_SEL_WRPLL1; 243 case DPLL_ID_WRPLL2: 244 return PORT_CLK_SEL_WRPLL2; 245 case DPLL_ID_SPLL: 246 return PORT_CLK_SEL_SPLL; 247 case DPLL_ID_LCPLL_810: 248 return PORT_CLK_SEL_LCPLL_810; 249 case DPLL_ID_LCPLL_1350: 250 return PORT_CLK_SEL_LCPLL_1350; 251 case DPLL_ID_LCPLL_2700: 252 return PORT_CLK_SEL_LCPLL_2700; 253 default: 254 MISSING_CASE(pll->info->id); 255 return PORT_CLK_SEL_NONE; 256 } 257 } 258 259 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 260 const struct intel_crtc_state *crtc_state) 261 { 262 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 263 int clock = crtc_state->port_clock; 264 const enum intel_dpll_id id = pll->info->id; 265 266 switch (id) { 267 default: 268 /* 269 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 270 * here, so do warn if this get passed in 271 */ 272 MISSING_CASE(id); 273 return DDI_CLK_SEL_NONE; 274 case DPLL_ID_ICL_TBTPLL: 275 switch (clock) { 276 case 162000: 277 return DDI_CLK_SEL_TBT_162; 278 case 270000: 279 return DDI_CLK_SEL_TBT_270; 280 case 540000: 281 return DDI_CLK_SEL_TBT_540; 282 case 810000: 283 return DDI_CLK_SEL_TBT_810; 284 default: 285 MISSING_CASE(clock); 286 return DDI_CLK_SEL_NONE; 287 } 288 case DPLL_ID_ICL_MGPLL1: 289 case DPLL_ID_ICL_MGPLL2: 290 case DPLL_ID_ICL_MGPLL3: 291 case DPLL_ID_ICL_MGPLL4: 292 case DPLL_ID_TGL_MGPLL5: 293 case DPLL_ID_TGL_MGPLL6: 294 return DDI_CLK_SEL_MG; 295 } 296 } 297 298 static u32 ddi_buf_phy_link_rate(int port_clock) 299 { 300 switch (port_clock) { 301 case 162000: 302 return DDI_BUF_PHY_LINK_RATE(0); 303 case 216000: 304 return DDI_BUF_PHY_LINK_RATE(4); 305 case 243000: 306 return DDI_BUF_PHY_LINK_RATE(5); 307 case 270000: 308 return DDI_BUF_PHY_LINK_RATE(1); 309 case 324000: 310 return DDI_BUF_PHY_LINK_RATE(6); 311 case 432000: 312 return DDI_BUF_PHY_LINK_RATE(7); 313 case 540000: 314 return DDI_BUF_PHY_LINK_RATE(2); 315 case 810000: 316 return DDI_BUF_PHY_LINK_RATE(3); 317 default: 318 MISSING_CASE(port_clock); 319 return DDI_BUF_PHY_LINK_RATE(0); 320 } 321 } 322 323 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 324 const struct intel_crtc_state *crtc_state) 325 { 326 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 327 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 328 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 329 enum phy phy = intel_port_to_phy(i915, encoder->port); 330 331 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 332 intel_dp->DP = dig_port->saved_port_bits | 333 DDI_PORT_WIDTH(crtc_state->lane_count) | 334 DDI_BUF_TRANS_SELECT(0); 335 336 if (DISPLAY_VER(i915) >= 14) { 337 if (intel_dp_is_uhbr(crtc_state)) 338 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 339 else 340 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 341 } 342 343 if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) { 344 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 345 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 346 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 347 } 348 } 349 350 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 351 enum port port) 352 { 353 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 354 355 switch (val) { 356 case DDI_CLK_SEL_NONE: 357 return 0; 358 case DDI_CLK_SEL_TBT_162: 359 return 162000; 360 case DDI_CLK_SEL_TBT_270: 361 return 270000; 362 case DDI_CLK_SEL_TBT_540: 363 return 540000; 364 case DDI_CLK_SEL_TBT_810: 365 return 810000; 366 default: 367 MISSING_CASE(val); 368 return 0; 369 } 370 } 371 372 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 373 { 374 /* CRT dotclock is determined via other means */ 375 if (pipe_config->has_pch_encoder) 376 return; 377 378 pipe_config->hw.adjusted_mode.crtc_clock = 379 intel_crtc_dotclock(pipe_config); 380 } 381 382 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 383 const struct drm_connector_state *conn_state) 384 { 385 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 386 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 387 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 388 u32 temp; 389 390 if (!intel_crtc_has_dp_encoder(crtc_state)) 391 return; 392 393 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 394 395 temp = DP_MSA_MISC_SYNC_CLOCK; 396 397 switch (crtc_state->pipe_bpp) { 398 case 18: 399 temp |= DP_MSA_MISC_6_BPC; 400 break; 401 case 24: 402 temp |= DP_MSA_MISC_8_BPC; 403 break; 404 case 30: 405 temp |= DP_MSA_MISC_10_BPC; 406 break; 407 case 36: 408 temp |= DP_MSA_MISC_12_BPC; 409 break; 410 default: 411 MISSING_CASE(crtc_state->pipe_bpp); 412 break; 413 } 414 415 /* nonsense combination */ 416 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 417 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 418 419 if (crtc_state->limited_color_range) 420 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 421 422 /* 423 * As per DP 1.2 spec section 2.3.4.3 while sending 424 * YCBCR 444 signals we should program MSA MISC1/0 fields with 425 * colorspace information. 426 */ 427 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 428 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 429 430 /* 431 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 432 * of Color Encoding Format and Content Color Gamut] while sending 433 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 434 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 435 */ 436 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 437 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 438 439 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 440 } 441 442 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 443 { 444 if (master_transcoder == TRANSCODER_EDP) 445 return 0; 446 else 447 return master_transcoder + 1; 448 } 449 450 static void 451 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, 452 const struct intel_crtc_state *crtc_state) 453 { 454 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 455 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 456 u32 val = 0; 457 458 if (intel_dp_is_uhbr(crtc_state)) 459 val = TRANS_DP2_128B132B_CHANNEL_CODING; 460 461 intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); 462 } 463 464 /* 465 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 466 * 467 * Only intended to be used by intel_ddi_enable_transcoder_func() and 468 * intel_ddi_config_transcoder_func(). 469 */ 470 static u32 471 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 472 const struct intel_crtc_state *crtc_state) 473 { 474 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 475 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 476 enum pipe pipe = crtc->pipe; 477 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 478 enum port port = encoder->port; 479 u32 temp; 480 481 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 482 temp = TRANS_DDI_FUNC_ENABLE; 483 if (DISPLAY_VER(dev_priv) >= 12) 484 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 485 else 486 temp |= TRANS_DDI_SELECT_PORT(port); 487 488 switch (crtc_state->pipe_bpp) { 489 default: 490 MISSING_CASE(crtc_state->pipe_bpp); 491 fallthrough; 492 case 18: 493 temp |= TRANS_DDI_BPC_6; 494 break; 495 case 24: 496 temp |= TRANS_DDI_BPC_8; 497 break; 498 case 30: 499 temp |= TRANS_DDI_BPC_10; 500 break; 501 case 36: 502 temp |= TRANS_DDI_BPC_12; 503 break; 504 } 505 506 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 507 temp |= TRANS_DDI_PVSYNC; 508 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 509 temp |= TRANS_DDI_PHSYNC; 510 511 if (cpu_transcoder == TRANSCODER_EDP) { 512 switch (pipe) { 513 default: 514 MISSING_CASE(pipe); 515 fallthrough; 516 case PIPE_A: 517 /* On Haswell, can only use the always-on power well for 518 * eDP when not using the panel fitter, and when not 519 * using motion blur mitigation (which we don't 520 * support). */ 521 if (crtc_state->pch_pfit.force_thru) 522 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 523 else 524 temp |= TRANS_DDI_EDP_INPUT_A_ON; 525 break; 526 case PIPE_B: 527 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 528 break; 529 case PIPE_C: 530 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 531 break; 532 } 533 } 534 535 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 536 if (crtc_state->has_hdmi_sink) 537 temp |= TRANS_DDI_MODE_SELECT_HDMI; 538 else 539 temp |= TRANS_DDI_MODE_SELECT_DVI; 540 541 if (crtc_state->hdmi_scrambling) 542 temp |= TRANS_DDI_HDMI_SCRAMBLING; 543 if (crtc_state->hdmi_high_tmds_clock_ratio) 544 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 545 if (DISPLAY_VER(dev_priv) >= 14) 546 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 547 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 548 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 549 temp |= (crtc_state->fdi_lanes - 1) << 1; 550 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 551 if (intel_dp_is_uhbr(crtc_state)) 552 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 553 else 554 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 555 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 556 557 if (DISPLAY_VER(dev_priv) >= 12) { 558 enum transcoder master; 559 560 master = crtc_state->mst_master_transcoder; 561 drm_WARN_ON(&dev_priv->drm, 562 master == INVALID_TRANSCODER); 563 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 564 } 565 } else { 566 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 567 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 568 } 569 570 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 571 crtc_state->master_transcoder != INVALID_TRANSCODER) { 572 u8 master_select = 573 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 574 575 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 576 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 577 } 578 579 return temp; 580 } 581 582 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 583 const struct intel_crtc_state *crtc_state) 584 { 585 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 586 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 587 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 588 589 if (DISPLAY_VER(dev_priv) >= 11) { 590 enum transcoder master_transcoder = crtc_state->master_transcoder; 591 u32 ctl2 = 0; 592 593 if (master_transcoder != INVALID_TRANSCODER) { 594 u8 master_select = 595 bdw_trans_port_sync_master_select(master_transcoder); 596 597 ctl2 |= PORT_SYNC_MODE_ENABLE | 598 PORT_SYNC_MODE_MASTER_SELECT(master_select); 599 } 600 601 intel_de_write(dev_priv, 602 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 603 } 604 605 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 606 intel_ddi_transcoder_func_reg_val_get(encoder, 607 crtc_state)); 608 } 609 610 /* 611 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 612 * bit. 613 */ 614 static void 615 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 616 const struct intel_crtc_state *crtc_state) 617 { 618 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 619 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 620 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 621 u32 ctl; 622 623 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 624 ctl &= ~TRANS_DDI_FUNC_ENABLE; 625 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 626 } 627 628 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 629 { 630 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 631 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 632 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 633 u32 ctl; 634 635 if (DISPLAY_VER(dev_priv) >= 11) 636 intel_de_write(dev_priv, 637 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 638 639 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 640 641 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 642 643 ctl &= ~TRANS_DDI_FUNC_ENABLE; 644 645 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 646 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 647 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 648 649 if (DISPLAY_VER(dev_priv) >= 12) { 650 if (!intel_dp_mst_is_master_trans(crtc_state)) { 651 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 652 TRANS_DDI_MODE_SELECT_MASK); 653 } 654 } else { 655 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 656 } 657 658 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 659 660 if (intel_has_quirk(dev_priv, QUIRK_INCREASE_DDI_DISABLED_TIME) && 661 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 662 drm_dbg_kms(&dev_priv->drm, 663 "Quirk Increase DDI disabled time\n"); 664 /* Quirk time at 100ms for reliable operation */ 665 msleep(100); 666 } 667 } 668 669 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 670 enum transcoder cpu_transcoder, 671 bool enable, u32 hdcp_mask) 672 { 673 struct drm_device *dev = intel_encoder->base.dev; 674 struct drm_i915_private *dev_priv = to_i915(dev); 675 intel_wakeref_t wakeref; 676 int ret = 0; 677 678 wakeref = intel_display_power_get_if_enabled(dev_priv, 679 intel_encoder->power_domain); 680 if (drm_WARN_ON(dev, !wakeref)) 681 return -ENXIO; 682 683 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 684 hdcp_mask, enable ? hdcp_mask : 0); 685 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 686 return ret; 687 } 688 689 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 690 { 691 struct drm_device *dev = intel_connector->base.dev; 692 struct drm_i915_private *dev_priv = to_i915(dev); 693 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 694 int type = intel_connector->base.connector_type; 695 enum port port = encoder->port; 696 enum transcoder cpu_transcoder; 697 intel_wakeref_t wakeref; 698 enum pipe pipe = 0; 699 u32 tmp; 700 bool ret; 701 702 wakeref = intel_display_power_get_if_enabled(dev_priv, 703 encoder->power_domain); 704 if (!wakeref) 705 return false; 706 707 if (!encoder->get_hw_state(encoder, &pipe)) { 708 ret = false; 709 goto out; 710 } 711 712 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 713 cpu_transcoder = TRANSCODER_EDP; 714 else 715 cpu_transcoder = (enum transcoder) pipe; 716 717 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 718 719 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 720 case TRANS_DDI_MODE_SELECT_HDMI: 721 case TRANS_DDI_MODE_SELECT_DVI: 722 ret = type == DRM_MODE_CONNECTOR_HDMIA; 723 break; 724 725 case TRANS_DDI_MODE_SELECT_DP_SST: 726 ret = type == DRM_MODE_CONNECTOR_eDP || 727 type == DRM_MODE_CONNECTOR_DisplayPort; 728 break; 729 730 case TRANS_DDI_MODE_SELECT_DP_MST: 731 /* if the transcoder is in MST state then 732 * connector isn't connected */ 733 ret = false; 734 break; 735 736 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 737 if (HAS_DP20(dev_priv)) 738 /* 128b/132b */ 739 ret = false; 740 else 741 /* FDI */ 742 ret = type == DRM_MODE_CONNECTOR_VGA; 743 break; 744 745 default: 746 ret = false; 747 break; 748 } 749 750 out: 751 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 752 753 return ret; 754 } 755 756 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 757 u8 *pipe_mask, bool *is_dp_mst) 758 { 759 struct drm_device *dev = encoder->base.dev; 760 struct drm_i915_private *dev_priv = to_i915(dev); 761 enum port port = encoder->port; 762 intel_wakeref_t wakeref; 763 enum pipe p; 764 u32 tmp; 765 u8 mst_pipe_mask; 766 767 *pipe_mask = 0; 768 *is_dp_mst = false; 769 770 wakeref = intel_display_power_get_if_enabled(dev_priv, 771 encoder->power_domain); 772 if (!wakeref) 773 return; 774 775 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 776 if (!(tmp & DDI_BUF_CTL_ENABLE)) 777 goto out; 778 779 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 780 tmp = intel_de_read(dev_priv, 781 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 782 783 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 784 default: 785 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 786 fallthrough; 787 case TRANS_DDI_EDP_INPUT_A_ON: 788 case TRANS_DDI_EDP_INPUT_A_ONOFF: 789 *pipe_mask = BIT(PIPE_A); 790 break; 791 case TRANS_DDI_EDP_INPUT_B_ONOFF: 792 *pipe_mask = BIT(PIPE_B); 793 break; 794 case TRANS_DDI_EDP_INPUT_C_ONOFF: 795 *pipe_mask = BIT(PIPE_C); 796 break; 797 } 798 799 goto out; 800 } 801 802 mst_pipe_mask = 0; 803 for_each_pipe(dev_priv, p) { 804 enum transcoder cpu_transcoder = (enum transcoder)p; 805 unsigned int port_mask, ddi_select; 806 intel_wakeref_t trans_wakeref; 807 808 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 809 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 810 if (!trans_wakeref) 811 continue; 812 813 if (DISPLAY_VER(dev_priv) >= 12) { 814 port_mask = TGL_TRANS_DDI_PORT_MASK; 815 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 816 } else { 817 port_mask = TRANS_DDI_PORT_MASK; 818 ddi_select = TRANS_DDI_SELECT_PORT(port); 819 } 820 821 tmp = intel_de_read(dev_priv, 822 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 823 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 824 trans_wakeref); 825 826 if ((tmp & port_mask) != ddi_select) 827 continue; 828 829 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST || 830 (HAS_DP20(dev_priv) && 831 (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) 832 mst_pipe_mask |= BIT(p); 833 834 *pipe_mask |= BIT(p); 835 } 836 837 if (!*pipe_mask) 838 drm_dbg_kms(&dev_priv->drm, 839 "No pipe for [ENCODER:%d:%s] found\n", 840 encoder->base.base.id, encoder->base.name); 841 842 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 843 drm_dbg_kms(&dev_priv->drm, 844 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 845 encoder->base.base.id, encoder->base.name, 846 *pipe_mask); 847 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 848 } 849 850 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 851 drm_dbg_kms(&dev_priv->drm, 852 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 853 encoder->base.base.id, encoder->base.name, 854 *pipe_mask, mst_pipe_mask); 855 else 856 *is_dp_mst = mst_pipe_mask; 857 858 out: 859 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 860 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 861 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 862 BXT_PHY_LANE_POWERDOWN_ACK | 863 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 864 drm_err(&dev_priv->drm, 865 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 866 encoder->base.base.id, encoder->base.name, tmp); 867 } 868 869 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 870 } 871 872 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 873 enum pipe *pipe) 874 { 875 u8 pipe_mask; 876 bool is_mst; 877 878 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 879 880 if (is_mst || !pipe_mask) 881 return false; 882 883 *pipe = ffs(pipe_mask) - 1; 884 885 return true; 886 } 887 888 static enum intel_display_power_domain 889 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 890 const struct intel_crtc_state *crtc_state) 891 { 892 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 893 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 894 895 /* 896 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 897 * DC states enabled at the same time, while for driver initiated AUX 898 * transfers we need the same AUX IOs to be powered but with DC states 899 * disabled. Accordingly use the AUX_IO_<port> power domain here which 900 * leaves DC states enabled. 901 * 902 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 903 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 904 * well, so we can acquire a wider AUX_<port> power domain reference 905 * instead of a specific AUX_IO_<port> reference without powering up any 906 * extra wells. 907 */ 908 if (intel_encoder_can_psr(&dig_port->base)) 909 return intel_display_power_aux_io_domain(i915, dig_port->aux_ch); 910 else if (DISPLAY_VER(i915) < 14 && 911 (intel_crtc_has_dp_encoder(crtc_state) || 912 intel_phy_is_tc(i915, phy))) 913 return intel_aux_power_domain(dig_port); 914 else 915 return POWER_DOMAIN_INVALID; 916 } 917 918 static void 919 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 920 const struct intel_crtc_state *crtc_state) 921 { 922 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 923 enum intel_display_power_domain domain = 924 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 925 926 drm_WARN_ON(&i915->drm, dig_port->aux_wakeref); 927 928 if (domain == POWER_DOMAIN_INVALID) 929 return; 930 931 dig_port->aux_wakeref = intel_display_power_get(i915, domain); 932 } 933 934 static void 935 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 936 const struct intel_crtc_state *crtc_state) 937 { 938 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 939 enum intel_display_power_domain domain = 940 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 941 intel_wakeref_t wf; 942 943 wf = fetch_and_zero(&dig_port->aux_wakeref); 944 if (!wf) 945 return; 946 947 intel_display_power_put(i915, domain, wf); 948 } 949 950 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 951 struct intel_crtc_state *crtc_state) 952 { 953 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 954 struct intel_digital_port *dig_port; 955 956 /* 957 * TODO: Add support for MST encoders. Atm, the following should never 958 * happen since fake-MST encoders don't set their get_power_domains() 959 * hook. 960 */ 961 if (drm_WARN_ON(&dev_priv->drm, 962 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 963 return; 964 965 dig_port = enc_to_dig_port(encoder); 966 967 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 968 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 969 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 970 dig_port->ddi_io_power_domain); 971 } 972 973 main_link_aux_power_domain_get(dig_port, crtc_state); 974 } 975 976 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 977 const struct intel_crtc_state *crtc_state) 978 { 979 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 980 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 981 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 982 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 983 u32 val; 984 985 if (cpu_transcoder == TRANSCODER_EDP) 986 return; 987 988 if (DISPLAY_VER(dev_priv) >= 13) 989 val = TGL_TRANS_CLK_SEL_PORT(phy); 990 else if (DISPLAY_VER(dev_priv) >= 12) 991 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 992 else 993 val = TRANS_CLK_SEL_PORT(encoder->port); 994 995 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 996 } 997 998 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 999 { 1000 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1001 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1002 u32 val; 1003 1004 if (cpu_transcoder == TRANSCODER_EDP) 1005 return; 1006 1007 if (DISPLAY_VER(dev_priv) >= 12) 1008 val = TGL_TRANS_CLK_SEL_DISABLED; 1009 else 1010 val = TRANS_CLK_SEL_DISABLED; 1011 1012 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 1013 } 1014 1015 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 1016 enum port port, u8 iboost) 1017 { 1018 u32 tmp; 1019 1020 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 1021 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1022 if (iboost) 1023 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1024 else 1025 tmp |= BALANCE_LEG_DISABLE(port); 1026 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 1027 } 1028 1029 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1030 const struct intel_crtc_state *crtc_state, 1031 int level) 1032 { 1033 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1034 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1035 u8 iboost; 1036 1037 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1038 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1039 else 1040 iboost = intel_bios_dp_boost_level(encoder->devdata); 1041 1042 if (iboost == 0) { 1043 const struct intel_ddi_buf_trans *trans; 1044 int n_entries; 1045 1046 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1047 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1048 return; 1049 1050 iboost = trans->entries[level].hsw.i_boost; 1051 } 1052 1053 /* Make sure that the requested I_boost is valid */ 1054 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1055 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 1056 return; 1057 } 1058 1059 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 1060 1061 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1062 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 1063 } 1064 1065 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1066 const struct intel_crtc_state *crtc_state) 1067 { 1068 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1069 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1070 int n_entries; 1071 1072 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1073 1074 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1075 n_entries = 1; 1076 if (drm_WARN_ON(&dev_priv->drm, 1077 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1078 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1079 1080 return index_to_dp_signal_levels[n_entries - 1] & 1081 DP_TRAIN_VOLTAGE_SWING_MASK; 1082 } 1083 1084 /* 1085 * We assume that the full set of pre-emphasis values can be 1086 * used on all DDI platforms. Should that change we need to 1087 * rethink this code. 1088 */ 1089 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1090 { 1091 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1092 } 1093 1094 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1095 int lane) 1096 { 1097 if (crtc_state->port_clock > 600000) 1098 return 0; 1099 1100 if (crtc_state->lane_count == 4) 1101 return lane >= 1 ? LOADGEN_SELECT : 0; 1102 else 1103 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1104 } 1105 1106 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1107 const struct intel_crtc_state *crtc_state) 1108 { 1109 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1110 const struct intel_ddi_buf_trans *trans; 1111 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1112 int n_entries, ln; 1113 u32 val; 1114 1115 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1116 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1117 return; 1118 1119 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1120 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1121 1122 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1123 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1124 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1125 intel_dp->hobl_active ? val : 0); 1126 } 1127 1128 /* Set PORT_TX_DW5 */ 1129 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1130 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1131 TAP2_DISABLE | TAP3_DISABLE); 1132 val |= SCALING_MODE_SEL(0x2); 1133 val |= RTERM_SELECT(0x6); 1134 val |= TAP3_DISABLE; 1135 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1136 1137 /* Program PORT_TX_DW2 */ 1138 for (ln = 0; ln < 4; ln++) { 1139 int level = intel_ddi_level(encoder, crtc_state, ln); 1140 1141 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), 1142 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1143 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1144 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1145 RCOMP_SCALAR(0x98)); 1146 } 1147 1148 /* Program PORT_TX_DW4 */ 1149 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1150 for (ln = 0; ln < 4; ln++) { 1151 int level = intel_ddi_level(encoder, crtc_state, ln); 1152 1153 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1154 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1155 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1156 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1157 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1158 } 1159 1160 /* Program PORT_TX_DW7 */ 1161 for (ln = 0; ln < 4; ln++) { 1162 int level = intel_ddi_level(encoder, crtc_state, ln); 1163 1164 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), 1165 N_SCALAR_MASK, 1166 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1167 } 1168 } 1169 1170 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1171 const struct intel_crtc_state *crtc_state) 1172 { 1173 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1174 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1175 u32 val; 1176 int ln; 1177 1178 /* 1179 * 1. If port type is eDP or DP, 1180 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1181 * else clear to 0b. 1182 */ 1183 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 1184 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1185 val &= ~COMMON_KEEPER_EN; 1186 else 1187 val |= COMMON_KEEPER_EN; 1188 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1189 1190 /* 2. Program loadgen select */ 1191 /* 1192 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1193 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1194 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1195 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1196 */ 1197 for (ln = 0; ln < 4; ln++) { 1198 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1199 LOADGEN_SELECT, 1200 icl_combo_phy_loadgen_select(crtc_state, ln)); 1201 } 1202 1203 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1204 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 1205 0, SUS_CLOCK_CONFIG); 1206 1207 /* 4. Clear training enable to change swing values */ 1208 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1209 val &= ~TX_TRAINING_EN; 1210 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1211 1212 /* 5. Program swing and de-emphasis */ 1213 icl_ddi_combo_vswing_program(encoder, crtc_state); 1214 1215 /* 6. Set training enable to trigger update */ 1216 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1217 val |= TX_TRAINING_EN; 1218 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1219 } 1220 1221 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1222 const struct intel_crtc_state *crtc_state) 1223 { 1224 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1225 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1226 const struct intel_ddi_buf_trans *trans; 1227 int n_entries, ln; 1228 1229 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1230 return; 1231 1232 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1233 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1234 return; 1235 1236 for (ln = 0; ln < 2; ln++) { 1237 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), 1238 CRI_USE_FS32, 0); 1239 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), 1240 CRI_USE_FS32, 0); 1241 } 1242 1243 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1244 for (ln = 0; ln < 2; ln++) { 1245 int level; 1246 1247 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1248 1249 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), 1250 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1251 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1252 1253 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1254 1255 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), 1256 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1257 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1258 } 1259 1260 /* Program MG_TX_DRVCTRL with values from vswing table */ 1261 for (ln = 0; ln < 2; ln++) { 1262 int level; 1263 1264 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1265 1266 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), 1267 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1268 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1269 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1270 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1271 CRI_TXDEEMPH_OVERRIDE_EN); 1272 1273 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1274 1275 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), 1276 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1277 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1278 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1279 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1280 CRI_TXDEEMPH_OVERRIDE_EN); 1281 1282 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1283 } 1284 1285 /* 1286 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1287 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1288 * values from table for which TX1 and TX2 enabled. 1289 */ 1290 for (ln = 0; ln < 2; ln++) { 1291 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), 1292 CFG_LOW_RATE_LKREN_EN, 1293 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1294 } 1295 1296 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1297 for (ln = 0; ln < 2; ln++) { 1298 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), 1299 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1300 CFG_AMI_CK_DIV_OVERRIDE_EN, 1301 crtc_state->port_clock > 500000 ? 1302 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1303 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1304 1305 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), 1306 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1307 CFG_AMI_CK_DIV_OVERRIDE_EN, 1308 crtc_state->port_clock > 500000 ? 1309 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1310 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1311 } 1312 1313 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1314 for (ln = 0; ln < 2; ln++) { 1315 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1316 0, CRI_CALCINIT); 1317 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1318 0, CRI_CALCINIT); 1319 } 1320 } 1321 1322 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1323 const struct intel_crtc_state *crtc_state) 1324 { 1325 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1326 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1327 const struct intel_ddi_buf_trans *trans; 1328 int n_entries, ln; 1329 1330 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1331 return; 1332 1333 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1334 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1335 return; 1336 1337 for (ln = 0; ln < 2; ln++) { 1338 int level; 1339 1340 intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1341 1342 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1343 1344 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln), 1345 DKL_TX_PRESHOOT_COEFF_MASK | 1346 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1347 DKL_TX_VSWING_CONTROL_MASK, 1348 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1349 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1350 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1351 1352 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1353 1354 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln), 1355 DKL_TX_PRESHOOT_COEFF_MASK | 1356 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1357 DKL_TX_VSWING_CONTROL_MASK, 1358 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1359 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1360 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1361 1362 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1363 DKL_TX_DP20BITMODE, 0); 1364 1365 if (IS_ALDERLAKE_P(dev_priv)) { 1366 u32 val; 1367 1368 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1369 if (ln == 0) { 1370 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1371 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1372 } else { 1373 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1374 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1375 } 1376 } else { 1377 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1378 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1379 } 1380 1381 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1382 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1383 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1384 val); 1385 } 1386 } 1387 } 1388 1389 static int translate_signal_level(struct intel_dp *intel_dp, 1390 u8 signal_levels) 1391 { 1392 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1393 int i; 1394 1395 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1396 if (index_to_dp_signal_levels[i] == signal_levels) 1397 return i; 1398 } 1399 1400 drm_WARN(&i915->drm, 1, 1401 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1402 signal_levels); 1403 1404 return 0; 1405 } 1406 1407 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1408 const struct intel_crtc_state *crtc_state, 1409 int lane) 1410 { 1411 u8 train_set = intel_dp->train_set[lane]; 1412 1413 if (intel_dp_is_uhbr(crtc_state)) { 1414 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1415 } else { 1416 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1417 DP_TRAIN_PRE_EMPHASIS_MASK); 1418 1419 return translate_signal_level(intel_dp, signal_levels); 1420 } 1421 } 1422 1423 int intel_ddi_level(struct intel_encoder *encoder, 1424 const struct intel_crtc_state *crtc_state, 1425 int lane) 1426 { 1427 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1428 const struct intel_ddi_buf_trans *trans; 1429 int level, n_entries; 1430 1431 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1432 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) 1433 return 0; 1434 1435 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1436 level = intel_ddi_hdmi_level(encoder, trans); 1437 else 1438 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1439 lane); 1440 1441 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) 1442 level = n_entries - 1; 1443 1444 return level; 1445 } 1446 1447 static void 1448 hsw_set_signal_levels(struct intel_encoder *encoder, 1449 const struct intel_crtc_state *crtc_state) 1450 { 1451 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1452 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1453 int level = intel_ddi_level(encoder, crtc_state, 0); 1454 enum port port = encoder->port; 1455 u32 signal_levels; 1456 1457 if (has_iboost(dev_priv)) 1458 skl_ddi_set_iboost(encoder, crtc_state, level); 1459 1460 /* HDMI ignores the rest */ 1461 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1462 return; 1463 1464 signal_levels = DDI_BUF_TRANS_SELECT(level); 1465 1466 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1467 signal_levels); 1468 1469 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1470 intel_dp->DP |= signal_levels; 1471 1472 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1473 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1474 } 1475 1476 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1477 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1478 { 1479 mutex_lock(&i915->display.dpll.lock); 1480 1481 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1482 1483 /* 1484 * "This step and the step before must be 1485 * done with separate register writes." 1486 */ 1487 intel_de_rmw(i915, reg, clk_off, 0); 1488 1489 mutex_unlock(&i915->display.dpll.lock); 1490 } 1491 1492 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1493 u32 clk_off) 1494 { 1495 mutex_lock(&i915->display.dpll.lock); 1496 1497 intel_de_rmw(i915, reg, 0, clk_off); 1498 1499 mutex_unlock(&i915->display.dpll.lock); 1500 } 1501 1502 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1503 u32 clk_off) 1504 { 1505 return !(intel_de_read(i915, reg) & clk_off); 1506 } 1507 1508 static struct intel_shared_dpll * 1509 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1510 u32 clk_sel_mask, u32 clk_sel_shift) 1511 { 1512 enum intel_dpll_id id; 1513 1514 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1515 1516 return intel_get_shared_dpll_by_id(i915, id); 1517 } 1518 1519 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1520 const struct intel_crtc_state *crtc_state) 1521 { 1522 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1523 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1524 enum phy phy = intel_port_to_phy(i915, encoder->port); 1525 1526 if (drm_WARN_ON(&i915->drm, !pll)) 1527 return; 1528 1529 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1530 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1531 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1532 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1533 } 1534 1535 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1536 { 1537 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1538 enum phy phy = intel_port_to_phy(i915, encoder->port); 1539 1540 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1541 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1542 } 1543 1544 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1545 { 1546 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1547 enum phy phy = intel_port_to_phy(i915, encoder->port); 1548 1549 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1550 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1551 } 1552 1553 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1554 { 1555 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1556 enum phy phy = intel_port_to_phy(i915, encoder->port); 1557 1558 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1559 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1560 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1561 } 1562 1563 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1564 const struct intel_crtc_state *crtc_state) 1565 { 1566 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1567 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1568 enum phy phy = intel_port_to_phy(i915, encoder->port); 1569 1570 if (drm_WARN_ON(&i915->drm, !pll)) 1571 return; 1572 1573 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1574 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1575 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1576 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1577 } 1578 1579 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1580 { 1581 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1582 enum phy phy = intel_port_to_phy(i915, encoder->port); 1583 1584 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1585 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1586 } 1587 1588 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1589 { 1590 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1591 enum phy phy = intel_port_to_phy(i915, encoder->port); 1592 1593 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1594 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1595 } 1596 1597 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1598 { 1599 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1600 enum phy phy = intel_port_to_phy(i915, encoder->port); 1601 1602 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1603 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1604 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1605 } 1606 1607 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1608 const struct intel_crtc_state *crtc_state) 1609 { 1610 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1611 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1612 enum phy phy = intel_port_to_phy(i915, encoder->port); 1613 1614 if (drm_WARN_ON(&i915->drm, !pll)) 1615 return; 1616 1617 /* 1618 * If we fail this, something went very wrong: first 2 PLLs should be 1619 * used by first 2 phys and last 2 PLLs by last phys 1620 */ 1621 if (drm_WARN_ON(&i915->drm, 1622 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1623 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1624 return; 1625 1626 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1627 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1628 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1629 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1630 } 1631 1632 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1633 { 1634 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1635 enum phy phy = intel_port_to_phy(i915, encoder->port); 1636 1637 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1638 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1639 } 1640 1641 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1642 { 1643 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1644 enum phy phy = intel_port_to_phy(i915, encoder->port); 1645 1646 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1647 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1648 } 1649 1650 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1651 { 1652 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1653 enum phy phy = intel_port_to_phy(i915, encoder->port); 1654 enum intel_dpll_id id; 1655 u32 val; 1656 1657 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1658 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1659 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1660 id = val; 1661 1662 /* 1663 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1664 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1665 * bit for phy C and D. 1666 */ 1667 if (phy >= PHY_C) 1668 id += DPLL_ID_DG1_DPLL2; 1669 1670 return intel_get_shared_dpll_by_id(i915, id); 1671 } 1672 1673 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1674 const struct intel_crtc_state *crtc_state) 1675 { 1676 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1677 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1678 enum phy phy = intel_port_to_phy(i915, encoder->port); 1679 1680 if (drm_WARN_ON(&i915->drm, !pll)) 1681 return; 1682 1683 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1684 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1685 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1686 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1687 } 1688 1689 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1690 { 1691 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1692 enum phy phy = intel_port_to_phy(i915, encoder->port); 1693 1694 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1695 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1696 } 1697 1698 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1699 { 1700 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1701 enum phy phy = intel_port_to_phy(i915, encoder->port); 1702 1703 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1704 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1705 } 1706 1707 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1708 { 1709 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1710 enum phy phy = intel_port_to_phy(i915, encoder->port); 1711 1712 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1713 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1714 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1715 } 1716 1717 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1718 const struct intel_crtc_state *crtc_state) 1719 { 1720 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1721 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1722 enum port port = encoder->port; 1723 1724 if (drm_WARN_ON(&i915->drm, !pll)) 1725 return; 1726 1727 /* 1728 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1729 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1730 */ 1731 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1732 1733 icl_ddi_combo_enable_clock(encoder, crtc_state); 1734 } 1735 1736 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1737 { 1738 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1739 enum port port = encoder->port; 1740 1741 icl_ddi_combo_disable_clock(encoder); 1742 1743 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1744 } 1745 1746 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1747 { 1748 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1749 enum port port = encoder->port; 1750 u32 tmp; 1751 1752 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1753 1754 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1755 return false; 1756 1757 return icl_ddi_combo_is_clock_enabled(encoder); 1758 } 1759 1760 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1761 const struct intel_crtc_state *crtc_state) 1762 { 1763 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1764 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1765 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1766 enum port port = encoder->port; 1767 1768 if (drm_WARN_ON(&i915->drm, !pll)) 1769 return; 1770 1771 intel_de_write(i915, DDI_CLK_SEL(port), 1772 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1773 1774 mutex_lock(&i915->display.dpll.lock); 1775 1776 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1777 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1778 1779 mutex_unlock(&i915->display.dpll.lock); 1780 } 1781 1782 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1783 { 1784 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1785 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1786 enum port port = encoder->port; 1787 1788 mutex_lock(&i915->display.dpll.lock); 1789 1790 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1791 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1792 1793 mutex_unlock(&i915->display.dpll.lock); 1794 1795 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1796 } 1797 1798 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1799 { 1800 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1801 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1802 enum port port = encoder->port; 1803 u32 tmp; 1804 1805 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1806 1807 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1808 return false; 1809 1810 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1811 1812 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1813 } 1814 1815 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1816 { 1817 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1818 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1819 enum port port = encoder->port; 1820 enum intel_dpll_id id; 1821 u32 tmp; 1822 1823 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1824 1825 switch (tmp & DDI_CLK_SEL_MASK) { 1826 case DDI_CLK_SEL_TBT_162: 1827 case DDI_CLK_SEL_TBT_270: 1828 case DDI_CLK_SEL_TBT_540: 1829 case DDI_CLK_SEL_TBT_810: 1830 id = DPLL_ID_ICL_TBTPLL; 1831 break; 1832 case DDI_CLK_SEL_MG: 1833 id = icl_tc_port_to_pll_id(tc_port); 1834 break; 1835 default: 1836 MISSING_CASE(tmp); 1837 fallthrough; 1838 case DDI_CLK_SEL_NONE: 1839 return NULL; 1840 } 1841 1842 return intel_get_shared_dpll_by_id(i915, id); 1843 } 1844 1845 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1846 { 1847 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1848 enum intel_dpll_id id; 1849 1850 switch (encoder->port) { 1851 case PORT_A: 1852 id = DPLL_ID_SKL_DPLL0; 1853 break; 1854 case PORT_B: 1855 id = DPLL_ID_SKL_DPLL1; 1856 break; 1857 case PORT_C: 1858 id = DPLL_ID_SKL_DPLL2; 1859 break; 1860 default: 1861 MISSING_CASE(encoder->port); 1862 return NULL; 1863 } 1864 1865 return intel_get_shared_dpll_by_id(i915, id); 1866 } 1867 1868 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1869 const struct intel_crtc_state *crtc_state) 1870 { 1871 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1872 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1873 enum port port = encoder->port; 1874 1875 if (drm_WARN_ON(&i915->drm, !pll)) 1876 return; 1877 1878 mutex_lock(&i915->display.dpll.lock); 1879 1880 intel_de_rmw(i915, DPLL_CTRL2, 1881 DPLL_CTRL2_DDI_CLK_OFF(port) | 1882 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1883 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1884 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1885 1886 mutex_unlock(&i915->display.dpll.lock); 1887 } 1888 1889 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1890 { 1891 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1892 enum port port = encoder->port; 1893 1894 mutex_lock(&i915->display.dpll.lock); 1895 1896 intel_de_rmw(i915, DPLL_CTRL2, 1897 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1898 1899 mutex_unlock(&i915->display.dpll.lock); 1900 } 1901 1902 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1903 { 1904 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1905 enum port port = encoder->port; 1906 1907 /* 1908 * FIXME Not sure if the override affects both 1909 * the PLL selection and the CLK_OFF bit. 1910 */ 1911 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1912 } 1913 1914 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1915 { 1916 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1917 enum port port = encoder->port; 1918 enum intel_dpll_id id; 1919 u32 tmp; 1920 1921 tmp = intel_de_read(i915, DPLL_CTRL2); 1922 1923 /* 1924 * FIXME Not sure if the override affects both 1925 * the PLL selection and the CLK_OFF bit. 1926 */ 1927 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1928 return NULL; 1929 1930 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1931 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1932 1933 return intel_get_shared_dpll_by_id(i915, id); 1934 } 1935 1936 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1937 const struct intel_crtc_state *crtc_state) 1938 { 1939 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1940 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1941 enum port port = encoder->port; 1942 1943 if (drm_WARN_ON(&i915->drm, !pll)) 1944 return; 1945 1946 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 1947 } 1948 1949 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 1950 { 1951 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1952 enum port port = encoder->port; 1953 1954 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1955 } 1956 1957 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 1958 { 1959 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1960 enum port port = encoder->port; 1961 1962 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 1963 } 1964 1965 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 1966 { 1967 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1968 enum port port = encoder->port; 1969 enum intel_dpll_id id; 1970 u32 tmp; 1971 1972 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 1973 1974 switch (tmp & PORT_CLK_SEL_MASK) { 1975 case PORT_CLK_SEL_WRPLL1: 1976 id = DPLL_ID_WRPLL1; 1977 break; 1978 case PORT_CLK_SEL_WRPLL2: 1979 id = DPLL_ID_WRPLL2; 1980 break; 1981 case PORT_CLK_SEL_SPLL: 1982 id = DPLL_ID_SPLL; 1983 break; 1984 case PORT_CLK_SEL_LCPLL_810: 1985 id = DPLL_ID_LCPLL_810; 1986 break; 1987 case PORT_CLK_SEL_LCPLL_1350: 1988 id = DPLL_ID_LCPLL_1350; 1989 break; 1990 case PORT_CLK_SEL_LCPLL_2700: 1991 id = DPLL_ID_LCPLL_2700; 1992 break; 1993 default: 1994 MISSING_CASE(tmp); 1995 fallthrough; 1996 case PORT_CLK_SEL_NONE: 1997 return NULL; 1998 } 1999 2000 return intel_get_shared_dpll_by_id(i915, id); 2001 } 2002 2003 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2004 const struct intel_crtc_state *crtc_state) 2005 { 2006 if (encoder->enable_clock) 2007 encoder->enable_clock(encoder, crtc_state); 2008 } 2009 2010 void intel_ddi_disable_clock(struct intel_encoder *encoder) 2011 { 2012 if (encoder->disable_clock) 2013 encoder->disable_clock(encoder); 2014 } 2015 2016 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2017 { 2018 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2019 u32 port_mask; 2020 bool ddi_clk_needed; 2021 2022 /* 2023 * In case of DP MST, we sanitize the primary encoder only, not the 2024 * virtual ones. 2025 */ 2026 if (encoder->type == INTEL_OUTPUT_DP_MST) 2027 return; 2028 2029 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2030 u8 pipe_mask; 2031 bool is_mst; 2032 2033 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2034 /* 2035 * In the unlikely case that BIOS enables DP in MST mode, just 2036 * warn since our MST HW readout is incomplete. 2037 */ 2038 if (drm_WARN_ON(&i915->drm, is_mst)) 2039 return; 2040 } 2041 2042 port_mask = BIT(encoder->port); 2043 ddi_clk_needed = encoder->base.crtc; 2044 2045 if (encoder->type == INTEL_OUTPUT_DSI) { 2046 struct intel_encoder *other_encoder; 2047 2048 port_mask = intel_dsi_encoder_ports(encoder); 2049 /* 2050 * Sanity check that we haven't incorrectly registered another 2051 * encoder using any of the ports of this DSI encoder. 2052 */ 2053 for_each_intel_encoder(&i915->drm, other_encoder) { 2054 if (other_encoder == encoder) 2055 continue; 2056 2057 if (drm_WARN_ON(&i915->drm, 2058 port_mask & BIT(other_encoder->port))) 2059 return; 2060 } 2061 /* 2062 * For DSI we keep the ddi clocks gated 2063 * except during enable/disable sequence. 2064 */ 2065 ddi_clk_needed = false; 2066 } 2067 2068 if (ddi_clk_needed || !encoder->is_clock_enabled || 2069 !encoder->is_clock_enabled(encoder)) 2070 return; 2071 2072 drm_notice(&i915->drm, 2073 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2074 encoder->base.base.id, encoder->base.name); 2075 2076 encoder->disable_clock(encoder); 2077 } 2078 2079 static void 2080 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2081 const struct intel_crtc_state *crtc_state) 2082 { 2083 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2084 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); 2085 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 2086 u32 ln0, ln1, pin_assignment; 2087 u8 width; 2088 2089 if (!intel_phy_is_tc(dev_priv, phy) || 2090 intel_tc_port_in_tbt_alt_mode(dig_port)) 2091 return; 2092 2093 if (DISPLAY_VER(dev_priv) >= 12) { 2094 ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)); 2095 ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)); 2096 } else { 2097 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2098 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2099 } 2100 2101 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2102 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2103 2104 /* DPPATC */ 2105 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2106 width = crtc_state->lane_count; 2107 2108 switch (pin_assignment) { 2109 case 0x0: 2110 drm_WARN_ON(&dev_priv->drm, 2111 !intel_tc_port_in_legacy_mode(dig_port)); 2112 if (width == 1) { 2113 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2114 } else { 2115 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2116 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2117 } 2118 break; 2119 case 0x1: 2120 if (width == 4) { 2121 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2122 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2123 } 2124 break; 2125 case 0x2: 2126 if (width == 2) { 2127 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2128 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2129 } 2130 break; 2131 case 0x3: 2132 case 0x5: 2133 if (width == 1) { 2134 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2135 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2136 } else { 2137 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2138 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2139 } 2140 break; 2141 case 0x4: 2142 case 0x6: 2143 if (width == 1) { 2144 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2145 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2146 } else { 2147 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2148 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2149 } 2150 break; 2151 default: 2152 MISSING_CASE(pin_assignment); 2153 } 2154 2155 if (DISPLAY_VER(dev_priv) >= 12) { 2156 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0); 2157 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1); 2158 } else { 2159 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2160 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2161 } 2162 } 2163 2164 static enum transcoder 2165 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2166 { 2167 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2168 return crtc_state->mst_master_transcoder; 2169 else 2170 return crtc_state->cpu_transcoder; 2171 } 2172 2173 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2174 const struct intel_crtc_state *crtc_state) 2175 { 2176 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2177 2178 if (DISPLAY_VER(dev_priv) >= 12) 2179 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state)); 2180 else 2181 return DP_TP_CTL(encoder->port); 2182 } 2183 2184 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2185 const struct intel_crtc_state *crtc_state) 2186 { 2187 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2188 2189 if (DISPLAY_VER(dev_priv) >= 12) 2190 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state)); 2191 else 2192 return DP_TP_STATUS(encoder->port); 2193 } 2194 2195 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2196 const struct intel_crtc_state *crtc_state, 2197 bool enable) 2198 { 2199 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2200 2201 if (!crtc_state->vrr.enable) 2202 return; 2203 2204 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2205 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2206 drm_dbg_kms(&i915->drm, 2207 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2208 str_enable_disable(enable)); 2209 } 2210 2211 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2212 const struct intel_crtc_state *crtc_state) 2213 { 2214 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2215 2216 if (!crtc_state->fec_enable) 2217 return; 2218 2219 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 2220 drm_dbg_kms(&i915->drm, 2221 "Failed to set FEC_READY in the sink\n"); 2222 } 2223 2224 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2225 const struct intel_crtc_state *crtc_state) 2226 { 2227 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2228 2229 if (!crtc_state->fec_enable) 2230 return; 2231 2232 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2233 0, DP_TP_CTL_FEC_ENABLE); 2234 } 2235 2236 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 2237 const struct intel_crtc_state *crtc_state) 2238 { 2239 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2240 2241 if (!crtc_state->fec_enable) 2242 return; 2243 2244 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2245 DP_TP_CTL_FEC_ENABLE, 0); 2246 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2247 } 2248 2249 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2250 const struct intel_crtc_state *crtc_state) 2251 { 2252 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2253 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2254 enum phy phy = intel_port_to_phy(i915, encoder->port); 2255 2256 if (intel_phy_is_combo(i915, phy)) { 2257 bool lane_reversal = 2258 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2259 2260 intel_combo_phy_power_up_lanes(i915, phy, false, 2261 crtc_state->lane_count, 2262 lane_reversal); 2263 } 2264 } 2265 2266 /* Splitter enable for eDP MSO is limited to certain pipes. */ 2267 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) 2268 { 2269 if (IS_ALDERLAKE_P(i915)) 2270 return BIT(PIPE_A) | BIT(PIPE_B); 2271 else 2272 return BIT(PIPE_A); 2273 } 2274 2275 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2276 struct intel_crtc_state *pipe_config) 2277 { 2278 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2279 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2280 enum pipe pipe = crtc->pipe; 2281 u32 dss1; 2282 2283 if (!HAS_MSO(i915)) 2284 return; 2285 2286 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2287 2288 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2289 if (!pipe_config->splitter.enable) 2290 return; 2291 2292 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { 2293 pipe_config->splitter.enable = false; 2294 return; 2295 } 2296 2297 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2298 default: 2299 drm_WARN(&i915->drm, true, 2300 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2301 fallthrough; 2302 case SPLITTER_CONFIGURATION_2_SEGMENT: 2303 pipe_config->splitter.link_count = 2; 2304 break; 2305 case SPLITTER_CONFIGURATION_4_SEGMENT: 2306 pipe_config->splitter.link_count = 4; 2307 break; 2308 } 2309 2310 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2311 } 2312 2313 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2314 { 2315 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2316 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2317 enum pipe pipe = crtc->pipe; 2318 u32 dss1 = 0; 2319 2320 if (!HAS_MSO(i915)) 2321 return; 2322 2323 if (crtc_state->splitter.enable) { 2324 dss1 |= SPLITTER_ENABLE; 2325 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2326 if (crtc_state->splitter.link_count == 2) 2327 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2328 else 2329 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2330 } 2331 2332 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2333 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2334 OVERLAP_PIXELS_MASK, dss1); 2335 } 2336 2337 static u8 mtl_get_port_width(u8 lane_count) 2338 { 2339 switch (lane_count) { 2340 case 1: 2341 return 0; 2342 case 2: 2343 return 1; 2344 case 3: 2345 return 4; 2346 case 4: 2347 return 3; 2348 default: 2349 MISSING_CASE(lane_count); 2350 return 4; 2351 } 2352 } 2353 2354 static void 2355 mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2356 { 2357 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2358 enum port port = encoder->port; 2359 2360 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port), 0, 2361 XELPDP_PORT_BUF_D2D_LINK_ENABLE); 2362 2363 if (wait_for_us((intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) & 2364 XELPDP_PORT_BUF_D2D_LINK_STATE), 100)) { 2365 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for PORT_BUF_CTL %c\n", 2366 port_name(port)); 2367 } 2368 } 2369 2370 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2371 const struct intel_crtc_state *crtc_state) 2372 { 2373 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2374 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2375 enum port port = encoder->port; 2376 u32 val; 2377 2378 val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)); 2379 val &= ~XELPDP_PORT_WIDTH_MASK; 2380 val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count)); 2381 2382 val &= ~XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK; 2383 if (intel_dp_is_uhbr(crtc_state)) 2384 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2385 else 2386 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2387 2388 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) 2389 val |= XELPDP_PORT_REVERSAL; 2390 2391 intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val); 2392 } 2393 2394 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2395 { 2396 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2397 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2398 u32 val; 2399 2400 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2401 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2402 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port), 2403 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2404 } 2405 2406 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2407 struct intel_encoder *encoder, 2408 const struct intel_crtc_state *crtc_state, 2409 const struct drm_connector_state *conn_state) 2410 { 2411 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2412 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2413 2414 intel_dp_set_link_params(intel_dp, 2415 crtc_state->port_clock, 2416 crtc_state->lane_count); 2417 2418 /* 2419 * We only configure what the register value will be here. Actual 2420 * enabling happens during link training farther down. 2421 */ 2422 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2423 2424 /* 2425 * 1. Enable Power Wells 2426 * 2427 * This was handled at the beginning of intel_atomic_commit_tail(), 2428 * before we called down into this function. 2429 */ 2430 2431 /* 2. PMdemand was already set */ 2432 2433 /* 3. Select Thunderbolt */ 2434 mtl_port_buf_ctl_io_selection(encoder); 2435 2436 /* 4. Enable Panel Power if PPS is required */ 2437 intel_pps_on(intel_dp); 2438 2439 /* 5. Enable the port PLL */ 2440 intel_ddi_enable_clock(encoder, crtc_state); 2441 2442 /* 2443 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2444 * Transcoder. 2445 */ 2446 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2447 2448 /* 2449 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2450 */ 2451 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2452 2453 /* 2454 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2455 * Transport Select 2456 */ 2457 intel_ddi_config_transcoder_func(encoder, crtc_state); 2458 2459 /* 2460 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2461 */ 2462 intel_ddi_mso_configure(crtc_state); 2463 2464 if (!is_mst) 2465 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2466 2467 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2468 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 2469 /* 2470 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2471 * in the FEC_CONFIGURATION register to 1 before initiating link 2472 * training 2473 */ 2474 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2475 2476 intel_dp_check_frl_training(intel_dp); 2477 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2478 2479 /* 2480 * 6. The rest of the below are substeps under the bspec's "Enable and 2481 * Train Display Port" step. Note that steps that are specific to 2482 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2483 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2484 * us when active_mst_links==0, so any steps designated for "single 2485 * stream or multi-stream master transcoder" can just be performed 2486 * unconditionally here. 2487 * 2488 * mtl_ddi_prepare_link_retrain() that is called by 2489 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2490 * 6.i and 6.j 2491 * 2492 * 6.k Follow DisplayPort specification training sequence (see notes for 2493 * failure handling) 2494 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2495 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2496 * (timeout after 800 us) 2497 */ 2498 intel_dp_start_link_train(intel_dp, crtc_state); 2499 2500 /* 6.n Set DP_TP_CTL link training to Normal */ 2501 if (!is_trans_port_sync_mode(crtc_state)) 2502 intel_dp_stop_link_train(intel_dp, crtc_state); 2503 2504 /* 6.o Configure and enable FEC if needed */ 2505 intel_ddi_enable_fec(encoder, crtc_state); 2506 2507 intel_dsc_dp_pps_write(encoder, crtc_state); 2508 } 2509 2510 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2511 struct intel_encoder *encoder, 2512 const struct intel_crtc_state *crtc_state, 2513 const struct drm_connector_state *conn_state) 2514 { 2515 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2516 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2517 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2518 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2519 2520 intel_dp_set_link_params(intel_dp, 2521 crtc_state->port_clock, 2522 crtc_state->lane_count); 2523 2524 /* 2525 * We only configure what the register value will be here. Actual 2526 * enabling happens during link training farther down. 2527 */ 2528 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2529 2530 /* 2531 * 1. Enable Power Wells 2532 * 2533 * This was handled at the beginning of intel_atomic_commit_tail(), 2534 * before we called down into this function. 2535 */ 2536 2537 /* 2. Enable Panel Power if PPS is required */ 2538 intel_pps_on(intel_dp); 2539 2540 /* 2541 * 3. For non-TBT Type-C ports, set FIA lane count 2542 * (DFLEXDPSP.DPX4TXLATC) 2543 * 2544 * This was done before tgl_ddi_pre_enable_dp by 2545 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2546 */ 2547 2548 /* 2549 * 4. Enable the port PLL. 2550 * 2551 * The PLL enabling itself was already done before this function by 2552 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2553 * configure the PLL to port mapping here. 2554 */ 2555 intel_ddi_enable_clock(encoder, crtc_state); 2556 2557 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2558 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2559 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2560 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2561 dig_port->ddi_io_power_domain); 2562 } 2563 2564 /* 6. Program DP_MODE */ 2565 icl_program_mg_dp_mode(dig_port, crtc_state); 2566 2567 /* 2568 * 7. The rest of the below are substeps under the bspec's "Enable and 2569 * Train Display Port" step. Note that steps that are specific to 2570 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2571 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2572 * us when active_mst_links==0, so any steps designated for "single 2573 * stream or multi-stream master transcoder" can just be performed 2574 * unconditionally here. 2575 */ 2576 2577 /* 2578 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2579 * Transcoder. 2580 */ 2581 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2582 2583 if (HAS_DP20(dev_priv)) 2584 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2585 2586 /* 2587 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2588 * Transport Select 2589 */ 2590 intel_ddi_config_transcoder_func(encoder, crtc_state); 2591 2592 /* 2593 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2594 * selected 2595 * 2596 * This will be handled by the intel_dp_start_link_train() farther 2597 * down this function. 2598 */ 2599 2600 /* 7.e Configure voltage swing and related IO settings */ 2601 encoder->set_signal_levels(encoder, crtc_state); 2602 2603 /* 2604 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2605 * the used lanes of the DDI. 2606 */ 2607 intel_ddi_power_up_lanes(encoder, crtc_state); 2608 2609 /* 2610 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2611 */ 2612 intel_ddi_mso_configure(crtc_state); 2613 2614 if (!is_mst) 2615 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2616 2617 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2618 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 2619 /* 2620 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2621 * in the FEC_CONFIGURATION register to 1 before initiating link 2622 * training 2623 */ 2624 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2625 2626 intel_dp_check_frl_training(intel_dp); 2627 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2628 2629 /* 2630 * 7.i Follow DisplayPort specification training sequence (see notes for 2631 * failure handling) 2632 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2633 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2634 * (timeout after 800 us) 2635 */ 2636 intel_dp_start_link_train(intel_dp, crtc_state); 2637 2638 /* 7.k Set DP_TP_CTL link training to Normal */ 2639 if (!is_trans_port_sync_mode(crtc_state)) 2640 intel_dp_stop_link_train(intel_dp, crtc_state); 2641 2642 /* 7.l Configure and enable FEC if needed */ 2643 intel_ddi_enable_fec(encoder, crtc_state); 2644 2645 intel_dsc_dp_pps_write(encoder, crtc_state); 2646 } 2647 2648 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2649 struct intel_encoder *encoder, 2650 const struct intel_crtc_state *crtc_state, 2651 const struct drm_connector_state *conn_state) 2652 { 2653 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2654 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2655 enum port port = encoder->port; 2656 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2657 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2658 2659 if (DISPLAY_VER(dev_priv) < 11) 2660 drm_WARN_ON(&dev_priv->drm, 2661 is_mst && (port == PORT_A || port == PORT_E)); 2662 else 2663 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2664 2665 intel_dp_set_link_params(intel_dp, 2666 crtc_state->port_clock, 2667 crtc_state->lane_count); 2668 2669 /* 2670 * We only configure what the register value will be here. Actual 2671 * enabling happens during link training farther down. 2672 */ 2673 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2674 2675 intel_pps_on(intel_dp); 2676 2677 intel_ddi_enable_clock(encoder, crtc_state); 2678 2679 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2680 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2681 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2682 dig_port->ddi_io_power_domain); 2683 } 2684 2685 icl_program_mg_dp_mode(dig_port, crtc_state); 2686 2687 if (has_buf_trans_select(dev_priv)) 2688 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2689 2690 encoder->set_signal_levels(encoder, crtc_state); 2691 2692 intel_ddi_power_up_lanes(encoder, crtc_state); 2693 2694 if (!is_mst) 2695 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2696 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2697 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 2698 true); 2699 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2700 intel_dp_start_link_train(intel_dp, crtc_state); 2701 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2702 !is_trans_port_sync_mode(crtc_state)) 2703 intel_dp_stop_link_train(intel_dp, crtc_state); 2704 2705 intel_ddi_enable_fec(encoder, crtc_state); 2706 2707 if (!is_mst) 2708 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2709 2710 intel_dsc_dp_pps_write(encoder, crtc_state); 2711 } 2712 2713 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2714 struct intel_encoder *encoder, 2715 const struct intel_crtc_state *crtc_state, 2716 const struct drm_connector_state *conn_state) 2717 { 2718 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2719 2720 if (HAS_DP20(dev_priv)) 2721 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2722 crtc_state); 2723 2724 if (DISPLAY_VER(dev_priv) >= 14) 2725 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2726 else if (DISPLAY_VER(dev_priv) >= 12) 2727 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2728 else 2729 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2730 2731 /* MST will call a setting of MSA after an allocating of Virtual Channel 2732 * from MST encoder pre_enable callback. 2733 */ 2734 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2735 intel_ddi_set_dp_msa(crtc_state, conn_state); 2736 } 2737 2738 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2739 struct intel_encoder *encoder, 2740 const struct intel_crtc_state *crtc_state, 2741 const struct drm_connector_state *conn_state) 2742 { 2743 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2744 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2745 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2746 2747 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2748 intel_ddi_enable_clock(encoder, crtc_state); 2749 2750 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2751 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2752 dig_port->ddi_io_power_domain); 2753 2754 icl_program_mg_dp_mode(dig_port, crtc_state); 2755 2756 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2757 2758 dig_port->set_infoframes(encoder, 2759 crtc_state->has_infoframe, 2760 crtc_state, conn_state); 2761 } 2762 2763 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2764 struct intel_encoder *encoder, 2765 const struct intel_crtc_state *crtc_state, 2766 const struct drm_connector_state *conn_state) 2767 { 2768 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2769 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2770 enum pipe pipe = crtc->pipe; 2771 2772 /* 2773 * When called from DP MST code: 2774 * - conn_state will be NULL 2775 * - encoder will be the main encoder (ie. mst->primary) 2776 * - the main connector associated with this port 2777 * won't be active or linked to a crtc 2778 * - crtc_state will be the state of the first stream to 2779 * be activated on this port, and it may not be the same 2780 * stream that will be deactivated last, but each stream 2781 * should have a state that is identical when it comes to 2782 * the DP link parameteres 2783 */ 2784 2785 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2786 2787 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2788 2789 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2790 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 2791 conn_state); 2792 } else { 2793 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2794 2795 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 2796 conn_state); 2797 2798 /* FIXME precompute everything properly */ 2799 /* FIXME how do we turn infoframes off again? */ 2800 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 2801 dig_port->set_infoframes(encoder, 2802 crtc_state->has_infoframe, 2803 crtc_state, conn_state); 2804 } 2805 } 2806 2807 static void 2808 mtl_ddi_disable_d2d_link(struct intel_encoder *encoder) 2809 { 2810 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2811 enum port port = encoder->port; 2812 2813 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port), 2814 XELPDP_PORT_BUF_D2D_LINK_ENABLE, 0); 2815 2816 if (wait_for_us(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) & 2817 XELPDP_PORT_BUF_D2D_LINK_STATE), 100)) 2818 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for PORT_BUF_CTL %c\n", 2819 port_name(port)); 2820 } 2821 2822 static void mtl_disable_ddi_buf(struct intel_encoder *encoder, 2823 const struct intel_crtc_state *crtc_state) 2824 { 2825 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2826 enum port port = encoder->port; 2827 u32 val; 2828 2829 /* 3.b Clear DDI_CTL_DE Enable to 0. */ 2830 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2831 if (val & DDI_BUF_CTL_ENABLE) { 2832 val &= ~DDI_BUF_CTL_ENABLE; 2833 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2834 2835 /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */ 2836 mtl_wait_ddi_buf_idle(dev_priv, port); 2837 } 2838 2839 /* 3.d Disable D2D Link */ 2840 mtl_ddi_disable_d2d_link(encoder); 2841 2842 /* 3.e Disable DP_TP_CTL */ 2843 if (intel_crtc_has_dp_encoder(crtc_state)) { 2844 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2845 DP_TP_CTL_ENABLE, 0); 2846 } 2847 } 2848 2849 static void disable_ddi_buf(struct intel_encoder *encoder, 2850 const struct intel_crtc_state *crtc_state) 2851 { 2852 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2853 enum port port = encoder->port; 2854 bool wait = false; 2855 u32 val; 2856 2857 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2858 if (val & DDI_BUF_CTL_ENABLE) { 2859 val &= ~DDI_BUF_CTL_ENABLE; 2860 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2861 wait = true; 2862 } 2863 2864 if (intel_crtc_has_dp_encoder(crtc_state)) 2865 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2866 DP_TP_CTL_ENABLE, 0); 2867 2868 /* Disable FEC in DP Sink */ 2869 intel_ddi_disable_fec_state(encoder, crtc_state); 2870 2871 if (wait) 2872 intel_wait_ddi_buf_idle(dev_priv, port); 2873 } 2874 2875 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 2876 const struct intel_crtc_state *crtc_state) 2877 { 2878 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2879 2880 if (DISPLAY_VER(dev_priv) >= 14) { 2881 mtl_disable_ddi_buf(encoder, crtc_state); 2882 2883 /* 3.f Disable DP_TP_CTL FEC Enable if it is needed */ 2884 intel_ddi_disable_fec_state(encoder, crtc_state); 2885 } else { 2886 disable_ddi_buf(encoder, crtc_state); 2887 } 2888 } 2889 2890 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 2891 struct intel_encoder *encoder, 2892 const struct intel_crtc_state *old_crtc_state, 2893 const struct drm_connector_state *old_conn_state) 2894 { 2895 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2896 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2897 struct intel_dp *intel_dp = &dig_port->dp; 2898 intel_wakeref_t wakeref; 2899 bool is_mst = intel_crtc_has_type(old_crtc_state, 2900 INTEL_OUTPUT_DP_MST); 2901 2902 if (!is_mst) 2903 intel_dp_set_infoframes(encoder, false, 2904 old_crtc_state, old_conn_state); 2905 2906 /* 2907 * Power down sink before disabling the port, otherwise we end 2908 * up getting interrupts from the sink on detecting link loss. 2909 */ 2910 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 2911 2912 if (DISPLAY_VER(dev_priv) >= 12) { 2913 if (is_mst) { 2914 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 2915 2916 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 2917 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 2918 0); 2919 } 2920 } else { 2921 if (!is_mst) 2922 intel_ddi_disable_transcoder_clock(old_crtc_state); 2923 } 2924 2925 intel_disable_ddi_buf(encoder, old_crtc_state); 2926 2927 /* 2928 * From TGL spec: "If single stream or multi-stream master transcoder: 2929 * Configure Transcoder Clock select to direct no clock to the 2930 * transcoder" 2931 */ 2932 if (DISPLAY_VER(dev_priv) >= 12) 2933 intel_ddi_disable_transcoder_clock(old_crtc_state); 2934 2935 intel_pps_vdd_on(intel_dp); 2936 intel_pps_off(intel_dp); 2937 2938 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 2939 2940 if (wakeref) 2941 intel_display_power_put(dev_priv, 2942 dig_port->ddi_io_power_domain, 2943 wakeref); 2944 2945 intel_ddi_disable_clock(encoder); 2946 2947 /* De-select Thunderbolt */ 2948 if (DISPLAY_VER(dev_priv) >= 14) 2949 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(encoder->port), 2950 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 2951 } 2952 2953 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 2954 struct intel_encoder *encoder, 2955 const struct intel_crtc_state *old_crtc_state, 2956 const struct drm_connector_state *old_conn_state) 2957 { 2958 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2959 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2960 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2961 intel_wakeref_t wakeref; 2962 2963 dig_port->set_infoframes(encoder, false, 2964 old_crtc_state, old_conn_state); 2965 2966 if (DISPLAY_VER(dev_priv) < 12) 2967 intel_ddi_disable_transcoder_clock(old_crtc_state); 2968 2969 intel_disable_ddi_buf(encoder, old_crtc_state); 2970 2971 if (DISPLAY_VER(dev_priv) >= 12) 2972 intel_ddi_disable_transcoder_clock(old_crtc_state); 2973 2974 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 2975 if (wakeref) 2976 intel_display_power_put(dev_priv, 2977 dig_port->ddi_io_power_domain, 2978 wakeref); 2979 2980 intel_ddi_disable_clock(encoder); 2981 2982 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 2983 } 2984 2985 static void intel_ddi_post_disable(struct intel_atomic_state *state, 2986 struct intel_encoder *encoder, 2987 const struct intel_crtc_state *old_crtc_state, 2988 const struct drm_connector_state *old_conn_state) 2989 { 2990 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2991 struct intel_crtc *slave_crtc; 2992 2993 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 2994 intel_crtc_vblank_off(old_crtc_state); 2995 2996 intel_disable_transcoder(old_crtc_state); 2997 2998 intel_ddi_disable_transcoder_func(old_crtc_state); 2999 3000 intel_dsc_disable(old_crtc_state); 3001 3002 if (DISPLAY_VER(dev_priv) >= 9) 3003 skl_scaler_disable(old_crtc_state); 3004 else 3005 ilk_pfit_disable(old_crtc_state); 3006 } 3007 3008 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc, 3009 intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) { 3010 const struct intel_crtc_state *old_slave_crtc_state = 3011 intel_atomic_get_old_crtc_state(state, slave_crtc); 3012 3013 intel_crtc_vblank_off(old_slave_crtc_state); 3014 3015 intel_dsc_disable(old_slave_crtc_state); 3016 skl_scaler_disable(old_slave_crtc_state); 3017 } 3018 3019 /* 3020 * When called from DP MST code: 3021 * - old_conn_state will be NULL 3022 * - encoder will be the main encoder (ie. mst->primary) 3023 * - the main connector associated with this port 3024 * won't be active or linked to a crtc 3025 * - old_crtc_state will be the state of the last stream to 3026 * be deactivated on this port, and it may not be the same 3027 * stream that was activated last, but each stream 3028 * should have a state that is identical when it comes to 3029 * the DP link parameteres 3030 */ 3031 3032 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3033 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3034 old_conn_state); 3035 else 3036 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3037 old_conn_state); 3038 } 3039 3040 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3041 struct intel_encoder *encoder, 3042 const struct intel_crtc_state *old_crtc_state, 3043 const struct drm_connector_state *old_conn_state) 3044 { 3045 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3046 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3047 enum phy phy = intel_port_to_phy(i915, encoder->port); 3048 bool is_tc_port = intel_phy_is_tc(i915, phy); 3049 3050 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3051 3052 if (is_tc_port) 3053 intel_tc_port_put_link(dig_port); 3054 } 3055 3056 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3057 struct intel_encoder *encoder, 3058 const struct intel_crtc_state *crtc_state) 3059 { 3060 const struct drm_connector_state *conn_state; 3061 struct drm_connector *conn; 3062 int i; 3063 3064 if (!crtc_state->sync_mode_slaves_mask) 3065 return; 3066 3067 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3068 struct intel_encoder *slave_encoder = 3069 to_intel_encoder(conn_state->best_encoder); 3070 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3071 const struct intel_crtc_state *slave_crtc_state; 3072 3073 if (!slave_crtc) 3074 continue; 3075 3076 slave_crtc_state = 3077 intel_atomic_get_new_crtc_state(state, slave_crtc); 3078 3079 if (slave_crtc_state->master_transcoder != 3080 crtc_state->cpu_transcoder) 3081 continue; 3082 3083 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3084 slave_crtc_state); 3085 } 3086 3087 usleep_range(200, 400); 3088 3089 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3090 crtc_state); 3091 } 3092 3093 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 3094 struct intel_encoder *encoder, 3095 const struct intel_crtc_state *crtc_state, 3096 const struct drm_connector_state *conn_state) 3097 { 3098 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3099 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3100 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3101 enum port port = encoder->port; 3102 3103 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 3104 intel_dp_stop_link_train(intel_dp, crtc_state); 3105 3106 drm_connector_update_privacy_screen(conn_state); 3107 intel_edp_backlight_on(crtc_state, conn_state); 3108 3109 if (!dig_port->lspcon.active || intel_dp_has_hdmi_sink(&dig_port->dp)) 3110 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3111 3112 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3113 3114 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3115 } 3116 3117 static i915_reg_t 3118 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3119 enum port port) 3120 { 3121 static const enum transcoder trans[] = { 3122 [PORT_A] = TRANSCODER_EDP, 3123 [PORT_B] = TRANSCODER_A, 3124 [PORT_C] = TRANSCODER_B, 3125 [PORT_D] = TRANSCODER_C, 3126 [PORT_E] = TRANSCODER_A, 3127 }; 3128 3129 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); 3130 3131 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 3132 port = PORT_A; 3133 3134 return CHICKEN_TRANS(trans[port]); 3135 } 3136 3137 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 3138 struct intel_encoder *encoder, 3139 const struct intel_crtc_state *crtc_state, 3140 const struct drm_connector_state *conn_state) 3141 { 3142 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3143 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3144 struct drm_connector *connector = conn_state->connector; 3145 enum port port = encoder->port; 3146 enum phy phy = intel_port_to_phy(dev_priv, port); 3147 u32 buf_ctl; 3148 3149 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3150 crtc_state->hdmi_high_tmds_clock_ratio, 3151 crtc_state->hdmi_scrambling)) 3152 drm_dbg_kms(&dev_priv->drm, 3153 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3154 connector->base.id, connector->name); 3155 3156 if (has_buf_trans_select(dev_priv)) 3157 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3158 3159 /* e. Enable D2D Link for C10/C20 Phy */ 3160 if (DISPLAY_VER(dev_priv) >= 14) 3161 mtl_ddi_enable_d2d(encoder); 3162 3163 encoder->set_signal_levels(encoder, crtc_state); 3164 3165 /* Display WA #1143: skl,kbl,cfl */ 3166 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 3167 /* 3168 * For some reason these chicken bits have been 3169 * stuffed into a transcoder register, event though 3170 * the bits affect a specific DDI port rather than 3171 * a specific transcoder. 3172 */ 3173 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 3174 u32 val; 3175 3176 val = intel_de_read(dev_priv, reg); 3177 3178 if (port == PORT_E) 3179 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3180 DDIE_TRAINING_OVERRIDE_VALUE; 3181 else 3182 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3183 DDI_TRAINING_OVERRIDE_VALUE; 3184 3185 intel_de_write(dev_priv, reg, val); 3186 intel_de_posting_read(dev_priv, reg); 3187 3188 udelay(1); 3189 3190 if (port == PORT_E) 3191 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3192 DDIE_TRAINING_OVERRIDE_VALUE); 3193 else 3194 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3195 DDI_TRAINING_OVERRIDE_VALUE); 3196 3197 intel_de_write(dev_priv, reg, val); 3198 } 3199 3200 intel_ddi_power_up_lanes(encoder, crtc_state); 3201 3202 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3203 * are ignored so nothing special needs to be done besides 3204 * enabling the port. 3205 * 3206 * On ADL_P the PHY link rate and lane count must be programmed but 3207 * these are both 0 for HDMI. 3208 * 3209 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3210 * is filled with lane count, already set in the crtc_state. 3211 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3212 */ 3213 buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE; 3214 if (DISPLAY_VER(dev_priv) >= 14) { 3215 u8 lane_count = mtl_get_port_width(crtc_state->lane_count); 3216 u32 port_buf = 0; 3217 3218 port_buf |= XELPDP_PORT_WIDTH(lane_count); 3219 3220 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) 3221 port_buf |= XELPDP_PORT_REVERSAL; 3222 3223 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port), 3224 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3225 3226 buf_ctl |= DDI_PORT_WIDTH(lane_count); 3227 } else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) { 3228 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3229 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3230 } 3231 3232 intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl); 3233 3234 intel_wait_ddi_buf_active(dev_priv, port); 3235 3236 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3237 } 3238 3239 static void intel_enable_ddi(struct intel_atomic_state *state, 3240 struct intel_encoder *encoder, 3241 const struct intel_crtc_state *crtc_state, 3242 const struct drm_connector_state *conn_state) 3243 { 3244 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 3245 3246 if (!intel_crtc_is_bigjoiner_slave(crtc_state)) 3247 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3248 3249 /* Enable/Disable DP2.0 SDP split config before transcoder */ 3250 intel_audio_sdp_split_update(encoder, crtc_state); 3251 3252 intel_enable_transcoder(crtc_state); 3253 3254 intel_crtc_vblank_on(crtc_state); 3255 3256 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3257 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 3258 else 3259 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 3260 3261 /* Enable hdcp if it's desired */ 3262 if (conn_state->content_protection == 3263 DRM_MODE_CONTENT_PROTECTION_DESIRED) 3264 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3265 } 3266 3267 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 3268 struct intel_encoder *encoder, 3269 const struct intel_crtc_state *old_crtc_state, 3270 const struct drm_connector_state *old_conn_state) 3271 { 3272 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3273 3274 intel_dp->link_trained = false; 3275 3276 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 3277 3278 intel_psr_disable(intel_dp, old_crtc_state); 3279 intel_edp_backlight_off(old_conn_state); 3280 /* Disable the decompression in DP Sink */ 3281 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 3282 false); 3283 /* Disable Ignore_MSA bit in DP Sink */ 3284 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3285 false); 3286 } 3287 3288 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 3289 struct intel_encoder *encoder, 3290 const struct intel_crtc_state *old_crtc_state, 3291 const struct drm_connector_state *old_conn_state) 3292 { 3293 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3294 struct drm_connector *connector = old_conn_state->connector; 3295 3296 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 3297 3298 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3299 false, false)) 3300 drm_dbg_kms(&i915->drm, 3301 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3302 connector->base.id, connector->name); 3303 } 3304 3305 static void intel_disable_ddi(struct intel_atomic_state *state, 3306 struct intel_encoder *encoder, 3307 const struct intel_crtc_state *old_crtc_state, 3308 const struct drm_connector_state *old_conn_state) 3309 { 3310 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3311 3312 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3313 3314 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3315 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 3316 old_conn_state); 3317 else 3318 intel_disable_ddi_dp(state, encoder, old_crtc_state, 3319 old_conn_state); 3320 } 3321 3322 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3323 struct intel_encoder *encoder, 3324 const struct intel_crtc_state *crtc_state, 3325 const struct drm_connector_state *conn_state) 3326 { 3327 intel_ddi_set_dp_msa(crtc_state, conn_state); 3328 3329 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3330 3331 intel_backlight_update(state, encoder, crtc_state, conn_state); 3332 drm_connector_update_privacy_screen(conn_state); 3333 } 3334 3335 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3336 struct intel_encoder *encoder, 3337 const struct intel_crtc_state *crtc_state, 3338 const struct drm_connector_state *conn_state) 3339 { 3340 3341 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3342 !intel_encoder_is_mst(encoder)) 3343 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3344 conn_state); 3345 3346 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3347 } 3348 3349 void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3350 struct intel_encoder *encoder, 3351 struct intel_crtc *crtc) 3352 { 3353 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3354 struct intel_crtc_state *crtc_state = 3355 intel_atomic_get_new_crtc_state(state, crtc); 3356 struct intel_crtc *slave_crtc; 3357 enum phy phy = intel_port_to_phy(i915, encoder->port); 3358 3359 /* FIXME: Add MTL pll_mgr */ 3360 if (DISPLAY_VER(i915) >= 14 || !intel_phy_is_tc(i915, phy)) 3361 return; 3362 3363 intel_update_active_dpll(state, crtc, encoder); 3364 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 3365 intel_crtc_bigjoiner_slave_pipes(crtc_state)) 3366 intel_update_active_dpll(state, slave_crtc, encoder); 3367 } 3368 3369 static void 3370 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3371 struct intel_encoder *encoder, 3372 const struct intel_crtc_state *crtc_state, 3373 const struct drm_connector_state *conn_state) 3374 { 3375 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3376 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3377 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3378 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3379 3380 if (is_tc_port) { 3381 struct intel_crtc *master_crtc = 3382 to_intel_crtc(crtc_state->uapi.crtc); 3383 3384 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3385 intel_ddi_update_active_dpll(state, encoder, master_crtc); 3386 } 3387 3388 main_link_aux_power_domain_get(dig_port, crtc_state); 3389 3390 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3391 /* 3392 * Program the lane count for static/dynamic connections on 3393 * Type-C ports. Skip this step for TBT. 3394 */ 3395 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3396 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3397 bxt_ddi_phy_set_lane_optim_mask(encoder, 3398 crtc_state->lane_lat_optim_mask); 3399 } 3400 3401 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3402 { 3403 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3404 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 3405 int ln; 3406 3407 for (ln = 0; ln < 2; ln++) 3408 intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0); 3409 } 3410 3411 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3412 const struct intel_crtc_state *crtc_state) 3413 { 3414 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3415 struct intel_encoder *encoder = &dig_port->base; 3416 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3417 enum port port = encoder->port; 3418 u32 dp_tp_ctl; 3419 3420 /* 3421 * TODO: To train with only a different voltage swing entry is not 3422 * necessary disable and enable port 3423 */ 3424 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3425 if (dp_tp_ctl & DP_TP_CTL_ENABLE) 3426 mtl_disable_ddi_buf(encoder, crtc_state); 3427 3428 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3429 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3430 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3431 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3432 } else { 3433 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3434 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3435 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3436 } 3437 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3438 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3439 3440 /* 6.f Enable D2D Link */ 3441 mtl_ddi_enable_d2d(encoder); 3442 3443 /* 6.g Configure voltage swing and related IO settings */ 3444 encoder->set_signal_levels(encoder, crtc_state); 3445 3446 /* 6.h Configure PORT_BUF_CTL1 */ 3447 mtl_port_buf_ctl_program(encoder, crtc_state); 3448 3449 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3450 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3451 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3452 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3453 3454 /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */ 3455 intel_wait_ddi_buf_active(dev_priv, port); 3456 } 3457 3458 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3459 const struct intel_crtc_state *crtc_state) 3460 { 3461 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3462 struct intel_encoder *encoder = &dig_port->base; 3463 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3464 enum port port = encoder->port; 3465 u32 dp_tp_ctl, ddi_buf_ctl; 3466 bool wait = false; 3467 3468 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3469 3470 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3471 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3472 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3473 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3474 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3475 wait = true; 3476 } 3477 3478 dp_tp_ctl &= ~DP_TP_CTL_ENABLE; 3479 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3480 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3481 3482 if (wait) 3483 intel_wait_ddi_buf_idle(dev_priv, port); 3484 } 3485 3486 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3487 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3488 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3489 } else { 3490 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3491 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3492 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3493 } 3494 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3495 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3496 3497 if (IS_ALDERLAKE_P(dev_priv) && 3498 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3499 adlp_tbt_to_dp_alt_switch_wa(encoder); 3500 3501 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3502 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3503 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3504 3505 intel_wait_ddi_buf_active(dev_priv, port); 3506 } 3507 3508 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3509 const struct intel_crtc_state *crtc_state, 3510 u8 dp_train_pat) 3511 { 3512 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3513 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3514 u32 temp; 3515 3516 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3517 3518 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3519 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3520 case DP_TRAINING_PATTERN_DISABLE: 3521 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3522 break; 3523 case DP_TRAINING_PATTERN_1: 3524 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3525 break; 3526 case DP_TRAINING_PATTERN_2: 3527 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3528 break; 3529 case DP_TRAINING_PATTERN_3: 3530 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3531 break; 3532 case DP_TRAINING_PATTERN_4: 3533 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3534 break; 3535 } 3536 3537 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3538 } 3539 3540 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3541 const struct intel_crtc_state *crtc_state) 3542 { 3543 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3544 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3545 enum port port = encoder->port; 3546 3547 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 3548 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3549 3550 /* 3551 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3552 * reason we need to set idle transmission mode is to work around a HW 3553 * issue where we enable the pipe while not in idle link-training mode. 3554 * In this case there is requirement to wait for a minimum number of 3555 * idle patterns to be sent. 3556 */ 3557 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3558 return; 3559 3560 if (intel_de_wait_for_set(dev_priv, 3561 dp_tp_status_reg(encoder, crtc_state), 3562 DP_TP_STATUS_IDLE_DONE, 1)) 3563 drm_err(&dev_priv->drm, 3564 "Timed out waiting for DP idle patterns\n"); 3565 } 3566 3567 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3568 enum transcoder cpu_transcoder) 3569 { 3570 if (cpu_transcoder == TRANSCODER_EDP) 3571 return false; 3572 3573 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) 3574 return false; 3575 3576 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3577 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3578 } 3579 3580 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 3581 struct intel_crtc_state *crtc_state) 3582 { 3583 if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000) 3584 crtc_state->min_voltage_level = 2; 3585 else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000) 3586 crtc_state->min_voltage_level = 3; 3587 else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000) 3588 crtc_state->min_voltage_level = 1; 3589 } 3590 3591 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3592 enum transcoder cpu_transcoder) 3593 { 3594 u32 master_select; 3595 3596 if (DISPLAY_VER(dev_priv) >= 11) { 3597 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 3598 3599 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3600 return INVALID_TRANSCODER; 3601 3602 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3603 } else { 3604 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3605 3606 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3607 return INVALID_TRANSCODER; 3608 3609 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3610 } 3611 3612 if (master_select == 0) 3613 return TRANSCODER_EDP; 3614 else 3615 return master_select - 1; 3616 } 3617 3618 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3619 { 3620 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3621 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3622 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3623 enum transcoder cpu_transcoder; 3624 3625 crtc_state->master_transcoder = 3626 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3627 3628 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3629 enum intel_display_power_domain power_domain; 3630 intel_wakeref_t trans_wakeref; 3631 3632 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3633 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3634 power_domain); 3635 3636 if (!trans_wakeref) 3637 continue; 3638 3639 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3640 crtc_state->cpu_transcoder) 3641 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3642 3643 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3644 } 3645 3646 drm_WARN_ON(&dev_priv->drm, 3647 crtc_state->master_transcoder != INVALID_TRANSCODER && 3648 crtc_state->sync_mode_slaves_mask); 3649 } 3650 3651 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 3652 struct intel_crtc_state *pipe_config) 3653 { 3654 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3655 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3656 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3657 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3658 u32 temp, flags = 0; 3659 3660 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3661 if (temp & TRANS_DDI_PHSYNC) 3662 flags |= DRM_MODE_FLAG_PHSYNC; 3663 else 3664 flags |= DRM_MODE_FLAG_NHSYNC; 3665 if (temp & TRANS_DDI_PVSYNC) 3666 flags |= DRM_MODE_FLAG_PVSYNC; 3667 else 3668 flags |= DRM_MODE_FLAG_NVSYNC; 3669 3670 pipe_config->hw.adjusted_mode.flags |= flags; 3671 3672 switch (temp & TRANS_DDI_BPC_MASK) { 3673 case TRANS_DDI_BPC_6: 3674 pipe_config->pipe_bpp = 18; 3675 break; 3676 case TRANS_DDI_BPC_8: 3677 pipe_config->pipe_bpp = 24; 3678 break; 3679 case TRANS_DDI_BPC_10: 3680 pipe_config->pipe_bpp = 30; 3681 break; 3682 case TRANS_DDI_BPC_12: 3683 pipe_config->pipe_bpp = 36; 3684 break; 3685 default: 3686 break; 3687 } 3688 3689 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3690 case TRANS_DDI_MODE_SELECT_HDMI: 3691 pipe_config->has_hdmi_sink = true; 3692 3693 pipe_config->infoframes.enable |= 3694 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3695 3696 if (pipe_config->infoframes.enable) 3697 pipe_config->has_infoframe = true; 3698 3699 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3700 pipe_config->hdmi_scrambling = true; 3701 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3702 pipe_config->hdmi_high_tmds_clock_ratio = true; 3703 fallthrough; 3704 case TRANS_DDI_MODE_SELECT_DVI: 3705 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3706 if (DISPLAY_VER(dev_priv) >= 14) 3707 pipe_config->lane_count = 3708 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3709 else 3710 pipe_config->lane_count = 4; 3711 break; 3712 case TRANS_DDI_MODE_SELECT_DP_SST: 3713 if (encoder->type == INTEL_OUTPUT_EDP) 3714 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3715 else 3716 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3717 pipe_config->lane_count = 3718 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3719 3720 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3721 &pipe_config->dp_m_n); 3722 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, 3723 &pipe_config->dp_m2_n2); 3724 3725 if (DISPLAY_VER(dev_priv) >= 11) { 3726 i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config); 3727 3728 pipe_config->fec_enable = 3729 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 3730 3731 drm_dbg_kms(&dev_priv->drm, 3732 "[ENCODER:%d:%s] Fec status: %u\n", 3733 encoder->base.base.id, encoder->base.name, 3734 pipe_config->fec_enable); 3735 } 3736 3737 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 3738 pipe_config->infoframes.enable |= 3739 intel_lspcon_infoframes_enabled(encoder, pipe_config); 3740 else 3741 pipe_config->infoframes.enable |= 3742 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3743 break; 3744 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 3745 if (!HAS_DP20(dev_priv)) { 3746 /* FDI */ 3747 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3748 break; 3749 } 3750 fallthrough; /* 128b/132b */ 3751 case TRANS_DDI_MODE_SELECT_DP_MST: 3752 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3753 pipe_config->lane_count = 3754 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3755 3756 if (DISPLAY_VER(dev_priv) >= 12) 3757 pipe_config->mst_master_transcoder = 3758 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 3759 3760 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3761 &pipe_config->dp_m_n); 3762 3763 pipe_config->infoframes.enable |= 3764 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3765 break; 3766 default: 3767 break; 3768 } 3769 } 3770 3771 static void intel_ddi_get_config(struct intel_encoder *encoder, 3772 struct intel_crtc_state *pipe_config) 3773 { 3774 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3775 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3776 3777 /* XXX: DSI transcoder paranoia */ 3778 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 3779 return; 3780 3781 intel_ddi_read_func_ctl(encoder, pipe_config); 3782 3783 intel_ddi_mso_get_config(encoder, pipe_config); 3784 3785 pipe_config->has_audio = 3786 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3787 3788 if (encoder->type == INTEL_OUTPUT_EDP) 3789 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 3790 3791 ddi_dotclock_get(pipe_config); 3792 3793 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3794 pipe_config->lane_lat_optim_mask = 3795 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 3796 3797 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3798 3799 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3800 3801 intel_read_infoframe(encoder, pipe_config, 3802 HDMI_INFOFRAME_TYPE_AVI, 3803 &pipe_config->infoframes.avi); 3804 intel_read_infoframe(encoder, pipe_config, 3805 HDMI_INFOFRAME_TYPE_SPD, 3806 &pipe_config->infoframes.spd); 3807 intel_read_infoframe(encoder, pipe_config, 3808 HDMI_INFOFRAME_TYPE_VENDOR, 3809 &pipe_config->infoframes.hdmi); 3810 intel_read_infoframe(encoder, pipe_config, 3811 HDMI_INFOFRAME_TYPE_DRM, 3812 &pipe_config->infoframes.drm); 3813 3814 if (DISPLAY_VER(dev_priv) >= 8) 3815 bdw_get_trans_port_sync_config(pipe_config); 3816 3817 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 3818 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 3819 3820 intel_psr_get_config(encoder, pipe_config); 3821 3822 intel_audio_codec_get_config(encoder, pipe_config); 3823 } 3824 3825 void intel_ddi_get_clock(struct intel_encoder *encoder, 3826 struct intel_crtc_state *crtc_state, 3827 struct intel_shared_dpll *pll) 3828 { 3829 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3830 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3831 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3832 bool pll_active; 3833 3834 if (drm_WARN_ON(&i915->drm, !pll)) 3835 return; 3836 3837 port_dpll->pll = pll; 3838 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3839 drm_WARN_ON(&i915->drm, !pll_active); 3840 3841 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3842 3843 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3844 &crtc_state->dpll_hw_state); 3845 } 3846 3847 static void mtl_ddi_get_config(struct intel_encoder *encoder, 3848 struct intel_crtc_state *crtc_state) 3849 { 3850 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3851 enum phy phy = intel_port_to_phy(i915, encoder->port); 3852 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3853 3854 if (intel_tc_port_in_tbt_alt_mode(dig_port)) { 3855 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 3856 } else if (intel_is_c10phy(i915, phy)) { 3857 intel_c10pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c10); 3858 intel_c10pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c10); 3859 crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10); 3860 } else { 3861 intel_c20pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c20); 3862 intel_c20pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c20); 3863 crtc_state->port_clock = intel_c20pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c20); 3864 } 3865 3866 intel_ddi_get_config(encoder, crtc_state); 3867 } 3868 3869 static void dg2_ddi_get_config(struct intel_encoder *encoder, 3870 struct intel_crtc_state *crtc_state) 3871 { 3872 intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state); 3873 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state); 3874 3875 intel_ddi_get_config(encoder, crtc_state); 3876 } 3877 3878 static void adls_ddi_get_config(struct intel_encoder *encoder, 3879 struct intel_crtc_state *crtc_state) 3880 { 3881 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 3882 intel_ddi_get_config(encoder, crtc_state); 3883 } 3884 3885 static void rkl_ddi_get_config(struct intel_encoder *encoder, 3886 struct intel_crtc_state *crtc_state) 3887 { 3888 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 3889 intel_ddi_get_config(encoder, crtc_state); 3890 } 3891 3892 static void dg1_ddi_get_config(struct intel_encoder *encoder, 3893 struct intel_crtc_state *crtc_state) 3894 { 3895 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 3896 intel_ddi_get_config(encoder, crtc_state); 3897 } 3898 3899 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 3900 struct intel_crtc_state *crtc_state) 3901 { 3902 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 3903 intel_ddi_get_config(encoder, crtc_state); 3904 } 3905 3906 static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll) 3907 { 3908 return pll->info->id == DPLL_ID_ICL_TBTPLL; 3909 } 3910 3911 static enum icl_port_dpll_id 3912 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 3913 const struct intel_crtc_state *crtc_state) 3914 { 3915 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3916 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 3917 3918 if (drm_WARN_ON(&i915->drm, !pll)) 3919 return ICL_PORT_DPLL_DEFAULT; 3920 3921 if (icl_ddi_tc_pll_is_tbt(pll)) 3922 return ICL_PORT_DPLL_DEFAULT; 3923 else 3924 return ICL_PORT_DPLL_MG_PHY; 3925 } 3926 3927 enum icl_port_dpll_id 3928 intel_ddi_port_pll_type(struct intel_encoder *encoder, 3929 const struct intel_crtc_state *crtc_state) 3930 { 3931 if (!encoder->port_pll_type) 3932 return ICL_PORT_DPLL_DEFAULT; 3933 3934 return encoder->port_pll_type(encoder, crtc_state); 3935 } 3936 3937 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 3938 struct intel_crtc_state *crtc_state, 3939 struct intel_shared_dpll *pll) 3940 { 3941 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3942 enum icl_port_dpll_id port_dpll_id; 3943 struct icl_port_dpll *port_dpll; 3944 bool pll_active; 3945 3946 if (drm_WARN_ON(&i915->drm, !pll)) 3947 return; 3948 3949 if (icl_ddi_tc_pll_is_tbt(pll)) 3950 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3951 else 3952 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 3953 3954 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3955 3956 port_dpll->pll = pll; 3957 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3958 drm_WARN_ON(&i915->drm, !pll_active); 3959 3960 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3961 3962 if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll)) 3963 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 3964 else 3965 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3966 &crtc_state->dpll_hw_state); 3967 } 3968 3969 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 3970 struct intel_crtc_state *crtc_state) 3971 { 3972 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 3973 intel_ddi_get_config(encoder, crtc_state); 3974 } 3975 3976 static void bxt_ddi_get_config(struct intel_encoder *encoder, 3977 struct intel_crtc_state *crtc_state) 3978 { 3979 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 3980 intel_ddi_get_config(encoder, crtc_state); 3981 } 3982 3983 static void skl_ddi_get_config(struct intel_encoder *encoder, 3984 struct intel_crtc_state *crtc_state) 3985 { 3986 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 3987 intel_ddi_get_config(encoder, crtc_state); 3988 } 3989 3990 void hsw_ddi_get_config(struct intel_encoder *encoder, 3991 struct intel_crtc_state *crtc_state) 3992 { 3993 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 3994 intel_ddi_get_config(encoder, crtc_state); 3995 } 3996 3997 static void intel_ddi_sync_state(struct intel_encoder *encoder, 3998 const struct intel_crtc_state *crtc_state) 3999 { 4000 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4001 enum phy phy = intel_port_to_phy(i915, encoder->port); 4002 4003 if (intel_phy_is_tc(i915, phy)) 4004 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4005 crtc_state); 4006 4007 if (crtc_state && intel_crtc_has_dp_encoder(crtc_state)) 4008 intel_dp_sync_state(encoder, crtc_state); 4009 } 4010 4011 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4012 struct intel_crtc_state *crtc_state) 4013 { 4014 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4015 enum phy phy = intel_port_to_phy(i915, encoder->port); 4016 bool fastset = true; 4017 4018 if (intel_phy_is_tc(i915, phy)) { 4019 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4020 encoder->base.base.id, encoder->base.name); 4021 crtc_state->uapi.mode_changed = true; 4022 fastset = false; 4023 } 4024 4025 if (intel_crtc_has_dp_encoder(crtc_state) && 4026 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4027 fastset = false; 4028 4029 return fastset; 4030 } 4031 4032 static enum intel_output_type 4033 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4034 struct intel_crtc_state *crtc_state, 4035 struct drm_connector_state *conn_state) 4036 { 4037 switch (conn_state->connector->connector_type) { 4038 case DRM_MODE_CONNECTOR_HDMIA: 4039 return INTEL_OUTPUT_HDMI; 4040 case DRM_MODE_CONNECTOR_eDP: 4041 return INTEL_OUTPUT_EDP; 4042 case DRM_MODE_CONNECTOR_DisplayPort: 4043 return INTEL_OUTPUT_DP; 4044 default: 4045 MISSING_CASE(conn_state->connector->connector_type); 4046 return INTEL_OUTPUT_UNUSED; 4047 } 4048 } 4049 4050 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4051 struct intel_crtc_state *pipe_config, 4052 struct drm_connector_state *conn_state) 4053 { 4054 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4055 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4056 enum port port = encoder->port; 4057 int ret; 4058 4059 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 4060 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4061 4062 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4063 pipe_config->has_hdmi_sink = 4064 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4065 4066 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4067 } else { 4068 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4069 } 4070 4071 if (ret) 4072 return ret; 4073 4074 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4075 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4076 pipe_config->pch_pfit.force_thru = 4077 pipe_config->pch_pfit.enabled || 4078 pipe_config->crc_enabled; 4079 4080 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4081 pipe_config->lane_lat_optim_mask = 4082 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4083 4084 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 4085 4086 return 0; 4087 } 4088 4089 static bool mode_equal(const struct drm_display_mode *mode1, 4090 const struct drm_display_mode *mode2) 4091 { 4092 return drm_mode_match(mode1, mode2, 4093 DRM_MODE_MATCH_TIMINGS | 4094 DRM_MODE_MATCH_FLAGS | 4095 DRM_MODE_MATCH_3D_FLAGS) && 4096 mode1->clock == mode2->clock; /* we want an exact match */ 4097 } 4098 4099 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4100 const struct intel_link_m_n *m_n_2) 4101 { 4102 return m_n_1->tu == m_n_2->tu && 4103 m_n_1->data_m == m_n_2->data_m && 4104 m_n_1->data_n == m_n_2->data_n && 4105 m_n_1->link_m == m_n_2->link_m && 4106 m_n_1->link_n == m_n_2->link_n; 4107 } 4108 4109 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4110 const struct intel_crtc_state *crtc_state2) 4111 { 4112 return crtc_state1->hw.active && crtc_state2->hw.active && 4113 crtc_state1->output_types == crtc_state2->output_types && 4114 crtc_state1->output_format == crtc_state2->output_format && 4115 crtc_state1->lane_count == crtc_state2->lane_count && 4116 crtc_state1->port_clock == crtc_state2->port_clock && 4117 mode_equal(&crtc_state1->hw.adjusted_mode, 4118 &crtc_state2->hw.adjusted_mode) && 4119 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4120 } 4121 4122 static u8 4123 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4124 int tile_group_id) 4125 { 4126 struct drm_connector *connector; 4127 const struct drm_connector_state *conn_state; 4128 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 4129 struct intel_atomic_state *state = 4130 to_intel_atomic_state(ref_crtc_state->uapi.state); 4131 u8 transcoders = 0; 4132 int i; 4133 4134 /* 4135 * We don't enable port sync on BDW due to missing w/as and 4136 * due to not having adjusted the modeset sequence appropriately. 4137 */ 4138 if (DISPLAY_VER(dev_priv) < 9) 4139 return 0; 4140 4141 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4142 return 0; 4143 4144 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4145 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4146 const struct intel_crtc_state *crtc_state; 4147 4148 if (!crtc) 4149 continue; 4150 4151 if (!connector->has_tile || 4152 connector->tile_group->id != 4153 tile_group_id) 4154 continue; 4155 crtc_state = intel_atomic_get_new_crtc_state(state, 4156 crtc); 4157 if (!crtcs_port_sync_compatible(ref_crtc_state, 4158 crtc_state)) 4159 continue; 4160 transcoders |= BIT(crtc_state->cpu_transcoder); 4161 } 4162 4163 return transcoders; 4164 } 4165 4166 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4167 struct intel_crtc_state *crtc_state, 4168 struct drm_connector_state *conn_state) 4169 { 4170 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4171 struct drm_connector *connector = conn_state->connector; 4172 u8 port_sync_transcoders = 0; 4173 4174 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]", 4175 encoder->base.base.id, encoder->base.name, 4176 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4177 4178 if (connector->has_tile) 4179 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4180 connector->tile_group->id); 4181 4182 /* 4183 * EDP Transcoders cannot be ensalved 4184 * make them a master always when present 4185 */ 4186 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4187 crtc_state->master_transcoder = TRANSCODER_EDP; 4188 else 4189 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4190 4191 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4192 crtc_state->master_transcoder = INVALID_TRANSCODER; 4193 crtc_state->sync_mode_slaves_mask = 4194 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4195 } 4196 4197 return 0; 4198 } 4199 4200 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4201 { 4202 struct drm_i915_private *i915 = to_i915(encoder->dev); 4203 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4204 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 4205 4206 intel_dp_encoder_flush_work(encoder); 4207 if (intel_phy_is_tc(i915, phy)) 4208 intel_tc_port_cleanup(dig_port); 4209 intel_display_power_flush_work(i915); 4210 4211 drm_encoder_cleanup(encoder); 4212 kfree(dig_port->hdcp_port_data.streams); 4213 kfree(dig_port); 4214 } 4215 4216 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4217 { 4218 struct drm_i915_private *i915 = to_i915(encoder->dev); 4219 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4220 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4221 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 4222 4223 intel_dp->reset_link_params = true; 4224 4225 intel_pps_encoder_reset(intel_dp); 4226 4227 if (intel_phy_is_tc(i915, phy)) 4228 intel_tc_port_init_mode(dig_port); 4229 } 4230 4231 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4232 { 4233 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4234 4235 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4236 4237 return 0; 4238 } 4239 4240 static const struct drm_encoder_funcs intel_ddi_funcs = { 4241 .reset = intel_ddi_encoder_reset, 4242 .destroy = intel_ddi_encoder_destroy, 4243 .late_register = intel_ddi_encoder_late_register, 4244 }; 4245 4246 static struct intel_connector * 4247 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4248 { 4249 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 4250 struct intel_connector *connector; 4251 enum port port = dig_port->base.port; 4252 4253 connector = intel_connector_alloc(); 4254 if (!connector) 4255 return NULL; 4256 4257 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4258 if (DISPLAY_VER(i915) >= 14) 4259 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4260 else 4261 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4262 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4263 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4264 4265 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4266 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4267 4268 if (!intel_dp_init_connector(dig_port, connector)) { 4269 kfree(connector); 4270 return NULL; 4271 } 4272 4273 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4274 struct drm_device *dev = dig_port->base.base.dev; 4275 struct drm_privacy_screen *privacy_screen; 4276 4277 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); 4278 if (!IS_ERR(privacy_screen)) { 4279 drm_connector_attach_privacy_screen_provider(&connector->base, 4280 privacy_screen); 4281 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4282 drm_warn(dev, "Error getting privacy-screen\n"); 4283 } 4284 } 4285 4286 return connector; 4287 } 4288 4289 static int modeset_pipe(struct drm_crtc *crtc, 4290 struct drm_modeset_acquire_ctx *ctx) 4291 { 4292 struct drm_atomic_state *state; 4293 struct drm_crtc_state *crtc_state; 4294 int ret; 4295 4296 state = drm_atomic_state_alloc(crtc->dev); 4297 if (!state) 4298 return -ENOMEM; 4299 4300 state->acquire_ctx = ctx; 4301 to_intel_atomic_state(state)->internal = true; 4302 4303 crtc_state = drm_atomic_get_crtc_state(state, crtc); 4304 if (IS_ERR(crtc_state)) { 4305 ret = PTR_ERR(crtc_state); 4306 goto out; 4307 } 4308 4309 crtc_state->connectors_changed = true; 4310 4311 ret = drm_atomic_commit(state); 4312 out: 4313 drm_atomic_state_put(state); 4314 4315 return ret; 4316 } 4317 4318 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4319 struct drm_modeset_acquire_ctx *ctx) 4320 { 4321 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4322 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4323 struct intel_connector *connector = hdmi->attached_connector; 4324 struct i2c_adapter *adapter = 4325 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 4326 struct drm_connector_state *conn_state; 4327 struct intel_crtc_state *crtc_state; 4328 struct intel_crtc *crtc; 4329 u8 config; 4330 int ret; 4331 4332 if (!connector || connector->base.status != connector_status_connected) 4333 return 0; 4334 4335 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4336 ctx); 4337 if (ret) 4338 return ret; 4339 4340 conn_state = connector->base.state; 4341 4342 crtc = to_intel_crtc(conn_state->crtc); 4343 if (!crtc) 4344 return 0; 4345 4346 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4347 if (ret) 4348 return ret; 4349 4350 crtc_state = to_intel_crtc_state(crtc->base.state); 4351 4352 drm_WARN_ON(&dev_priv->drm, 4353 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4354 4355 if (!crtc_state->hw.active) 4356 return 0; 4357 4358 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4359 !crtc_state->hdmi_scrambling) 4360 return 0; 4361 4362 if (conn_state->commit && 4363 !try_wait_for_completion(&conn_state->commit->hw_done)) 4364 return 0; 4365 4366 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 4367 if (ret < 0) { 4368 drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4369 connector->base.base.id, connector->base.name, ret); 4370 return 0; 4371 } 4372 4373 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4374 crtc_state->hdmi_high_tmds_clock_ratio && 4375 !!(config & SCDC_SCRAMBLING_ENABLE) == 4376 crtc_state->hdmi_scrambling) 4377 return 0; 4378 4379 /* 4380 * HDMI 2.0 says that one should not send scrambled data 4381 * prior to configuring the sink scrambling, and that 4382 * TMDS clock/data transmission should be suspended when 4383 * changing the TMDS clock rate in the sink. So let's 4384 * just do a full modeset here, even though some sinks 4385 * would be perfectly happy if were to just reconfigure 4386 * the SCDC settings on the fly. 4387 */ 4388 return modeset_pipe(&crtc->base, ctx); 4389 } 4390 4391 static enum intel_hotplug_state 4392 intel_ddi_hotplug(struct intel_encoder *encoder, 4393 struct intel_connector *connector) 4394 { 4395 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4396 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4397 struct intel_dp *intel_dp = &dig_port->dp; 4398 enum phy phy = intel_port_to_phy(i915, encoder->port); 4399 bool is_tc = intel_phy_is_tc(i915, phy); 4400 struct drm_modeset_acquire_ctx ctx; 4401 enum intel_hotplug_state state; 4402 int ret; 4403 4404 if (intel_dp->compliance.test_active && 4405 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 4406 intel_dp_phy_test(encoder); 4407 /* just do the PHY test and nothing else */ 4408 return INTEL_HOTPLUG_UNCHANGED; 4409 } 4410 4411 state = intel_encoder_hotplug(encoder, connector); 4412 4413 if (!intel_tc_port_link_reset(dig_port)) { 4414 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) { 4415 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4416 ret = intel_hdmi_reset_link(encoder, &ctx); 4417 else 4418 ret = intel_dp_retrain_link(encoder, &ctx); 4419 } 4420 4421 drm_WARN_ON(encoder->base.dev, ret); 4422 } 4423 4424 /* 4425 * Unpowered type-c dongles can take some time to boot and be 4426 * responsible, so here giving some time to those dongles to power up 4427 * and then retrying the probe. 4428 * 4429 * On many platforms the HDMI live state signal is known to be 4430 * unreliable, so we can't use it to detect if a sink is connected or 4431 * not. Instead we detect if it's connected based on whether we can 4432 * read the EDID or not. That in turn has a problem during disconnect, 4433 * since the HPD interrupt may be raised before the DDC lines get 4434 * disconnected (due to how the required length of DDC vs. HPD 4435 * connector pins are specified) and so we'll still be able to get a 4436 * valid EDID. To solve this schedule another detection cycle if this 4437 * time around we didn't detect any change in the sink's connection 4438 * status. 4439 * 4440 * Type-c connectors which get their HPD signal deasserted then 4441 * reasserted, without unplugging/replugging the sink from the 4442 * connector, introduce a delay until the AUX channel communication 4443 * becomes functional. Retry the detection for 5 seconds on type-c 4444 * connectors to account for this delay. 4445 */ 4446 if (state == INTEL_HOTPLUG_UNCHANGED && 4447 connector->hotplug_retries < (is_tc ? 5 : 1) && 4448 !dig_port->dp.is_mst) 4449 state = INTEL_HOTPLUG_RETRY; 4450 4451 return state; 4452 } 4453 4454 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4455 { 4456 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4457 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; 4458 4459 return intel_de_read(dev_priv, SDEISR) & bit; 4460 } 4461 4462 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4463 { 4464 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4465 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4466 4467 return intel_de_read(dev_priv, DEISR) & bit; 4468 } 4469 4470 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4471 { 4472 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4473 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4474 4475 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4476 } 4477 4478 static struct intel_connector * 4479 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4480 { 4481 struct intel_connector *connector; 4482 enum port port = dig_port->base.port; 4483 4484 connector = intel_connector_alloc(); 4485 if (!connector) 4486 return NULL; 4487 4488 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4489 intel_hdmi_init_connector(dig_port, connector); 4490 4491 return connector; 4492 } 4493 4494 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4495 { 4496 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4497 4498 if (dig_port->base.port != PORT_A) 4499 return false; 4500 4501 if (dig_port->saved_port_bits & DDI_A_4_LANES) 4502 return false; 4503 4504 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4505 * supported configuration 4506 */ 4507 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4508 return true; 4509 4510 return false; 4511 } 4512 4513 static int 4514 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4515 { 4516 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4517 enum port port = dig_port->base.port; 4518 int max_lanes = 4; 4519 4520 if (DISPLAY_VER(dev_priv) >= 11) 4521 return max_lanes; 4522 4523 if (port == PORT_A || port == PORT_E) { 4524 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4525 max_lanes = port == PORT_A ? 4 : 0; 4526 else 4527 /* Both A and E share 2 lanes */ 4528 max_lanes = 2; 4529 } 4530 4531 /* 4532 * Some BIOS might fail to set this bit on port A if eDP 4533 * wasn't lit up at boot. Force this bit set when needed 4534 * so we use the proper lane count for our calculations. 4535 */ 4536 if (intel_ddi_a_force_4_lanes(dig_port)) { 4537 drm_dbg_kms(&dev_priv->drm, 4538 "Forcing DDI_A_4_LANES for port A\n"); 4539 dig_port->saved_port_bits |= DDI_A_4_LANES; 4540 max_lanes = 4; 4541 } 4542 4543 return max_lanes; 4544 } 4545 4546 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4547 enum port port) 4548 { 4549 if (port >= PORT_D_XELPD) 4550 return HPD_PORT_D + port - PORT_D_XELPD; 4551 else if (port >= PORT_TC1) 4552 return HPD_PORT_TC1 + port - PORT_TC1; 4553 else 4554 return HPD_PORT_A + port - PORT_A; 4555 } 4556 4557 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4558 enum port port) 4559 { 4560 if (port >= PORT_TC1) 4561 return HPD_PORT_C + port - PORT_TC1; 4562 else 4563 return HPD_PORT_A + port - PORT_A; 4564 } 4565 4566 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4567 enum port port) 4568 { 4569 if (port >= PORT_TC1) 4570 return HPD_PORT_TC1 + port - PORT_TC1; 4571 else 4572 return HPD_PORT_A + port - PORT_A; 4573 } 4574 4575 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4576 enum port port) 4577 { 4578 if (HAS_PCH_TGP(dev_priv)) 4579 return tgl_hpd_pin(dev_priv, port); 4580 4581 if (port >= PORT_TC1) 4582 return HPD_PORT_C + port - PORT_TC1; 4583 else 4584 return HPD_PORT_A + port - PORT_A; 4585 } 4586 4587 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4588 enum port port) 4589 { 4590 if (port >= PORT_C) 4591 return HPD_PORT_TC1 + port - PORT_C; 4592 else 4593 return HPD_PORT_A + port - PORT_A; 4594 } 4595 4596 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4597 enum port port) 4598 { 4599 if (port == PORT_D) 4600 return HPD_PORT_A; 4601 4602 if (HAS_PCH_TGP(dev_priv)) 4603 return icl_hpd_pin(dev_priv, port); 4604 4605 return HPD_PORT_A + port - PORT_A; 4606 } 4607 4608 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4609 { 4610 if (HAS_PCH_TGP(dev_priv)) 4611 return icl_hpd_pin(dev_priv, port); 4612 4613 return HPD_PORT_A + port - PORT_A; 4614 } 4615 4616 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4617 { 4618 if (DISPLAY_VER(i915) >= 12) 4619 return port >= PORT_TC1; 4620 else if (DISPLAY_VER(i915) >= 11) 4621 return port >= PORT_C; 4622 else 4623 return false; 4624 } 4625 4626 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4627 { 4628 intel_dp_encoder_suspend(encoder); 4629 } 4630 4631 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 4632 { 4633 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4634 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4635 4636 intel_tc_port_suspend(dig_port); 4637 } 4638 4639 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 4640 { 4641 intel_dp_encoder_shutdown(encoder); 4642 intel_hdmi_encoder_shutdown(encoder); 4643 } 4644 4645 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 4646 { 4647 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4648 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4649 4650 intel_tc_port_cleanup(dig_port); 4651 } 4652 4653 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 4654 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 4655 4656 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 4657 { 4658 struct intel_digital_port *dig_port; 4659 struct intel_encoder *encoder; 4660 const struct intel_bios_encoder_data *devdata; 4661 bool init_hdmi, init_dp; 4662 enum phy phy = intel_port_to_phy(dev_priv, port); 4663 4664 /* 4665 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 4666 * have taken over some of the PHYs and made them unavailable to the 4667 * driver. In that case we should skip initializing the corresponding 4668 * outputs. 4669 */ 4670 if (intel_hti_uses_phy(dev_priv, phy)) { 4671 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 4672 port_name(port), phy_name(phy)); 4673 return; 4674 } 4675 4676 devdata = intel_bios_encoder_data_lookup(dev_priv, port); 4677 if (!devdata) { 4678 drm_dbg_kms(&dev_priv->drm, 4679 "VBT says port %c is not present\n", 4680 port_name(port)); 4681 return; 4682 } 4683 4684 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 4685 intel_bios_encoder_supports_hdmi(devdata); 4686 init_dp = intel_bios_encoder_supports_dp(devdata); 4687 4688 if (intel_bios_encoder_is_lspcon(devdata)) { 4689 /* 4690 * Lspcon device needs to be driven with DP connector 4691 * with special detection sequence. So make sure DP 4692 * is initialized before lspcon. 4693 */ 4694 init_dp = true; 4695 init_hdmi = false; 4696 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4697 port_name(port)); 4698 } 4699 4700 if (!init_dp && !init_hdmi) { 4701 drm_dbg_kms(&dev_priv->drm, 4702 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4703 port_name(port)); 4704 return; 4705 } 4706 4707 if (intel_phy_is_snps(dev_priv, phy) && 4708 dev_priv->display.snps.phy_failed_calibration & BIT(phy)) { 4709 drm_dbg_kms(&dev_priv->drm, 4710 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 4711 phy_name(phy)); 4712 } 4713 4714 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 4715 if (!dig_port) 4716 return; 4717 4718 encoder = &dig_port->base; 4719 encoder->devdata = devdata; 4720 4721 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 4722 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4723 DRM_MODE_ENCODER_TMDS, 4724 "DDI %c/PHY %c", 4725 port_name(port - PORT_D_XELPD + PORT_D), 4726 phy_name(phy)); 4727 } else if (DISPLAY_VER(dev_priv) >= 12) { 4728 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4729 4730 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4731 DRM_MODE_ENCODER_TMDS, 4732 "DDI %s%c/PHY %s%c", 4733 port >= PORT_TC1 ? "TC" : "", 4734 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 4735 tc_port != TC_PORT_NONE ? "TC" : "", 4736 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4737 } else if (DISPLAY_VER(dev_priv) >= 11) { 4738 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4739 4740 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4741 DRM_MODE_ENCODER_TMDS, 4742 "DDI %c%s/PHY %s%c", 4743 port_name(port), 4744 port >= PORT_C ? " (TC)" : "", 4745 tc_port != TC_PORT_NONE ? "TC" : "", 4746 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4747 } else { 4748 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4749 DRM_MODE_ENCODER_TMDS, 4750 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 4751 } 4752 4753 mutex_init(&dig_port->hdcp_mutex); 4754 dig_port->num_hdcp_streams = 0; 4755 4756 encoder->hotplug = intel_ddi_hotplug; 4757 encoder->compute_output_type = intel_ddi_compute_output_type; 4758 encoder->compute_config = intel_ddi_compute_config; 4759 encoder->compute_config_late = intel_ddi_compute_config_late; 4760 encoder->enable = intel_enable_ddi; 4761 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4762 encoder->pre_enable = intel_ddi_pre_enable; 4763 encoder->disable = intel_disable_ddi; 4764 encoder->post_pll_disable = intel_ddi_post_pll_disable; 4765 encoder->post_disable = intel_ddi_post_disable; 4766 encoder->update_pipe = intel_ddi_update_pipe; 4767 encoder->get_hw_state = intel_ddi_get_hw_state; 4768 encoder->sync_state = intel_ddi_sync_state; 4769 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 4770 encoder->suspend = intel_ddi_encoder_suspend; 4771 encoder->shutdown = intel_ddi_encoder_shutdown; 4772 encoder->get_power_domains = intel_ddi_get_power_domains; 4773 4774 encoder->type = INTEL_OUTPUT_DDI; 4775 encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 4776 encoder->port = port; 4777 encoder->cloneable = 0; 4778 encoder->pipe_mask = ~0; 4779 4780 if (DISPLAY_VER(dev_priv) >= 14) { 4781 encoder->enable_clock = intel_mtl_pll_enable; 4782 encoder->disable_clock = intel_mtl_pll_disable; 4783 encoder->port_pll_type = intel_mtl_port_pll_type; 4784 encoder->get_config = mtl_ddi_get_config; 4785 } else if (IS_DG2(dev_priv)) { 4786 encoder->enable_clock = intel_mpllb_enable; 4787 encoder->disable_clock = intel_mpllb_disable; 4788 encoder->get_config = dg2_ddi_get_config; 4789 } else if (IS_ALDERLAKE_S(dev_priv)) { 4790 encoder->enable_clock = adls_ddi_enable_clock; 4791 encoder->disable_clock = adls_ddi_disable_clock; 4792 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 4793 encoder->get_config = adls_ddi_get_config; 4794 } else if (IS_ROCKETLAKE(dev_priv)) { 4795 encoder->enable_clock = rkl_ddi_enable_clock; 4796 encoder->disable_clock = rkl_ddi_disable_clock; 4797 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 4798 encoder->get_config = rkl_ddi_get_config; 4799 } else if (IS_DG1(dev_priv)) { 4800 encoder->enable_clock = dg1_ddi_enable_clock; 4801 encoder->disable_clock = dg1_ddi_disable_clock; 4802 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 4803 encoder->get_config = dg1_ddi_get_config; 4804 } else if (IS_JSL_EHL(dev_priv)) { 4805 if (intel_ddi_is_tc(dev_priv, port)) { 4806 encoder->enable_clock = jsl_ddi_tc_enable_clock; 4807 encoder->disable_clock = jsl_ddi_tc_disable_clock; 4808 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 4809 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 4810 encoder->get_config = icl_ddi_combo_get_config; 4811 } else { 4812 encoder->enable_clock = icl_ddi_combo_enable_clock; 4813 encoder->disable_clock = icl_ddi_combo_disable_clock; 4814 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4815 encoder->get_config = icl_ddi_combo_get_config; 4816 } 4817 } else if (DISPLAY_VER(dev_priv) >= 11) { 4818 if (intel_ddi_is_tc(dev_priv, port)) { 4819 encoder->enable_clock = icl_ddi_tc_enable_clock; 4820 encoder->disable_clock = icl_ddi_tc_disable_clock; 4821 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 4822 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 4823 encoder->get_config = icl_ddi_tc_get_config; 4824 } else { 4825 encoder->enable_clock = icl_ddi_combo_enable_clock; 4826 encoder->disable_clock = icl_ddi_combo_disable_clock; 4827 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4828 encoder->get_config = icl_ddi_combo_get_config; 4829 } 4830 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4831 /* BXT/GLK have fixed PLL->port mapping */ 4832 encoder->get_config = bxt_ddi_get_config; 4833 } else if (DISPLAY_VER(dev_priv) == 9) { 4834 encoder->enable_clock = skl_ddi_enable_clock; 4835 encoder->disable_clock = skl_ddi_disable_clock; 4836 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 4837 encoder->get_config = skl_ddi_get_config; 4838 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4839 encoder->enable_clock = hsw_ddi_enable_clock; 4840 encoder->disable_clock = hsw_ddi_disable_clock; 4841 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 4842 encoder->get_config = hsw_ddi_get_config; 4843 } 4844 4845 if (DISPLAY_VER(dev_priv) >= 14) { 4846 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 4847 } else if (IS_DG2(dev_priv)) { 4848 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 4849 } else if (DISPLAY_VER(dev_priv) >= 12) { 4850 if (intel_phy_is_combo(dev_priv, phy)) 4851 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 4852 else 4853 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 4854 } else if (DISPLAY_VER(dev_priv) >= 11) { 4855 if (intel_phy_is_combo(dev_priv, phy)) 4856 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 4857 else 4858 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 4859 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4860 encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels; 4861 } else { 4862 encoder->set_signal_levels = hsw_set_signal_levels; 4863 } 4864 4865 intel_ddi_buf_trans_init(encoder); 4866 4867 if (DISPLAY_VER(dev_priv) >= 13) 4868 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 4869 else if (IS_DG1(dev_priv)) 4870 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 4871 else if (IS_ROCKETLAKE(dev_priv)) 4872 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 4873 else if (DISPLAY_VER(dev_priv) >= 12) 4874 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 4875 else if (IS_JSL_EHL(dev_priv)) 4876 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 4877 else if (DISPLAY_VER(dev_priv) == 11) 4878 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 4879 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 4880 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 4881 else 4882 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 4883 4884 if (DISPLAY_VER(dev_priv) >= 11) 4885 dig_port->saved_port_bits = 4886 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4887 & DDI_BUF_PORT_REVERSAL; 4888 else 4889 dig_port->saved_port_bits = 4890 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4891 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 4892 4893 if (intel_bios_encoder_lane_reversal(devdata)) 4894 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; 4895 4896 dig_port->dp.output_reg = INVALID_MMIO_REG; 4897 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 4898 dig_port->aux_ch = intel_dp_aux_ch(encoder); 4899 4900 if (intel_phy_is_tc(dev_priv, phy)) { 4901 bool is_legacy = 4902 !intel_bios_encoder_supports_typec_usb(devdata) && 4903 !intel_bios_encoder_supports_tbt(devdata); 4904 4905 if (!is_legacy && init_hdmi) { 4906 is_legacy = !init_dp; 4907 4908 drm_dbg_kms(&dev_priv->drm, 4909 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 4910 port_name(port), 4911 str_yes_no(init_dp), 4912 is_legacy ? "legacy" : "non-legacy"); 4913 } 4914 4915 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 4916 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 4917 4918 if (intel_tc_port_init(dig_port, is_legacy) < 0) 4919 goto err; 4920 } 4921 4922 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 4923 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port); 4924 4925 if (DISPLAY_VER(dev_priv) >= 11) { 4926 if (intel_phy_is_tc(dev_priv, phy)) 4927 dig_port->connected = intel_tc_port_connected; 4928 else 4929 dig_port->connected = lpt_digital_port_connected; 4930 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4931 dig_port->connected = bdw_digital_port_connected; 4932 } else if (DISPLAY_VER(dev_priv) == 9) { 4933 dig_port->connected = lpt_digital_port_connected; 4934 } else if (IS_BROADWELL(dev_priv)) { 4935 if (port == PORT_A) 4936 dig_port->connected = bdw_digital_port_connected; 4937 else 4938 dig_port->connected = lpt_digital_port_connected; 4939 } else if (IS_HASWELL(dev_priv)) { 4940 if (port == PORT_A) 4941 dig_port->connected = hsw_digital_port_connected; 4942 else 4943 dig_port->connected = lpt_digital_port_connected; 4944 } 4945 4946 intel_infoframe_init(dig_port); 4947 4948 if (init_dp) { 4949 if (!intel_ddi_init_dp_connector(dig_port)) 4950 goto err; 4951 4952 dig_port->hpd_pulse = intel_dp_hpd_pulse; 4953 4954 if (dig_port->dp.mso_link_count) 4955 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); 4956 } 4957 4958 /* 4959 * In theory we don't need the encoder->type check, 4960 * but leave it just in case we have some really bad VBTs... 4961 */ 4962 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 4963 if (!intel_ddi_init_hdmi_connector(dig_port)) 4964 goto err; 4965 } 4966 4967 return; 4968 4969 err: 4970 drm_encoder_cleanup(&encoder->base); 4971 kfree(dig_port); 4972 } 4973