1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 #include <linux/kernel.h> 6 7 #include <drm/drm_atomic_helper.h> 8 #include <drm/drm_atomic_uapi.h> 9 #include <drm/drm_damage_helper.h> 10 #include <drm/drm_plane_helper.h> 11 #include <drm/drm_fourcc.h> 12 13 #include "intel_atomic.h" 14 #include "intel_atomic_plane.h" 15 #include "intel_cursor.h" 16 #include "intel_de.h" 17 #include "intel_display_types.h" 18 #include "intel_display.h" 19 #include "intel_fb.h" 20 21 #include "intel_frontbuffer.h" 22 #include "intel_pm.h" 23 #include "intel_psr.h" 24 #include "intel_sprite.h" 25 26 /* Cursor formats */ 27 static const u32 intel_cursor_formats[] = { 28 DRM_FORMAT_ARGB8888, 29 }; 30 31 static const u64 cursor_format_modifiers[] = { 32 DRM_FORMAT_MOD_LINEAR, 33 DRM_FORMAT_MOD_INVALID 34 }; 35 36 static u32 intel_cursor_base(const struct intel_plane_state *plane_state) 37 { 38 struct drm_i915_private *dev_priv = 39 to_i915(plane_state->uapi.plane->dev); 40 const struct drm_framebuffer *fb = plane_state->hw.fb; 41 const struct drm_i915_gem_object *obj = intel_fb_obj(fb); 42 u32 base; 43 44 if (INTEL_INFO(dev_priv)->display.cursor_needs_physical) 45 base = sg_dma_address(obj->mm.pages->sgl); 46 else 47 base = intel_plane_ggtt_offset(plane_state); 48 49 return base + plane_state->view.color_plane[0].offset; 50 } 51 52 static u32 intel_cursor_position(const struct intel_plane_state *plane_state) 53 { 54 int x = plane_state->uapi.dst.x1; 55 int y = plane_state->uapi.dst.y1; 56 u32 pos = 0; 57 58 if (x < 0) { 59 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; 60 x = -x; 61 } 62 pos |= x << CURSOR_X_SHIFT; 63 64 if (y < 0) { 65 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; 66 y = -y; 67 } 68 pos |= y << CURSOR_Y_SHIFT; 69 70 return pos; 71 } 72 73 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state) 74 { 75 const struct drm_mode_config *config = 76 &plane_state->uapi.plane->dev->mode_config; 77 int width = drm_rect_width(&plane_state->uapi.dst); 78 int height = drm_rect_height(&plane_state->uapi.dst); 79 80 return width > 0 && width <= config->cursor_width && 81 height > 0 && height <= config->cursor_height; 82 } 83 84 static int intel_cursor_check_surface(struct intel_plane_state *plane_state) 85 { 86 struct drm_i915_private *dev_priv = 87 to_i915(plane_state->uapi.plane->dev); 88 unsigned int rotation = plane_state->hw.rotation; 89 int src_x, src_y; 90 u32 offset; 91 int ret; 92 93 ret = intel_plane_compute_gtt(plane_state); 94 if (ret) 95 return ret; 96 97 if (!plane_state->uapi.visible) 98 return 0; 99 100 src_x = plane_state->uapi.src.x1 >> 16; 101 src_y = plane_state->uapi.src.y1 >> 16; 102 103 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); 104 offset = intel_plane_compute_aligned_offset(&src_x, &src_y, 105 plane_state, 0); 106 107 if (src_x != 0 || src_y != 0) { 108 drm_dbg_kms(&dev_priv->drm, 109 "Arbitrary cursor panning not supported\n"); 110 return -EINVAL; 111 } 112 113 /* 114 * Put the final coordinates back so that the src 115 * coordinate checks will see the right values. 116 */ 117 drm_rect_translate_to(&plane_state->uapi.src, 118 src_x << 16, src_y << 16); 119 120 /* ILK+ do this automagically in hardware */ 121 if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) { 122 const struct drm_framebuffer *fb = plane_state->hw.fb; 123 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 124 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 125 126 offset += (src_h * src_w - 1) * fb->format->cpp[0]; 127 } 128 129 plane_state->view.color_plane[0].offset = offset; 130 plane_state->view.color_plane[0].x = src_x; 131 plane_state->view.color_plane[0].y = src_y; 132 133 return 0; 134 } 135 136 static int intel_check_cursor(struct intel_crtc_state *crtc_state, 137 struct intel_plane_state *plane_state) 138 { 139 const struct drm_framebuffer *fb = plane_state->hw.fb; 140 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 141 const struct drm_rect src = plane_state->uapi.src; 142 const struct drm_rect dst = plane_state->uapi.dst; 143 int ret; 144 145 if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) { 146 drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n"); 147 return -EINVAL; 148 } 149 150 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, 151 DRM_PLANE_HELPER_NO_SCALING, 152 DRM_PLANE_HELPER_NO_SCALING, 153 true); 154 if (ret) 155 return ret; 156 157 /* Use the unclipped src/dst rectangles, which we program to hw */ 158 plane_state->uapi.src = src; 159 plane_state->uapi.dst = dst; 160 161 ret = intel_cursor_check_surface(plane_state); 162 if (ret) 163 return ret; 164 165 if (!plane_state->uapi.visible) 166 return 0; 167 168 ret = intel_plane_check_src_coordinates(plane_state); 169 if (ret) 170 return ret; 171 172 return 0; 173 } 174 175 static unsigned int 176 i845_cursor_max_stride(struct intel_plane *plane, 177 u32 pixel_format, u64 modifier, 178 unsigned int rotation) 179 { 180 return 2048; 181 } 182 183 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) 184 { 185 u32 cntl = 0; 186 187 if (crtc_state->gamma_enable) 188 cntl |= CURSOR_GAMMA_ENABLE; 189 190 return cntl; 191 } 192 193 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state, 194 const struct intel_plane_state *plane_state) 195 { 196 return CURSOR_ENABLE | 197 CURSOR_FORMAT_ARGB | 198 CURSOR_STRIDE(plane_state->view.color_plane[0].stride); 199 } 200 201 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state) 202 { 203 int width = drm_rect_width(&plane_state->uapi.dst); 204 205 /* 206 * 845g/865g are only limited by the width of their cursors, 207 * the height is arbitrary up to the precision of the register. 208 */ 209 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64); 210 } 211 212 static int i845_check_cursor(struct intel_crtc_state *crtc_state, 213 struct intel_plane_state *plane_state) 214 { 215 const struct drm_framebuffer *fb = plane_state->hw.fb; 216 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 217 int ret; 218 219 ret = intel_check_cursor(crtc_state, plane_state); 220 if (ret) 221 return ret; 222 223 /* if we want to turn off the cursor ignore width and height */ 224 if (!fb) 225 return 0; 226 227 /* Check for which cursor types we support */ 228 if (!i845_cursor_size_ok(plane_state)) { 229 drm_dbg_kms(&i915->drm, 230 "Cursor dimension %dx%d not supported\n", 231 drm_rect_width(&plane_state->uapi.dst), 232 drm_rect_height(&plane_state->uapi.dst)); 233 return -EINVAL; 234 } 235 236 drm_WARN_ON(&i915->drm, plane_state->uapi.visible && 237 plane_state->view.color_plane[0].stride != fb->pitches[0]); 238 239 switch (fb->pitches[0]) { 240 case 256: 241 case 512: 242 case 1024: 243 case 2048: 244 break; 245 default: 246 drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n", 247 fb->pitches[0]); 248 return -EINVAL; 249 } 250 251 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state); 252 253 return 0; 254 } 255 256 static void i845_update_cursor(struct intel_plane *plane, 257 const struct intel_crtc_state *crtc_state, 258 const struct intel_plane_state *plane_state) 259 { 260 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 261 u32 cntl = 0, base = 0, pos = 0, size = 0; 262 unsigned long irqflags; 263 264 if (plane_state && plane_state->uapi.visible) { 265 unsigned int width = drm_rect_width(&plane_state->uapi.dst); 266 unsigned int height = drm_rect_height(&plane_state->uapi.dst); 267 268 cntl = plane_state->ctl | 269 i845_cursor_ctl_crtc(crtc_state); 270 271 size = (height << 12) | width; 272 273 base = intel_cursor_base(plane_state); 274 pos = intel_cursor_position(plane_state); 275 } 276 277 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 278 279 /* On these chipsets we can only modify the base/size/stride 280 * whilst the cursor is disabled. 281 */ 282 if (plane->cursor.base != base || 283 plane->cursor.size != size || 284 plane->cursor.cntl != cntl) { 285 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0); 286 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base); 287 intel_de_write_fw(dev_priv, CURSIZE, size); 288 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); 289 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl); 290 291 plane->cursor.base = base; 292 plane->cursor.size = size; 293 plane->cursor.cntl = cntl; 294 } else { 295 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); 296 } 297 298 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 299 } 300 301 static void i845_disable_cursor(struct intel_plane *plane, 302 const struct intel_crtc_state *crtc_state) 303 { 304 i845_update_cursor(plane, crtc_state, NULL); 305 } 306 307 static bool i845_cursor_get_hw_state(struct intel_plane *plane, 308 enum pipe *pipe) 309 { 310 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 311 enum intel_display_power_domain power_domain; 312 intel_wakeref_t wakeref; 313 bool ret; 314 315 power_domain = POWER_DOMAIN_PIPE(PIPE_A); 316 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 317 if (!wakeref) 318 return false; 319 320 ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE; 321 322 *pipe = PIPE_A; 323 324 intel_display_power_put(dev_priv, power_domain, wakeref); 325 326 return ret; 327 } 328 329 static unsigned int 330 i9xx_cursor_max_stride(struct intel_plane *plane, 331 u32 pixel_format, u64 modifier, 332 unsigned int rotation) 333 { 334 return plane->base.dev->mode_config.cursor_width * 4; 335 } 336 337 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) 338 { 339 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 340 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 341 u32 cntl = 0; 342 343 if (DISPLAY_VER(dev_priv) >= 11) 344 return cntl; 345 346 if (crtc_state->gamma_enable) 347 cntl = MCURSOR_GAMMA_ENABLE; 348 349 if (crtc_state->csc_enable) 350 cntl |= MCURSOR_PIPE_CSC_ENABLE; 351 352 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) 353 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe); 354 355 return cntl; 356 } 357 358 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, 359 const struct intel_plane_state *plane_state) 360 { 361 struct drm_i915_private *dev_priv = 362 to_i915(plane_state->uapi.plane->dev); 363 u32 cntl = 0; 364 365 if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) 366 cntl |= MCURSOR_TRICKLE_FEED_DISABLE; 367 368 switch (drm_rect_width(&plane_state->uapi.dst)) { 369 case 64: 370 cntl |= MCURSOR_MODE_64_ARGB_AX; 371 break; 372 case 128: 373 cntl |= MCURSOR_MODE_128_ARGB_AX; 374 break; 375 case 256: 376 cntl |= MCURSOR_MODE_256_ARGB_AX; 377 break; 378 default: 379 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst)); 380 return 0; 381 } 382 383 if (plane_state->hw.rotation & DRM_MODE_ROTATE_180) 384 cntl |= MCURSOR_ROTATE_180; 385 386 return cntl; 387 } 388 389 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state) 390 { 391 struct drm_i915_private *dev_priv = 392 to_i915(plane_state->uapi.plane->dev); 393 int width = drm_rect_width(&plane_state->uapi.dst); 394 int height = drm_rect_height(&plane_state->uapi.dst); 395 396 if (!intel_cursor_size_ok(plane_state)) 397 return false; 398 399 /* Cursor width is limited to a few power-of-two sizes */ 400 switch (width) { 401 case 256: 402 case 128: 403 case 64: 404 break; 405 default: 406 return false; 407 } 408 409 /* 410 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor 411 * height from 8 lines up to the cursor width, when the 412 * cursor is not rotated. Everything else requires square 413 * cursors. 414 */ 415 if (HAS_CUR_FBC(dev_priv) && 416 plane_state->hw.rotation & DRM_MODE_ROTATE_0) { 417 if (height < 8 || height > width) 418 return false; 419 } else { 420 if (height != width) 421 return false; 422 } 423 424 return true; 425 } 426 427 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state, 428 struct intel_plane_state *plane_state) 429 { 430 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 431 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 432 const struct drm_framebuffer *fb = plane_state->hw.fb; 433 enum pipe pipe = plane->pipe; 434 int ret; 435 436 ret = intel_check_cursor(crtc_state, plane_state); 437 if (ret) 438 return ret; 439 440 /* if we want to turn off the cursor ignore width and height */ 441 if (!fb) 442 return 0; 443 444 /* Check for which cursor types we support */ 445 if (!i9xx_cursor_size_ok(plane_state)) { 446 drm_dbg(&dev_priv->drm, 447 "Cursor dimension %dx%d not supported\n", 448 drm_rect_width(&plane_state->uapi.dst), 449 drm_rect_height(&plane_state->uapi.dst)); 450 return -EINVAL; 451 } 452 453 drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible && 454 plane_state->view.color_plane[0].stride != fb->pitches[0]); 455 456 if (fb->pitches[0] != 457 drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) { 458 drm_dbg_kms(&dev_priv->drm, 459 "Invalid cursor stride (%u) (cursor width %d)\n", 460 fb->pitches[0], 461 drm_rect_width(&plane_state->uapi.dst)); 462 return -EINVAL; 463 } 464 465 /* 466 * There's something wrong with the cursor on CHV pipe C. 467 * If it straddles the left edge of the screen then 468 * moving it away from the edge or disabling it often 469 * results in a pipe underrun, and often that can lead to 470 * dead pipe (constant underrun reported, and it scans 471 * out just a solid color). To recover from that, the 472 * display power well must be turned off and on again. 473 * Refuse the put the cursor into that compromised position. 474 */ 475 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C && 476 plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) { 477 drm_dbg_kms(&dev_priv->drm, 478 "CHV cursor C not allowed to straddle the left screen edge\n"); 479 return -EINVAL; 480 } 481 482 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state); 483 484 return 0; 485 } 486 487 static void i9xx_update_cursor(struct intel_plane *plane, 488 const struct intel_crtc_state *crtc_state, 489 const struct intel_plane_state *plane_state) 490 { 491 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 492 enum pipe pipe = plane->pipe; 493 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0; 494 unsigned long irqflags; 495 496 if (plane_state && plane_state->uapi.visible) { 497 int width = drm_rect_width(&plane_state->uapi.dst); 498 int height = drm_rect_height(&plane_state->uapi.dst); 499 500 cntl = plane_state->ctl | 501 i9xx_cursor_ctl_crtc(crtc_state); 502 503 if (width != height) 504 fbc_ctl = CUR_FBC_CTL_EN | (height - 1); 505 506 base = intel_cursor_base(plane_state); 507 pos = intel_cursor_position(plane_state); 508 } 509 510 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 511 512 /* 513 * On some platforms writing CURCNTR first will also 514 * cause CURPOS to be armed by the CURBASE write. 515 * Without the CURCNTR write the CURPOS write would 516 * arm itself. Thus we always update CURCNTR before 517 * CURPOS. 518 * 519 * On other platforms CURPOS always requires the 520 * CURBASE write to arm the update. Additonally 521 * a write to any of the cursor register will cancel 522 * an already armed cursor update. Thus leaving out 523 * the CURBASE write after CURPOS could lead to a 524 * cursor that doesn't appear to move, or even change 525 * shape. Thus we always write CURBASE. 526 * 527 * The other registers are armed by the CURBASE write 528 * except when the plane is getting enabled at which time 529 * the CURCNTR write arms the update. 530 */ 531 532 if (DISPLAY_VER(dev_priv) >= 9) 533 skl_write_cursor_wm(plane, crtc_state); 534 535 if (!intel_crtc_needs_modeset(crtc_state)) 536 intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, 0); 537 538 if (plane->cursor.base != base || 539 plane->cursor.size != fbc_ctl || 540 plane->cursor.cntl != cntl) { 541 if (HAS_CUR_FBC(dev_priv)) 542 intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe), 543 fbc_ctl); 544 intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl); 545 intel_de_write_fw(dev_priv, CURPOS(pipe), pos); 546 intel_de_write_fw(dev_priv, CURBASE(pipe), base); 547 548 plane->cursor.base = base; 549 plane->cursor.size = fbc_ctl; 550 plane->cursor.cntl = cntl; 551 } else { 552 intel_de_write_fw(dev_priv, CURPOS(pipe), pos); 553 intel_de_write_fw(dev_priv, CURBASE(pipe), base); 554 } 555 556 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 557 } 558 559 static void i9xx_disable_cursor(struct intel_plane *plane, 560 const struct intel_crtc_state *crtc_state) 561 { 562 i9xx_update_cursor(plane, crtc_state, NULL); 563 } 564 565 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane, 566 enum pipe *pipe) 567 { 568 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 569 enum intel_display_power_domain power_domain; 570 intel_wakeref_t wakeref; 571 bool ret; 572 u32 val; 573 574 /* 575 * Not 100% correct for planes that can move between pipes, 576 * but that's only the case for gen2-3 which don't have any 577 * display power wells. 578 */ 579 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 580 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 581 if (!wakeref) 582 return false; 583 584 val = intel_de_read(dev_priv, CURCNTR(plane->pipe)); 585 586 ret = val & MCURSOR_MODE; 587 588 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) 589 *pipe = plane->pipe; 590 else 591 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >> 592 MCURSOR_PIPE_SELECT_SHIFT; 593 594 intel_display_power_put(dev_priv, power_domain, wakeref); 595 596 return ret; 597 } 598 599 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane, 600 u32 format, u64 modifier) 601 { 602 return modifier == DRM_FORMAT_MOD_LINEAR && 603 format == DRM_FORMAT_ARGB8888; 604 } 605 606 static int 607 intel_legacy_cursor_update(struct drm_plane *_plane, 608 struct drm_crtc *_crtc, 609 struct drm_framebuffer *fb, 610 int crtc_x, int crtc_y, 611 unsigned int crtc_w, unsigned int crtc_h, 612 u32 src_x, u32 src_y, 613 u32 src_w, u32 src_h, 614 struct drm_modeset_acquire_ctx *ctx) 615 { 616 struct intel_plane *plane = to_intel_plane(_plane); 617 struct intel_crtc *crtc = to_intel_crtc(_crtc); 618 struct intel_plane_state *old_plane_state = 619 to_intel_plane_state(plane->base.state); 620 struct intel_plane_state *new_plane_state; 621 struct intel_crtc_state *crtc_state = 622 to_intel_crtc_state(crtc->base.state); 623 struct intel_crtc_state *new_crtc_state; 624 int ret; 625 626 /* 627 * When crtc is inactive or there is a modeset pending, 628 * wait for it to complete in the slowpath 629 * 630 * FIXME bigjoiner fastpath would be good 631 */ 632 if (!crtc_state->hw.active || intel_crtc_needs_modeset(crtc_state) || 633 crtc_state->update_pipe || crtc_state->bigjoiner) 634 goto slow; 635 636 /* 637 * Don't do an async update if there is an outstanding commit modifying 638 * the plane. This prevents our async update's changes from getting 639 * overridden by a previous synchronous update's state. 640 */ 641 if (old_plane_state->uapi.commit && 642 !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done)) 643 goto slow; 644 645 /* 646 * If any parameters change that may affect watermarks, 647 * take the slowpath. Only changing fb or position should be 648 * in the fastpath. 649 */ 650 if (old_plane_state->uapi.crtc != &crtc->base || 651 old_plane_state->uapi.src_w != src_w || 652 old_plane_state->uapi.src_h != src_h || 653 old_plane_state->uapi.crtc_w != crtc_w || 654 old_plane_state->uapi.crtc_h != crtc_h || 655 !old_plane_state->uapi.fb != !fb) 656 goto slow; 657 658 new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base)); 659 if (!new_plane_state) 660 return -ENOMEM; 661 662 new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base)); 663 if (!new_crtc_state) { 664 ret = -ENOMEM; 665 goto out_free; 666 } 667 668 drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb); 669 670 new_plane_state->uapi.src_x = src_x; 671 new_plane_state->uapi.src_y = src_y; 672 new_plane_state->uapi.src_w = src_w; 673 new_plane_state->uapi.src_h = src_h; 674 new_plane_state->uapi.crtc_x = crtc_x; 675 new_plane_state->uapi.crtc_y = crtc_y; 676 new_plane_state->uapi.crtc_w = crtc_w; 677 new_plane_state->uapi.crtc_h = crtc_h; 678 679 intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state, crtc); 680 681 ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state, 682 old_plane_state, new_plane_state); 683 if (ret) 684 goto out_free; 685 686 ret = intel_plane_pin_fb(new_plane_state); 687 if (ret) 688 goto out_free; 689 690 intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb), 691 ORIGIN_FLIP); 692 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 693 to_intel_frontbuffer(new_plane_state->hw.fb), 694 plane->frontbuffer_bit); 695 696 /* Swap plane state */ 697 plane->base.state = &new_plane_state->uapi; 698 699 /* 700 * We cannot swap crtc_state as it may be in use by an atomic commit or 701 * page flip that's running simultaneously. If we swap crtc_state and 702 * destroy the old state, we will cause a use-after-free there. 703 * 704 * Only update active_planes, which is needed for our internal 705 * bookkeeping. Either value will do the right thing when updating 706 * planes atomically. If the cursor was part of the atomic update then 707 * we would have taken the slowpath. 708 */ 709 crtc_state->active_planes = new_crtc_state->active_planes; 710 711 if (new_plane_state->uapi.visible) 712 intel_update_plane(plane, crtc_state, new_plane_state); 713 else 714 intel_disable_plane(plane, crtc_state); 715 716 intel_plane_unpin_fb(old_plane_state); 717 718 out_free: 719 if (new_crtc_state) 720 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi); 721 if (ret) 722 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi); 723 else 724 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi); 725 return ret; 726 727 slow: 728 return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb, 729 crtc_x, crtc_y, crtc_w, crtc_h, 730 src_x, src_y, src_w, src_h, ctx); 731 } 732 733 static const struct drm_plane_funcs intel_cursor_plane_funcs = { 734 .update_plane = intel_legacy_cursor_update, 735 .disable_plane = drm_atomic_helper_disable_plane, 736 .destroy = intel_plane_destroy, 737 .atomic_duplicate_state = intel_plane_duplicate_state, 738 .atomic_destroy_state = intel_plane_destroy_state, 739 .format_mod_supported = intel_cursor_format_mod_supported, 740 }; 741 742 struct intel_plane * 743 intel_cursor_plane_create(struct drm_i915_private *dev_priv, 744 enum pipe pipe) 745 { 746 struct intel_plane *cursor; 747 int ret, zpos; 748 749 cursor = intel_plane_alloc(); 750 if (IS_ERR(cursor)) 751 return cursor; 752 753 cursor->pipe = pipe; 754 cursor->i9xx_plane = (enum i9xx_plane_id) pipe; 755 cursor->id = PLANE_CURSOR; 756 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id); 757 758 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { 759 cursor->max_stride = i845_cursor_max_stride; 760 cursor->update_plane = i845_update_cursor; 761 cursor->disable_plane = i845_disable_cursor; 762 cursor->get_hw_state = i845_cursor_get_hw_state; 763 cursor->check_plane = i845_check_cursor; 764 } else { 765 cursor->max_stride = i9xx_cursor_max_stride; 766 cursor->update_plane = i9xx_update_cursor; 767 cursor->disable_plane = i9xx_disable_cursor; 768 cursor->get_hw_state = i9xx_cursor_get_hw_state; 769 cursor->check_plane = i9xx_check_cursor; 770 } 771 772 cursor->cursor.base = ~0; 773 cursor->cursor.cntl = ~0; 774 775 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv)) 776 cursor->cursor.size = ~0; 777 778 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, 779 0, &intel_cursor_plane_funcs, 780 intel_cursor_formats, 781 ARRAY_SIZE(intel_cursor_formats), 782 cursor_format_modifiers, 783 DRM_PLANE_TYPE_CURSOR, 784 "cursor %c", pipe_name(pipe)); 785 if (ret) 786 goto fail; 787 788 if (DISPLAY_VER(dev_priv) >= 4) 789 drm_plane_create_rotation_property(&cursor->base, 790 DRM_MODE_ROTATE_0, 791 DRM_MODE_ROTATE_0 | 792 DRM_MODE_ROTATE_180); 793 794 zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1; 795 drm_plane_create_zpos_immutable_property(&cursor->base, zpos); 796 797 if (DISPLAY_VER(dev_priv) >= 12) 798 drm_plane_enable_fb_damage_clips(&cursor->base); 799 800 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); 801 802 return cursor; 803 804 fail: 805 intel_plane_free(cursor); 806 807 return ERR_PTR(ret); 808 } 809