1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2020 Intel Corporation
4  */
5 #include <linux/kernel.h>
6 
7 #include <drm/drm_atomic_helper.h>
8 #include <drm/drm_atomic_uapi.h>
9 #include <drm/drm_blend.h>
10 #include <drm/drm_damage_helper.h>
11 #include <drm/drm_plane_helper.h>
12 #include <drm/drm_fourcc.h>
13 
14 #include "intel_atomic.h"
15 #include "intel_atomic_plane.h"
16 #include "intel_cursor.h"
17 #include "intel_de.h"
18 #include "intel_display_types.h"
19 #include "intel_display.h"
20 #include "intel_fb.h"
21 #include "intel_fb_pin.h"
22 #include "intel_frontbuffer.h"
23 #include "intel_pm.h"
24 #include "intel_psr.h"
25 #include "intel_sprite.h"
26 
27 /* Cursor formats */
28 static const u32 intel_cursor_formats[] = {
29 	DRM_FORMAT_ARGB8888,
30 };
31 
32 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
33 {
34 	struct drm_i915_private *dev_priv =
35 		to_i915(plane_state->uapi.plane->dev);
36 	const struct drm_framebuffer *fb = plane_state->hw.fb;
37 	const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
38 	u32 base;
39 
40 	if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
41 		base = sg_dma_address(obj->mm.pages->sgl);
42 	else
43 		base = intel_plane_ggtt_offset(plane_state);
44 
45 	return base + plane_state->view.color_plane[0].offset;
46 }
47 
48 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
49 {
50 	int x = plane_state->uapi.dst.x1;
51 	int y = plane_state->uapi.dst.y1;
52 	u32 pos = 0;
53 
54 	if (x < 0) {
55 		pos |= CURSOR_POS_X_SIGN;
56 		x = -x;
57 	}
58 	pos |= CURSOR_POS_X(x);
59 
60 	if (y < 0) {
61 		pos |= CURSOR_POS_Y_SIGN;
62 		y = -y;
63 	}
64 	pos |= CURSOR_POS_Y(y);
65 
66 	return pos;
67 }
68 
69 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
70 {
71 	const struct drm_mode_config *config =
72 		&plane_state->uapi.plane->dev->mode_config;
73 	int width = drm_rect_width(&plane_state->uapi.dst);
74 	int height = drm_rect_height(&plane_state->uapi.dst);
75 
76 	return width > 0 && width <= config->cursor_width &&
77 		height > 0 && height <= config->cursor_height;
78 }
79 
80 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
81 {
82 	struct drm_i915_private *dev_priv =
83 		to_i915(plane_state->uapi.plane->dev);
84 	unsigned int rotation = plane_state->hw.rotation;
85 	int src_x, src_y;
86 	u32 offset;
87 	int ret;
88 
89 	ret = intel_plane_compute_gtt(plane_state);
90 	if (ret)
91 		return ret;
92 
93 	if (!plane_state->uapi.visible)
94 		return 0;
95 
96 	src_x = plane_state->uapi.src.x1 >> 16;
97 	src_y = plane_state->uapi.src.y1 >> 16;
98 
99 	intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
100 	offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
101 						    plane_state, 0);
102 
103 	if (src_x != 0 || src_y != 0) {
104 		drm_dbg_kms(&dev_priv->drm,
105 			    "Arbitrary cursor panning not supported\n");
106 		return -EINVAL;
107 	}
108 
109 	/*
110 	 * Put the final coordinates back so that the src
111 	 * coordinate checks will see the right values.
112 	 */
113 	drm_rect_translate_to(&plane_state->uapi.src,
114 			      src_x << 16, src_y << 16);
115 
116 	/* ILK+ do this automagically in hardware */
117 	if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
118 		const struct drm_framebuffer *fb = plane_state->hw.fb;
119 		int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
120 		int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
121 
122 		offset += (src_h * src_w - 1) * fb->format->cpp[0];
123 	}
124 
125 	plane_state->view.color_plane[0].offset = offset;
126 	plane_state->view.color_plane[0].x = src_x;
127 	plane_state->view.color_plane[0].y = src_y;
128 
129 	return 0;
130 }
131 
132 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
133 			      struct intel_plane_state *plane_state)
134 {
135 	const struct drm_framebuffer *fb = plane_state->hw.fb;
136 	struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
137 	const struct drm_rect src = plane_state->uapi.src;
138 	const struct drm_rect dst = plane_state->uapi.dst;
139 	int ret;
140 
141 	if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
142 		drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n");
143 		return -EINVAL;
144 	}
145 
146 	ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
147 						DRM_PLANE_HELPER_NO_SCALING,
148 						DRM_PLANE_HELPER_NO_SCALING,
149 						true);
150 	if (ret)
151 		return ret;
152 
153 	/* Use the unclipped src/dst rectangles, which we program to hw */
154 	plane_state->uapi.src = src;
155 	plane_state->uapi.dst = dst;
156 
157 	/* final plane coordinates will be relative to the plane's pipe */
158 	drm_rect_translate(&plane_state->uapi.dst,
159 			   -crtc_state->pipe_src.x1,
160 			   -crtc_state->pipe_src.y1);
161 
162 	ret = intel_cursor_check_surface(plane_state);
163 	if (ret)
164 		return ret;
165 
166 	if (!plane_state->uapi.visible)
167 		return 0;
168 
169 	ret = intel_plane_check_src_coordinates(plane_state);
170 	if (ret)
171 		return ret;
172 
173 	return 0;
174 }
175 
176 static unsigned int
177 i845_cursor_max_stride(struct intel_plane *plane,
178 		       u32 pixel_format, u64 modifier,
179 		       unsigned int rotation)
180 {
181 	return 2048;
182 }
183 
184 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
185 {
186 	u32 cntl = 0;
187 
188 	if (crtc_state->gamma_enable)
189 		cntl |= CURSOR_PIPE_GAMMA_ENABLE;
190 
191 	return cntl;
192 }
193 
194 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
195 			   const struct intel_plane_state *plane_state)
196 {
197 	return CURSOR_ENABLE |
198 		CURSOR_FORMAT_ARGB |
199 		CURSOR_STRIDE(plane_state->view.color_plane[0].mapping_stride);
200 }
201 
202 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
203 {
204 	int width = drm_rect_width(&plane_state->uapi.dst);
205 
206 	/*
207 	 * 845g/865g are only limited by the width of their cursors,
208 	 * the height is arbitrary up to the precision of the register.
209 	 */
210 	return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
211 }
212 
213 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
214 			     struct intel_plane_state *plane_state)
215 {
216 	const struct drm_framebuffer *fb = plane_state->hw.fb;
217 	struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
218 	int ret;
219 
220 	ret = intel_check_cursor(crtc_state, plane_state);
221 	if (ret)
222 		return ret;
223 
224 	/* if we want to turn off the cursor ignore width and height */
225 	if (!fb)
226 		return 0;
227 
228 	/* Check for which cursor types we support */
229 	if (!i845_cursor_size_ok(plane_state)) {
230 		drm_dbg_kms(&i915->drm,
231 			    "Cursor dimension %dx%d not supported\n",
232 			    drm_rect_width(&plane_state->uapi.dst),
233 			    drm_rect_height(&plane_state->uapi.dst));
234 		return -EINVAL;
235 	}
236 
237 	drm_WARN_ON(&i915->drm, plane_state->uapi.visible &&
238 		    plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]);
239 
240 	switch (fb->pitches[0]) {
241 	case 256:
242 	case 512:
243 	case 1024:
244 	case 2048:
245 		break;
246 	default:
247 		 drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n",
248 			     fb->pitches[0]);
249 		return -EINVAL;
250 	}
251 
252 	plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
253 
254 	return 0;
255 }
256 
257 /* TODO: split into noarm+arm pair */
258 static void i845_cursor_update_arm(struct intel_plane *plane,
259 				   const struct intel_crtc_state *crtc_state,
260 				   const struct intel_plane_state *plane_state)
261 {
262 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
263 	u32 cntl = 0, base = 0, pos = 0, size = 0;
264 
265 	if (plane_state && plane_state->uapi.visible) {
266 		unsigned int width = drm_rect_width(&plane_state->uapi.dst);
267 		unsigned int height = drm_rect_height(&plane_state->uapi.dst);
268 
269 		cntl = plane_state->ctl |
270 			i845_cursor_ctl_crtc(crtc_state);
271 
272 		size = CURSOR_HEIGHT(height) | CURSOR_WIDTH(width);
273 
274 		base = intel_cursor_base(plane_state);
275 		pos = intel_cursor_position(plane_state);
276 	}
277 
278 	/* On these chipsets we can only modify the base/size/stride
279 	 * whilst the cursor is disabled.
280 	 */
281 	if (plane->cursor.base != base ||
282 	    plane->cursor.size != size ||
283 	    plane->cursor.cntl != cntl) {
284 		intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
285 		intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
286 		intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size);
287 		intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
288 		intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
289 
290 		plane->cursor.base = base;
291 		plane->cursor.size = size;
292 		plane->cursor.cntl = cntl;
293 	} else {
294 		intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
295 	}
296 }
297 
298 static void i845_cursor_disable_arm(struct intel_plane *plane,
299 				    const struct intel_crtc_state *crtc_state)
300 {
301 	i845_cursor_update_arm(plane, crtc_state, NULL);
302 }
303 
304 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
305 				     enum pipe *pipe)
306 {
307 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
308 	enum intel_display_power_domain power_domain;
309 	intel_wakeref_t wakeref;
310 	bool ret;
311 
312 	power_domain = POWER_DOMAIN_PIPE(PIPE_A);
313 	wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
314 	if (!wakeref)
315 		return false;
316 
317 	ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE;
318 
319 	*pipe = PIPE_A;
320 
321 	intel_display_power_put(dev_priv, power_domain, wakeref);
322 
323 	return ret;
324 }
325 
326 static unsigned int
327 i9xx_cursor_max_stride(struct intel_plane *plane,
328 		       u32 pixel_format, u64 modifier,
329 		       unsigned int rotation)
330 {
331 	return plane->base.dev->mode_config.cursor_width * 4;
332 }
333 
334 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
335 {
336 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
337 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
338 	u32 cntl = 0;
339 
340 	if (DISPLAY_VER(dev_priv) >= 11)
341 		return cntl;
342 
343 	if (crtc_state->gamma_enable)
344 		cntl = MCURSOR_PIPE_GAMMA_ENABLE;
345 
346 	if (crtc_state->csc_enable)
347 		cntl |= MCURSOR_PIPE_CSC_ENABLE;
348 
349 	if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
350 		cntl |= MCURSOR_PIPE_SEL(crtc->pipe);
351 
352 	return cntl;
353 }
354 
355 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
356 			   const struct intel_plane_state *plane_state)
357 {
358 	struct drm_i915_private *dev_priv =
359 		to_i915(plane_state->uapi.plane->dev);
360 	u32 cntl = 0;
361 
362 	if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
363 		cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
364 
365 	switch (drm_rect_width(&plane_state->uapi.dst)) {
366 	case 64:
367 		cntl |= MCURSOR_MODE_64_ARGB_AX;
368 		break;
369 	case 128:
370 		cntl |= MCURSOR_MODE_128_ARGB_AX;
371 		break;
372 	case 256:
373 		cntl |= MCURSOR_MODE_256_ARGB_AX;
374 		break;
375 	default:
376 		MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
377 		return 0;
378 	}
379 
380 	if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
381 		cntl |= MCURSOR_ROTATE_180;
382 
383 	/* Wa_22012358565:adl-p */
384 	if (DISPLAY_VER(dev_priv) == 13)
385 		cntl |= MCURSOR_ARB_SLOTS(1);
386 
387 	return cntl;
388 }
389 
390 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
391 {
392 	struct drm_i915_private *dev_priv =
393 		to_i915(plane_state->uapi.plane->dev);
394 	int width = drm_rect_width(&plane_state->uapi.dst);
395 	int height = drm_rect_height(&plane_state->uapi.dst);
396 
397 	if (!intel_cursor_size_ok(plane_state))
398 		return false;
399 
400 	/* Cursor width is limited to a few power-of-two sizes */
401 	switch (width) {
402 	case 256:
403 	case 128:
404 	case 64:
405 		break;
406 	default:
407 		return false;
408 	}
409 
410 	/*
411 	 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
412 	 * height from 8 lines up to the cursor width, when the
413 	 * cursor is not rotated. Everything else requires square
414 	 * cursors.
415 	 */
416 	if (HAS_CUR_FBC(dev_priv) &&
417 	    plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
418 		if (height < 8 || height > width)
419 			return false;
420 	} else {
421 		if (height != width)
422 			return false;
423 	}
424 
425 	return true;
426 }
427 
428 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
429 			     struct intel_plane_state *plane_state)
430 {
431 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
432 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
433 	const struct drm_framebuffer *fb = plane_state->hw.fb;
434 	enum pipe pipe = plane->pipe;
435 	int ret;
436 
437 	ret = intel_check_cursor(crtc_state, plane_state);
438 	if (ret)
439 		return ret;
440 
441 	/* if we want to turn off the cursor ignore width and height */
442 	if (!fb)
443 		return 0;
444 
445 	/* Check for which cursor types we support */
446 	if (!i9xx_cursor_size_ok(plane_state)) {
447 		drm_dbg(&dev_priv->drm,
448 			"Cursor dimension %dx%d not supported\n",
449 			drm_rect_width(&plane_state->uapi.dst),
450 			drm_rect_height(&plane_state->uapi.dst));
451 		return -EINVAL;
452 	}
453 
454 	drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible &&
455 		    plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]);
456 
457 	if (fb->pitches[0] !=
458 	    drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
459 		drm_dbg_kms(&dev_priv->drm,
460 			    "Invalid cursor stride (%u) (cursor width %d)\n",
461 			    fb->pitches[0],
462 			    drm_rect_width(&plane_state->uapi.dst));
463 		return -EINVAL;
464 	}
465 
466 	/*
467 	 * There's something wrong with the cursor on CHV pipe C.
468 	 * If it straddles the left edge of the screen then
469 	 * moving it away from the edge or disabling it often
470 	 * results in a pipe underrun, and often that can lead to
471 	 * dead pipe (constant underrun reported, and it scans
472 	 * out just a solid color). To recover from that, the
473 	 * display power well must be turned off and on again.
474 	 * Refuse the put the cursor into that compromised position.
475 	 */
476 	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
477 	    plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
478 		drm_dbg_kms(&dev_priv->drm,
479 			    "CHV cursor C not allowed to straddle the left screen edge\n");
480 		return -EINVAL;
481 	}
482 
483 	plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
484 
485 	return 0;
486 }
487 
488 /* TODO: split into noarm+arm pair */
489 static void i9xx_cursor_update_arm(struct intel_plane *plane,
490 				   const struct intel_crtc_state *crtc_state,
491 				   const struct intel_plane_state *plane_state)
492 {
493 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
494 	enum pipe pipe = plane->pipe;
495 	u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
496 
497 	if (plane_state && plane_state->uapi.visible) {
498 		int width = drm_rect_width(&plane_state->uapi.dst);
499 		int height = drm_rect_height(&plane_state->uapi.dst);
500 
501 		cntl = plane_state->ctl |
502 			i9xx_cursor_ctl_crtc(crtc_state);
503 
504 		if (width != height)
505 			fbc_ctl = CUR_FBC_EN | CUR_FBC_HEIGHT(height - 1);
506 
507 		base = intel_cursor_base(plane_state);
508 		pos = intel_cursor_position(plane_state);
509 	}
510 
511 	/*
512 	 * On some platforms writing CURCNTR first will also
513 	 * cause CURPOS to be armed by the CURBASE write.
514 	 * Without the CURCNTR write the CURPOS write would
515 	 * arm itself. Thus we always update CURCNTR before
516 	 * CURPOS.
517 	 *
518 	 * On other platforms CURPOS always requires the
519 	 * CURBASE write to arm the update. Additonally
520 	 * a write to any of the cursor register will cancel
521 	 * an already armed cursor update. Thus leaving out
522 	 * the CURBASE write after CURPOS could lead to a
523 	 * cursor that doesn't appear to move, or even change
524 	 * shape. Thus we always write CURBASE.
525 	 *
526 	 * The other registers are armed by the CURBASE write
527 	 * except when the plane is getting enabled at which time
528 	 * the CURCNTR write arms the update.
529 	 */
530 
531 	if (DISPLAY_VER(dev_priv) >= 9)
532 		skl_write_cursor_wm(plane, crtc_state);
533 
534 	if (plane_state)
535 		intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, 0);
536 	else
537 		intel_psr2_disable_plane_sel_fetch(plane, crtc_state);
538 
539 	if (plane->cursor.base != base ||
540 	    plane->cursor.size != fbc_ctl ||
541 	    plane->cursor.cntl != cntl) {
542 		if (HAS_CUR_FBC(dev_priv))
543 			intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe),
544 					  fbc_ctl);
545 		intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl);
546 		intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
547 		intel_de_write_fw(dev_priv, CURBASE(pipe), base);
548 
549 		plane->cursor.base = base;
550 		plane->cursor.size = fbc_ctl;
551 		plane->cursor.cntl = cntl;
552 	} else {
553 		intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
554 		intel_de_write_fw(dev_priv, CURBASE(pipe), base);
555 	}
556 }
557 
558 static void i9xx_cursor_disable_arm(struct intel_plane *plane,
559 				    const struct intel_crtc_state *crtc_state)
560 {
561 	i9xx_cursor_update_arm(plane, crtc_state, NULL);
562 }
563 
564 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
565 				     enum pipe *pipe)
566 {
567 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
568 	enum intel_display_power_domain power_domain;
569 	intel_wakeref_t wakeref;
570 	bool ret;
571 	u32 val;
572 
573 	/*
574 	 * Not 100% correct for planes that can move between pipes,
575 	 * but that's only the case for gen2-3 which don't have any
576 	 * display power wells.
577 	 */
578 	power_domain = POWER_DOMAIN_PIPE(plane->pipe);
579 	wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
580 	if (!wakeref)
581 		return false;
582 
583 	val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
584 
585 	ret = val & MCURSOR_MODE_MASK;
586 
587 	if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
588 		*pipe = plane->pipe;
589 	else
590 		*pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val);
591 
592 	intel_display_power_put(dev_priv, power_domain, wakeref);
593 
594 	return ret;
595 }
596 
597 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
598 					      u32 format, u64 modifier)
599 {
600 	if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
601 		return false;
602 
603 	return format == DRM_FORMAT_ARGB8888;
604 }
605 
606 static int
607 intel_legacy_cursor_update(struct drm_plane *_plane,
608 			   struct drm_crtc *_crtc,
609 			   struct drm_framebuffer *fb,
610 			   int crtc_x, int crtc_y,
611 			   unsigned int crtc_w, unsigned int crtc_h,
612 			   u32 src_x, u32 src_y,
613 			   u32 src_w, u32 src_h,
614 			   struct drm_modeset_acquire_ctx *ctx)
615 {
616 	struct intel_plane *plane = to_intel_plane(_plane);
617 	struct intel_crtc *crtc = to_intel_crtc(_crtc);
618 	struct intel_plane_state *old_plane_state =
619 		to_intel_plane_state(plane->base.state);
620 	struct intel_plane_state *new_plane_state;
621 	struct intel_crtc_state *crtc_state =
622 		to_intel_crtc_state(crtc->base.state);
623 	struct intel_crtc_state *new_crtc_state;
624 	int ret;
625 
626 	/*
627 	 * When crtc is inactive or there is a modeset pending,
628 	 * wait for it to complete in the slowpath.
629 	 * PSR2 selective fetch also requires the slow path as
630 	 * PSR2 plane and transcoder registers can only be updated during
631 	 * vblank.
632 	 *
633 	 * FIXME bigjoiner fastpath would be good
634 	 */
635 	if (!crtc_state->hw.active || intel_crtc_needs_modeset(crtc_state) ||
636 	    crtc_state->update_pipe || crtc_state->bigjoiner_pipes)
637 		goto slow;
638 
639 	/*
640 	 * Don't do an async update if there is an outstanding commit modifying
641 	 * the plane.  This prevents our async update's changes from getting
642 	 * overridden by a previous synchronous update's state.
643 	 */
644 	if (old_plane_state->uapi.commit &&
645 	    !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
646 		goto slow;
647 
648 	/*
649 	 * If any parameters change that may affect watermarks,
650 	 * take the slowpath. Only changing fb or position should be
651 	 * in the fastpath.
652 	 */
653 	if (old_plane_state->uapi.crtc != &crtc->base ||
654 	    old_plane_state->uapi.src_w != src_w ||
655 	    old_plane_state->uapi.src_h != src_h ||
656 	    old_plane_state->uapi.crtc_w != crtc_w ||
657 	    old_plane_state->uapi.crtc_h != crtc_h ||
658 	    !old_plane_state->uapi.fb != !fb)
659 		goto slow;
660 
661 	new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
662 	if (!new_plane_state)
663 		return -ENOMEM;
664 
665 	new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
666 	if (!new_crtc_state) {
667 		ret = -ENOMEM;
668 		goto out_free;
669 	}
670 
671 	drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
672 
673 	new_plane_state->uapi.src_x = src_x;
674 	new_plane_state->uapi.src_y = src_y;
675 	new_plane_state->uapi.src_w = src_w;
676 	new_plane_state->uapi.src_h = src_h;
677 	new_plane_state->uapi.crtc_x = crtc_x;
678 	new_plane_state->uapi.crtc_y = crtc_y;
679 	new_plane_state->uapi.crtc_w = crtc_w;
680 	new_plane_state->uapi.crtc_h = crtc_h;
681 
682 	intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state, crtc);
683 
684 	ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
685 						  old_plane_state, new_plane_state);
686 	if (ret)
687 		goto out_free;
688 
689 	ret = intel_plane_pin_fb(new_plane_state);
690 	if (ret)
691 		goto out_free;
692 
693 	intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
694 				ORIGIN_CURSOR_UPDATE);
695 	intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
696 				to_intel_frontbuffer(new_plane_state->hw.fb),
697 				plane->frontbuffer_bit);
698 
699 	/* Swap plane state */
700 	plane->base.state = &new_plane_state->uapi;
701 
702 	/*
703 	 * We cannot swap crtc_state as it may be in use by an atomic commit or
704 	 * page flip that's running simultaneously. If we swap crtc_state and
705 	 * destroy the old state, we will cause a use-after-free there.
706 	 *
707 	 * Only update active_planes, which is needed for our internal
708 	 * bookkeeping. Either value will do the right thing when updating
709 	 * planes atomically. If the cursor was part of the atomic update then
710 	 * we would have taken the slowpath.
711 	 */
712 	crtc_state->active_planes = new_crtc_state->active_planes;
713 
714 	/*
715 	 * Technically we should do a vblank evasion here to make
716 	 * sure all the cursor registers update on the same frame.
717 	 * For now just make sure the register writes happen as
718 	 * quickly as possible to minimize the race window.
719 	 */
720 	local_irq_disable();
721 
722 	if (new_plane_state->uapi.visible) {
723 		intel_plane_update_noarm(plane, crtc_state, new_plane_state);
724 		intel_plane_update_arm(plane, crtc_state, new_plane_state);
725 	} else {
726 		intel_plane_disable_arm(plane, crtc_state);
727 	}
728 
729 	local_irq_enable();
730 
731 	intel_plane_unpin_fb(old_plane_state);
732 
733 out_free:
734 	if (new_crtc_state)
735 		intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
736 	if (ret)
737 		intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
738 	else
739 		intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
740 	return ret;
741 
742 slow:
743 	return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
744 					      crtc_x, crtc_y, crtc_w, crtc_h,
745 					      src_x, src_y, src_w, src_h, ctx);
746 }
747 
748 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
749 	.update_plane = intel_legacy_cursor_update,
750 	.disable_plane = drm_atomic_helper_disable_plane,
751 	.destroy = intel_plane_destroy,
752 	.atomic_duplicate_state = intel_plane_duplicate_state,
753 	.atomic_destroy_state = intel_plane_destroy_state,
754 	.format_mod_supported = intel_cursor_format_mod_supported,
755 };
756 
757 struct intel_plane *
758 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
759 			  enum pipe pipe)
760 {
761 	struct intel_plane *cursor;
762 	int ret, zpos;
763 	u64 *modifiers;
764 
765 	cursor = intel_plane_alloc();
766 	if (IS_ERR(cursor))
767 		return cursor;
768 
769 	cursor->pipe = pipe;
770 	cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
771 	cursor->id = PLANE_CURSOR;
772 	cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
773 
774 	if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
775 		cursor->max_stride = i845_cursor_max_stride;
776 		cursor->update_arm = i845_cursor_update_arm;
777 		cursor->disable_arm = i845_cursor_disable_arm;
778 		cursor->get_hw_state = i845_cursor_get_hw_state;
779 		cursor->check_plane = i845_check_cursor;
780 	} else {
781 		cursor->max_stride = i9xx_cursor_max_stride;
782 		cursor->update_arm = i9xx_cursor_update_arm;
783 		cursor->disable_arm = i9xx_cursor_disable_arm;
784 		cursor->get_hw_state = i9xx_cursor_get_hw_state;
785 		cursor->check_plane = i9xx_check_cursor;
786 	}
787 
788 	cursor->cursor.base = ~0;
789 	cursor->cursor.cntl = ~0;
790 
791 	if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
792 		cursor->cursor.size = ~0;
793 
794 	modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_NONE);
795 
796 	ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
797 				       0, &intel_cursor_plane_funcs,
798 				       intel_cursor_formats,
799 				       ARRAY_SIZE(intel_cursor_formats),
800 				       modifiers,
801 				       DRM_PLANE_TYPE_CURSOR,
802 				       "cursor %c", pipe_name(pipe));
803 
804 	kfree(modifiers);
805 
806 	if (ret)
807 		goto fail;
808 
809 	if (DISPLAY_VER(dev_priv) >= 4)
810 		drm_plane_create_rotation_property(&cursor->base,
811 						   DRM_MODE_ROTATE_0,
812 						   DRM_MODE_ROTATE_0 |
813 						   DRM_MODE_ROTATE_180);
814 
815 	zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
816 	drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
817 
818 	if (DISPLAY_VER(dev_priv) >= 12)
819 		drm_plane_enable_fb_damage_clips(&cursor->base);
820 
821 	intel_plane_helper_add(cursor);
822 
823 	return cursor;
824 
825 fail:
826 	intel_plane_free(cursor);
827 
828 	return ERR_PTR(ret);
829 }
830