1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 #include <linux/kernel.h> 6 7 #include <drm/drm_atomic_helper.h> 8 #include <drm/drm_atomic_uapi.h> 9 #include <drm/drm_damage_helper.h> 10 #include <drm/drm_plane_helper.h> 11 #include <drm/drm_fourcc.h> 12 13 #include "intel_atomic.h" 14 #include "intel_atomic_plane.h" 15 #include "intel_cursor.h" 16 #include "intel_de.h" 17 #include "intel_display_types.h" 18 #include "intel_display.h" 19 #include "intel_fb.h" 20 #include "intel_fb_pin.h" 21 #include "intel_frontbuffer.h" 22 #include "intel_pm.h" 23 #include "intel_psr.h" 24 #include "intel_sprite.h" 25 26 /* Cursor formats */ 27 static const u32 intel_cursor_formats[] = { 28 DRM_FORMAT_ARGB8888, 29 }; 30 31 static u32 intel_cursor_base(const struct intel_plane_state *plane_state) 32 { 33 struct drm_i915_private *dev_priv = 34 to_i915(plane_state->uapi.plane->dev); 35 const struct drm_framebuffer *fb = plane_state->hw.fb; 36 const struct drm_i915_gem_object *obj = intel_fb_obj(fb); 37 u32 base; 38 39 if (INTEL_INFO(dev_priv)->display.cursor_needs_physical) 40 base = sg_dma_address(obj->mm.pages->sgl); 41 else 42 base = intel_plane_ggtt_offset(plane_state); 43 44 return base + plane_state->view.color_plane[0].offset; 45 } 46 47 static u32 intel_cursor_position(const struct intel_plane_state *plane_state) 48 { 49 int x = plane_state->uapi.dst.x1; 50 int y = plane_state->uapi.dst.y1; 51 u32 pos = 0; 52 53 if (x < 0) { 54 pos |= CURSOR_POS_X_SIGN; 55 x = -x; 56 } 57 pos |= CURSOR_POS_X(x); 58 59 if (y < 0) { 60 pos |= CURSOR_POS_Y_SIGN; 61 y = -y; 62 } 63 pos |= CURSOR_POS_Y(y); 64 65 return pos; 66 } 67 68 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state) 69 { 70 const struct drm_mode_config *config = 71 &plane_state->uapi.plane->dev->mode_config; 72 int width = drm_rect_width(&plane_state->uapi.dst); 73 int height = drm_rect_height(&plane_state->uapi.dst); 74 75 return width > 0 && width <= config->cursor_width && 76 height > 0 && height <= config->cursor_height; 77 } 78 79 static int intel_cursor_check_surface(struct intel_plane_state *plane_state) 80 { 81 struct drm_i915_private *dev_priv = 82 to_i915(plane_state->uapi.plane->dev); 83 unsigned int rotation = plane_state->hw.rotation; 84 int src_x, src_y; 85 u32 offset; 86 int ret; 87 88 ret = intel_plane_compute_gtt(plane_state); 89 if (ret) 90 return ret; 91 92 if (!plane_state->uapi.visible) 93 return 0; 94 95 src_x = plane_state->uapi.src.x1 >> 16; 96 src_y = plane_state->uapi.src.y1 >> 16; 97 98 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); 99 offset = intel_plane_compute_aligned_offset(&src_x, &src_y, 100 plane_state, 0); 101 102 if (src_x != 0 || src_y != 0) { 103 drm_dbg_kms(&dev_priv->drm, 104 "Arbitrary cursor panning not supported\n"); 105 return -EINVAL; 106 } 107 108 /* 109 * Put the final coordinates back so that the src 110 * coordinate checks will see the right values. 111 */ 112 drm_rect_translate_to(&plane_state->uapi.src, 113 src_x << 16, src_y << 16); 114 115 /* ILK+ do this automagically in hardware */ 116 if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) { 117 const struct drm_framebuffer *fb = plane_state->hw.fb; 118 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 119 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 120 121 offset += (src_h * src_w - 1) * fb->format->cpp[0]; 122 } 123 124 plane_state->view.color_plane[0].offset = offset; 125 plane_state->view.color_plane[0].x = src_x; 126 plane_state->view.color_plane[0].y = src_y; 127 128 return 0; 129 } 130 131 static int intel_check_cursor(struct intel_crtc_state *crtc_state, 132 struct intel_plane_state *plane_state) 133 { 134 const struct drm_framebuffer *fb = plane_state->hw.fb; 135 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 136 const struct drm_rect src = plane_state->uapi.src; 137 const struct drm_rect dst = plane_state->uapi.dst; 138 int ret; 139 140 if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) { 141 drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n"); 142 return -EINVAL; 143 } 144 145 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, 146 DRM_PLANE_HELPER_NO_SCALING, 147 DRM_PLANE_HELPER_NO_SCALING, 148 true); 149 if (ret) 150 return ret; 151 152 /* Use the unclipped src/dst rectangles, which we program to hw */ 153 plane_state->uapi.src = src; 154 plane_state->uapi.dst = dst; 155 156 ret = intel_cursor_check_surface(plane_state); 157 if (ret) 158 return ret; 159 160 if (!plane_state->uapi.visible) 161 return 0; 162 163 ret = intel_plane_check_src_coordinates(plane_state); 164 if (ret) 165 return ret; 166 167 return 0; 168 } 169 170 static unsigned int 171 i845_cursor_max_stride(struct intel_plane *plane, 172 u32 pixel_format, u64 modifier, 173 unsigned int rotation) 174 { 175 return 2048; 176 } 177 178 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) 179 { 180 u32 cntl = 0; 181 182 if (crtc_state->gamma_enable) 183 cntl |= CURSOR_PIPE_GAMMA_ENABLE; 184 185 return cntl; 186 } 187 188 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state, 189 const struct intel_plane_state *plane_state) 190 { 191 return CURSOR_ENABLE | 192 CURSOR_FORMAT_ARGB | 193 CURSOR_STRIDE(plane_state->view.color_plane[0].mapping_stride); 194 } 195 196 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state) 197 { 198 int width = drm_rect_width(&plane_state->uapi.dst); 199 200 /* 201 * 845g/865g are only limited by the width of their cursors, 202 * the height is arbitrary up to the precision of the register. 203 */ 204 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64); 205 } 206 207 static int i845_check_cursor(struct intel_crtc_state *crtc_state, 208 struct intel_plane_state *plane_state) 209 { 210 const struct drm_framebuffer *fb = plane_state->hw.fb; 211 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 212 int ret; 213 214 ret = intel_check_cursor(crtc_state, plane_state); 215 if (ret) 216 return ret; 217 218 /* if we want to turn off the cursor ignore width and height */ 219 if (!fb) 220 return 0; 221 222 /* Check for which cursor types we support */ 223 if (!i845_cursor_size_ok(plane_state)) { 224 drm_dbg_kms(&i915->drm, 225 "Cursor dimension %dx%d not supported\n", 226 drm_rect_width(&plane_state->uapi.dst), 227 drm_rect_height(&plane_state->uapi.dst)); 228 return -EINVAL; 229 } 230 231 drm_WARN_ON(&i915->drm, plane_state->uapi.visible && 232 plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]); 233 234 switch (fb->pitches[0]) { 235 case 256: 236 case 512: 237 case 1024: 238 case 2048: 239 break; 240 default: 241 drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n", 242 fb->pitches[0]); 243 return -EINVAL; 244 } 245 246 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state); 247 248 return 0; 249 } 250 251 /* TODO: split into noarm+arm pair */ 252 static void i845_cursor_update_arm(struct intel_plane *plane, 253 const struct intel_crtc_state *crtc_state, 254 const struct intel_plane_state *plane_state) 255 { 256 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 257 u32 cntl = 0, base = 0, pos = 0, size = 0; 258 unsigned long irqflags; 259 260 if (plane_state && plane_state->uapi.visible) { 261 unsigned int width = drm_rect_width(&plane_state->uapi.dst); 262 unsigned int height = drm_rect_height(&plane_state->uapi.dst); 263 264 cntl = plane_state->ctl | 265 i845_cursor_ctl_crtc(crtc_state); 266 267 size = CURSOR_HEIGHT(height) | CURSOR_WIDTH(width); 268 269 base = intel_cursor_base(plane_state); 270 pos = intel_cursor_position(plane_state); 271 } 272 273 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 274 275 /* On these chipsets we can only modify the base/size/stride 276 * whilst the cursor is disabled. 277 */ 278 if (plane->cursor.base != base || 279 plane->cursor.size != size || 280 plane->cursor.cntl != cntl) { 281 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0); 282 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base); 283 intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size); 284 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); 285 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl); 286 287 plane->cursor.base = base; 288 plane->cursor.size = size; 289 plane->cursor.cntl = cntl; 290 } else { 291 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); 292 } 293 294 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 295 } 296 297 static void i845_cursor_disable_arm(struct intel_plane *plane, 298 const struct intel_crtc_state *crtc_state) 299 { 300 i845_cursor_update_arm(plane, crtc_state, NULL); 301 } 302 303 static bool i845_cursor_get_hw_state(struct intel_plane *plane, 304 enum pipe *pipe) 305 { 306 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 307 enum intel_display_power_domain power_domain; 308 intel_wakeref_t wakeref; 309 bool ret; 310 311 power_domain = POWER_DOMAIN_PIPE(PIPE_A); 312 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 313 if (!wakeref) 314 return false; 315 316 ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE; 317 318 *pipe = PIPE_A; 319 320 intel_display_power_put(dev_priv, power_domain, wakeref); 321 322 return ret; 323 } 324 325 static unsigned int 326 i9xx_cursor_max_stride(struct intel_plane *plane, 327 u32 pixel_format, u64 modifier, 328 unsigned int rotation) 329 { 330 return plane->base.dev->mode_config.cursor_width * 4; 331 } 332 333 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) 334 { 335 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 336 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 337 u32 cntl = 0; 338 339 if (DISPLAY_VER(dev_priv) >= 11) 340 return cntl; 341 342 if (crtc_state->gamma_enable) 343 cntl = MCURSOR_PIPE_GAMMA_ENABLE; 344 345 if (crtc_state->csc_enable) 346 cntl |= MCURSOR_PIPE_CSC_ENABLE; 347 348 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) 349 cntl |= MCURSOR_PIPE_SEL(crtc->pipe); 350 351 return cntl; 352 } 353 354 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, 355 const struct intel_plane_state *plane_state) 356 { 357 struct drm_i915_private *dev_priv = 358 to_i915(plane_state->uapi.plane->dev); 359 u32 cntl = 0; 360 361 if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) 362 cntl |= MCURSOR_TRICKLE_FEED_DISABLE; 363 364 switch (drm_rect_width(&plane_state->uapi.dst)) { 365 case 64: 366 cntl |= MCURSOR_MODE_64_ARGB_AX; 367 break; 368 case 128: 369 cntl |= MCURSOR_MODE_128_ARGB_AX; 370 break; 371 case 256: 372 cntl |= MCURSOR_MODE_256_ARGB_AX; 373 break; 374 default: 375 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst)); 376 return 0; 377 } 378 379 if (plane_state->hw.rotation & DRM_MODE_ROTATE_180) 380 cntl |= MCURSOR_ROTATE_180; 381 382 /* Wa_22012358565:adl-p */ 383 if (DISPLAY_VER(dev_priv) == 13) 384 cntl |= MCURSOR_ARB_SLOTS(1); 385 386 return cntl; 387 } 388 389 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state) 390 { 391 struct drm_i915_private *dev_priv = 392 to_i915(plane_state->uapi.plane->dev); 393 int width = drm_rect_width(&plane_state->uapi.dst); 394 int height = drm_rect_height(&plane_state->uapi.dst); 395 396 if (!intel_cursor_size_ok(plane_state)) 397 return false; 398 399 /* Cursor width is limited to a few power-of-two sizes */ 400 switch (width) { 401 case 256: 402 case 128: 403 case 64: 404 break; 405 default: 406 return false; 407 } 408 409 /* 410 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor 411 * height from 8 lines up to the cursor width, when the 412 * cursor is not rotated. Everything else requires square 413 * cursors. 414 */ 415 if (HAS_CUR_FBC(dev_priv) && 416 plane_state->hw.rotation & DRM_MODE_ROTATE_0) { 417 if (height < 8 || height > width) 418 return false; 419 } else { 420 if (height != width) 421 return false; 422 } 423 424 return true; 425 } 426 427 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state, 428 struct intel_plane_state *plane_state) 429 { 430 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 431 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 432 const struct drm_framebuffer *fb = plane_state->hw.fb; 433 enum pipe pipe = plane->pipe; 434 int ret; 435 436 ret = intel_check_cursor(crtc_state, plane_state); 437 if (ret) 438 return ret; 439 440 /* if we want to turn off the cursor ignore width and height */ 441 if (!fb) 442 return 0; 443 444 /* Check for which cursor types we support */ 445 if (!i9xx_cursor_size_ok(plane_state)) { 446 drm_dbg(&dev_priv->drm, 447 "Cursor dimension %dx%d not supported\n", 448 drm_rect_width(&plane_state->uapi.dst), 449 drm_rect_height(&plane_state->uapi.dst)); 450 return -EINVAL; 451 } 452 453 drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible && 454 plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]); 455 456 if (fb->pitches[0] != 457 drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) { 458 drm_dbg_kms(&dev_priv->drm, 459 "Invalid cursor stride (%u) (cursor width %d)\n", 460 fb->pitches[0], 461 drm_rect_width(&plane_state->uapi.dst)); 462 return -EINVAL; 463 } 464 465 /* 466 * There's something wrong with the cursor on CHV pipe C. 467 * If it straddles the left edge of the screen then 468 * moving it away from the edge or disabling it often 469 * results in a pipe underrun, and often that can lead to 470 * dead pipe (constant underrun reported, and it scans 471 * out just a solid color). To recover from that, the 472 * display power well must be turned off and on again. 473 * Refuse the put the cursor into that compromised position. 474 */ 475 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C && 476 plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) { 477 drm_dbg_kms(&dev_priv->drm, 478 "CHV cursor C not allowed to straddle the left screen edge\n"); 479 return -EINVAL; 480 } 481 482 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state); 483 484 return 0; 485 } 486 487 /* TODO: split into noarm+arm pair */ 488 static void i9xx_cursor_update_arm(struct intel_plane *plane, 489 const struct intel_crtc_state *crtc_state, 490 const struct intel_plane_state *plane_state) 491 { 492 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 493 enum pipe pipe = plane->pipe; 494 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0; 495 unsigned long irqflags; 496 497 if (plane_state && plane_state->uapi.visible) { 498 int width = drm_rect_width(&plane_state->uapi.dst); 499 int height = drm_rect_height(&plane_state->uapi.dst); 500 501 cntl = plane_state->ctl | 502 i9xx_cursor_ctl_crtc(crtc_state); 503 504 if (width != height) 505 fbc_ctl = CUR_FBC_EN | CUR_FBC_HEIGHT(height - 1); 506 507 base = intel_cursor_base(plane_state); 508 pos = intel_cursor_position(plane_state); 509 } 510 511 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 512 513 /* 514 * On some platforms writing CURCNTR first will also 515 * cause CURPOS to be armed by the CURBASE write. 516 * Without the CURCNTR write the CURPOS write would 517 * arm itself. Thus we always update CURCNTR before 518 * CURPOS. 519 * 520 * On other platforms CURPOS always requires the 521 * CURBASE write to arm the update. Additonally 522 * a write to any of the cursor register will cancel 523 * an already armed cursor update. Thus leaving out 524 * the CURBASE write after CURPOS could lead to a 525 * cursor that doesn't appear to move, or even change 526 * shape. Thus we always write CURBASE. 527 * 528 * The other registers are armed by the CURBASE write 529 * except when the plane is getting enabled at which time 530 * the CURCNTR write arms the update. 531 */ 532 533 if (DISPLAY_VER(dev_priv) >= 9) 534 skl_write_cursor_wm(plane, crtc_state); 535 536 if (plane_state) 537 intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, 0); 538 else 539 intel_psr2_disable_plane_sel_fetch(plane, crtc_state); 540 541 if (plane->cursor.base != base || 542 plane->cursor.size != fbc_ctl || 543 plane->cursor.cntl != cntl) { 544 if (HAS_CUR_FBC(dev_priv)) 545 intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe), 546 fbc_ctl); 547 intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl); 548 intel_de_write_fw(dev_priv, CURPOS(pipe), pos); 549 intel_de_write_fw(dev_priv, CURBASE(pipe), base); 550 551 plane->cursor.base = base; 552 plane->cursor.size = fbc_ctl; 553 plane->cursor.cntl = cntl; 554 } else { 555 intel_de_write_fw(dev_priv, CURPOS(pipe), pos); 556 intel_de_write_fw(dev_priv, CURBASE(pipe), base); 557 } 558 559 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 560 } 561 562 static void i9xx_cursor_disable_arm(struct intel_plane *plane, 563 const struct intel_crtc_state *crtc_state) 564 { 565 i9xx_cursor_update_arm(plane, crtc_state, NULL); 566 } 567 568 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane, 569 enum pipe *pipe) 570 { 571 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 572 enum intel_display_power_domain power_domain; 573 intel_wakeref_t wakeref; 574 bool ret; 575 u32 val; 576 577 /* 578 * Not 100% correct for planes that can move between pipes, 579 * but that's only the case for gen2-3 which don't have any 580 * display power wells. 581 */ 582 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 583 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 584 if (!wakeref) 585 return false; 586 587 val = intel_de_read(dev_priv, CURCNTR(plane->pipe)); 588 589 ret = val & MCURSOR_MODE_MASK; 590 591 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) 592 *pipe = plane->pipe; 593 else 594 *pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val); 595 596 intel_display_power_put(dev_priv, power_domain, wakeref); 597 598 return ret; 599 } 600 601 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane, 602 u32 format, u64 modifier) 603 { 604 if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) 605 return false; 606 607 return format == DRM_FORMAT_ARGB8888; 608 } 609 610 static int 611 intel_legacy_cursor_update(struct drm_plane *_plane, 612 struct drm_crtc *_crtc, 613 struct drm_framebuffer *fb, 614 int crtc_x, int crtc_y, 615 unsigned int crtc_w, unsigned int crtc_h, 616 u32 src_x, u32 src_y, 617 u32 src_w, u32 src_h, 618 struct drm_modeset_acquire_ctx *ctx) 619 { 620 struct intel_plane *plane = to_intel_plane(_plane); 621 struct intel_crtc *crtc = to_intel_crtc(_crtc); 622 struct intel_plane_state *old_plane_state = 623 to_intel_plane_state(plane->base.state); 624 struct intel_plane_state *new_plane_state; 625 struct intel_crtc_state *crtc_state = 626 to_intel_crtc_state(crtc->base.state); 627 struct intel_crtc_state *new_crtc_state; 628 int ret; 629 630 /* 631 * When crtc is inactive or there is a modeset pending, 632 * wait for it to complete in the slowpath. 633 * PSR2 selective fetch also requires the slow path as 634 * PSR2 plane and transcoder registers can only be updated during 635 * vblank. 636 * 637 * FIXME bigjoiner fastpath would be good 638 */ 639 if (!crtc_state->hw.active || intel_crtc_needs_modeset(crtc_state) || 640 crtc_state->update_pipe || crtc_state->bigjoiner) 641 goto slow; 642 643 /* 644 * Don't do an async update if there is an outstanding commit modifying 645 * the plane. This prevents our async update's changes from getting 646 * overridden by a previous synchronous update's state. 647 */ 648 if (old_plane_state->uapi.commit && 649 !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done)) 650 goto slow; 651 652 /* 653 * If any parameters change that may affect watermarks, 654 * take the slowpath. Only changing fb or position should be 655 * in the fastpath. 656 */ 657 if (old_plane_state->uapi.crtc != &crtc->base || 658 old_plane_state->uapi.src_w != src_w || 659 old_plane_state->uapi.src_h != src_h || 660 old_plane_state->uapi.crtc_w != crtc_w || 661 old_plane_state->uapi.crtc_h != crtc_h || 662 !old_plane_state->uapi.fb != !fb) 663 goto slow; 664 665 new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base)); 666 if (!new_plane_state) 667 return -ENOMEM; 668 669 new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base)); 670 if (!new_crtc_state) { 671 ret = -ENOMEM; 672 goto out_free; 673 } 674 675 drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb); 676 677 new_plane_state->uapi.src_x = src_x; 678 new_plane_state->uapi.src_y = src_y; 679 new_plane_state->uapi.src_w = src_w; 680 new_plane_state->uapi.src_h = src_h; 681 new_plane_state->uapi.crtc_x = crtc_x; 682 new_plane_state->uapi.crtc_y = crtc_y; 683 new_plane_state->uapi.crtc_w = crtc_w; 684 new_plane_state->uapi.crtc_h = crtc_h; 685 686 intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state, crtc); 687 688 ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state, 689 old_plane_state, new_plane_state); 690 if (ret) 691 goto out_free; 692 693 ret = intel_plane_pin_fb(new_plane_state); 694 if (ret) 695 goto out_free; 696 697 intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb), 698 ORIGIN_CURSOR_UPDATE); 699 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 700 to_intel_frontbuffer(new_plane_state->hw.fb), 701 plane->frontbuffer_bit); 702 703 /* Swap plane state */ 704 plane->base.state = &new_plane_state->uapi; 705 706 /* 707 * We cannot swap crtc_state as it may be in use by an atomic commit or 708 * page flip that's running simultaneously. If we swap crtc_state and 709 * destroy the old state, we will cause a use-after-free there. 710 * 711 * Only update active_planes, which is needed for our internal 712 * bookkeeping. Either value will do the right thing when updating 713 * planes atomically. If the cursor was part of the atomic update then 714 * we would have taken the slowpath. 715 */ 716 crtc_state->active_planes = new_crtc_state->active_planes; 717 718 if (new_plane_state->uapi.visible) { 719 intel_plane_update_noarm(plane, crtc_state, new_plane_state); 720 intel_plane_update_arm(plane, crtc_state, new_plane_state); 721 } else { 722 intel_plane_disable_arm(plane, crtc_state); 723 } 724 725 intel_plane_unpin_fb(old_plane_state); 726 727 out_free: 728 if (new_crtc_state) 729 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi); 730 if (ret) 731 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi); 732 else 733 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi); 734 return ret; 735 736 slow: 737 return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb, 738 crtc_x, crtc_y, crtc_w, crtc_h, 739 src_x, src_y, src_w, src_h, ctx); 740 } 741 742 static const struct drm_plane_funcs intel_cursor_plane_funcs = { 743 .update_plane = intel_legacy_cursor_update, 744 .disable_plane = drm_atomic_helper_disable_plane, 745 .destroy = intel_plane_destroy, 746 .atomic_duplicate_state = intel_plane_duplicate_state, 747 .atomic_destroy_state = intel_plane_destroy_state, 748 .format_mod_supported = intel_cursor_format_mod_supported, 749 }; 750 751 struct intel_plane * 752 intel_cursor_plane_create(struct drm_i915_private *dev_priv, 753 enum pipe pipe) 754 { 755 struct intel_plane *cursor; 756 int ret, zpos; 757 u64 *modifiers; 758 759 cursor = intel_plane_alloc(); 760 if (IS_ERR(cursor)) 761 return cursor; 762 763 cursor->pipe = pipe; 764 cursor->i9xx_plane = (enum i9xx_plane_id) pipe; 765 cursor->id = PLANE_CURSOR; 766 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id); 767 768 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { 769 cursor->max_stride = i845_cursor_max_stride; 770 cursor->update_arm = i845_cursor_update_arm; 771 cursor->disable_arm = i845_cursor_disable_arm; 772 cursor->get_hw_state = i845_cursor_get_hw_state; 773 cursor->check_plane = i845_check_cursor; 774 } else { 775 cursor->max_stride = i9xx_cursor_max_stride; 776 cursor->update_arm = i9xx_cursor_update_arm; 777 cursor->disable_arm = i9xx_cursor_disable_arm; 778 cursor->get_hw_state = i9xx_cursor_get_hw_state; 779 cursor->check_plane = i9xx_check_cursor; 780 } 781 782 cursor->cursor.base = ~0; 783 cursor->cursor.cntl = ~0; 784 785 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv)) 786 cursor->cursor.size = ~0; 787 788 modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_NONE); 789 790 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, 791 0, &intel_cursor_plane_funcs, 792 intel_cursor_formats, 793 ARRAY_SIZE(intel_cursor_formats), 794 modifiers, 795 DRM_PLANE_TYPE_CURSOR, 796 "cursor %c", pipe_name(pipe)); 797 798 kfree(modifiers); 799 800 if (ret) 801 goto fail; 802 803 if (DISPLAY_VER(dev_priv) >= 4) 804 drm_plane_create_rotation_property(&cursor->base, 805 DRM_MODE_ROTATE_0, 806 DRM_MODE_ROTATE_0 | 807 DRM_MODE_ROTATE_180); 808 809 zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1; 810 drm_plane_create_zpos_immutable_property(&cursor->base, zpos); 811 812 if (DISPLAY_VER(dev_priv) >= 12) 813 drm_plane_enable_fb_damage_clips(&cursor->base); 814 815 intel_plane_helper_add(cursor); 816 817 return cursor; 818 819 fail: 820 intel_plane_free(cursor); 821 822 return ERR_PTR(ret); 823 } 824