1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 #include <linux/kernel.h> 6 7 #include <drm/drm_atomic_helper.h> 8 #include <drm/drm_atomic_uapi.h> 9 #include <drm/drm_damage_helper.h> 10 #include <drm/drm_plane_helper.h> 11 #include <drm/drm_fourcc.h> 12 13 #include "intel_atomic.h" 14 #include "intel_atomic_plane.h" 15 #include "intel_cursor.h" 16 #include "intel_display_types.h" 17 #include "intel_display.h" 18 19 #include "intel_frontbuffer.h" 20 #include "intel_pm.h" 21 #include "intel_psr.h" 22 #include "intel_sprite.h" 23 24 /* Cursor formats */ 25 static const u32 intel_cursor_formats[] = { 26 DRM_FORMAT_ARGB8888, 27 }; 28 29 static const u64 cursor_format_modifiers[] = { 30 DRM_FORMAT_MOD_LINEAR, 31 DRM_FORMAT_MOD_INVALID 32 }; 33 34 static u32 intel_cursor_base(const struct intel_plane_state *plane_state) 35 { 36 struct drm_i915_private *dev_priv = 37 to_i915(plane_state->uapi.plane->dev); 38 const struct drm_framebuffer *fb = plane_state->hw.fb; 39 const struct drm_i915_gem_object *obj = intel_fb_obj(fb); 40 u32 base; 41 42 if (INTEL_INFO(dev_priv)->display.cursor_needs_physical) 43 base = sg_dma_address(obj->mm.pages->sgl); 44 else 45 base = intel_plane_ggtt_offset(plane_state); 46 47 return base + plane_state->color_plane[0].offset; 48 } 49 50 static u32 intel_cursor_position(const struct intel_plane_state *plane_state) 51 { 52 int x = plane_state->uapi.dst.x1; 53 int y = plane_state->uapi.dst.y1; 54 u32 pos = 0; 55 56 if (x < 0) { 57 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; 58 x = -x; 59 } 60 pos |= x << CURSOR_X_SHIFT; 61 62 if (y < 0) { 63 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; 64 y = -y; 65 } 66 pos |= y << CURSOR_Y_SHIFT; 67 68 return pos; 69 } 70 71 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state) 72 { 73 const struct drm_mode_config *config = 74 &plane_state->uapi.plane->dev->mode_config; 75 int width = drm_rect_width(&plane_state->uapi.dst); 76 int height = drm_rect_height(&plane_state->uapi.dst); 77 78 return width > 0 && width <= config->cursor_width && 79 height > 0 && height <= config->cursor_height; 80 } 81 82 static int intel_cursor_check_surface(struct intel_plane_state *plane_state) 83 { 84 struct drm_i915_private *dev_priv = 85 to_i915(plane_state->uapi.plane->dev); 86 unsigned int rotation = plane_state->hw.rotation; 87 int src_x, src_y; 88 u32 offset; 89 int ret; 90 91 ret = intel_plane_compute_gtt(plane_state); 92 if (ret) 93 return ret; 94 95 if (!plane_state->uapi.visible) 96 return 0; 97 98 src_x = plane_state->uapi.src.x1 >> 16; 99 src_y = plane_state->uapi.src.y1 >> 16; 100 101 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); 102 offset = intel_plane_compute_aligned_offset(&src_x, &src_y, 103 plane_state, 0); 104 105 if (src_x != 0 || src_y != 0) { 106 drm_dbg_kms(&dev_priv->drm, 107 "Arbitrary cursor panning not supported\n"); 108 return -EINVAL; 109 } 110 111 /* 112 * Put the final coordinates back so that the src 113 * coordinate checks will see the right values. 114 */ 115 drm_rect_translate_to(&plane_state->uapi.src, 116 src_x << 16, src_y << 16); 117 118 /* ILK+ do this automagically in hardware */ 119 if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) { 120 const struct drm_framebuffer *fb = plane_state->hw.fb; 121 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 122 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 123 124 offset += (src_h * src_w - 1) * fb->format->cpp[0]; 125 } 126 127 plane_state->color_plane[0].offset = offset; 128 plane_state->color_plane[0].x = src_x; 129 plane_state->color_plane[0].y = src_y; 130 131 return 0; 132 } 133 134 static int intel_check_cursor(struct intel_crtc_state *crtc_state, 135 struct intel_plane_state *plane_state) 136 { 137 const struct drm_framebuffer *fb = plane_state->hw.fb; 138 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 139 const struct drm_rect src = plane_state->uapi.src; 140 const struct drm_rect dst = plane_state->uapi.dst; 141 int ret; 142 143 if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) { 144 drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n"); 145 return -EINVAL; 146 } 147 148 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, 149 DRM_PLANE_HELPER_NO_SCALING, 150 DRM_PLANE_HELPER_NO_SCALING, 151 true); 152 if (ret) 153 return ret; 154 155 /* Use the unclipped src/dst rectangles, which we program to hw */ 156 plane_state->uapi.src = src; 157 plane_state->uapi.dst = dst; 158 159 ret = intel_cursor_check_surface(plane_state); 160 if (ret) 161 return ret; 162 163 if (!plane_state->uapi.visible) 164 return 0; 165 166 ret = intel_plane_check_src_coordinates(plane_state); 167 if (ret) 168 return ret; 169 170 return 0; 171 } 172 173 static unsigned int 174 i845_cursor_max_stride(struct intel_plane *plane, 175 u32 pixel_format, u64 modifier, 176 unsigned int rotation) 177 { 178 return 2048; 179 } 180 181 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) 182 { 183 u32 cntl = 0; 184 185 if (crtc_state->gamma_enable) 186 cntl |= CURSOR_GAMMA_ENABLE; 187 188 return cntl; 189 } 190 191 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state, 192 const struct intel_plane_state *plane_state) 193 { 194 return CURSOR_ENABLE | 195 CURSOR_FORMAT_ARGB | 196 CURSOR_STRIDE(plane_state->color_plane[0].stride); 197 } 198 199 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state) 200 { 201 int width = drm_rect_width(&plane_state->uapi.dst); 202 203 /* 204 * 845g/865g are only limited by the width of their cursors, 205 * the height is arbitrary up to the precision of the register. 206 */ 207 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64); 208 } 209 210 static int i845_check_cursor(struct intel_crtc_state *crtc_state, 211 struct intel_plane_state *plane_state) 212 { 213 const struct drm_framebuffer *fb = plane_state->hw.fb; 214 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 215 int ret; 216 217 ret = intel_check_cursor(crtc_state, plane_state); 218 if (ret) 219 return ret; 220 221 /* if we want to turn off the cursor ignore width and height */ 222 if (!fb) 223 return 0; 224 225 /* Check for which cursor types we support */ 226 if (!i845_cursor_size_ok(plane_state)) { 227 drm_dbg_kms(&i915->drm, 228 "Cursor dimension %dx%d not supported\n", 229 drm_rect_width(&plane_state->uapi.dst), 230 drm_rect_height(&plane_state->uapi.dst)); 231 return -EINVAL; 232 } 233 234 drm_WARN_ON(&i915->drm, plane_state->uapi.visible && 235 plane_state->color_plane[0].stride != fb->pitches[0]); 236 237 switch (fb->pitches[0]) { 238 case 256: 239 case 512: 240 case 1024: 241 case 2048: 242 break; 243 default: 244 drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n", 245 fb->pitches[0]); 246 return -EINVAL; 247 } 248 249 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state); 250 251 return 0; 252 } 253 254 static void i845_update_cursor(struct intel_plane *plane, 255 const struct intel_crtc_state *crtc_state, 256 const struct intel_plane_state *plane_state) 257 { 258 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 259 u32 cntl = 0, base = 0, pos = 0, size = 0; 260 unsigned long irqflags; 261 262 if (plane_state && plane_state->uapi.visible) { 263 unsigned int width = drm_rect_width(&plane_state->uapi.dst); 264 unsigned int height = drm_rect_height(&plane_state->uapi.dst); 265 266 cntl = plane_state->ctl | 267 i845_cursor_ctl_crtc(crtc_state); 268 269 size = (height << 12) | width; 270 271 base = intel_cursor_base(plane_state); 272 pos = intel_cursor_position(plane_state); 273 } 274 275 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 276 277 /* On these chipsets we can only modify the base/size/stride 278 * whilst the cursor is disabled. 279 */ 280 if (plane->cursor.base != base || 281 plane->cursor.size != size || 282 plane->cursor.cntl != cntl) { 283 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0); 284 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base); 285 intel_de_write_fw(dev_priv, CURSIZE, size); 286 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); 287 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl); 288 289 plane->cursor.base = base; 290 plane->cursor.size = size; 291 plane->cursor.cntl = cntl; 292 } else { 293 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); 294 } 295 296 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 297 } 298 299 static void i845_disable_cursor(struct intel_plane *plane, 300 const struct intel_crtc_state *crtc_state) 301 { 302 i845_update_cursor(plane, crtc_state, NULL); 303 } 304 305 static bool i845_cursor_get_hw_state(struct intel_plane *plane, 306 enum pipe *pipe) 307 { 308 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 309 enum intel_display_power_domain power_domain; 310 intel_wakeref_t wakeref; 311 bool ret; 312 313 power_domain = POWER_DOMAIN_PIPE(PIPE_A); 314 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 315 if (!wakeref) 316 return false; 317 318 ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE; 319 320 *pipe = PIPE_A; 321 322 intel_display_power_put(dev_priv, power_domain, wakeref); 323 324 return ret; 325 } 326 327 static unsigned int 328 i9xx_cursor_max_stride(struct intel_plane *plane, 329 u32 pixel_format, u64 modifier, 330 unsigned int rotation) 331 { 332 return plane->base.dev->mode_config.cursor_width * 4; 333 } 334 335 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) 336 { 337 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 338 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 339 u32 cntl = 0; 340 341 if (INTEL_GEN(dev_priv) >= 11) 342 return cntl; 343 344 if (crtc_state->gamma_enable) 345 cntl = MCURSOR_GAMMA_ENABLE; 346 347 if (crtc_state->csc_enable) 348 cntl |= MCURSOR_PIPE_CSC_ENABLE; 349 350 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) 351 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe); 352 353 return cntl; 354 } 355 356 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, 357 const struct intel_plane_state *plane_state) 358 { 359 struct drm_i915_private *dev_priv = 360 to_i915(plane_state->uapi.plane->dev); 361 u32 cntl = 0; 362 363 if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) 364 cntl |= MCURSOR_TRICKLE_FEED_DISABLE; 365 366 switch (drm_rect_width(&plane_state->uapi.dst)) { 367 case 64: 368 cntl |= MCURSOR_MODE_64_ARGB_AX; 369 break; 370 case 128: 371 cntl |= MCURSOR_MODE_128_ARGB_AX; 372 break; 373 case 256: 374 cntl |= MCURSOR_MODE_256_ARGB_AX; 375 break; 376 default: 377 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst)); 378 return 0; 379 } 380 381 if (plane_state->hw.rotation & DRM_MODE_ROTATE_180) 382 cntl |= MCURSOR_ROTATE_180; 383 384 return cntl; 385 } 386 387 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state) 388 { 389 struct drm_i915_private *dev_priv = 390 to_i915(plane_state->uapi.plane->dev); 391 int width = drm_rect_width(&plane_state->uapi.dst); 392 int height = drm_rect_height(&plane_state->uapi.dst); 393 394 if (!intel_cursor_size_ok(plane_state)) 395 return false; 396 397 /* Cursor width is limited to a few power-of-two sizes */ 398 switch (width) { 399 case 256: 400 case 128: 401 case 64: 402 break; 403 default: 404 return false; 405 } 406 407 /* 408 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor 409 * height from 8 lines up to the cursor width, when the 410 * cursor is not rotated. Everything else requires square 411 * cursors. 412 */ 413 if (HAS_CUR_FBC(dev_priv) && 414 plane_state->hw.rotation & DRM_MODE_ROTATE_0) { 415 if (height < 8 || height > width) 416 return false; 417 } else { 418 if (height != width) 419 return false; 420 } 421 422 return true; 423 } 424 425 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state, 426 struct intel_plane_state *plane_state) 427 { 428 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 429 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 430 const struct drm_framebuffer *fb = plane_state->hw.fb; 431 enum pipe pipe = plane->pipe; 432 int ret; 433 434 ret = intel_check_cursor(crtc_state, plane_state); 435 if (ret) 436 return ret; 437 438 /* if we want to turn off the cursor ignore width and height */ 439 if (!fb) 440 return 0; 441 442 /* Check for which cursor types we support */ 443 if (!i9xx_cursor_size_ok(plane_state)) { 444 drm_dbg(&dev_priv->drm, 445 "Cursor dimension %dx%d not supported\n", 446 drm_rect_width(&plane_state->uapi.dst), 447 drm_rect_height(&plane_state->uapi.dst)); 448 return -EINVAL; 449 } 450 451 drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible && 452 plane_state->color_plane[0].stride != fb->pitches[0]); 453 454 if (fb->pitches[0] != 455 drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) { 456 drm_dbg_kms(&dev_priv->drm, 457 "Invalid cursor stride (%u) (cursor width %d)\n", 458 fb->pitches[0], 459 drm_rect_width(&plane_state->uapi.dst)); 460 return -EINVAL; 461 } 462 463 /* 464 * There's something wrong with the cursor on CHV pipe C. 465 * If it straddles the left edge of the screen then 466 * moving it away from the edge or disabling it often 467 * results in a pipe underrun, and often that can lead to 468 * dead pipe (constant underrun reported, and it scans 469 * out just a solid color). To recover from that, the 470 * display power well must be turned off and on again. 471 * Refuse the put the cursor into that compromised position. 472 */ 473 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C && 474 plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) { 475 drm_dbg_kms(&dev_priv->drm, 476 "CHV cursor C not allowed to straddle the left screen edge\n"); 477 return -EINVAL; 478 } 479 480 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state); 481 482 return 0; 483 } 484 485 static void i9xx_update_cursor(struct intel_plane *plane, 486 const struct intel_crtc_state *crtc_state, 487 const struct intel_plane_state *plane_state) 488 { 489 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 490 enum pipe pipe = plane->pipe; 491 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0; 492 unsigned long irqflags; 493 494 if (plane_state && plane_state->uapi.visible) { 495 int width = drm_rect_width(&plane_state->uapi.dst); 496 int height = drm_rect_height(&plane_state->uapi.dst); 497 498 cntl = plane_state->ctl | 499 i9xx_cursor_ctl_crtc(crtc_state); 500 501 if (width != height) 502 fbc_ctl = CUR_FBC_CTL_EN | (height - 1); 503 504 base = intel_cursor_base(plane_state); 505 pos = intel_cursor_position(plane_state); 506 } 507 508 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 509 510 /* 511 * On some platforms writing CURCNTR first will also 512 * cause CURPOS to be armed by the CURBASE write. 513 * Without the CURCNTR write the CURPOS write would 514 * arm itself. Thus we always update CURCNTR before 515 * CURPOS. 516 * 517 * On other platforms CURPOS always requires the 518 * CURBASE write to arm the update. Additonally 519 * a write to any of the cursor register will cancel 520 * an already armed cursor update. Thus leaving out 521 * the CURBASE write after CURPOS could lead to a 522 * cursor that doesn't appear to move, or even change 523 * shape. Thus we always write CURBASE. 524 * 525 * The other registers are armed by the CURBASE write 526 * except when the plane is getting enabled at which time 527 * the CURCNTR write arms the update. 528 */ 529 530 if (INTEL_GEN(dev_priv) >= 9) 531 skl_write_cursor_wm(plane, crtc_state); 532 533 if (!intel_crtc_needs_modeset(crtc_state)) 534 intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, 0); 535 536 if (plane->cursor.base != base || 537 plane->cursor.size != fbc_ctl || 538 plane->cursor.cntl != cntl) { 539 if (HAS_CUR_FBC(dev_priv)) 540 intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe), 541 fbc_ctl); 542 intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl); 543 intel_de_write_fw(dev_priv, CURPOS(pipe), pos); 544 intel_de_write_fw(dev_priv, CURBASE(pipe), base); 545 546 plane->cursor.base = base; 547 plane->cursor.size = fbc_ctl; 548 plane->cursor.cntl = cntl; 549 } else { 550 intel_de_write_fw(dev_priv, CURPOS(pipe), pos); 551 intel_de_write_fw(dev_priv, CURBASE(pipe), base); 552 } 553 554 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 555 } 556 557 static void i9xx_disable_cursor(struct intel_plane *plane, 558 const struct intel_crtc_state *crtc_state) 559 { 560 i9xx_update_cursor(plane, crtc_state, NULL); 561 } 562 563 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane, 564 enum pipe *pipe) 565 { 566 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 567 enum intel_display_power_domain power_domain; 568 intel_wakeref_t wakeref; 569 bool ret; 570 u32 val; 571 572 /* 573 * Not 100% correct for planes that can move between pipes, 574 * but that's only the case for gen2-3 which don't have any 575 * display power wells. 576 */ 577 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 578 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 579 if (!wakeref) 580 return false; 581 582 val = intel_de_read(dev_priv, CURCNTR(plane->pipe)); 583 584 ret = val & MCURSOR_MODE; 585 586 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) 587 *pipe = plane->pipe; 588 else 589 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >> 590 MCURSOR_PIPE_SELECT_SHIFT; 591 592 intel_display_power_put(dev_priv, power_domain, wakeref); 593 594 return ret; 595 } 596 597 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane, 598 u32 format, u64 modifier) 599 { 600 return modifier == DRM_FORMAT_MOD_LINEAR && 601 format == DRM_FORMAT_ARGB8888; 602 } 603 604 static int 605 intel_legacy_cursor_update(struct drm_plane *_plane, 606 struct drm_crtc *_crtc, 607 struct drm_framebuffer *fb, 608 int crtc_x, int crtc_y, 609 unsigned int crtc_w, unsigned int crtc_h, 610 u32 src_x, u32 src_y, 611 u32 src_w, u32 src_h, 612 struct drm_modeset_acquire_ctx *ctx) 613 { 614 struct intel_plane *plane = to_intel_plane(_plane); 615 struct intel_crtc *crtc = to_intel_crtc(_crtc); 616 struct intel_plane_state *old_plane_state = 617 to_intel_plane_state(plane->base.state); 618 struct intel_plane_state *new_plane_state; 619 struct intel_crtc_state *crtc_state = 620 to_intel_crtc_state(crtc->base.state); 621 struct intel_crtc_state *new_crtc_state; 622 int ret; 623 624 /* 625 * When crtc is inactive or there is a modeset pending, 626 * wait for it to complete in the slowpath 627 * 628 * FIXME bigjoiner fastpath would be good 629 */ 630 if (!crtc_state->hw.active || intel_crtc_needs_modeset(crtc_state) || 631 crtc_state->update_pipe || crtc_state->bigjoiner) 632 goto slow; 633 634 /* 635 * Don't do an async update if there is an outstanding commit modifying 636 * the plane. This prevents our async update's changes from getting 637 * overridden by a previous synchronous update's state. 638 */ 639 if (old_plane_state->uapi.commit && 640 !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done)) 641 goto slow; 642 643 /* 644 * If any parameters change that may affect watermarks, 645 * take the slowpath. Only changing fb or position should be 646 * in the fastpath. 647 */ 648 if (old_plane_state->uapi.crtc != &crtc->base || 649 old_plane_state->uapi.src_w != src_w || 650 old_plane_state->uapi.src_h != src_h || 651 old_plane_state->uapi.crtc_w != crtc_w || 652 old_plane_state->uapi.crtc_h != crtc_h || 653 !old_plane_state->uapi.fb != !fb) 654 goto slow; 655 656 new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base)); 657 if (!new_plane_state) 658 return -ENOMEM; 659 660 new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base)); 661 if (!new_crtc_state) { 662 ret = -ENOMEM; 663 goto out_free; 664 } 665 666 drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb); 667 668 new_plane_state->uapi.src_x = src_x; 669 new_plane_state->uapi.src_y = src_y; 670 new_plane_state->uapi.src_w = src_w; 671 new_plane_state->uapi.src_h = src_h; 672 new_plane_state->uapi.crtc_x = crtc_x; 673 new_plane_state->uapi.crtc_y = crtc_y; 674 new_plane_state->uapi.crtc_w = crtc_w; 675 new_plane_state->uapi.crtc_h = crtc_h; 676 677 intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state, crtc); 678 679 ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state, 680 old_plane_state, new_plane_state); 681 if (ret) 682 goto out_free; 683 684 ret = intel_plane_pin_fb(new_plane_state); 685 if (ret) 686 goto out_free; 687 688 intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb), 689 ORIGIN_FLIP); 690 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 691 to_intel_frontbuffer(new_plane_state->hw.fb), 692 plane->frontbuffer_bit); 693 694 /* Swap plane state */ 695 plane->base.state = &new_plane_state->uapi; 696 697 /* 698 * We cannot swap crtc_state as it may be in use by an atomic commit or 699 * page flip that's running simultaneously. If we swap crtc_state and 700 * destroy the old state, we will cause a use-after-free there. 701 * 702 * Only update active_planes, which is needed for our internal 703 * bookkeeping. Either value will do the right thing when updating 704 * planes atomically. If the cursor was part of the atomic update then 705 * we would have taken the slowpath. 706 */ 707 crtc_state->active_planes = new_crtc_state->active_planes; 708 709 if (new_plane_state->uapi.visible) 710 intel_update_plane(plane, crtc_state, new_plane_state); 711 else 712 intel_disable_plane(plane, crtc_state); 713 714 intel_plane_unpin_fb(old_plane_state); 715 716 out_free: 717 if (new_crtc_state) 718 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi); 719 if (ret) 720 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi); 721 else 722 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi); 723 return ret; 724 725 slow: 726 return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb, 727 crtc_x, crtc_y, crtc_w, crtc_h, 728 src_x, src_y, src_w, src_h, ctx); 729 } 730 731 static const struct drm_plane_funcs intel_cursor_plane_funcs = { 732 .update_plane = intel_legacy_cursor_update, 733 .disable_plane = drm_atomic_helper_disable_plane, 734 .destroy = intel_plane_destroy, 735 .atomic_duplicate_state = intel_plane_duplicate_state, 736 .atomic_destroy_state = intel_plane_destroy_state, 737 .format_mod_supported = intel_cursor_format_mod_supported, 738 }; 739 740 struct intel_plane * 741 intel_cursor_plane_create(struct drm_i915_private *dev_priv, 742 enum pipe pipe) 743 { 744 struct intel_plane *cursor; 745 int ret, zpos; 746 747 cursor = intel_plane_alloc(); 748 if (IS_ERR(cursor)) 749 return cursor; 750 751 cursor->pipe = pipe; 752 cursor->i9xx_plane = (enum i9xx_plane_id) pipe; 753 cursor->id = PLANE_CURSOR; 754 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id); 755 756 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { 757 cursor->max_stride = i845_cursor_max_stride; 758 cursor->update_plane = i845_update_cursor; 759 cursor->disable_plane = i845_disable_cursor; 760 cursor->get_hw_state = i845_cursor_get_hw_state; 761 cursor->check_plane = i845_check_cursor; 762 } else { 763 cursor->max_stride = i9xx_cursor_max_stride; 764 cursor->update_plane = i9xx_update_cursor; 765 cursor->disable_plane = i9xx_disable_cursor; 766 cursor->get_hw_state = i9xx_cursor_get_hw_state; 767 cursor->check_plane = i9xx_check_cursor; 768 } 769 770 cursor->cursor.base = ~0; 771 cursor->cursor.cntl = ~0; 772 773 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv)) 774 cursor->cursor.size = ~0; 775 776 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, 777 0, &intel_cursor_plane_funcs, 778 intel_cursor_formats, 779 ARRAY_SIZE(intel_cursor_formats), 780 cursor_format_modifiers, 781 DRM_PLANE_TYPE_CURSOR, 782 "cursor %c", pipe_name(pipe)); 783 if (ret) 784 goto fail; 785 786 if (INTEL_GEN(dev_priv) >= 4) 787 drm_plane_create_rotation_property(&cursor->base, 788 DRM_MODE_ROTATE_0, 789 DRM_MODE_ROTATE_0 | 790 DRM_MODE_ROTATE_180); 791 792 zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1; 793 drm_plane_create_zpos_immutable_property(&cursor->base, zpos); 794 795 if (INTEL_GEN(dev_priv) >= 12) 796 drm_plane_enable_fb_damage_clips(&cursor->base); 797 798 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); 799 800 return cursor; 801 802 fail: 803 intel_plane_free(cursor); 804 805 return ERR_PTR(ret); 806 } 807