1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 #include <linux/kernel.h> 6 7 #include <drm/drm_atomic_helper.h> 8 #include <drm/drm_atomic_uapi.h> 9 #include <drm/drm_blend.h> 10 #include <drm/drm_damage_helper.h> 11 #include <drm/drm_fourcc.h> 12 13 #include "i915_reg.h" 14 #include "intel_atomic.h" 15 #include "intel_atomic_plane.h" 16 #include "intel_cursor.h" 17 #include "intel_de.h" 18 #include "intel_display.h" 19 #include "intel_display_types.h" 20 #include "intel_fb.h" 21 #include "intel_fb_pin.h" 22 #include "intel_frontbuffer.h" 23 #include "intel_psr.h" 24 #include "skl_watermark.h" 25 26 #include "gem/i915_gem_object.h" 27 28 /* Cursor formats */ 29 static const u32 intel_cursor_formats[] = { 30 DRM_FORMAT_ARGB8888, 31 }; 32 33 static u32 intel_cursor_base(const struct intel_plane_state *plane_state) 34 { 35 struct drm_i915_private *dev_priv = 36 to_i915(plane_state->uapi.plane->dev); 37 const struct drm_framebuffer *fb = plane_state->hw.fb; 38 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 39 u32 base; 40 41 if (DISPLAY_INFO(dev_priv)->cursor_needs_physical) 42 base = i915_gem_object_get_dma_address(obj, 0); 43 else 44 base = intel_plane_ggtt_offset(plane_state); 45 46 return base + plane_state->view.color_plane[0].offset; 47 } 48 49 static u32 intel_cursor_position(const struct intel_plane_state *plane_state) 50 { 51 int x = plane_state->uapi.dst.x1; 52 int y = plane_state->uapi.dst.y1; 53 u32 pos = 0; 54 55 if (x < 0) { 56 pos |= CURSOR_POS_X_SIGN; 57 x = -x; 58 } 59 pos |= CURSOR_POS_X(x); 60 61 if (y < 0) { 62 pos |= CURSOR_POS_Y_SIGN; 63 y = -y; 64 } 65 pos |= CURSOR_POS_Y(y); 66 67 return pos; 68 } 69 70 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state) 71 { 72 const struct drm_mode_config *config = 73 &plane_state->uapi.plane->dev->mode_config; 74 int width = drm_rect_width(&plane_state->uapi.dst); 75 int height = drm_rect_height(&plane_state->uapi.dst); 76 77 return width > 0 && width <= config->cursor_width && 78 height > 0 && height <= config->cursor_height; 79 } 80 81 static int intel_cursor_check_surface(struct intel_plane_state *plane_state) 82 { 83 struct drm_i915_private *dev_priv = 84 to_i915(plane_state->uapi.plane->dev); 85 unsigned int rotation = plane_state->hw.rotation; 86 int src_x, src_y; 87 u32 offset; 88 int ret; 89 90 ret = intel_plane_compute_gtt(plane_state); 91 if (ret) 92 return ret; 93 94 if (!plane_state->uapi.visible) 95 return 0; 96 97 src_x = plane_state->uapi.src.x1 >> 16; 98 src_y = plane_state->uapi.src.y1 >> 16; 99 100 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); 101 offset = intel_plane_compute_aligned_offset(&src_x, &src_y, 102 plane_state, 0); 103 104 if (src_x != 0 || src_y != 0) { 105 drm_dbg_kms(&dev_priv->drm, 106 "Arbitrary cursor panning not supported\n"); 107 return -EINVAL; 108 } 109 110 /* 111 * Put the final coordinates back so that the src 112 * coordinate checks will see the right values. 113 */ 114 drm_rect_translate_to(&plane_state->uapi.src, 115 src_x << 16, src_y << 16); 116 117 /* ILK+ do this automagically in hardware */ 118 if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) { 119 const struct drm_framebuffer *fb = plane_state->hw.fb; 120 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 121 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 122 123 offset += (src_h * src_w - 1) * fb->format->cpp[0]; 124 } 125 126 plane_state->view.color_plane[0].offset = offset; 127 plane_state->view.color_plane[0].x = src_x; 128 plane_state->view.color_plane[0].y = src_y; 129 130 return 0; 131 } 132 133 static int intel_check_cursor(struct intel_crtc_state *crtc_state, 134 struct intel_plane_state *plane_state) 135 { 136 const struct drm_framebuffer *fb = plane_state->hw.fb; 137 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 138 const struct drm_rect src = plane_state->uapi.src; 139 const struct drm_rect dst = plane_state->uapi.dst; 140 int ret; 141 142 if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) { 143 drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n"); 144 return -EINVAL; 145 } 146 147 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, 148 DRM_PLANE_NO_SCALING, 149 DRM_PLANE_NO_SCALING, 150 true); 151 if (ret) 152 return ret; 153 154 /* Use the unclipped src/dst rectangles, which we program to hw */ 155 plane_state->uapi.src = src; 156 plane_state->uapi.dst = dst; 157 158 /* final plane coordinates will be relative to the plane's pipe */ 159 drm_rect_translate(&plane_state->uapi.dst, 160 -crtc_state->pipe_src.x1, 161 -crtc_state->pipe_src.y1); 162 163 ret = intel_cursor_check_surface(plane_state); 164 if (ret) 165 return ret; 166 167 if (!plane_state->uapi.visible) 168 return 0; 169 170 ret = intel_plane_check_src_coordinates(plane_state); 171 if (ret) 172 return ret; 173 174 return 0; 175 } 176 177 static unsigned int 178 i845_cursor_max_stride(struct intel_plane *plane, 179 u32 pixel_format, u64 modifier, 180 unsigned int rotation) 181 { 182 return 2048; 183 } 184 185 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) 186 { 187 u32 cntl = 0; 188 189 if (crtc_state->gamma_enable) 190 cntl |= CURSOR_PIPE_GAMMA_ENABLE; 191 192 return cntl; 193 } 194 195 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state, 196 const struct intel_plane_state *plane_state) 197 { 198 return CURSOR_ENABLE | 199 CURSOR_FORMAT_ARGB | 200 CURSOR_STRIDE(plane_state->view.color_plane[0].mapping_stride); 201 } 202 203 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state) 204 { 205 int width = drm_rect_width(&plane_state->uapi.dst); 206 207 /* 208 * 845g/865g are only limited by the width of their cursors, 209 * the height is arbitrary up to the precision of the register. 210 */ 211 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64); 212 } 213 214 static int i845_check_cursor(struct intel_crtc_state *crtc_state, 215 struct intel_plane_state *plane_state) 216 { 217 const struct drm_framebuffer *fb = plane_state->hw.fb; 218 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 219 int ret; 220 221 ret = intel_check_cursor(crtc_state, plane_state); 222 if (ret) 223 return ret; 224 225 /* if we want to turn off the cursor ignore width and height */ 226 if (!fb) 227 return 0; 228 229 /* Check for which cursor types we support */ 230 if (!i845_cursor_size_ok(plane_state)) { 231 drm_dbg_kms(&i915->drm, 232 "Cursor dimension %dx%d not supported\n", 233 drm_rect_width(&plane_state->uapi.dst), 234 drm_rect_height(&plane_state->uapi.dst)); 235 return -EINVAL; 236 } 237 238 drm_WARN_ON(&i915->drm, plane_state->uapi.visible && 239 plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]); 240 241 switch (fb->pitches[0]) { 242 case 256: 243 case 512: 244 case 1024: 245 case 2048: 246 break; 247 default: 248 drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n", 249 fb->pitches[0]); 250 return -EINVAL; 251 } 252 253 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state); 254 255 return 0; 256 } 257 258 /* TODO: split into noarm+arm pair */ 259 static void i845_cursor_update_arm(struct intel_plane *plane, 260 const struct intel_crtc_state *crtc_state, 261 const struct intel_plane_state *plane_state) 262 { 263 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 264 u32 cntl = 0, base = 0, pos = 0, size = 0; 265 266 if (plane_state && plane_state->uapi.visible) { 267 unsigned int width = drm_rect_width(&plane_state->uapi.dst); 268 unsigned int height = drm_rect_height(&plane_state->uapi.dst); 269 270 cntl = plane_state->ctl | 271 i845_cursor_ctl_crtc(crtc_state); 272 273 size = CURSOR_HEIGHT(height) | CURSOR_WIDTH(width); 274 275 base = intel_cursor_base(plane_state); 276 pos = intel_cursor_position(plane_state); 277 } 278 279 /* On these chipsets we can only modify the base/size/stride 280 * whilst the cursor is disabled. 281 */ 282 if (plane->cursor.base != base || 283 plane->cursor.size != size || 284 plane->cursor.cntl != cntl) { 285 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0); 286 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base); 287 intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size); 288 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); 289 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl); 290 291 plane->cursor.base = base; 292 plane->cursor.size = size; 293 plane->cursor.cntl = cntl; 294 } else { 295 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); 296 } 297 } 298 299 static void i845_cursor_disable_arm(struct intel_plane *plane, 300 const struct intel_crtc_state *crtc_state) 301 { 302 i845_cursor_update_arm(plane, crtc_state, NULL); 303 } 304 305 static bool i845_cursor_get_hw_state(struct intel_plane *plane, 306 enum pipe *pipe) 307 { 308 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 309 enum intel_display_power_domain power_domain; 310 intel_wakeref_t wakeref; 311 bool ret; 312 313 power_domain = POWER_DOMAIN_PIPE(PIPE_A); 314 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 315 if (!wakeref) 316 return false; 317 318 ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE; 319 320 *pipe = PIPE_A; 321 322 intel_display_power_put(dev_priv, power_domain, wakeref); 323 324 return ret; 325 } 326 327 static unsigned int 328 i9xx_cursor_max_stride(struct intel_plane *plane, 329 u32 pixel_format, u64 modifier, 330 unsigned int rotation) 331 { 332 return plane->base.dev->mode_config.cursor_width * 4; 333 } 334 335 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) 336 { 337 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 338 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 339 u32 cntl = 0; 340 341 if (DISPLAY_VER(dev_priv) >= 11) 342 return cntl; 343 344 if (crtc_state->gamma_enable) 345 cntl = MCURSOR_PIPE_GAMMA_ENABLE; 346 347 if (crtc_state->csc_enable) 348 cntl |= MCURSOR_PIPE_CSC_ENABLE; 349 350 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) 351 cntl |= MCURSOR_PIPE_SEL(crtc->pipe); 352 353 return cntl; 354 } 355 356 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, 357 const struct intel_plane_state *plane_state) 358 { 359 struct drm_i915_private *dev_priv = 360 to_i915(plane_state->uapi.plane->dev); 361 u32 cntl = 0; 362 363 if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) 364 cntl |= MCURSOR_TRICKLE_FEED_DISABLE; 365 366 switch (drm_rect_width(&plane_state->uapi.dst)) { 367 case 64: 368 cntl |= MCURSOR_MODE_64_ARGB_AX; 369 break; 370 case 128: 371 cntl |= MCURSOR_MODE_128_ARGB_AX; 372 break; 373 case 256: 374 cntl |= MCURSOR_MODE_256_ARGB_AX; 375 break; 376 default: 377 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst)); 378 return 0; 379 } 380 381 if (plane_state->hw.rotation & DRM_MODE_ROTATE_180) 382 cntl |= MCURSOR_ROTATE_180; 383 384 /* Wa_22012358565:adl-p */ 385 if (DISPLAY_VER(dev_priv) == 13) 386 cntl |= MCURSOR_ARB_SLOTS(1); 387 388 return cntl; 389 } 390 391 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state) 392 { 393 struct drm_i915_private *dev_priv = 394 to_i915(plane_state->uapi.plane->dev); 395 int width = drm_rect_width(&plane_state->uapi.dst); 396 int height = drm_rect_height(&plane_state->uapi.dst); 397 398 if (!intel_cursor_size_ok(plane_state)) 399 return false; 400 401 /* Cursor width is limited to a few power-of-two sizes */ 402 switch (width) { 403 case 256: 404 case 128: 405 case 64: 406 break; 407 default: 408 return false; 409 } 410 411 /* 412 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor 413 * height from 8 lines up to the cursor width, when the 414 * cursor is not rotated. Everything else requires square 415 * cursors. 416 */ 417 if (HAS_CUR_FBC(dev_priv) && 418 plane_state->hw.rotation & DRM_MODE_ROTATE_0) { 419 if (height < 8 || height > width) 420 return false; 421 } else { 422 if (height != width) 423 return false; 424 } 425 426 return true; 427 } 428 429 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state, 430 struct intel_plane_state *plane_state) 431 { 432 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 433 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 434 const struct drm_framebuffer *fb = plane_state->hw.fb; 435 enum pipe pipe = plane->pipe; 436 int ret; 437 438 ret = intel_check_cursor(crtc_state, plane_state); 439 if (ret) 440 return ret; 441 442 /* if we want to turn off the cursor ignore width and height */ 443 if (!fb) 444 return 0; 445 446 /* Check for which cursor types we support */ 447 if (!i9xx_cursor_size_ok(plane_state)) { 448 drm_dbg(&dev_priv->drm, 449 "Cursor dimension %dx%d not supported\n", 450 drm_rect_width(&plane_state->uapi.dst), 451 drm_rect_height(&plane_state->uapi.dst)); 452 return -EINVAL; 453 } 454 455 drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible && 456 plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]); 457 458 if (fb->pitches[0] != 459 drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) { 460 drm_dbg_kms(&dev_priv->drm, 461 "Invalid cursor stride (%u) (cursor width %d)\n", 462 fb->pitches[0], 463 drm_rect_width(&plane_state->uapi.dst)); 464 return -EINVAL; 465 } 466 467 /* 468 * There's something wrong with the cursor on CHV pipe C. 469 * If it straddles the left edge of the screen then 470 * moving it away from the edge or disabling it often 471 * results in a pipe underrun, and often that can lead to 472 * dead pipe (constant underrun reported, and it scans 473 * out just a solid color). To recover from that, the 474 * display power well must be turned off and on again. 475 * Refuse the put the cursor into that compromised position. 476 */ 477 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C && 478 plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) { 479 drm_dbg_kms(&dev_priv->drm, 480 "CHV cursor C not allowed to straddle the left screen edge\n"); 481 return -EINVAL; 482 } 483 484 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state); 485 486 return 0; 487 } 488 489 /* TODO: split into noarm+arm pair */ 490 static void i9xx_cursor_update_arm(struct intel_plane *plane, 491 const struct intel_crtc_state *crtc_state, 492 const struct intel_plane_state *plane_state) 493 { 494 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 495 enum pipe pipe = plane->pipe; 496 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0; 497 498 if (plane_state && plane_state->uapi.visible) { 499 int width = drm_rect_width(&plane_state->uapi.dst); 500 int height = drm_rect_height(&plane_state->uapi.dst); 501 502 cntl = plane_state->ctl | 503 i9xx_cursor_ctl_crtc(crtc_state); 504 505 if (width != height) 506 fbc_ctl = CUR_FBC_EN | CUR_FBC_HEIGHT(height - 1); 507 508 base = intel_cursor_base(plane_state); 509 pos = intel_cursor_position(plane_state); 510 } 511 512 /* 513 * On some platforms writing CURCNTR first will also 514 * cause CURPOS to be armed by the CURBASE write. 515 * Without the CURCNTR write the CURPOS write would 516 * arm itself. Thus we always update CURCNTR before 517 * CURPOS. 518 * 519 * On other platforms CURPOS always requires the 520 * CURBASE write to arm the update. Additonally 521 * a write to any of the cursor register will cancel 522 * an already armed cursor update. Thus leaving out 523 * the CURBASE write after CURPOS could lead to a 524 * cursor that doesn't appear to move, or even change 525 * shape. Thus we always write CURBASE. 526 * 527 * The other registers are armed by the CURBASE write 528 * except when the plane is getting enabled at which time 529 * the CURCNTR write arms the update. 530 */ 531 532 if (DISPLAY_VER(dev_priv) >= 9) 533 skl_write_cursor_wm(plane, crtc_state); 534 535 if (plane_state) 536 intel_psr2_program_plane_sel_fetch_arm(plane, crtc_state, 537 plane_state); 538 else 539 intel_psr2_disable_plane_sel_fetch_arm(plane, crtc_state); 540 541 if (plane->cursor.base != base || 542 plane->cursor.size != fbc_ctl || 543 plane->cursor.cntl != cntl) { 544 if (HAS_CUR_FBC(dev_priv)) 545 intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe), 546 fbc_ctl); 547 intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl); 548 intel_de_write_fw(dev_priv, CURPOS(pipe), pos); 549 intel_de_write_fw(dev_priv, CURBASE(pipe), base); 550 551 plane->cursor.base = base; 552 plane->cursor.size = fbc_ctl; 553 plane->cursor.cntl = cntl; 554 } else { 555 intel_de_write_fw(dev_priv, CURPOS(pipe), pos); 556 intel_de_write_fw(dev_priv, CURBASE(pipe), base); 557 } 558 } 559 560 static void i9xx_cursor_disable_arm(struct intel_plane *plane, 561 const struct intel_crtc_state *crtc_state) 562 { 563 i9xx_cursor_update_arm(plane, crtc_state, NULL); 564 } 565 566 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane, 567 enum pipe *pipe) 568 { 569 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 570 enum intel_display_power_domain power_domain; 571 intel_wakeref_t wakeref; 572 bool ret; 573 u32 val; 574 575 /* 576 * Not 100% correct for planes that can move between pipes, 577 * but that's only the case for gen2-3 which don't have any 578 * display power wells. 579 */ 580 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 581 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 582 if (!wakeref) 583 return false; 584 585 val = intel_de_read(dev_priv, CURCNTR(plane->pipe)); 586 587 ret = val & MCURSOR_MODE_MASK; 588 589 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) 590 *pipe = plane->pipe; 591 else 592 *pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val); 593 594 intel_display_power_put(dev_priv, power_domain, wakeref); 595 596 return ret; 597 } 598 599 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane, 600 u32 format, u64 modifier) 601 { 602 if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) 603 return false; 604 605 return format == DRM_FORMAT_ARGB8888; 606 } 607 608 static int 609 intel_legacy_cursor_update(struct drm_plane *_plane, 610 struct drm_crtc *_crtc, 611 struct drm_framebuffer *fb, 612 int crtc_x, int crtc_y, 613 unsigned int crtc_w, unsigned int crtc_h, 614 u32 src_x, u32 src_y, 615 u32 src_w, u32 src_h, 616 struct drm_modeset_acquire_ctx *ctx) 617 { 618 struct intel_plane *plane = to_intel_plane(_plane); 619 struct intel_crtc *crtc = to_intel_crtc(_crtc); 620 struct intel_plane_state *old_plane_state = 621 to_intel_plane_state(plane->base.state); 622 struct intel_plane_state *new_plane_state; 623 struct intel_crtc_state *crtc_state = 624 to_intel_crtc_state(crtc->base.state); 625 struct intel_crtc_state *new_crtc_state; 626 int ret; 627 628 /* 629 * When crtc is inactive or there is a modeset pending, 630 * wait for it to complete in the slowpath. 631 * PSR2 selective fetch also requires the slow path as 632 * PSR2 plane and transcoder registers can only be updated during 633 * vblank. 634 * 635 * FIXME bigjoiner fastpath would be good 636 */ 637 if (!crtc_state->hw.active || 638 intel_crtc_needs_modeset(crtc_state) || 639 intel_crtc_needs_fastset(crtc_state) || 640 crtc_state->bigjoiner_pipes) 641 goto slow; 642 643 /* 644 * Don't do an async update if there is an outstanding commit modifying 645 * the plane. This prevents our async update's changes from getting 646 * overridden by a previous synchronous update's state. 647 */ 648 if (old_plane_state->uapi.commit && 649 !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done)) 650 goto slow; 651 652 /* 653 * If any parameters change that may affect watermarks, 654 * take the slowpath. Only changing fb or position should be 655 * in the fastpath. 656 */ 657 if (old_plane_state->uapi.crtc != &crtc->base || 658 old_plane_state->uapi.src_w != src_w || 659 old_plane_state->uapi.src_h != src_h || 660 old_plane_state->uapi.crtc_w != crtc_w || 661 old_plane_state->uapi.crtc_h != crtc_h || 662 !old_plane_state->uapi.fb != !fb) 663 goto slow; 664 665 new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base)); 666 if (!new_plane_state) 667 return -ENOMEM; 668 669 new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base)); 670 if (!new_crtc_state) { 671 ret = -ENOMEM; 672 goto out_free; 673 } 674 675 drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb); 676 677 new_plane_state->uapi.src_x = src_x; 678 new_plane_state->uapi.src_y = src_y; 679 new_plane_state->uapi.src_w = src_w; 680 new_plane_state->uapi.src_h = src_h; 681 new_plane_state->uapi.crtc_x = crtc_x; 682 new_plane_state->uapi.crtc_y = crtc_y; 683 new_plane_state->uapi.crtc_w = crtc_w; 684 new_plane_state->uapi.crtc_h = crtc_h; 685 686 intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state, crtc); 687 688 ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state, 689 old_plane_state, new_plane_state); 690 if (ret) 691 goto out_free; 692 693 ret = intel_plane_pin_fb(new_plane_state); 694 if (ret) 695 goto out_free; 696 697 intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb), 698 ORIGIN_CURSOR_UPDATE); 699 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 700 to_intel_frontbuffer(new_plane_state->hw.fb), 701 plane->frontbuffer_bit); 702 703 /* Swap plane state */ 704 plane->base.state = &new_plane_state->uapi; 705 706 /* 707 * We cannot swap crtc_state as it may be in use by an atomic commit or 708 * page flip that's running simultaneously. If we swap crtc_state and 709 * destroy the old state, we will cause a use-after-free there. 710 * 711 * Only update active_planes, which is needed for our internal 712 * bookkeeping. Either value will do the right thing when updating 713 * planes atomically. If the cursor was part of the atomic update then 714 * we would have taken the slowpath. 715 */ 716 crtc_state->active_planes = new_crtc_state->active_planes; 717 718 /* 719 * Technically we should do a vblank evasion here to make 720 * sure all the cursor registers update on the same frame. 721 * For now just make sure the register writes happen as 722 * quickly as possible to minimize the race window. 723 */ 724 local_irq_disable(); 725 726 if (new_plane_state->uapi.visible) { 727 intel_plane_update_noarm(plane, crtc_state, new_plane_state); 728 intel_plane_update_arm(plane, crtc_state, new_plane_state); 729 } else { 730 intel_plane_disable_arm(plane, crtc_state); 731 } 732 733 local_irq_enable(); 734 735 intel_plane_unpin_fb(old_plane_state); 736 737 out_free: 738 if (new_crtc_state) 739 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi); 740 if (ret) 741 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi); 742 else 743 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi); 744 return ret; 745 746 slow: 747 return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb, 748 crtc_x, crtc_y, crtc_w, crtc_h, 749 src_x, src_y, src_w, src_h, ctx); 750 } 751 752 static const struct drm_plane_funcs intel_cursor_plane_funcs = { 753 .update_plane = intel_legacy_cursor_update, 754 .disable_plane = drm_atomic_helper_disable_plane, 755 .destroy = intel_plane_destroy, 756 .atomic_duplicate_state = intel_plane_duplicate_state, 757 .atomic_destroy_state = intel_plane_destroy_state, 758 .format_mod_supported = intel_cursor_format_mod_supported, 759 }; 760 761 struct intel_plane * 762 intel_cursor_plane_create(struct drm_i915_private *dev_priv, 763 enum pipe pipe) 764 { 765 struct intel_plane *cursor; 766 int ret, zpos; 767 u64 *modifiers; 768 769 cursor = intel_plane_alloc(); 770 if (IS_ERR(cursor)) 771 return cursor; 772 773 cursor->pipe = pipe; 774 cursor->i9xx_plane = (enum i9xx_plane_id) pipe; 775 cursor->id = PLANE_CURSOR; 776 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id); 777 778 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { 779 cursor->max_stride = i845_cursor_max_stride; 780 cursor->update_arm = i845_cursor_update_arm; 781 cursor->disable_arm = i845_cursor_disable_arm; 782 cursor->get_hw_state = i845_cursor_get_hw_state; 783 cursor->check_plane = i845_check_cursor; 784 } else { 785 cursor->max_stride = i9xx_cursor_max_stride; 786 cursor->update_arm = i9xx_cursor_update_arm; 787 cursor->disable_arm = i9xx_cursor_disable_arm; 788 cursor->get_hw_state = i9xx_cursor_get_hw_state; 789 cursor->check_plane = i9xx_check_cursor; 790 } 791 792 cursor->cursor.base = ~0; 793 cursor->cursor.cntl = ~0; 794 795 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv)) 796 cursor->cursor.size = ~0; 797 798 modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_NONE); 799 800 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, 801 0, &intel_cursor_plane_funcs, 802 intel_cursor_formats, 803 ARRAY_SIZE(intel_cursor_formats), 804 modifiers, 805 DRM_PLANE_TYPE_CURSOR, 806 "cursor %c", pipe_name(pipe)); 807 808 kfree(modifiers); 809 810 if (ret) 811 goto fail; 812 813 if (DISPLAY_VER(dev_priv) >= 4) 814 drm_plane_create_rotation_property(&cursor->base, 815 DRM_MODE_ROTATE_0, 816 DRM_MODE_ROTATE_0 | 817 DRM_MODE_ROTATE_180); 818 819 zpos = DISPLAY_RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1; 820 drm_plane_create_zpos_immutable_property(&cursor->base, zpos); 821 822 if (DISPLAY_VER(dev_priv) >= 12) 823 drm_plane_enable_fb_damage_clips(&cursor->base); 824 825 intel_plane_helper_add(cursor); 826 827 return cursor; 828 829 fail: 830 intel_plane_free(cursor); 831 832 return ERR_PTR(ret); 833 } 834