1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 #include <linux/kernel.h> 6 7 #include <drm/drm_atomic_helper.h> 8 #include <drm/drm_atomic_uapi.h> 9 #include <drm/drm_damage_helper.h> 10 #include <drm/drm_plane_helper.h> 11 #include <drm/drm_fourcc.h> 12 13 #include "intel_atomic.h" 14 #include "intel_atomic_plane.h" 15 #include "intel_cursor.h" 16 #include "intel_de.h" 17 #include "intel_display_types.h" 18 #include "intel_display.h" 19 #include "intel_fb.h" 20 #include "intel_fb_pin.h" 21 #include "intel_frontbuffer.h" 22 #include "intel_pm.h" 23 #include "intel_psr.h" 24 #include "intel_sprite.h" 25 26 /* Cursor formats */ 27 static const u32 intel_cursor_formats[] = { 28 DRM_FORMAT_ARGB8888, 29 }; 30 31 static u32 intel_cursor_base(const struct intel_plane_state *plane_state) 32 { 33 struct drm_i915_private *dev_priv = 34 to_i915(plane_state->uapi.plane->dev); 35 const struct drm_framebuffer *fb = plane_state->hw.fb; 36 const struct drm_i915_gem_object *obj = intel_fb_obj(fb); 37 u32 base; 38 39 if (INTEL_INFO(dev_priv)->display.cursor_needs_physical) 40 base = sg_dma_address(obj->mm.pages->sgl); 41 else 42 base = intel_plane_ggtt_offset(plane_state); 43 44 return base + plane_state->view.color_plane[0].offset; 45 } 46 47 static u32 intel_cursor_position(const struct intel_plane_state *plane_state) 48 { 49 int x = plane_state->uapi.dst.x1; 50 int y = plane_state->uapi.dst.y1; 51 u32 pos = 0; 52 53 if (x < 0) { 54 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; 55 x = -x; 56 } 57 pos |= x << CURSOR_X_SHIFT; 58 59 if (y < 0) { 60 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; 61 y = -y; 62 } 63 pos |= y << CURSOR_Y_SHIFT; 64 65 return pos; 66 } 67 68 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state) 69 { 70 const struct drm_mode_config *config = 71 &plane_state->uapi.plane->dev->mode_config; 72 int width = drm_rect_width(&plane_state->uapi.dst); 73 int height = drm_rect_height(&plane_state->uapi.dst); 74 75 return width > 0 && width <= config->cursor_width && 76 height > 0 && height <= config->cursor_height; 77 } 78 79 static int intel_cursor_check_surface(struct intel_plane_state *plane_state) 80 { 81 struct drm_i915_private *dev_priv = 82 to_i915(plane_state->uapi.plane->dev); 83 unsigned int rotation = plane_state->hw.rotation; 84 int src_x, src_y; 85 u32 offset; 86 int ret; 87 88 ret = intel_plane_compute_gtt(plane_state); 89 if (ret) 90 return ret; 91 92 if (!plane_state->uapi.visible) 93 return 0; 94 95 src_x = plane_state->uapi.src.x1 >> 16; 96 src_y = plane_state->uapi.src.y1 >> 16; 97 98 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); 99 offset = intel_plane_compute_aligned_offset(&src_x, &src_y, 100 plane_state, 0); 101 102 if (src_x != 0 || src_y != 0) { 103 drm_dbg_kms(&dev_priv->drm, 104 "Arbitrary cursor panning not supported\n"); 105 return -EINVAL; 106 } 107 108 /* 109 * Put the final coordinates back so that the src 110 * coordinate checks will see the right values. 111 */ 112 drm_rect_translate_to(&plane_state->uapi.src, 113 src_x << 16, src_y << 16); 114 115 /* ILK+ do this automagically in hardware */ 116 if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) { 117 const struct drm_framebuffer *fb = plane_state->hw.fb; 118 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 119 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 120 121 offset += (src_h * src_w - 1) * fb->format->cpp[0]; 122 } 123 124 plane_state->view.color_plane[0].offset = offset; 125 plane_state->view.color_plane[0].x = src_x; 126 plane_state->view.color_plane[0].y = src_y; 127 128 return 0; 129 } 130 131 static int intel_check_cursor(struct intel_crtc_state *crtc_state, 132 struct intel_plane_state *plane_state) 133 { 134 const struct drm_framebuffer *fb = plane_state->hw.fb; 135 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 136 const struct drm_rect src = plane_state->uapi.src; 137 const struct drm_rect dst = plane_state->uapi.dst; 138 int ret; 139 140 if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) { 141 drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n"); 142 return -EINVAL; 143 } 144 145 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, 146 DRM_PLANE_HELPER_NO_SCALING, 147 DRM_PLANE_HELPER_NO_SCALING, 148 true); 149 if (ret) 150 return ret; 151 152 /* Use the unclipped src/dst rectangles, which we program to hw */ 153 plane_state->uapi.src = src; 154 plane_state->uapi.dst = dst; 155 156 ret = intel_cursor_check_surface(plane_state); 157 if (ret) 158 return ret; 159 160 if (!plane_state->uapi.visible) 161 return 0; 162 163 ret = intel_plane_check_src_coordinates(plane_state); 164 if (ret) 165 return ret; 166 167 return 0; 168 } 169 170 static unsigned int 171 i845_cursor_max_stride(struct intel_plane *plane, 172 u32 pixel_format, u64 modifier, 173 unsigned int rotation) 174 { 175 return 2048; 176 } 177 178 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) 179 { 180 u32 cntl = 0; 181 182 if (crtc_state->gamma_enable) 183 cntl |= CURSOR_GAMMA_ENABLE; 184 185 return cntl; 186 } 187 188 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state, 189 const struct intel_plane_state *plane_state) 190 { 191 return CURSOR_ENABLE | 192 CURSOR_FORMAT_ARGB | 193 CURSOR_STRIDE(plane_state->view.color_plane[0].stride); 194 } 195 196 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state) 197 { 198 int width = drm_rect_width(&plane_state->uapi.dst); 199 200 /* 201 * 845g/865g are only limited by the width of their cursors, 202 * the height is arbitrary up to the precision of the register. 203 */ 204 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64); 205 } 206 207 static int i845_check_cursor(struct intel_crtc_state *crtc_state, 208 struct intel_plane_state *plane_state) 209 { 210 const struct drm_framebuffer *fb = plane_state->hw.fb; 211 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 212 int ret; 213 214 ret = intel_check_cursor(crtc_state, plane_state); 215 if (ret) 216 return ret; 217 218 /* if we want to turn off the cursor ignore width and height */ 219 if (!fb) 220 return 0; 221 222 /* Check for which cursor types we support */ 223 if (!i845_cursor_size_ok(plane_state)) { 224 drm_dbg_kms(&i915->drm, 225 "Cursor dimension %dx%d not supported\n", 226 drm_rect_width(&plane_state->uapi.dst), 227 drm_rect_height(&plane_state->uapi.dst)); 228 return -EINVAL; 229 } 230 231 drm_WARN_ON(&i915->drm, plane_state->uapi.visible && 232 plane_state->view.color_plane[0].stride != fb->pitches[0]); 233 234 switch (fb->pitches[0]) { 235 case 256: 236 case 512: 237 case 1024: 238 case 2048: 239 break; 240 default: 241 drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n", 242 fb->pitches[0]); 243 return -EINVAL; 244 } 245 246 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state); 247 248 return 0; 249 } 250 251 static void i845_update_cursor(struct intel_plane *plane, 252 const struct intel_crtc_state *crtc_state, 253 const struct intel_plane_state *plane_state) 254 { 255 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 256 u32 cntl = 0, base = 0, pos = 0, size = 0; 257 unsigned long irqflags; 258 259 if (plane_state && plane_state->uapi.visible) { 260 unsigned int width = drm_rect_width(&plane_state->uapi.dst); 261 unsigned int height = drm_rect_height(&plane_state->uapi.dst); 262 263 cntl = plane_state->ctl | 264 i845_cursor_ctl_crtc(crtc_state); 265 266 size = (height << 12) | width; 267 268 base = intel_cursor_base(plane_state); 269 pos = intel_cursor_position(plane_state); 270 } 271 272 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 273 274 /* On these chipsets we can only modify the base/size/stride 275 * whilst the cursor is disabled. 276 */ 277 if (plane->cursor.base != base || 278 plane->cursor.size != size || 279 plane->cursor.cntl != cntl) { 280 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0); 281 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base); 282 intel_de_write_fw(dev_priv, CURSIZE, size); 283 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); 284 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl); 285 286 plane->cursor.base = base; 287 plane->cursor.size = size; 288 plane->cursor.cntl = cntl; 289 } else { 290 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); 291 } 292 293 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 294 } 295 296 static void i845_disable_cursor(struct intel_plane *plane, 297 const struct intel_crtc_state *crtc_state) 298 { 299 i845_update_cursor(plane, crtc_state, NULL); 300 } 301 302 static bool i845_cursor_get_hw_state(struct intel_plane *plane, 303 enum pipe *pipe) 304 { 305 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 306 enum intel_display_power_domain power_domain; 307 intel_wakeref_t wakeref; 308 bool ret; 309 310 power_domain = POWER_DOMAIN_PIPE(PIPE_A); 311 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 312 if (!wakeref) 313 return false; 314 315 ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE; 316 317 *pipe = PIPE_A; 318 319 intel_display_power_put(dev_priv, power_domain, wakeref); 320 321 return ret; 322 } 323 324 static unsigned int 325 i9xx_cursor_max_stride(struct intel_plane *plane, 326 u32 pixel_format, u64 modifier, 327 unsigned int rotation) 328 { 329 return plane->base.dev->mode_config.cursor_width * 4; 330 } 331 332 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) 333 { 334 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 335 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 336 u32 cntl = 0; 337 338 if (DISPLAY_VER(dev_priv) >= 11) 339 return cntl; 340 341 if (crtc_state->gamma_enable) 342 cntl = MCURSOR_GAMMA_ENABLE; 343 344 if (crtc_state->csc_enable) 345 cntl |= MCURSOR_PIPE_CSC_ENABLE; 346 347 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) 348 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe); 349 350 return cntl; 351 } 352 353 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, 354 const struct intel_plane_state *plane_state) 355 { 356 struct drm_i915_private *dev_priv = 357 to_i915(plane_state->uapi.plane->dev); 358 u32 cntl = 0; 359 360 if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) 361 cntl |= MCURSOR_TRICKLE_FEED_DISABLE; 362 363 switch (drm_rect_width(&plane_state->uapi.dst)) { 364 case 64: 365 cntl |= MCURSOR_MODE_64_ARGB_AX; 366 break; 367 case 128: 368 cntl |= MCURSOR_MODE_128_ARGB_AX; 369 break; 370 case 256: 371 cntl |= MCURSOR_MODE_256_ARGB_AX; 372 break; 373 default: 374 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst)); 375 return 0; 376 } 377 378 if (plane_state->hw.rotation & DRM_MODE_ROTATE_180) 379 cntl |= MCURSOR_ROTATE_180; 380 381 /* Wa_22012358565:adl-p */ 382 if (DISPLAY_VER(dev_priv) == 13) 383 cntl |= MCURSOR_ARB_SLOTS(1); 384 385 return cntl; 386 } 387 388 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state) 389 { 390 struct drm_i915_private *dev_priv = 391 to_i915(plane_state->uapi.plane->dev); 392 int width = drm_rect_width(&plane_state->uapi.dst); 393 int height = drm_rect_height(&plane_state->uapi.dst); 394 395 if (!intel_cursor_size_ok(plane_state)) 396 return false; 397 398 /* Cursor width is limited to a few power-of-two sizes */ 399 switch (width) { 400 case 256: 401 case 128: 402 case 64: 403 break; 404 default: 405 return false; 406 } 407 408 /* 409 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor 410 * height from 8 lines up to the cursor width, when the 411 * cursor is not rotated. Everything else requires square 412 * cursors. 413 */ 414 if (HAS_CUR_FBC(dev_priv) && 415 plane_state->hw.rotation & DRM_MODE_ROTATE_0) { 416 if (height < 8 || height > width) 417 return false; 418 } else { 419 if (height != width) 420 return false; 421 } 422 423 return true; 424 } 425 426 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state, 427 struct intel_plane_state *plane_state) 428 { 429 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 430 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 431 const struct drm_framebuffer *fb = plane_state->hw.fb; 432 enum pipe pipe = plane->pipe; 433 int ret; 434 435 ret = intel_check_cursor(crtc_state, plane_state); 436 if (ret) 437 return ret; 438 439 /* if we want to turn off the cursor ignore width and height */ 440 if (!fb) 441 return 0; 442 443 /* Check for which cursor types we support */ 444 if (!i9xx_cursor_size_ok(plane_state)) { 445 drm_dbg(&dev_priv->drm, 446 "Cursor dimension %dx%d not supported\n", 447 drm_rect_width(&plane_state->uapi.dst), 448 drm_rect_height(&plane_state->uapi.dst)); 449 return -EINVAL; 450 } 451 452 drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible && 453 plane_state->view.color_plane[0].stride != fb->pitches[0]); 454 455 if (fb->pitches[0] != 456 drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) { 457 drm_dbg_kms(&dev_priv->drm, 458 "Invalid cursor stride (%u) (cursor width %d)\n", 459 fb->pitches[0], 460 drm_rect_width(&plane_state->uapi.dst)); 461 return -EINVAL; 462 } 463 464 /* 465 * There's something wrong with the cursor on CHV pipe C. 466 * If it straddles the left edge of the screen then 467 * moving it away from the edge or disabling it often 468 * results in a pipe underrun, and often that can lead to 469 * dead pipe (constant underrun reported, and it scans 470 * out just a solid color). To recover from that, the 471 * display power well must be turned off and on again. 472 * Refuse the put the cursor into that compromised position. 473 */ 474 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C && 475 plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) { 476 drm_dbg_kms(&dev_priv->drm, 477 "CHV cursor C not allowed to straddle the left screen edge\n"); 478 return -EINVAL; 479 } 480 481 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state); 482 483 return 0; 484 } 485 486 static void i9xx_update_cursor(struct intel_plane *plane, 487 const struct intel_crtc_state *crtc_state, 488 const struct intel_plane_state *plane_state) 489 { 490 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 491 enum pipe pipe = plane->pipe; 492 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0; 493 unsigned long irqflags; 494 495 if (plane_state && plane_state->uapi.visible) { 496 int width = drm_rect_width(&plane_state->uapi.dst); 497 int height = drm_rect_height(&plane_state->uapi.dst); 498 499 cntl = plane_state->ctl | 500 i9xx_cursor_ctl_crtc(crtc_state); 501 502 if (width != height) 503 fbc_ctl = CUR_FBC_CTL_EN | (height - 1); 504 505 base = intel_cursor_base(plane_state); 506 pos = intel_cursor_position(plane_state); 507 } 508 509 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 510 511 /* 512 * On some platforms writing CURCNTR first will also 513 * cause CURPOS to be armed by the CURBASE write. 514 * Without the CURCNTR write the CURPOS write would 515 * arm itself. Thus we always update CURCNTR before 516 * CURPOS. 517 * 518 * On other platforms CURPOS always requires the 519 * CURBASE write to arm the update. Additonally 520 * a write to any of the cursor register will cancel 521 * an already armed cursor update. Thus leaving out 522 * the CURBASE write after CURPOS could lead to a 523 * cursor that doesn't appear to move, or even change 524 * shape. Thus we always write CURBASE. 525 * 526 * The other registers are armed by the CURBASE write 527 * except when the plane is getting enabled at which time 528 * the CURCNTR write arms the update. 529 */ 530 531 if (DISPLAY_VER(dev_priv) >= 9) 532 skl_write_cursor_wm(plane, crtc_state); 533 534 if (plane_state) 535 intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, 0); 536 else 537 intel_psr2_disable_plane_sel_fetch(plane, crtc_state); 538 539 if (plane->cursor.base != base || 540 plane->cursor.size != fbc_ctl || 541 plane->cursor.cntl != cntl) { 542 if (HAS_CUR_FBC(dev_priv)) 543 intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe), 544 fbc_ctl); 545 intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl); 546 intel_de_write_fw(dev_priv, CURPOS(pipe), pos); 547 intel_de_write_fw(dev_priv, CURBASE(pipe), base); 548 549 plane->cursor.base = base; 550 plane->cursor.size = fbc_ctl; 551 plane->cursor.cntl = cntl; 552 } else { 553 intel_de_write_fw(dev_priv, CURPOS(pipe), pos); 554 intel_de_write_fw(dev_priv, CURBASE(pipe), base); 555 } 556 557 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 558 } 559 560 static void i9xx_disable_cursor(struct intel_plane *plane, 561 const struct intel_crtc_state *crtc_state) 562 { 563 i9xx_update_cursor(plane, crtc_state, NULL); 564 } 565 566 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane, 567 enum pipe *pipe) 568 { 569 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 570 enum intel_display_power_domain power_domain; 571 intel_wakeref_t wakeref; 572 bool ret; 573 u32 val; 574 575 /* 576 * Not 100% correct for planes that can move between pipes, 577 * but that's only the case for gen2-3 which don't have any 578 * display power wells. 579 */ 580 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 581 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 582 if (!wakeref) 583 return false; 584 585 val = intel_de_read(dev_priv, CURCNTR(plane->pipe)); 586 587 ret = val & MCURSOR_MODE; 588 589 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) 590 *pipe = plane->pipe; 591 else 592 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >> 593 MCURSOR_PIPE_SELECT_SHIFT; 594 595 intel_display_power_put(dev_priv, power_domain, wakeref); 596 597 return ret; 598 } 599 600 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane, 601 u32 format, u64 modifier) 602 { 603 if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) 604 return false; 605 606 return format == DRM_FORMAT_ARGB8888; 607 } 608 609 static int 610 intel_legacy_cursor_update(struct drm_plane *_plane, 611 struct drm_crtc *_crtc, 612 struct drm_framebuffer *fb, 613 int crtc_x, int crtc_y, 614 unsigned int crtc_w, unsigned int crtc_h, 615 u32 src_x, u32 src_y, 616 u32 src_w, u32 src_h, 617 struct drm_modeset_acquire_ctx *ctx) 618 { 619 struct intel_plane *plane = to_intel_plane(_plane); 620 struct intel_crtc *crtc = to_intel_crtc(_crtc); 621 struct intel_plane_state *old_plane_state = 622 to_intel_plane_state(plane->base.state); 623 struct intel_plane_state *new_plane_state; 624 struct intel_crtc_state *crtc_state = 625 to_intel_crtc_state(crtc->base.state); 626 struct intel_crtc_state *new_crtc_state; 627 int ret; 628 629 /* 630 * When crtc is inactive or there is a modeset pending, 631 * wait for it to complete in the slowpath. 632 * PSR2 selective fetch also requires the slow path as 633 * PSR2 plane and transcoder registers can only be updated during 634 * vblank. 635 * 636 * FIXME bigjoiner fastpath would be good 637 */ 638 if (!crtc_state->hw.active || intel_crtc_needs_modeset(crtc_state) || 639 crtc_state->update_pipe || crtc_state->bigjoiner) 640 goto slow; 641 642 /* 643 * Don't do an async update if there is an outstanding commit modifying 644 * the plane. This prevents our async update's changes from getting 645 * overridden by a previous synchronous update's state. 646 */ 647 if (old_plane_state->uapi.commit && 648 !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done)) 649 goto slow; 650 651 /* 652 * If any parameters change that may affect watermarks, 653 * take the slowpath. Only changing fb or position should be 654 * in the fastpath. 655 */ 656 if (old_plane_state->uapi.crtc != &crtc->base || 657 old_plane_state->uapi.src_w != src_w || 658 old_plane_state->uapi.src_h != src_h || 659 old_plane_state->uapi.crtc_w != crtc_w || 660 old_plane_state->uapi.crtc_h != crtc_h || 661 !old_plane_state->uapi.fb != !fb) 662 goto slow; 663 664 new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base)); 665 if (!new_plane_state) 666 return -ENOMEM; 667 668 new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base)); 669 if (!new_crtc_state) { 670 ret = -ENOMEM; 671 goto out_free; 672 } 673 674 drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb); 675 676 new_plane_state->uapi.src_x = src_x; 677 new_plane_state->uapi.src_y = src_y; 678 new_plane_state->uapi.src_w = src_w; 679 new_plane_state->uapi.src_h = src_h; 680 new_plane_state->uapi.crtc_x = crtc_x; 681 new_plane_state->uapi.crtc_y = crtc_y; 682 new_plane_state->uapi.crtc_w = crtc_w; 683 new_plane_state->uapi.crtc_h = crtc_h; 684 685 intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state, crtc); 686 687 ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state, 688 old_plane_state, new_plane_state); 689 if (ret) 690 goto out_free; 691 692 ret = intel_plane_pin_fb(new_plane_state); 693 if (ret) 694 goto out_free; 695 696 intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb), 697 ORIGIN_CURSOR_UPDATE); 698 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 699 to_intel_frontbuffer(new_plane_state->hw.fb), 700 plane->frontbuffer_bit); 701 702 /* Swap plane state */ 703 plane->base.state = &new_plane_state->uapi; 704 705 /* 706 * We cannot swap crtc_state as it may be in use by an atomic commit or 707 * page flip that's running simultaneously. If we swap crtc_state and 708 * destroy the old state, we will cause a use-after-free there. 709 * 710 * Only update active_planes, which is needed for our internal 711 * bookkeeping. Either value will do the right thing when updating 712 * planes atomically. If the cursor was part of the atomic update then 713 * we would have taken the slowpath. 714 */ 715 crtc_state->active_planes = new_crtc_state->active_planes; 716 717 if (new_plane_state->uapi.visible) 718 intel_update_plane(plane, crtc_state, new_plane_state); 719 else 720 intel_disable_plane(plane, crtc_state); 721 722 intel_plane_unpin_fb(old_plane_state); 723 724 out_free: 725 if (new_crtc_state) 726 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi); 727 if (ret) 728 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi); 729 else 730 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi); 731 return ret; 732 733 slow: 734 return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb, 735 crtc_x, crtc_y, crtc_w, crtc_h, 736 src_x, src_y, src_w, src_h, ctx); 737 } 738 739 static const struct drm_plane_funcs intel_cursor_plane_funcs = { 740 .update_plane = intel_legacy_cursor_update, 741 .disable_plane = drm_atomic_helper_disable_plane, 742 .destroy = intel_plane_destroy, 743 .atomic_duplicate_state = intel_plane_duplicate_state, 744 .atomic_destroy_state = intel_plane_destroy_state, 745 .format_mod_supported = intel_cursor_format_mod_supported, 746 }; 747 748 struct intel_plane * 749 intel_cursor_plane_create(struct drm_i915_private *dev_priv, 750 enum pipe pipe) 751 { 752 struct intel_plane *cursor; 753 int ret, zpos; 754 u64 *modifiers; 755 756 cursor = intel_plane_alloc(); 757 if (IS_ERR(cursor)) 758 return cursor; 759 760 cursor->pipe = pipe; 761 cursor->i9xx_plane = (enum i9xx_plane_id) pipe; 762 cursor->id = PLANE_CURSOR; 763 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id); 764 765 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { 766 cursor->max_stride = i845_cursor_max_stride; 767 cursor->update_plane = i845_update_cursor; 768 cursor->disable_plane = i845_disable_cursor; 769 cursor->get_hw_state = i845_cursor_get_hw_state; 770 cursor->check_plane = i845_check_cursor; 771 } else { 772 cursor->max_stride = i9xx_cursor_max_stride; 773 cursor->update_plane = i9xx_update_cursor; 774 cursor->disable_plane = i9xx_disable_cursor; 775 cursor->get_hw_state = i9xx_cursor_get_hw_state; 776 cursor->check_plane = i9xx_check_cursor; 777 } 778 779 cursor->cursor.base = ~0; 780 cursor->cursor.cntl = ~0; 781 782 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv)) 783 cursor->cursor.size = ~0; 784 785 modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_NONE); 786 787 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, 788 0, &intel_cursor_plane_funcs, 789 intel_cursor_formats, 790 ARRAY_SIZE(intel_cursor_formats), 791 modifiers, 792 DRM_PLANE_TYPE_CURSOR, 793 "cursor %c", pipe_name(pipe)); 794 795 kfree(modifiers); 796 797 if (ret) 798 goto fail; 799 800 if (DISPLAY_VER(dev_priv) >= 4) 801 drm_plane_create_rotation_property(&cursor->base, 802 DRM_MODE_ROTATE_0, 803 DRM_MODE_ROTATE_0 | 804 DRM_MODE_ROTATE_180); 805 806 zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1; 807 drm_plane_create_zpos_immutable_property(&cursor->base, zpos); 808 809 if (DISPLAY_VER(dev_priv) >= 12) 810 drm_plane_enable_fb_damage_clips(&cursor->base); 811 812 intel_plane_helper_add(cursor); 813 814 return cursor; 815 816 fail: 817 intel_plane_free(cursor); 818 819 return ERR_PTR(ret); 820 } 821