1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include <drm/drm_edid.h> 7 8 #include "i915_drv.h" 9 #include "intel_crtc_state_dump.h" 10 #include "intel_display_types.h" 11 #include "intel_hdmi.h" 12 #include "intel_vrr.h" 13 14 static void intel_dump_crtc_timings(struct drm_i915_private *i915, 15 const struct drm_display_mode *mode) 16 { 17 drm_dbg_kms(&i915->drm, "crtc timings: clock=%d, " 18 "hd=%d hb=%d-%d hs=%d-%d ht=%d, " 19 "vd=%d vb=%d-%d vs=%d-%d vt=%d, " 20 "flags=0x%x\n", 21 mode->crtc_clock, 22 mode->crtc_hdisplay, mode->crtc_hblank_start, mode->crtc_hblank_end, 23 mode->crtc_hsync_start, mode->crtc_hsync_end, mode->crtc_htotal, 24 mode->crtc_vdisplay, mode->crtc_vblank_start, mode->crtc_vblank_end, 25 mode->crtc_vsync_start, mode->crtc_vsync_end, mode->crtc_vtotal, 26 mode->flags); 27 } 28 29 static void 30 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config, 31 const char *id, unsigned int lane_count, 32 const struct intel_link_m_n *m_n) 33 { 34 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); 35 36 drm_dbg_kms(&i915->drm, 37 "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n", 38 id, lane_count, 39 m_n->data_m, m_n->data_n, 40 m_n->link_m, m_n->link_n, m_n->tu); 41 } 42 43 static void 44 intel_dump_infoframe(struct drm_i915_private *i915, 45 const union hdmi_infoframe *frame) 46 { 47 if (!drm_debug_enabled(DRM_UT_KMS)) 48 return; 49 50 hdmi_infoframe_log(KERN_DEBUG, i915->drm.dev, frame); 51 } 52 53 static void 54 intel_dump_dp_vsc_sdp(struct drm_i915_private *i915, 55 const struct drm_dp_vsc_sdp *vsc) 56 { 57 if (!drm_debug_enabled(DRM_UT_KMS)) 58 return; 59 60 drm_dp_vsc_sdp_log(KERN_DEBUG, i915->drm.dev, vsc); 61 } 62 63 static void 64 intel_dump_buffer(struct drm_i915_private *i915, 65 const char *prefix, const u8 *buf, size_t len) 66 { 67 if (!drm_debug_enabled(DRM_UT_KMS)) 68 return; 69 70 print_hex_dump(KERN_DEBUG, prefix, DUMP_PREFIX_NONE, 71 16, 0, buf, len, false); 72 } 73 74 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x 75 76 static const char * const output_type_str[] = { 77 OUTPUT_TYPE(UNUSED), 78 OUTPUT_TYPE(ANALOG), 79 OUTPUT_TYPE(DVO), 80 OUTPUT_TYPE(SDVO), 81 OUTPUT_TYPE(LVDS), 82 OUTPUT_TYPE(TVOUT), 83 OUTPUT_TYPE(HDMI), 84 OUTPUT_TYPE(DP), 85 OUTPUT_TYPE(EDP), 86 OUTPUT_TYPE(DSI), 87 OUTPUT_TYPE(DDI), 88 OUTPUT_TYPE(DP_MST), 89 }; 90 91 #undef OUTPUT_TYPE 92 93 static void snprintf_output_types(char *buf, size_t len, 94 unsigned int output_types) 95 { 96 char *str = buf; 97 int i; 98 99 str[0] = '\0'; 100 101 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) { 102 int r; 103 104 if ((output_types & BIT(i)) == 0) 105 continue; 106 107 r = snprintf(str, len, "%s%s", 108 str != buf ? "," : "", output_type_str[i]); 109 if (r >= len) 110 break; 111 str += r; 112 len -= r; 113 114 output_types &= ~BIT(i); 115 } 116 117 WARN_ON_ONCE(output_types != 0); 118 } 119 120 static const char * const output_format_str[] = { 121 [INTEL_OUTPUT_FORMAT_RGB] = "RGB", 122 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0", 123 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4", 124 }; 125 126 const char *intel_output_format_name(enum intel_output_format format) 127 { 128 if (format >= ARRAY_SIZE(output_format_str)) 129 return "invalid"; 130 return output_format_str[format]; 131 } 132 133 static void intel_dump_plane_state(const struct intel_plane_state *plane_state) 134 { 135 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 136 struct drm_i915_private *i915 = to_i915(plane->base.dev); 137 const struct drm_framebuffer *fb = plane_state->hw.fb; 138 139 if (!fb) { 140 drm_dbg_kms(&i915->drm, 141 "[PLANE:%d:%s] fb: [NOFB], visible: %s\n", 142 plane->base.base.id, plane->base.name, 143 str_yes_no(plane_state->uapi.visible)); 144 return; 145 } 146 147 drm_dbg_kms(&i915->drm, 148 "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n", 149 plane->base.base.id, plane->base.name, 150 fb->base.id, fb->width, fb->height, &fb->format->format, 151 fb->modifier, str_yes_no(plane_state->uapi.visible)); 152 drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d, scaling_filter: %d\n", 153 plane_state->hw.rotation, plane_state->scaler_id, plane_state->hw.scaling_filter); 154 if (plane_state->uapi.visible) 155 drm_dbg_kms(&i915->drm, 156 "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n", 157 DRM_RECT_FP_ARG(&plane_state->uapi.src), 158 DRM_RECT_ARG(&plane_state->uapi.dst)); 159 } 160 161 void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, 162 struct intel_atomic_state *state, 163 const char *context) 164 { 165 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 166 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 167 const struct intel_plane_state *plane_state; 168 struct intel_plane *plane; 169 char buf[64]; 170 int i; 171 172 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] enable: %s [%s]\n", 173 crtc->base.base.id, crtc->base.name, 174 str_yes_no(pipe_config->hw.enable), context); 175 176 if (!pipe_config->hw.enable) 177 goto dump_planes; 178 179 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); 180 drm_dbg_kms(&i915->drm, 181 "active: %s, output_types: %s (0x%x), output format: %s\n", 182 str_yes_no(pipe_config->hw.active), 183 buf, pipe_config->output_types, 184 intel_output_format_name(pipe_config->output_format)); 185 186 drm_dbg_kms(&i915->drm, 187 "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", 188 transcoder_name(pipe_config->cpu_transcoder), 189 pipe_config->pipe_bpp, pipe_config->dither); 190 191 drm_dbg_kms(&i915->drm, "MST master transcoder: %s\n", 192 transcoder_name(pipe_config->mst_master_transcoder)); 193 194 drm_dbg_kms(&i915->drm, 195 "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n", 196 transcoder_name(pipe_config->master_transcoder), 197 pipe_config->sync_mode_slaves_mask); 198 199 drm_dbg_kms(&i915->drm, "bigjoiner: %s, pipes: 0x%x\n", 200 intel_crtc_is_bigjoiner_slave(pipe_config) ? "slave" : 201 intel_crtc_is_bigjoiner_master(pipe_config) ? "master" : "no", 202 pipe_config->bigjoiner_pipes); 203 204 drm_dbg_kms(&i915->drm, "splitter: %s, link count %d, overlap %d\n", 205 str_enabled_disabled(pipe_config->splitter.enable), 206 pipe_config->splitter.link_count, 207 pipe_config->splitter.pixel_overlap); 208 209 if (pipe_config->has_pch_encoder) 210 intel_dump_m_n_config(pipe_config, "fdi", 211 pipe_config->fdi_lanes, 212 &pipe_config->fdi_m_n); 213 214 if (intel_crtc_has_dp_encoder(pipe_config)) { 215 intel_dump_m_n_config(pipe_config, "dp m_n", 216 pipe_config->lane_count, 217 &pipe_config->dp_m_n); 218 intel_dump_m_n_config(pipe_config, "dp m2_n2", 219 pipe_config->lane_count, 220 &pipe_config->dp_m2_n2); 221 } 222 223 drm_dbg_kms(&i915->drm, "framestart delay: %d, MSA timing delay: %d\n", 224 pipe_config->framestart_delay, pipe_config->msa_timing_delay); 225 226 drm_dbg_kms(&i915->drm, 227 "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n", 228 pipe_config->has_audio, pipe_config->has_infoframe, 229 pipe_config->infoframes.enable); 230 231 if (pipe_config->infoframes.enable & 232 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) 233 drm_dbg_kms(&i915->drm, "GCP: 0x%x\n", 234 pipe_config->infoframes.gcp); 235 if (pipe_config->infoframes.enable & 236 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) 237 intel_dump_infoframe(i915, &pipe_config->infoframes.avi); 238 if (pipe_config->infoframes.enable & 239 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD)) 240 intel_dump_infoframe(i915, &pipe_config->infoframes.spd); 241 if (pipe_config->infoframes.enable & 242 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR)) 243 intel_dump_infoframe(i915, &pipe_config->infoframes.hdmi); 244 if (pipe_config->infoframes.enable & 245 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) 246 intel_dump_infoframe(i915, &pipe_config->infoframes.drm); 247 if (pipe_config->infoframes.enable & 248 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) 249 intel_dump_infoframe(i915, &pipe_config->infoframes.drm); 250 if (pipe_config->infoframes.enable & 251 intel_hdmi_infoframe_enable(DP_SDP_VSC)) 252 intel_dump_dp_vsc_sdp(i915, &pipe_config->infoframes.vsc); 253 254 if (pipe_config->has_audio) 255 intel_dump_buffer(i915, "ELD: ", pipe_config->eld, 256 drm_eld_size(pipe_config->eld)); 257 258 drm_dbg_kms(&i915->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n", 259 str_yes_no(pipe_config->vrr.enable), 260 pipe_config->vrr.vmin, pipe_config->vrr.vmax, 261 pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband, 262 pipe_config->vrr.flipline, 263 intel_vrr_vmin_vblank_start(pipe_config), 264 intel_vrr_vmax_vblank_start(pipe_config)); 265 266 drm_dbg_kms(&i915->drm, "requested mode: " DRM_MODE_FMT "\n", 267 DRM_MODE_ARG(&pipe_config->hw.mode)); 268 drm_dbg_kms(&i915->drm, "adjusted mode: " DRM_MODE_FMT "\n", 269 DRM_MODE_ARG(&pipe_config->hw.adjusted_mode)); 270 intel_dump_crtc_timings(i915, &pipe_config->hw.adjusted_mode); 271 drm_dbg_kms(&i915->drm, "pipe mode: " DRM_MODE_FMT "\n", 272 DRM_MODE_ARG(&pipe_config->hw.pipe_mode)); 273 intel_dump_crtc_timings(i915, &pipe_config->hw.pipe_mode); 274 drm_dbg_kms(&i915->drm, 275 "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n", 276 pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src), 277 pipe_config->pixel_rate); 278 279 drm_dbg_kms(&i915->drm, "linetime: %d, ips linetime: %d\n", 280 pipe_config->linetime, pipe_config->ips_linetime); 281 282 if (DISPLAY_VER(i915) >= 9) 283 drm_dbg_kms(&i915->drm, 284 "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d, scaling_filter: %d\n", 285 crtc->num_scalers, 286 pipe_config->scaler_state.scaler_users, 287 pipe_config->scaler_state.scaler_id, 288 pipe_config->hw.scaling_filter); 289 290 if (HAS_GMCH(i915)) 291 drm_dbg_kms(&i915->drm, 292 "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", 293 pipe_config->gmch_pfit.control, 294 pipe_config->gmch_pfit.pgm_ratios, 295 pipe_config->gmch_pfit.lvds_border_bits); 296 else 297 drm_dbg_kms(&i915->drm, 298 "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n", 299 DRM_RECT_ARG(&pipe_config->pch_pfit.dst), 300 str_enabled_disabled(pipe_config->pch_pfit.enabled), 301 str_yes_no(pipe_config->pch_pfit.force_thru)); 302 303 drm_dbg_kms(&i915->drm, "ips: %i, double wide: %i, drrs: %i\n", 304 pipe_config->ips_enabled, pipe_config->double_wide, 305 pipe_config->has_drrs); 306 307 intel_dpll_dump_hw_state(i915, &pipe_config->dpll_hw_state); 308 309 if (IS_CHERRYVIEW(i915)) 310 drm_dbg_kms(&i915->drm, 311 "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 312 pipe_config->cgm_mode, pipe_config->gamma_mode, 313 pipe_config->gamma_enable, pipe_config->csc_enable); 314 else 315 drm_dbg_kms(&i915->drm, 316 "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 317 pipe_config->csc_mode, pipe_config->gamma_mode, 318 pipe_config->gamma_enable, pipe_config->csc_enable); 319 320 drm_dbg_kms(&i915->drm, "pre csc lut: %s%d entries, post csc lut: %d entries\n", 321 pipe_config->pre_csc_lut && pipe_config->pre_csc_lut == 322 i915->display.color.glk_linear_degamma_lut ? "(linear) " : "", 323 pipe_config->pre_csc_lut ? 324 drm_color_lut_size(pipe_config->pre_csc_lut) : 0, 325 pipe_config->post_csc_lut ? 326 drm_color_lut_size(pipe_config->post_csc_lut) : 0); 327 328 dump_planes: 329 if (!state) 330 return; 331 332 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 333 if (plane->pipe == crtc->pipe) 334 intel_dump_plane_state(plane_state); 335 } 336 } 337