1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 #include <linux/kernel.h> 6 #include <linux/slab.h> 7 8 #include <drm/drm_atomic_helper.h> 9 #include <drm/drm_fourcc.h> 10 #include <drm/drm_plane.h> 11 #include <drm/drm_plane_helper.h> 12 13 #include "intel_atomic.h" 14 #include "intel_atomic_plane.h" 15 #include "intel_color.h" 16 #include "intel_crtc.h" 17 #include "intel_cursor.h" 18 #include "intel_display_debugfs.h" 19 #include "intel_display_types.h" 20 #include "intel_pipe_crc.h" 21 #include "intel_sprite.h" 22 #include "i9xx_plane.h" 23 24 static void assert_vblank_disabled(struct drm_crtc *crtc) 25 { 26 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) 27 drm_crtc_vblank_put(crtc); 28 } 29 30 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) 31 { 32 struct drm_device *dev = crtc->base.dev; 33 struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)]; 34 35 if (!vblank->max_vblank_count) 36 return (u32)drm_crtc_accurate_vblank_count(&crtc->base); 37 38 return crtc->base.funcs->get_vblank_counter(&crtc->base); 39 } 40 41 u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state) 42 { 43 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 44 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 45 u32 mode_flags = crtc->mode_flags; 46 47 /* 48 * From Gen 11, In case of dsi cmd mode, frame counter wouldnt 49 * have updated at the beginning of TE, if we want to use 50 * the hw counter, then we would find it updated in only 51 * the next TE, hence switching to sw counter. 52 */ 53 if (mode_flags & (I915_MODE_FLAG_DSI_USE_TE0 | I915_MODE_FLAG_DSI_USE_TE1)) 54 return 0; 55 56 /* 57 * On i965gm the hardware frame counter reads 58 * zero when the TV encoder is enabled :( 59 */ 60 if (IS_I965GM(dev_priv) && 61 (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT))) 62 return 0; 63 64 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) 65 return 0xffffffff; /* full 32 bit counter */ 66 else if (INTEL_GEN(dev_priv) >= 3) 67 return 0xffffff; /* only 24 bits of frame count */ 68 else 69 return 0; /* Gen2 doesn't have a hardware frame counter */ 70 } 71 72 void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state) 73 { 74 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 75 76 assert_vblank_disabled(&crtc->base); 77 drm_crtc_set_max_vblank_count(&crtc->base, 78 intel_crtc_max_vblank_count(crtc_state)); 79 drm_crtc_vblank_on(&crtc->base); 80 } 81 82 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state) 83 { 84 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 85 86 drm_crtc_vblank_off(&crtc->base); 87 assert_vblank_disabled(&crtc->base); 88 } 89 90 struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc) 91 { 92 struct intel_crtc_state *crtc_state; 93 94 crtc_state = kmalloc(sizeof(*crtc_state), GFP_KERNEL); 95 96 if (crtc_state) 97 intel_crtc_state_reset(crtc_state, crtc); 98 99 return crtc_state; 100 } 101 102 void intel_crtc_state_reset(struct intel_crtc_state *crtc_state, 103 struct intel_crtc *crtc) 104 { 105 memset(crtc_state, 0, sizeof(*crtc_state)); 106 107 __drm_atomic_helper_crtc_state_reset(&crtc_state->uapi, &crtc->base); 108 109 crtc_state->cpu_transcoder = INVALID_TRANSCODER; 110 crtc_state->master_transcoder = INVALID_TRANSCODER; 111 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 112 crtc_state->scaler_state.scaler_id = -1; 113 crtc_state->mst_master_transcoder = INVALID_TRANSCODER; 114 } 115 116 static struct intel_crtc *intel_crtc_alloc(void) 117 { 118 struct intel_crtc_state *crtc_state; 119 struct intel_crtc *crtc; 120 121 crtc = kzalloc(sizeof(*crtc), GFP_KERNEL); 122 if (!crtc) 123 return ERR_PTR(-ENOMEM); 124 125 crtc_state = intel_crtc_state_alloc(crtc); 126 if (!crtc_state) { 127 kfree(crtc); 128 return ERR_PTR(-ENOMEM); 129 } 130 131 crtc->base.state = &crtc_state->uapi; 132 crtc->config = crtc_state; 133 134 return crtc; 135 } 136 137 static void intel_crtc_free(struct intel_crtc *crtc) 138 { 139 intel_crtc_destroy_state(&crtc->base, crtc->base.state); 140 kfree(crtc); 141 } 142 143 static void intel_crtc_destroy(struct drm_crtc *crtc) 144 { 145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 146 147 drm_crtc_cleanup(crtc); 148 kfree(intel_crtc); 149 } 150 151 static int intel_crtc_late_register(struct drm_crtc *crtc) 152 { 153 intel_crtc_debugfs_add(crtc); 154 return 0; 155 } 156 157 #define INTEL_CRTC_FUNCS \ 158 .set_config = drm_atomic_helper_set_config, \ 159 .destroy = intel_crtc_destroy, \ 160 .page_flip = drm_atomic_helper_page_flip, \ 161 .atomic_duplicate_state = intel_crtc_duplicate_state, \ 162 .atomic_destroy_state = intel_crtc_destroy_state, \ 163 .set_crc_source = intel_crtc_set_crc_source, \ 164 .verify_crc_source = intel_crtc_verify_crc_source, \ 165 .get_crc_sources = intel_crtc_get_crc_sources, \ 166 .late_register = intel_crtc_late_register 167 168 static const struct drm_crtc_funcs bdw_crtc_funcs = { 169 INTEL_CRTC_FUNCS, 170 171 .get_vblank_counter = g4x_get_vblank_counter, 172 .enable_vblank = bdw_enable_vblank, 173 .disable_vblank = bdw_disable_vblank, 174 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, 175 }; 176 177 static const struct drm_crtc_funcs ilk_crtc_funcs = { 178 INTEL_CRTC_FUNCS, 179 180 .get_vblank_counter = g4x_get_vblank_counter, 181 .enable_vblank = ilk_enable_vblank, 182 .disable_vblank = ilk_disable_vblank, 183 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, 184 }; 185 186 static const struct drm_crtc_funcs g4x_crtc_funcs = { 187 INTEL_CRTC_FUNCS, 188 189 .get_vblank_counter = g4x_get_vblank_counter, 190 .enable_vblank = i965_enable_vblank, 191 .disable_vblank = i965_disable_vblank, 192 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, 193 }; 194 195 static const struct drm_crtc_funcs i965_crtc_funcs = { 196 INTEL_CRTC_FUNCS, 197 198 .get_vblank_counter = i915_get_vblank_counter, 199 .enable_vblank = i965_enable_vblank, 200 .disable_vblank = i965_disable_vblank, 201 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, 202 }; 203 204 static const struct drm_crtc_funcs i915gm_crtc_funcs = { 205 INTEL_CRTC_FUNCS, 206 207 .get_vblank_counter = i915_get_vblank_counter, 208 .enable_vblank = i915gm_enable_vblank, 209 .disable_vblank = i915gm_disable_vblank, 210 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, 211 }; 212 213 static const struct drm_crtc_funcs i915_crtc_funcs = { 214 INTEL_CRTC_FUNCS, 215 216 .get_vblank_counter = i915_get_vblank_counter, 217 .enable_vblank = i8xx_enable_vblank, 218 .disable_vblank = i8xx_disable_vblank, 219 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, 220 }; 221 222 static const struct drm_crtc_funcs i8xx_crtc_funcs = { 223 INTEL_CRTC_FUNCS, 224 225 /* no hw vblank counter */ 226 .enable_vblank = i8xx_enable_vblank, 227 .disable_vblank = i8xx_disable_vblank, 228 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, 229 }; 230 231 int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) 232 { 233 struct intel_plane *primary, *cursor; 234 const struct drm_crtc_funcs *funcs; 235 struct intel_crtc *crtc; 236 int sprite, ret; 237 238 crtc = intel_crtc_alloc(); 239 if (IS_ERR(crtc)) 240 return PTR_ERR(crtc); 241 242 crtc->pipe = pipe; 243 crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[pipe]; 244 245 primary = intel_primary_plane_create(dev_priv, pipe); 246 if (IS_ERR(primary)) { 247 ret = PTR_ERR(primary); 248 goto fail; 249 } 250 crtc->plane_ids_mask |= BIT(primary->id); 251 252 for_each_sprite(dev_priv, pipe, sprite) { 253 struct intel_plane *plane; 254 255 plane = intel_sprite_plane_create(dev_priv, pipe, sprite); 256 if (IS_ERR(plane)) { 257 ret = PTR_ERR(plane); 258 goto fail; 259 } 260 crtc->plane_ids_mask |= BIT(plane->id); 261 } 262 263 cursor = intel_cursor_plane_create(dev_priv, pipe); 264 if (IS_ERR(cursor)) { 265 ret = PTR_ERR(cursor); 266 goto fail; 267 } 268 crtc->plane_ids_mask |= BIT(cursor->id); 269 270 if (HAS_GMCH(dev_priv)) { 271 if (IS_CHERRYVIEW(dev_priv) || 272 IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv)) 273 funcs = &g4x_crtc_funcs; 274 else if (IS_GEN(dev_priv, 4)) 275 funcs = &i965_crtc_funcs; 276 else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv)) 277 funcs = &i915gm_crtc_funcs; 278 else if (IS_GEN(dev_priv, 3)) 279 funcs = &i915_crtc_funcs; 280 else 281 funcs = &i8xx_crtc_funcs; 282 } else { 283 if (INTEL_GEN(dev_priv) >= 8) 284 funcs = &bdw_crtc_funcs; 285 else 286 funcs = &ilk_crtc_funcs; 287 } 288 289 ret = drm_crtc_init_with_planes(&dev_priv->drm, &crtc->base, 290 &primary->base, &cursor->base, 291 funcs, "pipe %c", pipe_name(pipe)); 292 if (ret) 293 goto fail; 294 295 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) || 296 dev_priv->pipe_to_crtc_mapping[pipe] != NULL); 297 dev_priv->pipe_to_crtc_mapping[pipe] = crtc; 298 299 if (INTEL_GEN(dev_priv) < 9) { 300 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane; 301 302 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || 303 dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL); 304 dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc; 305 } 306 307 if (INTEL_GEN(dev_priv) >= 10) 308 drm_crtc_create_scaling_filter_property(&crtc->base, 309 BIT(DRM_SCALING_FILTER_DEFAULT) | 310 BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR)); 311 312 intel_color_init(crtc); 313 314 intel_crtc_crc_init(crtc); 315 316 drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe); 317 318 return 0; 319 320 fail: 321 intel_crtc_free(crtc); 322 323 return ret; 324 } 325