1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 #include <linux/kernel.h> 6 #include <linux/slab.h> 7 8 #include <drm/drm_atomic_helper.h> 9 #include <drm/drm_fourcc.h> 10 #include <drm/drm_plane.h> 11 #include <drm/drm_plane_helper.h> 12 13 #include "intel_atomic.h" 14 #include "intel_atomic_plane.h" 15 #include "intel_color.h" 16 #include "intel_crtc.h" 17 #include "intel_cursor.h" 18 #include "intel_display_debugfs.h" 19 #include "intel_display_types.h" 20 #include "intel_pipe_crc.h" 21 #include "intel_sprite.h" 22 #include "i9xx_plane.h" 23 24 static void assert_vblank_disabled(struct drm_crtc *crtc) 25 { 26 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) 27 drm_crtc_vblank_put(crtc); 28 } 29 30 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) 31 { 32 struct drm_device *dev = crtc->base.dev; 33 struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)]; 34 35 if (!vblank->max_vblank_count) 36 return (u32)drm_crtc_accurate_vblank_count(&crtc->base); 37 38 return crtc->base.funcs->get_vblank_counter(&crtc->base); 39 } 40 41 u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state) 42 { 43 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 44 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 45 u32 mode_flags = crtc->mode_flags; 46 47 /* 48 * From Gen 11, In case of dsi cmd mode, frame counter wouldnt 49 * have updated at the beginning of TE, if we want to use 50 * the hw counter, then we would find it updated in only 51 * the next TE, hence switching to sw counter. 52 */ 53 if (mode_flags & (I915_MODE_FLAG_DSI_USE_TE0 | I915_MODE_FLAG_DSI_USE_TE1)) 54 return 0; 55 56 /* 57 * On i965gm the hardware frame counter reads 58 * zero when the TV encoder is enabled :( 59 */ 60 if (IS_I965GM(dev_priv) && 61 (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT))) 62 return 0; 63 64 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) 65 return 0xffffffff; /* full 32 bit counter */ 66 else if (INTEL_GEN(dev_priv) >= 3) 67 return 0xffffff; /* only 24 bits of frame count */ 68 else 69 return 0; /* Gen2 doesn't have a hardware frame counter */ 70 } 71 72 void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state) 73 { 74 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 75 76 assert_vblank_disabled(&crtc->base); 77 drm_crtc_set_max_vblank_count(&crtc->base, 78 intel_crtc_max_vblank_count(crtc_state)); 79 drm_crtc_vblank_on(&crtc->base); 80 } 81 82 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state) 83 { 84 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 85 86 drm_crtc_vblank_off(&crtc->base); 87 assert_vblank_disabled(&crtc->base); 88 } 89 90 struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc) 91 { 92 struct intel_crtc_state *crtc_state; 93 94 crtc_state = kmalloc(sizeof(*crtc_state), GFP_KERNEL); 95 96 if (crtc_state) 97 intel_crtc_state_reset(crtc_state, crtc); 98 99 return crtc_state; 100 } 101 102 void intel_crtc_state_reset(struct intel_crtc_state *crtc_state, 103 struct intel_crtc *crtc) 104 { 105 memset(crtc_state, 0, sizeof(*crtc_state)); 106 107 __drm_atomic_helper_crtc_state_reset(&crtc_state->uapi, &crtc->base); 108 109 crtc_state->cpu_transcoder = INVALID_TRANSCODER; 110 crtc_state->master_transcoder = INVALID_TRANSCODER; 111 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 112 crtc_state->output_format = INTEL_OUTPUT_FORMAT_INVALID; 113 crtc_state->scaler_state.scaler_id = -1; 114 crtc_state->mst_master_transcoder = INVALID_TRANSCODER; 115 } 116 117 static struct intel_crtc *intel_crtc_alloc(void) 118 { 119 struct intel_crtc_state *crtc_state; 120 struct intel_crtc *crtc; 121 122 crtc = kzalloc(sizeof(*crtc), GFP_KERNEL); 123 if (!crtc) 124 return ERR_PTR(-ENOMEM); 125 126 crtc_state = intel_crtc_state_alloc(crtc); 127 if (!crtc_state) { 128 kfree(crtc); 129 return ERR_PTR(-ENOMEM); 130 } 131 132 crtc->base.state = &crtc_state->uapi; 133 crtc->config = crtc_state; 134 135 return crtc; 136 } 137 138 static void intel_crtc_free(struct intel_crtc *crtc) 139 { 140 intel_crtc_destroy_state(&crtc->base, crtc->base.state); 141 kfree(crtc); 142 } 143 144 static void intel_crtc_destroy(struct drm_crtc *crtc) 145 { 146 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 147 148 drm_crtc_cleanup(crtc); 149 kfree(intel_crtc); 150 } 151 152 static int intel_crtc_late_register(struct drm_crtc *crtc) 153 { 154 intel_crtc_debugfs_add(crtc); 155 return 0; 156 } 157 158 #define INTEL_CRTC_FUNCS \ 159 .set_config = drm_atomic_helper_set_config, \ 160 .destroy = intel_crtc_destroy, \ 161 .page_flip = drm_atomic_helper_page_flip, \ 162 .atomic_duplicate_state = intel_crtc_duplicate_state, \ 163 .atomic_destroy_state = intel_crtc_destroy_state, \ 164 .set_crc_source = intel_crtc_set_crc_source, \ 165 .verify_crc_source = intel_crtc_verify_crc_source, \ 166 .get_crc_sources = intel_crtc_get_crc_sources, \ 167 .late_register = intel_crtc_late_register 168 169 static const struct drm_crtc_funcs bdw_crtc_funcs = { 170 INTEL_CRTC_FUNCS, 171 172 .get_vblank_counter = g4x_get_vblank_counter, 173 .enable_vblank = bdw_enable_vblank, 174 .disable_vblank = bdw_disable_vblank, 175 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, 176 }; 177 178 static const struct drm_crtc_funcs ilk_crtc_funcs = { 179 INTEL_CRTC_FUNCS, 180 181 .get_vblank_counter = g4x_get_vblank_counter, 182 .enable_vblank = ilk_enable_vblank, 183 .disable_vblank = ilk_disable_vblank, 184 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, 185 }; 186 187 static const struct drm_crtc_funcs g4x_crtc_funcs = { 188 INTEL_CRTC_FUNCS, 189 190 .get_vblank_counter = g4x_get_vblank_counter, 191 .enable_vblank = i965_enable_vblank, 192 .disable_vblank = i965_disable_vblank, 193 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, 194 }; 195 196 static const struct drm_crtc_funcs i965_crtc_funcs = { 197 INTEL_CRTC_FUNCS, 198 199 .get_vblank_counter = i915_get_vblank_counter, 200 .enable_vblank = i965_enable_vblank, 201 .disable_vblank = i965_disable_vblank, 202 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, 203 }; 204 205 static const struct drm_crtc_funcs i915gm_crtc_funcs = { 206 INTEL_CRTC_FUNCS, 207 208 .get_vblank_counter = i915_get_vblank_counter, 209 .enable_vblank = i915gm_enable_vblank, 210 .disable_vblank = i915gm_disable_vblank, 211 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, 212 }; 213 214 static const struct drm_crtc_funcs i915_crtc_funcs = { 215 INTEL_CRTC_FUNCS, 216 217 .get_vblank_counter = i915_get_vblank_counter, 218 .enable_vblank = i8xx_enable_vblank, 219 .disable_vblank = i8xx_disable_vblank, 220 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, 221 }; 222 223 static const struct drm_crtc_funcs i8xx_crtc_funcs = { 224 INTEL_CRTC_FUNCS, 225 226 /* no hw vblank counter */ 227 .enable_vblank = i8xx_enable_vblank, 228 .disable_vblank = i8xx_disable_vblank, 229 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, 230 }; 231 232 int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) 233 { 234 struct intel_plane *primary, *cursor; 235 const struct drm_crtc_funcs *funcs; 236 struct intel_crtc *crtc; 237 int sprite, ret; 238 239 crtc = intel_crtc_alloc(); 240 if (IS_ERR(crtc)) 241 return PTR_ERR(crtc); 242 243 crtc->pipe = pipe; 244 crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[pipe]; 245 246 primary = intel_primary_plane_create(dev_priv, pipe); 247 if (IS_ERR(primary)) { 248 ret = PTR_ERR(primary); 249 goto fail; 250 } 251 crtc->plane_ids_mask |= BIT(primary->id); 252 253 for_each_sprite(dev_priv, pipe, sprite) { 254 struct intel_plane *plane; 255 256 plane = intel_sprite_plane_create(dev_priv, pipe, sprite); 257 if (IS_ERR(plane)) { 258 ret = PTR_ERR(plane); 259 goto fail; 260 } 261 crtc->plane_ids_mask |= BIT(plane->id); 262 } 263 264 cursor = intel_cursor_plane_create(dev_priv, pipe); 265 if (IS_ERR(cursor)) { 266 ret = PTR_ERR(cursor); 267 goto fail; 268 } 269 crtc->plane_ids_mask |= BIT(cursor->id); 270 271 if (HAS_GMCH(dev_priv)) { 272 if (IS_CHERRYVIEW(dev_priv) || 273 IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv)) 274 funcs = &g4x_crtc_funcs; 275 else if (IS_GEN(dev_priv, 4)) 276 funcs = &i965_crtc_funcs; 277 else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv)) 278 funcs = &i915gm_crtc_funcs; 279 else if (IS_GEN(dev_priv, 3)) 280 funcs = &i915_crtc_funcs; 281 else 282 funcs = &i8xx_crtc_funcs; 283 } else { 284 if (INTEL_GEN(dev_priv) >= 8) 285 funcs = &bdw_crtc_funcs; 286 else 287 funcs = &ilk_crtc_funcs; 288 } 289 290 ret = drm_crtc_init_with_planes(&dev_priv->drm, &crtc->base, 291 &primary->base, &cursor->base, 292 funcs, "pipe %c", pipe_name(pipe)); 293 if (ret) 294 goto fail; 295 296 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) || 297 dev_priv->pipe_to_crtc_mapping[pipe] != NULL); 298 dev_priv->pipe_to_crtc_mapping[pipe] = crtc; 299 300 if (INTEL_GEN(dev_priv) < 9) { 301 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane; 302 303 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || 304 dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL); 305 dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc; 306 } 307 308 if (INTEL_GEN(dev_priv) >= 10) 309 drm_crtc_create_scaling_filter_property(&crtc->base, 310 BIT(DRM_SCALING_FILTER_DEFAULT) | 311 BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR)); 312 313 intel_color_init(crtc); 314 315 intel_crtc_crc_init(crtc); 316 317 drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe); 318 319 return 0; 320 321 fail: 322 intel_crtc_free(crtc); 323 324 return ret; 325 } 326