1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dmi.h> 28 #include <linux/i2c.h> 29 #include <linux/slab.h> 30 31 #include <drm/drm_atomic_helper.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_edid.h> 34 #include <drm/drm_probe_helper.h> 35 36 #include "i915_drv.h" 37 #include "i915_irq.h" 38 #include "i915_reg.h" 39 #include "intel_connector.h" 40 #include "intel_crt.h" 41 #include "intel_crtc.h" 42 #include "intel_ddi.h" 43 #include "intel_ddi_buf_trans.h" 44 #include "intel_de.h" 45 #include "intel_display_types.h" 46 #include "intel_fdi.h" 47 #include "intel_fdi_regs.h" 48 #include "intel_fifo_underrun.h" 49 #include "intel_gmbus.h" 50 #include "intel_hotplug.h" 51 #include "intel_pch_display.h" 52 #include "intel_pch_refclk.h" 53 54 /* Here's the desired hotplug mode */ 55 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ 56 ADPA_CRT_HOTPLUG_WARMUP_10MS | \ 57 ADPA_CRT_HOTPLUG_SAMPLE_4S | \ 58 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ 59 ADPA_CRT_HOTPLUG_VOLREF_325MV | \ 60 ADPA_CRT_HOTPLUG_ENABLE) 61 62 struct intel_crt { 63 struct intel_encoder base; 64 /* DPMS state is stored in the connector, which we need in the 65 * encoder's enable/disable callbacks */ 66 struct intel_connector *connector; 67 bool force_hotplug_required; 68 i915_reg_t adpa_reg; 69 }; 70 71 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) 72 { 73 return container_of(encoder, struct intel_crt, base); 74 } 75 76 static struct intel_crt *intel_attached_crt(struct intel_connector *connector) 77 { 78 return intel_encoder_to_crt(intel_attached_encoder(connector)); 79 } 80 81 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv, 82 i915_reg_t adpa_reg, enum pipe *pipe) 83 { 84 u32 val; 85 86 val = intel_de_read(dev_priv, adpa_reg); 87 88 /* asserts want to know the pipe even if the port is disabled */ 89 if (HAS_PCH_CPT(dev_priv)) 90 *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT; 91 else 92 *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT; 93 94 return val & ADPA_DAC_ENABLE; 95 } 96 97 static bool intel_crt_get_hw_state(struct intel_encoder *encoder, 98 enum pipe *pipe) 99 { 100 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 101 struct intel_crt *crt = intel_encoder_to_crt(encoder); 102 intel_wakeref_t wakeref; 103 bool ret; 104 105 wakeref = intel_display_power_get_if_enabled(dev_priv, 106 encoder->power_domain); 107 if (!wakeref) 108 return false; 109 110 ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe); 111 112 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 113 114 return ret; 115 } 116 117 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) 118 { 119 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 120 struct intel_crt *crt = intel_encoder_to_crt(encoder); 121 u32 tmp, flags = 0; 122 123 tmp = intel_de_read(dev_priv, crt->adpa_reg); 124 125 if (tmp & ADPA_HSYNC_ACTIVE_HIGH) 126 flags |= DRM_MODE_FLAG_PHSYNC; 127 else 128 flags |= DRM_MODE_FLAG_NHSYNC; 129 130 if (tmp & ADPA_VSYNC_ACTIVE_HIGH) 131 flags |= DRM_MODE_FLAG_PVSYNC; 132 else 133 flags |= DRM_MODE_FLAG_NVSYNC; 134 135 return flags; 136 } 137 138 static void intel_crt_get_config(struct intel_encoder *encoder, 139 struct intel_crtc_state *pipe_config) 140 { 141 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 142 143 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); 144 145 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; 146 } 147 148 static void hsw_crt_get_config(struct intel_encoder *encoder, 149 struct intel_crtc_state *pipe_config) 150 { 151 lpt_pch_get_config(pipe_config); 152 153 hsw_ddi_get_config(encoder, pipe_config); 154 155 pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | 156 DRM_MODE_FLAG_NHSYNC | 157 DRM_MODE_FLAG_PVSYNC | 158 DRM_MODE_FLAG_NVSYNC); 159 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); 160 } 161 162 /* Note: The caller is required to filter out dpms modes not supported by the 163 * platform. */ 164 static void intel_crt_set_dpms(struct intel_encoder *encoder, 165 const struct intel_crtc_state *crtc_state, 166 int mode) 167 { 168 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 169 struct intel_crt *crt = intel_encoder_to_crt(encoder); 170 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 171 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 172 u32 adpa; 173 174 if (DISPLAY_VER(dev_priv) >= 5) 175 adpa = ADPA_HOTPLUG_BITS; 176 else 177 adpa = 0; 178 179 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 180 adpa |= ADPA_HSYNC_ACTIVE_HIGH; 181 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 182 adpa |= ADPA_VSYNC_ACTIVE_HIGH; 183 184 /* For CPT allow 3 pipe config, for others just use A or B */ 185 if (HAS_PCH_LPT(dev_priv)) 186 ; /* Those bits don't exist here */ 187 else if (HAS_PCH_CPT(dev_priv)) 188 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe); 189 else 190 adpa |= ADPA_PIPE_SEL(crtc->pipe); 191 192 if (!HAS_PCH_SPLIT(dev_priv)) 193 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 194 195 switch (mode) { 196 case DRM_MODE_DPMS_ON: 197 adpa |= ADPA_DAC_ENABLE; 198 break; 199 case DRM_MODE_DPMS_STANDBY: 200 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; 201 break; 202 case DRM_MODE_DPMS_SUSPEND: 203 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; 204 break; 205 case DRM_MODE_DPMS_OFF: 206 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; 207 break; 208 } 209 210 intel_de_write(dev_priv, crt->adpa_reg, adpa); 211 } 212 213 static void intel_disable_crt(struct intel_atomic_state *state, 214 struct intel_encoder *encoder, 215 const struct intel_crtc_state *old_crtc_state, 216 const struct drm_connector_state *old_conn_state) 217 { 218 intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF); 219 } 220 221 static void pch_disable_crt(struct intel_atomic_state *state, 222 struct intel_encoder *encoder, 223 const struct intel_crtc_state *old_crtc_state, 224 const struct drm_connector_state *old_conn_state) 225 { 226 } 227 228 static void pch_post_disable_crt(struct intel_atomic_state *state, 229 struct intel_encoder *encoder, 230 const struct intel_crtc_state *old_crtc_state, 231 const struct drm_connector_state *old_conn_state) 232 { 233 intel_disable_crt(state, encoder, old_crtc_state, old_conn_state); 234 } 235 236 static void hsw_disable_crt(struct intel_atomic_state *state, 237 struct intel_encoder *encoder, 238 const struct intel_crtc_state *old_crtc_state, 239 const struct drm_connector_state *old_conn_state) 240 { 241 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 242 243 drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder); 244 245 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 246 } 247 248 static void hsw_post_disable_crt(struct intel_atomic_state *state, 249 struct intel_encoder *encoder, 250 const struct intel_crtc_state *old_crtc_state, 251 const struct drm_connector_state *old_conn_state) 252 { 253 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 254 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 255 256 intel_crtc_vblank_off(old_crtc_state); 257 258 intel_disable_transcoder(old_crtc_state); 259 260 intel_ddi_disable_transcoder_func(old_crtc_state); 261 262 ilk_pfit_disable(old_crtc_state); 263 264 intel_ddi_disable_transcoder_clock(old_crtc_state); 265 266 pch_post_disable_crt(state, encoder, old_crtc_state, old_conn_state); 267 268 lpt_pch_disable(state, crtc); 269 270 hsw_fdi_disable(encoder); 271 272 drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder); 273 274 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 275 } 276 277 static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state, 278 struct intel_encoder *encoder, 279 const struct intel_crtc_state *crtc_state, 280 const struct drm_connector_state *conn_state) 281 { 282 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 283 284 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder); 285 286 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 287 } 288 289 static void hsw_pre_enable_crt(struct intel_atomic_state *state, 290 struct intel_encoder *encoder, 291 const struct intel_crtc_state *crtc_state, 292 const struct drm_connector_state *conn_state) 293 { 294 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 295 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 296 enum pipe pipe = crtc->pipe; 297 298 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder); 299 300 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 301 302 hsw_fdi_link_train(encoder, crtc_state); 303 304 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 305 } 306 307 static void hsw_enable_crt(struct intel_atomic_state *state, 308 struct intel_encoder *encoder, 309 const struct intel_crtc_state *crtc_state, 310 const struct drm_connector_state *conn_state) 311 { 312 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 313 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 314 enum pipe pipe = crtc->pipe; 315 316 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder); 317 318 intel_ddi_enable_transcoder_func(encoder, crtc_state); 319 320 intel_enable_transcoder(crtc_state); 321 322 lpt_pch_enable(state, crtc); 323 324 intel_crtc_vblank_on(crtc_state); 325 326 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); 327 328 intel_crtc_wait_for_next_vblank(crtc); 329 intel_crtc_wait_for_next_vblank(crtc); 330 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 331 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 332 } 333 334 static void intel_enable_crt(struct intel_atomic_state *state, 335 struct intel_encoder *encoder, 336 const struct intel_crtc_state *crtc_state, 337 const struct drm_connector_state *conn_state) 338 { 339 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); 340 } 341 342 static enum drm_mode_status 343 intel_crt_mode_valid(struct drm_connector *connector, 344 struct drm_display_mode *mode) 345 { 346 struct drm_device *dev = connector->dev; 347 struct drm_i915_private *dev_priv = to_i915(dev); 348 int max_dotclk = dev_priv->max_dotclk_freq; 349 int max_clock; 350 351 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 352 return MODE_NO_DBLESCAN; 353 354 if (mode->clock < 25000) 355 return MODE_CLOCK_LOW; 356 357 if (HAS_PCH_LPT(dev_priv)) 358 max_clock = 180000; 359 else if (IS_VALLEYVIEW(dev_priv)) 360 /* 361 * 270 MHz due to current DPLL limits, 362 * DAC limit supposedly 355 MHz. 363 */ 364 max_clock = 270000; 365 else if (IS_DISPLAY_VER(dev_priv, 3, 4)) 366 max_clock = 400000; 367 else 368 max_clock = 350000; 369 if (mode->clock > max_clock) 370 return MODE_CLOCK_HIGH; 371 372 if (mode->clock > max_dotclk) 373 return MODE_CLOCK_HIGH; 374 375 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ 376 if (HAS_PCH_LPT(dev_priv) && 377 ilk_get_lanes_required(mode->clock, 270000, 24) > 2) 378 return MODE_CLOCK_HIGH; 379 380 /* HSW/BDW FDI limited to 4k */ 381 if (mode->hdisplay > 4096) 382 return MODE_H_ILLEGAL; 383 384 return MODE_OK; 385 } 386 387 static int intel_crt_compute_config(struct intel_encoder *encoder, 388 struct intel_crtc_state *pipe_config, 389 struct drm_connector_state *conn_state) 390 { 391 struct drm_display_mode *adjusted_mode = 392 &pipe_config->hw.adjusted_mode; 393 394 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 395 return -EINVAL; 396 397 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 398 399 return 0; 400 } 401 402 static int pch_crt_compute_config(struct intel_encoder *encoder, 403 struct intel_crtc_state *pipe_config, 404 struct drm_connector_state *conn_state) 405 { 406 struct drm_display_mode *adjusted_mode = 407 &pipe_config->hw.adjusted_mode; 408 409 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 410 return -EINVAL; 411 412 pipe_config->has_pch_encoder = true; 413 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 414 415 return 0; 416 } 417 418 static int hsw_crt_compute_config(struct intel_encoder *encoder, 419 struct intel_crtc_state *pipe_config, 420 struct drm_connector_state *conn_state) 421 { 422 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 423 struct drm_display_mode *adjusted_mode = 424 &pipe_config->hw.adjusted_mode; 425 426 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 427 return -EINVAL; 428 429 /* HSW/BDW FDI limited to 4k */ 430 if (adjusted_mode->crtc_hdisplay > 4096 || 431 adjusted_mode->crtc_hblank_start > 4096) 432 return -EINVAL; 433 434 pipe_config->has_pch_encoder = true; 435 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 436 437 /* LPT FDI RX only supports 8bpc. */ 438 if (HAS_PCH_LPT(dev_priv)) { 439 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { 440 drm_dbg_kms(&dev_priv->drm, 441 "LPT only supports 24bpp\n"); 442 return -EINVAL; 443 } 444 445 pipe_config->pipe_bpp = 24; 446 } 447 448 /* FDI must always be 2.7 GHz */ 449 pipe_config->port_clock = 135000 * 2; 450 451 adjusted_mode->crtc_clock = lpt_iclkip(pipe_config); 452 453 return 0; 454 } 455 456 static bool ilk_crt_detect_hotplug(struct drm_connector *connector) 457 { 458 struct drm_device *dev = connector->dev; 459 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 460 struct drm_i915_private *dev_priv = to_i915(dev); 461 u32 adpa; 462 bool ret; 463 464 /* The first time through, trigger an explicit detection cycle */ 465 if (crt->force_hotplug_required) { 466 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv); 467 u32 save_adpa; 468 469 crt->force_hotplug_required = false; 470 471 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); 472 drm_dbg_kms(&dev_priv->drm, 473 "trigger hotplug detect cycle: adpa=0x%x\n", adpa); 474 475 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 476 if (turn_off_dac) 477 adpa &= ~ADPA_DAC_ENABLE; 478 479 intel_de_write(dev_priv, crt->adpa_reg, adpa); 480 481 if (intel_de_wait_for_clear(dev_priv, 482 crt->adpa_reg, 483 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 484 1000)) 485 drm_dbg_kms(&dev_priv->drm, 486 "timed out waiting for FORCE_TRIGGER"); 487 488 if (turn_off_dac) { 489 intel_de_write(dev_priv, crt->adpa_reg, save_adpa); 490 intel_de_posting_read(dev_priv, crt->adpa_reg); 491 } 492 } 493 494 /* Check the status to see if both blue and green are on now */ 495 adpa = intel_de_read(dev_priv, crt->adpa_reg); 496 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 497 ret = true; 498 else 499 ret = false; 500 drm_dbg_kms(&dev_priv->drm, "ironlake hotplug adpa=0x%x, result %d\n", 501 adpa, ret); 502 503 return ret; 504 } 505 506 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) 507 { 508 struct drm_device *dev = connector->dev; 509 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 510 struct drm_i915_private *dev_priv = to_i915(dev); 511 bool reenable_hpd; 512 u32 adpa; 513 bool ret; 514 u32 save_adpa; 515 516 /* 517 * Doing a force trigger causes a hpd interrupt to get sent, which can 518 * get us stuck in a loop if we're polling: 519 * - We enable power wells and reset the ADPA 520 * - output_poll_exec does force probe on VGA, triggering a hpd 521 * - HPD handler waits for poll to unlock dev->mode_config.mutex 522 * - output_poll_exec shuts off the ADPA, unlocks 523 * dev->mode_config.mutex 524 * - HPD handler runs, resets ADPA and brings us back to the start 525 * 526 * Just disable HPD interrupts here to prevent this 527 */ 528 reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin); 529 530 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); 531 drm_dbg_kms(&dev_priv->drm, 532 "trigger hotplug detect cycle: adpa=0x%x\n", adpa); 533 534 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 535 536 intel_de_write(dev_priv, crt->adpa_reg, adpa); 537 538 if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg, 539 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) { 540 drm_dbg_kms(&dev_priv->drm, 541 "timed out waiting for FORCE_TRIGGER"); 542 intel_de_write(dev_priv, crt->adpa_reg, save_adpa); 543 } 544 545 /* Check the status to see if both blue and green are on now */ 546 adpa = intel_de_read(dev_priv, crt->adpa_reg); 547 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 548 ret = true; 549 else 550 ret = false; 551 552 drm_dbg_kms(&dev_priv->drm, 553 "valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); 554 555 if (reenable_hpd) 556 intel_hpd_enable(dev_priv, crt->base.hpd_pin); 557 558 return ret; 559 } 560 561 static bool intel_crt_detect_hotplug(struct drm_connector *connector) 562 { 563 struct drm_device *dev = connector->dev; 564 struct drm_i915_private *dev_priv = to_i915(dev); 565 u32 stat; 566 bool ret = false; 567 int i, tries = 0; 568 569 if (HAS_PCH_SPLIT(dev_priv)) 570 return ilk_crt_detect_hotplug(connector); 571 572 if (IS_VALLEYVIEW(dev_priv)) 573 return valleyview_crt_detect_hotplug(connector); 574 575 /* 576 * On 4 series desktop, CRT detect sequence need to be done twice 577 * to get a reliable result. 578 */ 579 580 if (IS_G45(dev_priv)) 581 tries = 2; 582 else 583 tries = 1; 584 585 for (i = 0; i < tries ; i++) { 586 /* turn on the FORCE_DETECT */ 587 i915_hotplug_interrupt_update(dev_priv, 588 CRT_HOTPLUG_FORCE_DETECT, 589 CRT_HOTPLUG_FORCE_DETECT); 590 /* wait for FORCE_DETECT to go off */ 591 if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN, 592 CRT_HOTPLUG_FORCE_DETECT, 1000)) 593 drm_dbg_kms(&dev_priv->drm, 594 "timed out waiting for FORCE_DETECT to go off"); 595 } 596 597 stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT); 598 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) 599 ret = true; 600 601 /* clear the interrupt we just generated, if any */ 602 intel_de_write(dev_priv, PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); 603 604 i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); 605 606 return ret; 607 } 608 609 static struct edid *intel_crt_get_edid(struct drm_connector *connector, 610 struct i2c_adapter *i2c) 611 { 612 struct edid *edid; 613 614 edid = drm_get_edid(connector, i2c); 615 616 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 617 drm_dbg_kms(connector->dev, 618 "CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); 619 intel_gmbus_force_bit(i2c, true); 620 edid = drm_get_edid(connector, i2c); 621 intel_gmbus_force_bit(i2c, false); 622 } 623 624 return edid; 625 } 626 627 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ 628 static int intel_crt_ddc_get_modes(struct drm_connector *connector, 629 struct i2c_adapter *adapter) 630 { 631 struct edid *edid; 632 int ret; 633 634 edid = intel_crt_get_edid(connector, adapter); 635 if (!edid) 636 return 0; 637 638 ret = intel_connector_update_modes(connector, edid); 639 kfree(edid); 640 641 return ret; 642 } 643 644 static bool intel_crt_detect_ddc(struct drm_connector *connector) 645 { 646 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 647 struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev); 648 struct edid *edid; 649 struct i2c_adapter *i2c; 650 bool ret = false; 651 652 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->display.vbt.crt_ddc_pin); 653 edid = intel_crt_get_edid(connector, i2c); 654 655 if (edid) { 656 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; 657 658 /* 659 * This may be a DVI-I connector with a shared DDC 660 * link between analog and digital outputs, so we 661 * have to check the EDID input spec of the attached device. 662 */ 663 if (!is_digital) { 664 drm_dbg_kms(&dev_priv->drm, 665 "CRT detected via DDC:0x50 [EDID]\n"); 666 ret = true; 667 } else { 668 drm_dbg_kms(&dev_priv->drm, 669 "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); 670 } 671 } else { 672 drm_dbg_kms(&dev_priv->drm, 673 "CRT not detected via DDC:0x50 [no valid EDID found]\n"); 674 } 675 676 kfree(edid); 677 678 return ret; 679 } 680 681 static enum drm_connector_status 682 intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe) 683 { 684 struct drm_device *dev = crt->base.base.dev; 685 struct drm_i915_private *dev_priv = to_i915(dev); 686 enum transcoder cpu_transcoder = (enum transcoder)pipe; 687 u32 save_bclrpat; 688 u32 save_vtotal; 689 u32 vtotal, vactive; 690 u32 vsample; 691 u32 vblank, vblank_start, vblank_end; 692 u32 dsl; 693 u8 st00; 694 enum drm_connector_status status; 695 696 drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n"); 697 698 save_bclrpat = intel_de_read(dev_priv, BCLRPAT(cpu_transcoder)); 699 save_vtotal = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)); 700 vblank = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder)); 701 702 vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1; 703 vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1; 704 705 vblank_start = REG_FIELD_GET(VBLANK_START_MASK, vblank) + 1; 706 vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1; 707 708 /* Set the border color to purple. */ 709 intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), 0x500050); 710 711 if (DISPLAY_VER(dev_priv) != 2) { 712 u32 transconf = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); 713 714 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), 715 transconf | TRANSCONF_FORCE_BORDER); 716 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 717 /* Wait for next Vblank to substitue 718 * border color for Color info */ 719 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe)); 720 st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE); 721 status = ((st00 & (1 << 4)) != 0) ? 722 connector_status_connected : 723 connector_status_disconnected; 724 725 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), transconf); 726 } else { 727 bool restore_vblank = false; 728 int count, detect; 729 730 /* 731 * If there isn't any border, add some. 732 * Yes, this will flicker 733 */ 734 if (vblank_start <= vactive && vblank_end >= vtotal) { 735 u32 vsync = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder)); 736 u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1; 737 738 vblank_start = vsync_start; 739 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), 740 VBLANK_START(vblank_start - 1) | 741 VBLANK_END(vblank_end - 1)); 742 restore_vblank = true; 743 } 744 /* sample in the vertical border, selecting the larger one */ 745 if (vblank_start - vactive >= vtotal - vblank_end) 746 vsample = (vblank_start + vactive) >> 1; 747 else 748 vsample = (vtotal + vblank_end) >> 1; 749 750 /* 751 * Wait for the border to be displayed 752 */ 753 while (intel_de_read(dev_priv, PIPEDSL(pipe)) >= vactive) 754 ; 755 while ((dsl = intel_de_read(dev_priv, PIPEDSL(pipe))) <= vsample) 756 ; 757 /* 758 * Watch ST00 for an entire scanline 759 */ 760 detect = 0; 761 count = 0; 762 do { 763 count++; 764 /* Read the ST00 VGA status register */ 765 st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE); 766 if (st00 & (1 << 4)) 767 detect++; 768 } while ((intel_de_read(dev_priv, PIPEDSL(pipe)) == dsl)); 769 770 /* restore vblank if necessary */ 771 if (restore_vblank) 772 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), vblank); 773 /* 774 * If more than 3/4 of the scanline detected a monitor, 775 * then it is assumed to be present. This works even on i830, 776 * where there isn't any way to force the border color across 777 * the screen 778 */ 779 status = detect * 4 > count * 3 ? 780 connector_status_connected : 781 connector_status_disconnected; 782 } 783 784 /* Restore previous settings */ 785 intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), save_bclrpat); 786 787 return status; 788 } 789 790 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id) 791 { 792 DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident); 793 return 1; 794 } 795 796 static const struct dmi_system_id intel_spurious_crt_detect[] = { 797 { 798 .callback = intel_spurious_crt_detect_dmi_callback, 799 .ident = "ACER ZGB", 800 .matches = { 801 DMI_MATCH(DMI_SYS_VENDOR, "ACER"), 802 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), 803 }, 804 }, 805 { 806 .callback = intel_spurious_crt_detect_dmi_callback, 807 .ident = "Intel DZ77BH-55K", 808 .matches = { 809 DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"), 810 DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"), 811 }, 812 }, 813 { } 814 }; 815 816 static int 817 intel_crt_detect(struct drm_connector *connector, 818 struct drm_modeset_acquire_ctx *ctx, 819 bool force) 820 { 821 struct drm_i915_private *dev_priv = to_i915(connector->dev); 822 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 823 struct intel_encoder *intel_encoder = &crt->base; 824 intel_wakeref_t wakeref; 825 int status, ret; 826 struct intel_load_detect_pipe tmp; 827 828 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s] force=%d\n", 829 connector->base.id, connector->name, 830 force); 831 832 if (!INTEL_DISPLAY_ENABLED(dev_priv)) 833 return connector_status_disconnected; 834 835 if (dev_priv->params.load_detect_test) { 836 wakeref = intel_display_power_get(dev_priv, 837 intel_encoder->power_domain); 838 goto load_detect; 839 } 840 841 /* Skip machines without VGA that falsely report hotplug events */ 842 if (dmi_check_system(intel_spurious_crt_detect)) 843 return connector_status_disconnected; 844 845 wakeref = intel_display_power_get(dev_priv, 846 intel_encoder->power_domain); 847 848 if (I915_HAS_HOTPLUG(dev_priv)) { 849 /* We can not rely on the HPD pin always being correctly wired 850 * up, for example many KVM do not pass it through, and so 851 * only trust an assertion that the monitor is connected. 852 */ 853 if (intel_crt_detect_hotplug(connector)) { 854 drm_dbg_kms(&dev_priv->drm, 855 "CRT detected via hotplug\n"); 856 status = connector_status_connected; 857 goto out; 858 } else 859 drm_dbg_kms(&dev_priv->drm, 860 "CRT not detected via hotplug\n"); 861 } 862 863 if (intel_crt_detect_ddc(connector)) { 864 status = connector_status_connected; 865 goto out; 866 } 867 868 /* Load detection is broken on HPD capable machines. Whoever wants a 869 * broken monitor (without edid) to work behind a broken kvm (that fails 870 * to have the right resistors for HP detection) needs to fix this up. 871 * For now just bail out. */ 872 if (I915_HAS_HOTPLUG(dev_priv)) { 873 status = connector_status_disconnected; 874 goto out; 875 } 876 877 load_detect: 878 if (!force) { 879 status = connector->status; 880 goto out; 881 } 882 883 /* for pre-945g platforms use load detect */ 884 ret = intel_get_load_detect_pipe(connector, &tmp, ctx); 885 if (ret > 0) { 886 if (intel_crt_detect_ddc(connector)) 887 status = connector_status_connected; 888 else if (DISPLAY_VER(dev_priv) < 4) 889 status = intel_crt_load_detect(crt, 890 to_intel_crtc(connector->state->crtc)->pipe); 891 else if (dev_priv->params.load_detect_test) 892 status = connector_status_disconnected; 893 else 894 status = connector_status_unknown; 895 intel_release_load_detect_pipe(connector, &tmp, ctx); 896 } else if (ret == 0) { 897 status = connector_status_unknown; 898 } else { 899 status = ret; 900 } 901 902 out: 903 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 904 905 /* 906 * Make sure the refs for power wells enabled during detect are 907 * dropped to avoid a new detect cycle triggered by HPD polling. 908 */ 909 intel_display_power_flush_work(dev_priv); 910 911 return status; 912 } 913 914 static int intel_crt_get_modes(struct drm_connector *connector) 915 { 916 struct drm_device *dev = connector->dev; 917 struct drm_i915_private *dev_priv = to_i915(dev); 918 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 919 struct intel_encoder *intel_encoder = &crt->base; 920 intel_wakeref_t wakeref; 921 struct i2c_adapter *i2c; 922 int ret; 923 924 wakeref = intel_display_power_get(dev_priv, 925 intel_encoder->power_domain); 926 927 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->display.vbt.crt_ddc_pin); 928 ret = intel_crt_ddc_get_modes(connector, i2c); 929 if (ret || !IS_G4X(dev_priv)) 930 goto out; 931 932 /* Try to probe digital port for output in DVI-I -> VGA mode. */ 933 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); 934 ret = intel_crt_ddc_get_modes(connector, i2c); 935 936 out: 937 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 938 939 return ret; 940 } 941 942 void intel_crt_reset(struct drm_encoder *encoder) 943 { 944 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 945 struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder)); 946 947 if (DISPLAY_VER(dev_priv) >= 5) { 948 u32 adpa; 949 950 adpa = intel_de_read(dev_priv, crt->adpa_reg); 951 adpa &= ~ADPA_CRT_HOTPLUG_MASK; 952 adpa |= ADPA_HOTPLUG_BITS; 953 intel_de_write(dev_priv, crt->adpa_reg, adpa); 954 intel_de_posting_read(dev_priv, crt->adpa_reg); 955 956 drm_dbg_kms(&dev_priv->drm, "crt adpa set to 0x%x\n", adpa); 957 crt->force_hotplug_required = true; 958 } 959 960 } 961 962 /* 963 * Routines for controlling stuff on the analog port 964 */ 965 966 static const struct drm_connector_funcs intel_crt_connector_funcs = { 967 .fill_modes = drm_helper_probe_single_connector_modes, 968 .late_register = intel_connector_register, 969 .early_unregister = intel_connector_unregister, 970 .destroy = intel_connector_destroy, 971 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 972 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 973 }; 974 975 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { 976 .detect_ctx = intel_crt_detect, 977 .mode_valid = intel_crt_mode_valid, 978 .get_modes = intel_crt_get_modes, 979 }; 980 981 static const struct drm_encoder_funcs intel_crt_enc_funcs = { 982 .reset = intel_crt_reset, 983 .destroy = intel_encoder_destroy, 984 }; 985 986 void intel_crt_init(struct drm_i915_private *dev_priv) 987 { 988 struct drm_connector *connector; 989 struct intel_crt *crt; 990 struct intel_connector *intel_connector; 991 i915_reg_t adpa_reg; 992 u32 adpa; 993 994 if (HAS_PCH_SPLIT(dev_priv)) 995 adpa_reg = PCH_ADPA; 996 else if (IS_VALLEYVIEW(dev_priv)) 997 adpa_reg = VLV_ADPA; 998 else 999 adpa_reg = ADPA; 1000 1001 adpa = intel_de_read(dev_priv, adpa_reg); 1002 if ((adpa & ADPA_DAC_ENABLE) == 0) { 1003 /* 1004 * On some machines (some IVB at least) CRT can be 1005 * fused off, but there's no known fuse bit to 1006 * indicate that. On these machine the ADPA register 1007 * works normally, except the DAC enable bit won't 1008 * take. So the only way to tell is attempt to enable 1009 * it and see what happens. 1010 */ 1011 intel_de_write(dev_priv, adpa_reg, 1012 adpa | ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); 1013 if ((intel_de_read(dev_priv, adpa_reg) & ADPA_DAC_ENABLE) == 0) 1014 return; 1015 intel_de_write(dev_priv, adpa_reg, adpa); 1016 } 1017 1018 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); 1019 if (!crt) 1020 return; 1021 1022 intel_connector = intel_connector_alloc(); 1023 if (!intel_connector) { 1024 kfree(crt); 1025 return; 1026 } 1027 1028 connector = &intel_connector->base; 1029 crt->connector = intel_connector; 1030 drm_connector_init(&dev_priv->drm, &intel_connector->base, 1031 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); 1032 1033 drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs, 1034 DRM_MODE_ENCODER_DAC, "CRT"); 1035 1036 intel_connector_attach_encoder(intel_connector, &crt->base); 1037 1038 crt->base.type = INTEL_OUTPUT_ANALOG; 1039 crt->base.cloneable = BIT(INTEL_OUTPUT_DVO) | BIT(INTEL_OUTPUT_HDMI); 1040 if (IS_I830(dev_priv)) 1041 crt->base.pipe_mask = BIT(PIPE_A); 1042 else 1043 crt->base.pipe_mask = ~0; 1044 1045 if (DISPLAY_VER(dev_priv) != 2) 1046 connector->interlace_allowed = true; 1047 1048 crt->adpa_reg = adpa_reg; 1049 1050 crt->base.power_domain = POWER_DOMAIN_PORT_CRT; 1051 1052 if (I915_HAS_HOTPLUG(dev_priv) && 1053 !dmi_check_system(intel_spurious_crt_detect)) { 1054 crt->base.hpd_pin = HPD_CRT; 1055 crt->base.hotplug = intel_encoder_hotplug; 1056 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 1057 } else { 1058 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1059 } 1060 1061 if (HAS_DDI(dev_priv)) { 1062 crt->base.port = PORT_E; 1063 crt->base.get_config = hsw_crt_get_config; 1064 crt->base.get_hw_state = intel_ddi_get_hw_state; 1065 crt->base.compute_config = hsw_crt_compute_config; 1066 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt; 1067 crt->base.pre_enable = hsw_pre_enable_crt; 1068 crt->base.enable = hsw_enable_crt; 1069 crt->base.disable = hsw_disable_crt; 1070 crt->base.post_disable = hsw_post_disable_crt; 1071 crt->base.enable_clock = hsw_ddi_enable_clock; 1072 crt->base.disable_clock = hsw_ddi_disable_clock; 1073 crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled; 1074 1075 intel_ddi_buf_trans_init(&crt->base); 1076 } else { 1077 if (HAS_PCH_SPLIT(dev_priv)) { 1078 crt->base.compute_config = pch_crt_compute_config; 1079 crt->base.disable = pch_disable_crt; 1080 crt->base.post_disable = pch_post_disable_crt; 1081 } else { 1082 crt->base.compute_config = intel_crt_compute_config; 1083 crt->base.disable = intel_disable_crt; 1084 } 1085 crt->base.port = PORT_NONE; 1086 crt->base.get_config = intel_crt_get_config; 1087 crt->base.get_hw_state = intel_crt_get_hw_state; 1088 crt->base.enable = intel_enable_crt; 1089 } 1090 intel_connector->get_hw_state = intel_connector_get_hw_state; 1091 1092 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); 1093 1094 /* 1095 * TODO: find a proper way to discover whether we need to set the the 1096 * polarity and link reversal bits or not, instead of relying on the 1097 * BIOS. 1098 */ 1099 if (HAS_PCH_LPT(dev_priv)) { 1100 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | 1101 FDI_RX_LINK_REVERSAL_OVERRIDE; 1102 1103 dev_priv->display.fdi.rx_config = intel_de_read(dev_priv, 1104 FDI_RX_CTL(PIPE_A)) & fdi_config; 1105 } 1106 1107 intel_crt_reset(&crt->base.base); 1108 } 1109