1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dmi.h> 28 #include <linux/i2c.h> 29 #include <linux/slab.h> 30 31 #include <drm/drm_atomic_helper.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_edid.h> 34 #include <drm/drm_probe_helper.h> 35 #include <drm/i915_drm.h> 36 37 #include "i915_drv.h" 38 #include "intel_connector.h" 39 #include "intel_crt.h" 40 #include "intel_ddi.h" 41 #include "intel_drv.h" 42 #include "intel_fifo_underrun.h" 43 #include "intel_gmbus.h" 44 #include "intel_hotplug.h" 45 46 /* Here's the desired hotplug mode */ 47 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ 48 ADPA_CRT_HOTPLUG_WARMUP_10MS | \ 49 ADPA_CRT_HOTPLUG_SAMPLE_4S | \ 50 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ 51 ADPA_CRT_HOTPLUG_VOLREF_325MV | \ 52 ADPA_CRT_HOTPLUG_ENABLE) 53 54 struct intel_crt { 55 struct intel_encoder base; 56 /* DPMS state is stored in the connector, which we need in the 57 * encoder's enable/disable callbacks */ 58 struct intel_connector *connector; 59 bool force_hotplug_required; 60 i915_reg_t adpa_reg; 61 }; 62 63 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) 64 { 65 return container_of(encoder, struct intel_crt, base); 66 } 67 68 static struct intel_crt *intel_attached_crt(struct drm_connector *connector) 69 { 70 return intel_encoder_to_crt(intel_attached_encoder(connector)); 71 } 72 73 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv, 74 i915_reg_t adpa_reg, enum pipe *pipe) 75 { 76 u32 val; 77 78 val = I915_READ(adpa_reg); 79 80 /* asserts want to know the pipe even if the port is disabled */ 81 if (HAS_PCH_CPT(dev_priv)) 82 *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT; 83 else 84 *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT; 85 86 return val & ADPA_DAC_ENABLE; 87 } 88 89 static bool intel_crt_get_hw_state(struct intel_encoder *encoder, 90 enum pipe *pipe) 91 { 92 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 93 struct intel_crt *crt = intel_encoder_to_crt(encoder); 94 intel_wakeref_t wakeref; 95 bool ret; 96 97 wakeref = intel_display_power_get_if_enabled(dev_priv, 98 encoder->power_domain); 99 if (!wakeref) 100 return false; 101 102 ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe); 103 104 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 105 106 return ret; 107 } 108 109 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) 110 { 111 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 112 struct intel_crt *crt = intel_encoder_to_crt(encoder); 113 u32 tmp, flags = 0; 114 115 tmp = I915_READ(crt->adpa_reg); 116 117 if (tmp & ADPA_HSYNC_ACTIVE_HIGH) 118 flags |= DRM_MODE_FLAG_PHSYNC; 119 else 120 flags |= DRM_MODE_FLAG_NHSYNC; 121 122 if (tmp & ADPA_VSYNC_ACTIVE_HIGH) 123 flags |= DRM_MODE_FLAG_PVSYNC; 124 else 125 flags |= DRM_MODE_FLAG_NVSYNC; 126 127 return flags; 128 } 129 130 static void intel_crt_get_config(struct intel_encoder *encoder, 131 struct intel_crtc_state *pipe_config) 132 { 133 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 134 135 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); 136 137 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; 138 } 139 140 static void hsw_crt_get_config(struct intel_encoder *encoder, 141 struct intel_crtc_state *pipe_config) 142 { 143 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 144 145 intel_ddi_get_config(encoder, pipe_config); 146 147 pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | 148 DRM_MODE_FLAG_NHSYNC | 149 DRM_MODE_FLAG_PVSYNC | 150 DRM_MODE_FLAG_NVSYNC); 151 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); 152 153 pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); 154 } 155 156 /* Note: The caller is required to filter out dpms modes not supported by the 157 * platform. */ 158 static void intel_crt_set_dpms(struct intel_encoder *encoder, 159 const struct intel_crtc_state *crtc_state, 160 int mode) 161 { 162 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 163 struct intel_crt *crt = intel_encoder_to_crt(encoder); 164 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 165 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; 166 u32 adpa; 167 168 if (INTEL_GEN(dev_priv) >= 5) 169 adpa = ADPA_HOTPLUG_BITS; 170 else 171 adpa = 0; 172 173 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 174 adpa |= ADPA_HSYNC_ACTIVE_HIGH; 175 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 176 adpa |= ADPA_VSYNC_ACTIVE_HIGH; 177 178 /* For CPT allow 3 pipe config, for others just use A or B */ 179 if (HAS_PCH_LPT(dev_priv)) 180 ; /* Those bits don't exist here */ 181 else if (HAS_PCH_CPT(dev_priv)) 182 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe); 183 else 184 adpa |= ADPA_PIPE_SEL(crtc->pipe); 185 186 if (!HAS_PCH_SPLIT(dev_priv)) 187 I915_WRITE(BCLRPAT(crtc->pipe), 0); 188 189 switch (mode) { 190 case DRM_MODE_DPMS_ON: 191 adpa |= ADPA_DAC_ENABLE; 192 break; 193 case DRM_MODE_DPMS_STANDBY: 194 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; 195 break; 196 case DRM_MODE_DPMS_SUSPEND: 197 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; 198 break; 199 case DRM_MODE_DPMS_OFF: 200 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; 201 break; 202 } 203 204 I915_WRITE(crt->adpa_reg, adpa); 205 } 206 207 static void intel_disable_crt(struct intel_encoder *encoder, 208 const struct intel_crtc_state *old_crtc_state, 209 const struct drm_connector_state *old_conn_state) 210 { 211 intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF); 212 } 213 214 static void pch_disable_crt(struct intel_encoder *encoder, 215 const struct intel_crtc_state *old_crtc_state, 216 const struct drm_connector_state *old_conn_state) 217 { 218 } 219 220 static void pch_post_disable_crt(struct intel_encoder *encoder, 221 const struct intel_crtc_state *old_crtc_state, 222 const struct drm_connector_state *old_conn_state) 223 { 224 intel_disable_crt(encoder, old_crtc_state, old_conn_state); 225 } 226 227 static void hsw_disable_crt(struct intel_encoder *encoder, 228 const struct intel_crtc_state *old_crtc_state, 229 const struct drm_connector_state *old_conn_state) 230 { 231 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 232 233 WARN_ON(!old_crtc_state->has_pch_encoder); 234 235 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 236 } 237 238 static void hsw_post_disable_crt(struct intel_encoder *encoder, 239 const struct intel_crtc_state *old_crtc_state, 240 const struct drm_connector_state *old_conn_state) 241 { 242 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 243 244 intel_ddi_disable_pipe_clock(old_crtc_state); 245 246 pch_post_disable_crt(encoder, old_crtc_state, old_conn_state); 247 248 lpt_disable_pch_transcoder(dev_priv); 249 lpt_disable_iclkip(dev_priv); 250 251 intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state); 252 253 WARN_ON(!old_crtc_state->has_pch_encoder); 254 255 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 256 } 257 258 static void hsw_pre_pll_enable_crt(struct intel_encoder *encoder, 259 const struct intel_crtc_state *crtc_state, 260 const struct drm_connector_state *conn_state) 261 { 262 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 263 264 WARN_ON(!crtc_state->has_pch_encoder); 265 266 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 267 } 268 269 static void hsw_pre_enable_crt(struct intel_encoder *encoder, 270 const struct intel_crtc_state *crtc_state, 271 const struct drm_connector_state *conn_state) 272 { 273 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 274 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 275 enum pipe pipe = crtc->pipe; 276 277 WARN_ON(!crtc_state->has_pch_encoder); 278 279 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 280 281 dev_priv->display.fdi_link_train(crtc, crtc_state); 282 283 intel_ddi_enable_pipe_clock(crtc_state); 284 } 285 286 static void hsw_enable_crt(struct intel_encoder *encoder, 287 const struct intel_crtc_state *crtc_state, 288 const struct drm_connector_state *conn_state) 289 { 290 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 291 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 292 enum pipe pipe = crtc->pipe; 293 294 WARN_ON(!crtc_state->has_pch_encoder); 295 296 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); 297 298 intel_wait_for_vblank(dev_priv, pipe); 299 intel_wait_for_vblank(dev_priv, pipe); 300 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 301 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 302 } 303 304 static void intel_enable_crt(struct intel_encoder *encoder, 305 const struct intel_crtc_state *crtc_state, 306 const struct drm_connector_state *conn_state) 307 { 308 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); 309 } 310 311 static enum drm_mode_status 312 intel_crt_mode_valid(struct drm_connector *connector, 313 struct drm_display_mode *mode) 314 { 315 struct drm_device *dev = connector->dev; 316 struct drm_i915_private *dev_priv = to_i915(dev); 317 int max_dotclk = dev_priv->max_dotclk_freq; 318 int max_clock; 319 320 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 321 return MODE_NO_DBLESCAN; 322 323 if (mode->clock < 25000) 324 return MODE_CLOCK_LOW; 325 326 if (HAS_PCH_LPT(dev_priv)) 327 max_clock = 180000; 328 else if (IS_VALLEYVIEW(dev_priv)) 329 /* 330 * 270 MHz due to current DPLL limits, 331 * DAC limit supposedly 355 MHz. 332 */ 333 max_clock = 270000; 334 else if (IS_GEN_RANGE(dev_priv, 3, 4)) 335 max_clock = 400000; 336 else 337 max_clock = 350000; 338 if (mode->clock > max_clock) 339 return MODE_CLOCK_HIGH; 340 341 if (mode->clock > max_dotclk) 342 return MODE_CLOCK_HIGH; 343 344 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ 345 if (HAS_PCH_LPT(dev_priv) && 346 (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) 347 return MODE_CLOCK_HIGH; 348 349 /* HSW/BDW FDI limited to 4k */ 350 if (mode->hdisplay > 4096) 351 return MODE_H_ILLEGAL; 352 353 return MODE_OK; 354 } 355 356 static int intel_crt_compute_config(struct intel_encoder *encoder, 357 struct intel_crtc_state *pipe_config, 358 struct drm_connector_state *conn_state) 359 { 360 struct drm_display_mode *adjusted_mode = 361 &pipe_config->base.adjusted_mode; 362 363 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 364 return -EINVAL; 365 366 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 367 368 return 0; 369 } 370 371 static int pch_crt_compute_config(struct intel_encoder *encoder, 372 struct intel_crtc_state *pipe_config, 373 struct drm_connector_state *conn_state) 374 { 375 struct drm_display_mode *adjusted_mode = 376 &pipe_config->base.adjusted_mode; 377 378 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 379 return -EINVAL; 380 381 pipe_config->has_pch_encoder = true; 382 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 383 384 return 0; 385 } 386 387 static int hsw_crt_compute_config(struct intel_encoder *encoder, 388 struct intel_crtc_state *pipe_config, 389 struct drm_connector_state *conn_state) 390 { 391 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 392 struct drm_display_mode *adjusted_mode = 393 &pipe_config->base.adjusted_mode; 394 395 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 396 return -EINVAL; 397 398 /* HSW/BDW FDI limited to 4k */ 399 if (adjusted_mode->crtc_hdisplay > 4096 || 400 adjusted_mode->crtc_hblank_start > 4096) 401 return -EINVAL; 402 403 pipe_config->has_pch_encoder = true; 404 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 405 406 /* LPT FDI RX only supports 8bpc. */ 407 if (HAS_PCH_LPT(dev_priv)) { 408 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { 409 DRM_DEBUG_KMS("LPT only supports 24bpp\n"); 410 return -EINVAL; 411 } 412 413 pipe_config->pipe_bpp = 24; 414 } 415 416 /* FDI must always be 2.7 GHz */ 417 pipe_config->port_clock = 135000 * 2; 418 419 return 0; 420 } 421 422 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) 423 { 424 struct drm_device *dev = connector->dev; 425 struct intel_crt *crt = intel_attached_crt(connector); 426 struct drm_i915_private *dev_priv = to_i915(dev); 427 u32 adpa; 428 bool ret; 429 430 /* The first time through, trigger an explicit detection cycle */ 431 if (crt->force_hotplug_required) { 432 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv); 433 u32 save_adpa; 434 435 crt->force_hotplug_required = 0; 436 437 save_adpa = adpa = I915_READ(crt->adpa_reg); 438 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 439 440 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 441 if (turn_off_dac) 442 adpa &= ~ADPA_DAC_ENABLE; 443 444 I915_WRITE(crt->adpa_reg, adpa); 445 446 if (intel_wait_for_register(&dev_priv->uncore, 447 crt->adpa_reg, 448 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0, 449 1000)) 450 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 451 452 if (turn_off_dac) { 453 I915_WRITE(crt->adpa_reg, save_adpa); 454 POSTING_READ(crt->adpa_reg); 455 } 456 } 457 458 /* Check the status to see if both blue and green are on now */ 459 adpa = I915_READ(crt->adpa_reg); 460 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 461 ret = true; 462 else 463 ret = false; 464 DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); 465 466 return ret; 467 } 468 469 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) 470 { 471 struct drm_device *dev = connector->dev; 472 struct intel_crt *crt = intel_attached_crt(connector); 473 struct drm_i915_private *dev_priv = to_i915(dev); 474 bool reenable_hpd; 475 u32 adpa; 476 bool ret; 477 u32 save_adpa; 478 479 /* 480 * Doing a force trigger causes a hpd interrupt to get sent, which can 481 * get us stuck in a loop if we're polling: 482 * - We enable power wells and reset the ADPA 483 * - output_poll_exec does force probe on VGA, triggering a hpd 484 * - HPD handler waits for poll to unlock dev->mode_config.mutex 485 * - output_poll_exec shuts off the ADPA, unlocks 486 * dev->mode_config.mutex 487 * - HPD handler runs, resets ADPA and brings us back to the start 488 * 489 * Just disable HPD interrupts here to prevent this 490 */ 491 reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin); 492 493 save_adpa = adpa = I915_READ(crt->adpa_reg); 494 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 495 496 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 497 498 I915_WRITE(crt->adpa_reg, adpa); 499 500 if (intel_wait_for_register(&dev_priv->uncore, 501 crt->adpa_reg, 502 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0, 503 1000)) { 504 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 505 I915_WRITE(crt->adpa_reg, save_adpa); 506 } 507 508 /* Check the status to see if both blue and green are on now */ 509 adpa = I915_READ(crt->adpa_reg); 510 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 511 ret = true; 512 else 513 ret = false; 514 515 DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); 516 517 if (reenable_hpd) 518 intel_hpd_enable(dev_priv, crt->base.hpd_pin); 519 520 return ret; 521 } 522 523 static bool intel_crt_detect_hotplug(struct drm_connector *connector) 524 { 525 struct drm_device *dev = connector->dev; 526 struct drm_i915_private *dev_priv = to_i915(dev); 527 u32 stat; 528 bool ret = false; 529 int i, tries = 0; 530 531 if (HAS_PCH_SPLIT(dev_priv)) 532 return intel_ironlake_crt_detect_hotplug(connector); 533 534 if (IS_VALLEYVIEW(dev_priv)) 535 return valleyview_crt_detect_hotplug(connector); 536 537 /* 538 * On 4 series desktop, CRT detect sequence need to be done twice 539 * to get a reliable result. 540 */ 541 542 if (IS_G45(dev_priv)) 543 tries = 2; 544 else 545 tries = 1; 546 547 for (i = 0; i < tries ; i++) { 548 /* turn on the FORCE_DETECT */ 549 i915_hotplug_interrupt_update(dev_priv, 550 CRT_HOTPLUG_FORCE_DETECT, 551 CRT_HOTPLUG_FORCE_DETECT); 552 /* wait for FORCE_DETECT to go off */ 553 if (intel_wait_for_register(&dev_priv->uncore, PORT_HOTPLUG_EN, 554 CRT_HOTPLUG_FORCE_DETECT, 0, 555 1000)) 556 DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); 557 } 558 559 stat = I915_READ(PORT_HOTPLUG_STAT); 560 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) 561 ret = true; 562 563 /* clear the interrupt we just generated, if any */ 564 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); 565 566 i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); 567 568 return ret; 569 } 570 571 static struct edid *intel_crt_get_edid(struct drm_connector *connector, 572 struct i2c_adapter *i2c) 573 { 574 struct edid *edid; 575 576 edid = drm_get_edid(connector, i2c); 577 578 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 579 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); 580 intel_gmbus_force_bit(i2c, true); 581 edid = drm_get_edid(connector, i2c); 582 intel_gmbus_force_bit(i2c, false); 583 } 584 585 return edid; 586 } 587 588 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ 589 static int intel_crt_ddc_get_modes(struct drm_connector *connector, 590 struct i2c_adapter *adapter) 591 { 592 struct edid *edid; 593 int ret; 594 595 edid = intel_crt_get_edid(connector, adapter); 596 if (!edid) 597 return 0; 598 599 ret = intel_connector_update_modes(connector, edid); 600 kfree(edid); 601 602 return ret; 603 } 604 605 static bool intel_crt_detect_ddc(struct drm_connector *connector) 606 { 607 struct intel_crt *crt = intel_attached_crt(connector); 608 struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev); 609 struct edid *edid; 610 struct i2c_adapter *i2c; 611 bool ret = false; 612 613 BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); 614 615 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 616 edid = intel_crt_get_edid(connector, i2c); 617 618 if (edid) { 619 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; 620 621 /* 622 * This may be a DVI-I connector with a shared DDC 623 * link between analog and digital outputs, so we 624 * have to check the EDID input spec of the attached device. 625 */ 626 if (!is_digital) { 627 DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); 628 ret = true; 629 } else { 630 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); 631 } 632 } else { 633 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); 634 } 635 636 kfree(edid); 637 638 return ret; 639 } 640 641 static enum drm_connector_status 642 intel_crt_load_detect(struct intel_crt *crt, u32 pipe) 643 { 644 struct drm_device *dev = crt->base.base.dev; 645 struct drm_i915_private *dev_priv = to_i915(dev); 646 struct intel_uncore *uncore = &dev_priv->uncore; 647 u32 save_bclrpat; 648 u32 save_vtotal; 649 u32 vtotal, vactive; 650 u32 vsample; 651 u32 vblank, vblank_start, vblank_end; 652 u32 dsl; 653 i915_reg_t bclrpat_reg, vtotal_reg, 654 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg; 655 u8 st00; 656 enum drm_connector_status status; 657 658 DRM_DEBUG_KMS("starting load-detect on CRT\n"); 659 660 bclrpat_reg = BCLRPAT(pipe); 661 vtotal_reg = VTOTAL(pipe); 662 vblank_reg = VBLANK(pipe); 663 vsync_reg = VSYNC(pipe); 664 pipeconf_reg = PIPECONF(pipe); 665 pipe_dsl_reg = PIPEDSL(pipe); 666 667 save_bclrpat = intel_uncore_read(uncore, bclrpat_reg); 668 save_vtotal = intel_uncore_read(uncore, vtotal_reg); 669 vblank = intel_uncore_read(uncore, vblank_reg); 670 671 vtotal = ((save_vtotal >> 16) & 0xfff) + 1; 672 vactive = (save_vtotal & 0x7ff) + 1; 673 674 vblank_start = (vblank & 0xfff) + 1; 675 vblank_end = ((vblank >> 16) & 0xfff) + 1; 676 677 /* Set the border color to purple. */ 678 intel_uncore_write(uncore, bclrpat_reg, 0x500050); 679 680 if (!IS_GEN(dev_priv, 2)) { 681 u32 pipeconf = intel_uncore_read(uncore, pipeconf_reg); 682 intel_uncore_write(uncore, 683 pipeconf_reg, 684 pipeconf | PIPECONF_FORCE_BORDER); 685 intel_uncore_posting_read(uncore, pipeconf_reg); 686 /* Wait for next Vblank to substitue 687 * border color for Color info */ 688 intel_wait_for_vblank(dev_priv, pipe); 689 st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE); 690 status = ((st00 & (1 << 4)) != 0) ? 691 connector_status_connected : 692 connector_status_disconnected; 693 694 intel_uncore_write(uncore, pipeconf_reg, pipeconf); 695 } else { 696 bool restore_vblank = false; 697 int count, detect; 698 699 /* 700 * If there isn't any border, add some. 701 * Yes, this will flicker 702 */ 703 if (vblank_start <= vactive && vblank_end >= vtotal) { 704 u32 vsync = I915_READ(vsync_reg); 705 u32 vsync_start = (vsync & 0xffff) + 1; 706 707 vblank_start = vsync_start; 708 intel_uncore_write(uncore, 709 vblank_reg, 710 (vblank_start - 1) | 711 ((vblank_end - 1) << 16)); 712 restore_vblank = true; 713 } 714 /* sample in the vertical border, selecting the larger one */ 715 if (vblank_start - vactive >= vtotal - vblank_end) 716 vsample = (vblank_start + vactive) >> 1; 717 else 718 vsample = (vtotal + vblank_end) >> 1; 719 720 /* 721 * Wait for the border to be displayed 722 */ 723 while (intel_uncore_read(uncore, pipe_dsl_reg) >= vactive) 724 ; 725 while ((dsl = intel_uncore_read(uncore, pipe_dsl_reg)) <= 726 vsample) 727 ; 728 /* 729 * Watch ST00 for an entire scanline 730 */ 731 detect = 0; 732 count = 0; 733 do { 734 count++; 735 /* Read the ST00 VGA status register */ 736 st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE); 737 if (st00 & (1 << 4)) 738 detect++; 739 } while ((intel_uncore_read(uncore, pipe_dsl_reg) == dsl)); 740 741 /* restore vblank if necessary */ 742 if (restore_vblank) 743 intel_uncore_write(uncore, vblank_reg, vblank); 744 /* 745 * If more than 3/4 of the scanline detected a monitor, 746 * then it is assumed to be present. This works even on i830, 747 * where there isn't any way to force the border color across 748 * the screen 749 */ 750 status = detect * 4 > count * 3 ? 751 connector_status_connected : 752 connector_status_disconnected; 753 } 754 755 /* Restore previous settings */ 756 intel_uncore_write(uncore, bclrpat_reg, save_bclrpat); 757 758 return status; 759 } 760 761 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id) 762 { 763 DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident); 764 return 1; 765 } 766 767 static const struct dmi_system_id intel_spurious_crt_detect[] = { 768 { 769 .callback = intel_spurious_crt_detect_dmi_callback, 770 .ident = "ACER ZGB", 771 .matches = { 772 DMI_MATCH(DMI_SYS_VENDOR, "ACER"), 773 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), 774 }, 775 }, 776 { 777 .callback = intel_spurious_crt_detect_dmi_callback, 778 .ident = "Intel DZ77BH-55K", 779 .matches = { 780 DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"), 781 DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"), 782 }, 783 }, 784 { } 785 }; 786 787 static int 788 intel_crt_detect(struct drm_connector *connector, 789 struct drm_modeset_acquire_ctx *ctx, 790 bool force) 791 { 792 struct drm_i915_private *dev_priv = to_i915(connector->dev); 793 struct intel_crt *crt = intel_attached_crt(connector); 794 struct intel_encoder *intel_encoder = &crt->base; 795 intel_wakeref_t wakeref; 796 int status, ret; 797 struct intel_load_detect_pipe tmp; 798 799 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", 800 connector->base.id, connector->name, 801 force); 802 803 if (i915_modparams.load_detect_test) { 804 wakeref = intel_display_power_get(dev_priv, 805 intel_encoder->power_domain); 806 goto load_detect; 807 } 808 809 /* Skip machines without VGA that falsely report hotplug events */ 810 if (dmi_check_system(intel_spurious_crt_detect)) 811 return connector_status_disconnected; 812 813 wakeref = intel_display_power_get(dev_priv, 814 intel_encoder->power_domain); 815 816 if (I915_HAS_HOTPLUG(dev_priv)) { 817 /* We can not rely on the HPD pin always being correctly wired 818 * up, for example many KVM do not pass it through, and so 819 * only trust an assertion that the monitor is connected. 820 */ 821 if (intel_crt_detect_hotplug(connector)) { 822 DRM_DEBUG_KMS("CRT detected via hotplug\n"); 823 status = connector_status_connected; 824 goto out; 825 } else 826 DRM_DEBUG_KMS("CRT not detected via hotplug\n"); 827 } 828 829 if (intel_crt_detect_ddc(connector)) { 830 status = connector_status_connected; 831 goto out; 832 } 833 834 /* Load detection is broken on HPD capable machines. Whoever wants a 835 * broken monitor (without edid) to work behind a broken kvm (that fails 836 * to have the right resistors for HP detection) needs to fix this up. 837 * For now just bail out. */ 838 if (I915_HAS_HOTPLUG(dev_priv)) { 839 status = connector_status_disconnected; 840 goto out; 841 } 842 843 load_detect: 844 if (!force) { 845 status = connector->status; 846 goto out; 847 } 848 849 /* for pre-945g platforms use load detect */ 850 ret = intel_get_load_detect_pipe(connector, NULL, &tmp, ctx); 851 if (ret > 0) { 852 if (intel_crt_detect_ddc(connector)) 853 status = connector_status_connected; 854 else if (INTEL_GEN(dev_priv) < 4) 855 status = intel_crt_load_detect(crt, 856 to_intel_crtc(connector->state->crtc)->pipe); 857 else if (i915_modparams.load_detect_test) 858 status = connector_status_disconnected; 859 else 860 status = connector_status_unknown; 861 intel_release_load_detect_pipe(connector, &tmp, ctx); 862 } else if (ret == 0) { 863 status = connector_status_unknown; 864 } else { 865 status = ret; 866 } 867 868 out: 869 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 870 return status; 871 } 872 873 static int intel_crt_get_modes(struct drm_connector *connector) 874 { 875 struct drm_device *dev = connector->dev; 876 struct drm_i915_private *dev_priv = to_i915(dev); 877 struct intel_crt *crt = intel_attached_crt(connector); 878 struct intel_encoder *intel_encoder = &crt->base; 879 intel_wakeref_t wakeref; 880 struct i2c_adapter *i2c; 881 int ret; 882 883 wakeref = intel_display_power_get(dev_priv, 884 intel_encoder->power_domain); 885 886 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 887 ret = intel_crt_ddc_get_modes(connector, i2c); 888 if (ret || !IS_G4X(dev_priv)) 889 goto out; 890 891 /* Try to probe digital port for output in DVI-I -> VGA mode. */ 892 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); 893 ret = intel_crt_ddc_get_modes(connector, i2c); 894 895 out: 896 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 897 898 return ret; 899 } 900 901 void intel_crt_reset(struct drm_encoder *encoder) 902 { 903 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 904 struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder)); 905 906 if (INTEL_GEN(dev_priv) >= 5) { 907 u32 adpa; 908 909 adpa = I915_READ(crt->adpa_reg); 910 adpa &= ~ADPA_CRT_HOTPLUG_MASK; 911 adpa |= ADPA_HOTPLUG_BITS; 912 I915_WRITE(crt->adpa_reg, adpa); 913 POSTING_READ(crt->adpa_reg); 914 915 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa); 916 crt->force_hotplug_required = 1; 917 } 918 919 } 920 921 /* 922 * Routines for controlling stuff on the analog port 923 */ 924 925 static const struct drm_connector_funcs intel_crt_connector_funcs = { 926 .fill_modes = drm_helper_probe_single_connector_modes, 927 .late_register = intel_connector_register, 928 .early_unregister = intel_connector_unregister, 929 .destroy = intel_connector_destroy, 930 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 931 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 932 }; 933 934 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { 935 .detect_ctx = intel_crt_detect, 936 .mode_valid = intel_crt_mode_valid, 937 .get_modes = intel_crt_get_modes, 938 }; 939 940 static const struct drm_encoder_funcs intel_crt_enc_funcs = { 941 .reset = intel_crt_reset, 942 .destroy = intel_encoder_destroy, 943 }; 944 945 void intel_crt_init(struct drm_i915_private *dev_priv) 946 { 947 struct drm_connector *connector; 948 struct intel_crt *crt; 949 struct intel_connector *intel_connector; 950 i915_reg_t adpa_reg; 951 u32 adpa; 952 953 if (HAS_PCH_SPLIT(dev_priv)) 954 adpa_reg = PCH_ADPA; 955 else if (IS_VALLEYVIEW(dev_priv)) 956 adpa_reg = VLV_ADPA; 957 else 958 adpa_reg = ADPA; 959 960 adpa = I915_READ(adpa_reg); 961 if ((adpa & ADPA_DAC_ENABLE) == 0) { 962 /* 963 * On some machines (some IVB at least) CRT can be 964 * fused off, but there's no known fuse bit to 965 * indicate that. On these machine the ADPA register 966 * works normally, except the DAC enable bit won't 967 * take. So the only way to tell is attempt to enable 968 * it and see what happens. 969 */ 970 I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE | 971 ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); 972 if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0) 973 return; 974 I915_WRITE(adpa_reg, adpa); 975 } 976 977 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); 978 if (!crt) 979 return; 980 981 intel_connector = intel_connector_alloc(); 982 if (!intel_connector) { 983 kfree(crt); 984 return; 985 } 986 987 connector = &intel_connector->base; 988 crt->connector = intel_connector; 989 drm_connector_init(&dev_priv->drm, &intel_connector->base, 990 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); 991 992 drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs, 993 DRM_MODE_ENCODER_DAC, "CRT"); 994 995 intel_connector_attach_encoder(intel_connector, &crt->base); 996 997 crt->base.type = INTEL_OUTPUT_ANALOG; 998 crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); 999 if (IS_I830(dev_priv)) 1000 crt->base.crtc_mask = (1 << 0); 1001 else 1002 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 1003 1004 if (IS_GEN(dev_priv, 2)) 1005 connector->interlace_allowed = 0; 1006 else 1007 connector->interlace_allowed = 1; 1008 connector->doublescan_allowed = 0; 1009 1010 crt->adpa_reg = adpa_reg; 1011 1012 crt->base.power_domain = POWER_DOMAIN_PORT_CRT; 1013 1014 if (I915_HAS_HOTPLUG(dev_priv) && 1015 !dmi_check_system(intel_spurious_crt_detect)) { 1016 crt->base.hpd_pin = HPD_CRT; 1017 crt->base.hotplug = intel_encoder_hotplug; 1018 } 1019 1020 if (HAS_DDI(dev_priv)) { 1021 crt->base.port = PORT_E; 1022 crt->base.get_config = hsw_crt_get_config; 1023 crt->base.get_hw_state = intel_ddi_get_hw_state; 1024 crt->base.compute_config = hsw_crt_compute_config; 1025 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt; 1026 crt->base.pre_enable = hsw_pre_enable_crt; 1027 crt->base.enable = hsw_enable_crt; 1028 crt->base.disable = hsw_disable_crt; 1029 crt->base.post_disable = hsw_post_disable_crt; 1030 } else { 1031 if (HAS_PCH_SPLIT(dev_priv)) { 1032 crt->base.compute_config = pch_crt_compute_config; 1033 crt->base.disable = pch_disable_crt; 1034 crt->base.post_disable = pch_post_disable_crt; 1035 } else { 1036 crt->base.compute_config = intel_crt_compute_config; 1037 crt->base.disable = intel_disable_crt; 1038 } 1039 crt->base.port = PORT_NONE; 1040 crt->base.get_config = intel_crt_get_config; 1041 crt->base.get_hw_state = intel_crt_get_hw_state; 1042 crt->base.enable = intel_enable_crt; 1043 } 1044 intel_connector->get_hw_state = intel_connector_get_hw_state; 1045 1046 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); 1047 1048 if (!I915_HAS_HOTPLUG(dev_priv)) 1049 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1050 1051 /* 1052 * Configure the automatic hotplug detection stuff 1053 */ 1054 crt->force_hotplug_required = 0; 1055 1056 /* 1057 * TODO: find a proper way to discover whether we need to set the the 1058 * polarity and link reversal bits or not, instead of relying on the 1059 * BIOS. 1060 */ 1061 if (HAS_PCH_LPT(dev_priv)) { 1062 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | 1063 FDI_RX_LINK_REVERSAL_OVERRIDE; 1064 1065 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; 1066 } 1067 1068 intel_crt_reset(&crt->base.base); 1069 } 1070