1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *	Eric Anholt <eric@anholt.net>
25  */
26 
27 #include <linux/dmi.h>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 
31 #include <drm/drm_atomic_helper.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_edid.h>
34 #include <drm/drm_probe_helper.h>
35 
36 #include "i915_drv.h"
37 #include "intel_connector.h"
38 #include "intel_crt.h"
39 #include "intel_crtc.h"
40 #include "intel_ddi.h"
41 #include "intel_ddi_buf_trans.h"
42 #include "intel_de.h"
43 #include "intel_display_types.h"
44 #include "intel_fdi.h"
45 #include "intel_fifo_underrun.h"
46 #include "intel_gmbus.h"
47 #include "intel_hotplug.h"
48 #include "intel_pch_display.h"
49 #include "intel_pch_refclk.h"
50 
51 /* Here's the desired hotplug mode */
52 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |		\
53 			   ADPA_CRT_HOTPLUG_WARMUP_10MS |		\
54 			   ADPA_CRT_HOTPLUG_SAMPLE_4S |			\
55 			   ADPA_CRT_HOTPLUG_VOLTAGE_50 |		\
56 			   ADPA_CRT_HOTPLUG_VOLREF_325MV |		\
57 			   ADPA_CRT_HOTPLUG_ENABLE)
58 
59 struct intel_crt {
60 	struct intel_encoder base;
61 	/* DPMS state is stored in the connector, which we need in the
62 	 * encoder's enable/disable callbacks */
63 	struct intel_connector *connector;
64 	bool force_hotplug_required;
65 	i915_reg_t adpa_reg;
66 };
67 
68 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
69 {
70 	return container_of(encoder, struct intel_crt, base);
71 }
72 
73 static struct intel_crt *intel_attached_crt(struct intel_connector *connector)
74 {
75 	return intel_encoder_to_crt(intel_attached_encoder(connector));
76 }
77 
78 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
79 			    i915_reg_t adpa_reg, enum pipe *pipe)
80 {
81 	u32 val;
82 
83 	val = intel_de_read(dev_priv, adpa_reg);
84 
85 	/* asserts want to know the pipe even if the port is disabled */
86 	if (HAS_PCH_CPT(dev_priv))
87 		*pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT;
88 	else
89 		*pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;
90 
91 	return val & ADPA_DAC_ENABLE;
92 }
93 
94 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
95 				   enum pipe *pipe)
96 {
97 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
98 	struct intel_crt *crt = intel_encoder_to_crt(encoder);
99 	intel_wakeref_t wakeref;
100 	bool ret;
101 
102 	wakeref = intel_display_power_get_if_enabled(dev_priv,
103 						     encoder->power_domain);
104 	if (!wakeref)
105 		return false;
106 
107 	ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
108 
109 	intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
110 
111 	return ret;
112 }
113 
114 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
115 {
116 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
117 	struct intel_crt *crt = intel_encoder_to_crt(encoder);
118 	u32 tmp, flags = 0;
119 
120 	tmp = intel_de_read(dev_priv, crt->adpa_reg);
121 
122 	if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
123 		flags |= DRM_MODE_FLAG_PHSYNC;
124 	else
125 		flags |= DRM_MODE_FLAG_NHSYNC;
126 
127 	if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
128 		flags |= DRM_MODE_FLAG_PVSYNC;
129 	else
130 		flags |= DRM_MODE_FLAG_NVSYNC;
131 
132 	return flags;
133 }
134 
135 static void intel_crt_get_config(struct intel_encoder *encoder,
136 				 struct intel_crtc_state *pipe_config)
137 {
138 	pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
139 
140 	pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
141 
142 	pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
143 }
144 
145 static void hsw_crt_get_config(struct intel_encoder *encoder,
146 			       struct intel_crtc_state *pipe_config)
147 {
148 	lpt_pch_get_config(pipe_config);
149 
150 	hsw_ddi_get_config(encoder, pipe_config);
151 
152 	pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
153 					      DRM_MODE_FLAG_NHSYNC |
154 					      DRM_MODE_FLAG_PVSYNC |
155 					      DRM_MODE_FLAG_NVSYNC);
156 	pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
157 }
158 
159 /* Note: The caller is required to filter out dpms modes not supported by the
160  * platform. */
161 static void intel_crt_set_dpms(struct intel_encoder *encoder,
162 			       const struct intel_crtc_state *crtc_state,
163 			       int mode)
164 {
165 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
166 	struct intel_crt *crt = intel_encoder_to_crt(encoder);
167 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
168 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
169 	u32 adpa;
170 
171 	if (DISPLAY_VER(dev_priv) >= 5)
172 		adpa = ADPA_HOTPLUG_BITS;
173 	else
174 		adpa = 0;
175 
176 	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
177 		adpa |= ADPA_HSYNC_ACTIVE_HIGH;
178 	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
179 		adpa |= ADPA_VSYNC_ACTIVE_HIGH;
180 
181 	/* For CPT allow 3 pipe config, for others just use A or B */
182 	if (HAS_PCH_LPT(dev_priv))
183 		; /* Those bits don't exist here */
184 	else if (HAS_PCH_CPT(dev_priv))
185 		adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
186 	else
187 		adpa |= ADPA_PIPE_SEL(crtc->pipe);
188 
189 	if (!HAS_PCH_SPLIT(dev_priv))
190 		intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
191 
192 	switch (mode) {
193 	case DRM_MODE_DPMS_ON:
194 		adpa |= ADPA_DAC_ENABLE;
195 		break;
196 	case DRM_MODE_DPMS_STANDBY:
197 		adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
198 		break;
199 	case DRM_MODE_DPMS_SUSPEND:
200 		adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
201 		break;
202 	case DRM_MODE_DPMS_OFF:
203 		adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
204 		break;
205 	}
206 
207 	intel_de_write(dev_priv, crt->adpa_reg, adpa);
208 }
209 
210 static void intel_disable_crt(struct intel_atomic_state *state,
211 			      struct intel_encoder *encoder,
212 			      const struct intel_crtc_state *old_crtc_state,
213 			      const struct drm_connector_state *old_conn_state)
214 {
215 	intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
216 }
217 
218 static void pch_disable_crt(struct intel_atomic_state *state,
219 			    struct intel_encoder *encoder,
220 			    const struct intel_crtc_state *old_crtc_state,
221 			    const struct drm_connector_state *old_conn_state)
222 {
223 }
224 
225 static void pch_post_disable_crt(struct intel_atomic_state *state,
226 				 struct intel_encoder *encoder,
227 				 const struct intel_crtc_state *old_crtc_state,
228 				 const struct drm_connector_state *old_conn_state)
229 {
230 	intel_disable_crt(state, encoder, old_crtc_state, old_conn_state);
231 }
232 
233 static void hsw_disable_crt(struct intel_atomic_state *state,
234 			    struct intel_encoder *encoder,
235 			    const struct intel_crtc_state *old_crtc_state,
236 			    const struct drm_connector_state *old_conn_state)
237 {
238 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
239 
240 	drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
241 
242 	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
243 }
244 
245 static void hsw_post_disable_crt(struct intel_atomic_state *state,
246 				 struct intel_encoder *encoder,
247 				 const struct intel_crtc_state *old_crtc_state,
248 				 const struct drm_connector_state *old_conn_state)
249 {
250 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
251 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
252 
253 	intel_crtc_vblank_off(old_crtc_state);
254 
255 	intel_disable_transcoder(old_crtc_state);
256 
257 	intel_ddi_disable_transcoder_func(old_crtc_state);
258 
259 	ilk_pfit_disable(old_crtc_state);
260 
261 	intel_ddi_disable_pipe_clock(old_crtc_state);
262 
263 	pch_post_disable_crt(state, encoder, old_crtc_state, old_conn_state);
264 
265 	lpt_pch_disable(state, crtc);
266 
267 	hsw_fdi_disable(encoder);
268 
269 	drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
270 
271 	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
272 }
273 
274 static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state,
275 				   struct intel_encoder *encoder,
276 				   const struct intel_crtc_state *crtc_state,
277 				   const struct drm_connector_state *conn_state)
278 {
279 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
280 
281 	drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
282 
283 	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
284 }
285 
286 static void hsw_pre_enable_crt(struct intel_atomic_state *state,
287 			       struct intel_encoder *encoder,
288 			       const struct intel_crtc_state *crtc_state,
289 			       const struct drm_connector_state *conn_state)
290 {
291 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
292 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
293 	enum pipe pipe = crtc->pipe;
294 
295 	drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
296 
297 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
298 
299 	hsw_fdi_link_train(encoder, crtc_state);
300 
301 	intel_ddi_enable_pipe_clock(encoder, crtc_state);
302 }
303 
304 static void hsw_enable_crt(struct intel_atomic_state *state,
305 			   struct intel_encoder *encoder,
306 			   const struct intel_crtc_state *crtc_state,
307 			   const struct drm_connector_state *conn_state)
308 {
309 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
310 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
311 	enum pipe pipe = crtc->pipe;
312 
313 	drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
314 
315 	intel_ddi_enable_transcoder_func(encoder, crtc_state);
316 
317 	intel_enable_transcoder(crtc_state);
318 
319 	lpt_pch_enable(state, crtc);
320 
321 	intel_crtc_vblank_on(crtc_state);
322 
323 	intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
324 
325 	intel_crtc_wait_for_next_vblank(crtc);
326 	intel_crtc_wait_for_next_vblank(crtc);
327 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
328 	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
329 }
330 
331 static void intel_enable_crt(struct intel_atomic_state *state,
332 			     struct intel_encoder *encoder,
333 			     const struct intel_crtc_state *crtc_state,
334 			     const struct drm_connector_state *conn_state)
335 {
336 	intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
337 }
338 
339 static enum drm_mode_status
340 intel_crt_mode_valid(struct drm_connector *connector,
341 		     struct drm_display_mode *mode)
342 {
343 	struct drm_device *dev = connector->dev;
344 	struct drm_i915_private *dev_priv = to_i915(dev);
345 	int max_dotclk = dev_priv->max_dotclk_freq;
346 	int max_clock;
347 
348 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
349 		return MODE_NO_DBLESCAN;
350 
351 	if (mode->clock < 25000)
352 		return MODE_CLOCK_LOW;
353 
354 	if (HAS_PCH_LPT(dev_priv))
355 		max_clock = 180000;
356 	else if (IS_VALLEYVIEW(dev_priv))
357 		/*
358 		 * 270 MHz due to current DPLL limits,
359 		 * DAC limit supposedly 355 MHz.
360 		 */
361 		max_clock = 270000;
362 	else if (IS_DISPLAY_VER(dev_priv, 3, 4))
363 		max_clock = 400000;
364 	else
365 		max_clock = 350000;
366 	if (mode->clock > max_clock)
367 		return MODE_CLOCK_HIGH;
368 
369 	if (mode->clock > max_dotclk)
370 		return MODE_CLOCK_HIGH;
371 
372 	/* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
373 	if (HAS_PCH_LPT(dev_priv) &&
374 	    ilk_get_lanes_required(mode->clock, 270000, 24) > 2)
375 		return MODE_CLOCK_HIGH;
376 
377 	/* HSW/BDW FDI limited to 4k */
378 	if (mode->hdisplay > 4096)
379 		return MODE_H_ILLEGAL;
380 
381 	return MODE_OK;
382 }
383 
384 static int intel_crt_compute_config(struct intel_encoder *encoder,
385 				    struct intel_crtc_state *pipe_config,
386 				    struct drm_connector_state *conn_state)
387 {
388 	struct drm_display_mode *adjusted_mode =
389 		&pipe_config->hw.adjusted_mode;
390 
391 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
392 		return -EINVAL;
393 
394 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
395 
396 	return 0;
397 }
398 
399 static int pch_crt_compute_config(struct intel_encoder *encoder,
400 				  struct intel_crtc_state *pipe_config,
401 				  struct drm_connector_state *conn_state)
402 {
403 	struct drm_display_mode *adjusted_mode =
404 		&pipe_config->hw.adjusted_mode;
405 
406 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
407 		return -EINVAL;
408 
409 	pipe_config->has_pch_encoder = true;
410 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
411 
412 	return 0;
413 }
414 
415 static int hsw_crt_compute_config(struct intel_encoder *encoder,
416 				  struct intel_crtc_state *pipe_config,
417 				  struct drm_connector_state *conn_state)
418 {
419 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
420 	struct drm_display_mode *adjusted_mode =
421 		&pipe_config->hw.adjusted_mode;
422 
423 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
424 		return -EINVAL;
425 
426 	/* HSW/BDW FDI limited to 4k */
427 	if (adjusted_mode->crtc_hdisplay > 4096 ||
428 	    adjusted_mode->crtc_hblank_start > 4096)
429 		return -EINVAL;
430 
431 	pipe_config->has_pch_encoder = true;
432 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
433 
434 	/* LPT FDI RX only supports 8bpc. */
435 	if (HAS_PCH_LPT(dev_priv)) {
436 		if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
437 			drm_dbg_kms(&dev_priv->drm,
438 				    "LPT only supports 24bpp\n");
439 			return -EINVAL;
440 		}
441 
442 		pipe_config->pipe_bpp = 24;
443 	}
444 
445 	/* FDI must always be 2.7 GHz */
446 	pipe_config->port_clock = 135000 * 2;
447 
448 	adjusted_mode->crtc_clock = lpt_iclkip(pipe_config);
449 
450 	return 0;
451 }
452 
453 static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
454 {
455 	struct drm_device *dev = connector->dev;
456 	struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
457 	struct drm_i915_private *dev_priv = to_i915(dev);
458 	u32 adpa;
459 	bool ret;
460 
461 	/* The first time through, trigger an explicit detection cycle */
462 	if (crt->force_hotplug_required) {
463 		bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
464 		u32 save_adpa;
465 
466 		crt->force_hotplug_required = false;
467 
468 		save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
469 		drm_dbg_kms(&dev_priv->drm,
470 			    "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
471 
472 		adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
473 		if (turn_off_dac)
474 			adpa &= ~ADPA_DAC_ENABLE;
475 
476 		intel_de_write(dev_priv, crt->adpa_reg, adpa);
477 
478 		if (intel_de_wait_for_clear(dev_priv,
479 					    crt->adpa_reg,
480 					    ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
481 					    1000))
482 			drm_dbg_kms(&dev_priv->drm,
483 				    "timed out waiting for FORCE_TRIGGER");
484 
485 		if (turn_off_dac) {
486 			intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
487 			intel_de_posting_read(dev_priv, crt->adpa_reg);
488 		}
489 	}
490 
491 	/* Check the status to see if both blue and green are on now */
492 	adpa = intel_de_read(dev_priv, crt->adpa_reg);
493 	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
494 		ret = true;
495 	else
496 		ret = false;
497 	drm_dbg_kms(&dev_priv->drm, "ironlake hotplug adpa=0x%x, result %d\n",
498 		    adpa, ret);
499 
500 	return ret;
501 }
502 
503 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
504 {
505 	struct drm_device *dev = connector->dev;
506 	struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
507 	struct drm_i915_private *dev_priv = to_i915(dev);
508 	bool reenable_hpd;
509 	u32 adpa;
510 	bool ret;
511 	u32 save_adpa;
512 
513 	/*
514 	 * Doing a force trigger causes a hpd interrupt to get sent, which can
515 	 * get us stuck in a loop if we're polling:
516 	 *  - We enable power wells and reset the ADPA
517 	 *  - output_poll_exec does force probe on VGA, triggering a hpd
518 	 *  - HPD handler waits for poll to unlock dev->mode_config.mutex
519 	 *  - output_poll_exec shuts off the ADPA, unlocks
520 	 *    dev->mode_config.mutex
521 	 *  - HPD handler runs, resets ADPA and brings us back to the start
522 	 *
523 	 * Just disable HPD interrupts here to prevent this
524 	 */
525 	reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
526 
527 	save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
528 	drm_dbg_kms(&dev_priv->drm,
529 		    "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
530 
531 	adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
532 
533 	intel_de_write(dev_priv, crt->adpa_reg, adpa);
534 
535 	if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg,
536 				    ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) {
537 		drm_dbg_kms(&dev_priv->drm,
538 			    "timed out waiting for FORCE_TRIGGER");
539 		intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
540 	}
541 
542 	/* Check the status to see if both blue and green are on now */
543 	adpa = intel_de_read(dev_priv, crt->adpa_reg);
544 	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
545 		ret = true;
546 	else
547 		ret = false;
548 
549 	drm_dbg_kms(&dev_priv->drm,
550 		    "valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
551 
552 	if (reenable_hpd)
553 		intel_hpd_enable(dev_priv, crt->base.hpd_pin);
554 
555 	return ret;
556 }
557 
558 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
559 {
560 	struct drm_device *dev = connector->dev;
561 	struct drm_i915_private *dev_priv = to_i915(dev);
562 	u32 stat;
563 	bool ret = false;
564 	int i, tries = 0;
565 
566 	if (HAS_PCH_SPLIT(dev_priv))
567 		return ilk_crt_detect_hotplug(connector);
568 
569 	if (IS_VALLEYVIEW(dev_priv))
570 		return valleyview_crt_detect_hotplug(connector);
571 
572 	/*
573 	 * On 4 series desktop, CRT detect sequence need to be done twice
574 	 * to get a reliable result.
575 	 */
576 
577 	if (IS_G45(dev_priv))
578 		tries = 2;
579 	else
580 		tries = 1;
581 
582 	for (i = 0; i < tries ; i++) {
583 		/* turn on the FORCE_DETECT */
584 		i915_hotplug_interrupt_update(dev_priv,
585 					      CRT_HOTPLUG_FORCE_DETECT,
586 					      CRT_HOTPLUG_FORCE_DETECT);
587 		/* wait for FORCE_DETECT to go off */
588 		if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN,
589 					    CRT_HOTPLUG_FORCE_DETECT, 1000))
590 			drm_dbg_kms(&dev_priv->drm,
591 				    "timed out waiting for FORCE_DETECT to go off");
592 	}
593 
594 	stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT);
595 	if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
596 		ret = true;
597 
598 	/* clear the interrupt we just generated, if any */
599 	intel_de_write(dev_priv, PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
600 
601 	i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
602 
603 	return ret;
604 }
605 
606 static struct edid *intel_crt_get_edid(struct drm_connector *connector,
607 				struct i2c_adapter *i2c)
608 {
609 	struct edid *edid;
610 
611 	edid = drm_get_edid(connector, i2c);
612 
613 	if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
614 		drm_dbg_kms(connector->dev,
615 			    "CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
616 		intel_gmbus_force_bit(i2c, true);
617 		edid = drm_get_edid(connector, i2c);
618 		intel_gmbus_force_bit(i2c, false);
619 	}
620 
621 	return edid;
622 }
623 
624 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
625 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
626 				struct i2c_adapter *adapter)
627 {
628 	struct edid *edid;
629 	int ret;
630 
631 	edid = intel_crt_get_edid(connector, adapter);
632 	if (!edid)
633 		return 0;
634 
635 	ret = intel_connector_update_modes(connector, edid);
636 	kfree(edid);
637 
638 	return ret;
639 }
640 
641 static bool intel_crt_detect_ddc(struct drm_connector *connector)
642 {
643 	struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
644 	struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
645 	struct edid *edid;
646 	struct i2c_adapter *i2c;
647 	bool ret = false;
648 
649 	i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->display.vbt.crt_ddc_pin);
650 	edid = intel_crt_get_edid(connector, i2c);
651 
652 	if (edid) {
653 		bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
654 
655 		/*
656 		 * This may be a DVI-I connector with a shared DDC
657 		 * link between analog and digital outputs, so we
658 		 * have to check the EDID input spec of the attached device.
659 		 */
660 		if (!is_digital) {
661 			drm_dbg_kms(&dev_priv->drm,
662 				    "CRT detected via DDC:0x50 [EDID]\n");
663 			ret = true;
664 		} else {
665 			drm_dbg_kms(&dev_priv->drm,
666 				    "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
667 		}
668 	} else {
669 		drm_dbg_kms(&dev_priv->drm,
670 			    "CRT not detected via DDC:0x50 [no valid EDID found]\n");
671 	}
672 
673 	kfree(edid);
674 
675 	return ret;
676 }
677 
678 static enum drm_connector_status
679 intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
680 {
681 	struct drm_device *dev = crt->base.base.dev;
682 	struct drm_i915_private *dev_priv = to_i915(dev);
683 	struct intel_uncore *uncore = &dev_priv->uncore;
684 	u32 save_bclrpat;
685 	u32 save_vtotal;
686 	u32 vtotal, vactive;
687 	u32 vsample;
688 	u32 vblank, vblank_start, vblank_end;
689 	u32 dsl;
690 	i915_reg_t bclrpat_reg, vtotal_reg,
691 		vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
692 	u8 st00;
693 	enum drm_connector_status status;
694 
695 	drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n");
696 
697 	bclrpat_reg = BCLRPAT(pipe);
698 	vtotal_reg = VTOTAL(pipe);
699 	vblank_reg = VBLANK(pipe);
700 	vsync_reg = VSYNC(pipe);
701 	pipeconf_reg = PIPECONF(pipe);
702 	pipe_dsl_reg = PIPEDSL(pipe);
703 
704 	save_bclrpat = intel_uncore_read(uncore, bclrpat_reg);
705 	save_vtotal = intel_uncore_read(uncore, vtotal_reg);
706 	vblank = intel_uncore_read(uncore, vblank_reg);
707 
708 	vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
709 	vactive = (save_vtotal & 0x7ff) + 1;
710 
711 	vblank_start = (vblank & 0xfff) + 1;
712 	vblank_end = ((vblank >> 16) & 0xfff) + 1;
713 
714 	/* Set the border color to purple. */
715 	intel_uncore_write(uncore, bclrpat_reg, 0x500050);
716 
717 	if (DISPLAY_VER(dev_priv) != 2) {
718 		u32 pipeconf = intel_uncore_read(uncore, pipeconf_reg);
719 		intel_uncore_write(uncore,
720 				   pipeconf_reg,
721 				   pipeconf | PIPECONF_FORCE_BORDER);
722 		intel_uncore_posting_read(uncore, pipeconf_reg);
723 		/* Wait for next Vblank to substitue
724 		 * border color for Color info */
725 		intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
726 		st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE);
727 		status = ((st00 & (1 << 4)) != 0) ?
728 			connector_status_connected :
729 			connector_status_disconnected;
730 
731 		intel_uncore_write(uncore, pipeconf_reg, pipeconf);
732 	} else {
733 		bool restore_vblank = false;
734 		int count, detect;
735 
736 		/*
737 		* If there isn't any border, add some.
738 		* Yes, this will flicker
739 		*/
740 		if (vblank_start <= vactive && vblank_end >= vtotal) {
741 			u32 vsync = intel_de_read(dev_priv, vsync_reg);
742 			u32 vsync_start = (vsync & 0xffff) + 1;
743 
744 			vblank_start = vsync_start;
745 			intel_uncore_write(uncore,
746 					   vblank_reg,
747 					   (vblank_start - 1) |
748 					   ((vblank_end - 1) << 16));
749 			restore_vblank = true;
750 		}
751 		/* sample in the vertical border, selecting the larger one */
752 		if (vblank_start - vactive >= vtotal - vblank_end)
753 			vsample = (vblank_start + vactive) >> 1;
754 		else
755 			vsample = (vtotal + vblank_end) >> 1;
756 
757 		/*
758 		 * Wait for the border to be displayed
759 		 */
760 		while (intel_uncore_read(uncore, pipe_dsl_reg) >= vactive)
761 			;
762 		while ((dsl = intel_uncore_read(uncore, pipe_dsl_reg)) <=
763 		       vsample)
764 			;
765 		/*
766 		 * Watch ST00 for an entire scanline
767 		 */
768 		detect = 0;
769 		count = 0;
770 		do {
771 			count++;
772 			/* Read the ST00 VGA status register */
773 			st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE);
774 			if (st00 & (1 << 4))
775 				detect++;
776 		} while ((intel_uncore_read(uncore, pipe_dsl_reg) == dsl));
777 
778 		/* restore vblank if necessary */
779 		if (restore_vblank)
780 			intel_uncore_write(uncore, vblank_reg, vblank);
781 		/*
782 		 * If more than 3/4 of the scanline detected a monitor,
783 		 * then it is assumed to be present. This works even on i830,
784 		 * where there isn't any way to force the border color across
785 		 * the screen
786 		 */
787 		status = detect * 4 > count * 3 ?
788 			 connector_status_connected :
789 			 connector_status_disconnected;
790 	}
791 
792 	/* Restore previous settings */
793 	intel_uncore_write(uncore, bclrpat_reg, save_bclrpat);
794 
795 	return status;
796 }
797 
798 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id)
799 {
800 	DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident);
801 	return 1;
802 }
803 
804 static const struct dmi_system_id intel_spurious_crt_detect[] = {
805 	{
806 		.callback = intel_spurious_crt_detect_dmi_callback,
807 		.ident = "ACER ZGB",
808 		.matches = {
809 			DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
810 			DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
811 		},
812 	},
813 	{
814 		.callback = intel_spurious_crt_detect_dmi_callback,
815 		.ident = "Intel DZ77BH-55K",
816 		.matches = {
817 			DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"),
818 			DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
819 		},
820 	},
821 	{ }
822 };
823 
824 static int
825 intel_crt_detect(struct drm_connector *connector,
826 		 struct drm_modeset_acquire_ctx *ctx,
827 		 bool force)
828 {
829 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
830 	struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
831 	struct intel_encoder *intel_encoder = &crt->base;
832 	intel_wakeref_t wakeref;
833 	int status, ret;
834 	struct intel_load_detect_pipe tmp;
835 
836 	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s] force=%d\n",
837 		    connector->base.id, connector->name,
838 		    force);
839 
840 	if (!INTEL_DISPLAY_ENABLED(dev_priv))
841 		return connector_status_disconnected;
842 
843 	if (dev_priv->params.load_detect_test) {
844 		wakeref = intel_display_power_get(dev_priv,
845 						  intel_encoder->power_domain);
846 		goto load_detect;
847 	}
848 
849 	/* Skip machines without VGA that falsely report hotplug events */
850 	if (dmi_check_system(intel_spurious_crt_detect))
851 		return connector_status_disconnected;
852 
853 	wakeref = intel_display_power_get(dev_priv,
854 					  intel_encoder->power_domain);
855 
856 	if (I915_HAS_HOTPLUG(dev_priv)) {
857 		/* We can not rely on the HPD pin always being correctly wired
858 		 * up, for example many KVM do not pass it through, and so
859 		 * only trust an assertion that the monitor is connected.
860 		 */
861 		if (intel_crt_detect_hotplug(connector)) {
862 			drm_dbg_kms(&dev_priv->drm,
863 				    "CRT detected via hotplug\n");
864 			status = connector_status_connected;
865 			goto out;
866 		} else
867 			drm_dbg_kms(&dev_priv->drm,
868 				    "CRT not detected via hotplug\n");
869 	}
870 
871 	if (intel_crt_detect_ddc(connector)) {
872 		status = connector_status_connected;
873 		goto out;
874 	}
875 
876 	/* Load detection is broken on HPD capable machines. Whoever wants a
877 	 * broken monitor (without edid) to work behind a broken kvm (that fails
878 	 * to have the right resistors for HP detection) needs to fix this up.
879 	 * For now just bail out. */
880 	if (I915_HAS_HOTPLUG(dev_priv)) {
881 		status = connector_status_disconnected;
882 		goto out;
883 	}
884 
885 load_detect:
886 	if (!force) {
887 		status = connector->status;
888 		goto out;
889 	}
890 
891 	/* for pre-945g platforms use load detect */
892 	ret = intel_get_load_detect_pipe(connector, &tmp, ctx);
893 	if (ret > 0) {
894 		if (intel_crt_detect_ddc(connector))
895 			status = connector_status_connected;
896 		else if (DISPLAY_VER(dev_priv) < 4)
897 			status = intel_crt_load_detect(crt,
898 				to_intel_crtc(connector->state->crtc)->pipe);
899 		else if (dev_priv->params.load_detect_test)
900 			status = connector_status_disconnected;
901 		else
902 			status = connector_status_unknown;
903 		intel_release_load_detect_pipe(connector, &tmp, ctx);
904 	} else if (ret == 0) {
905 		status = connector_status_unknown;
906 	} else {
907 		status = ret;
908 	}
909 
910 out:
911 	intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
912 
913 	/*
914 	 * Make sure the refs for power wells enabled during detect are
915 	 * dropped to avoid a new detect cycle triggered by HPD polling.
916 	 */
917 	intel_display_power_flush_work(dev_priv);
918 
919 	return status;
920 }
921 
922 static int intel_crt_get_modes(struct drm_connector *connector)
923 {
924 	struct drm_device *dev = connector->dev;
925 	struct drm_i915_private *dev_priv = to_i915(dev);
926 	struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
927 	struct intel_encoder *intel_encoder = &crt->base;
928 	intel_wakeref_t wakeref;
929 	struct i2c_adapter *i2c;
930 	int ret;
931 
932 	wakeref = intel_display_power_get(dev_priv,
933 					  intel_encoder->power_domain);
934 
935 	i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->display.vbt.crt_ddc_pin);
936 	ret = intel_crt_ddc_get_modes(connector, i2c);
937 	if (ret || !IS_G4X(dev_priv))
938 		goto out;
939 
940 	/* Try to probe digital port for output in DVI-I -> VGA mode. */
941 	i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
942 	ret = intel_crt_ddc_get_modes(connector, i2c);
943 
944 out:
945 	intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
946 
947 	return ret;
948 }
949 
950 void intel_crt_reset(struct drm_encoder *encoder)
951 {
952 	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
953 	struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
954 
955 	if (DISPLAY_VER(dev_priv) >= 5) {
956 		u32 adpa;
957 
958 		adpa = intel_de_read(dev_priv, crt->adpa_reg);
959 		adpa &= ~ADPA_CRT_HOTPLUG_MASK;
960 		adpa |= ADPA_HOTPLUG_BITS;
961 		intel_de_write(dev_priv, crt->adpa_reg, adpa);
962 		intel_de_posting_read(dev_priv, crt->adpa_reg);
963 
964 		drm_dbg_kms(&dev_priv->drm, "crt adpa set to 0x%x\n", adpa);
965 		crt->force_hotplug_required = true;
966 	}
967 
968 }
969 
970 /*
971  * Routines for controlling stuff on the analog port
972  */
973 
974 static const struct drm_connector_funcs intel_crt_connector_funcs = {
975 	.fill_modes = drm_helper_probe_single_connector_modes,
976 	.late_register = intel_connector_register,
977 	.early_unregister = intel_connector_unregister,
978 	.destroy = intel_connector_destroy,
979 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
980 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
981 };
982 
983 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
984 	.detect_ctx = intel_crt_detect,
985 	.mode_valid = intel_crt_mode_valid,
986 	.get_modes = intel_crt_get_modes,
987 };
988 
989 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
990 	.reset = intel_crt_reset,
991 	.destroy = intel_encoder_destroy,
992 };
993 
994 void intel_crt_init(struct drm_i915_private *dev_priv)
995 {
996 	struct drm_connector *connector;
997 	struct intel_crt *crt;
998 	struct intel_connector *intel_connector;
999 	i915_reg_t adpa_reg;
1000 	u32 adpa;
1001 
1002 	if (HAS_PCH_SPLIT(dev_priv))
1003 		adpa_reg = PCH_ADPA;
1004 	else if (IS_VALLEYVIEW(dev_priv))
1005 		adpa_reg = VLV_ADPA;
1006 	else
1007 		adpa_reg = ADPA;
1008 
1009 	adpa = intel_de_read(dev_priv, adpa_reg);
1010 	if ((adpa & ADPA_DAC_ENABLE) == 0) {
1011 		/*
1012 		 * On some machines (some IVB at least) CRT can be
1013 		 * fused off, but there's no known fuse bit to
1014 		 * indicate that. On these machine the ADPA register
1015 		 * works normally, except the DAC enable bit won't
1016 		 * take. So the only way to tell is attempt to enable
1017 		 * it and see what happens.
1018 		 */
1019 		intel_de_write(dev_priv, adpa_reg,
1020 			       adpa | ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
1021 		if ((intel_de_read(dev_priv, adpa_reg) & ADPA_DAC_ENABLE) == 0)
1022 			return;
1023 		intel_de_write(dev_priv, adpa_reg, adpa);
1024 	}
1025 
1026 	crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
1027 	if (!crt)
1028 		return;
1029 
1030 	intel_connector = intel_connector_alloc();
1031 	if (!intel_connector) {
1032 		kfree(crt);
1033 		return;
1034 	}
1035 
1036 	connector = &intel_connector->base;
1037 	crt->connector = intel_connector;
1038 	drm_connector_init(&dev_priv->drm, &intel_connector->base,
1039 			   &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
1040 
1041 	drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
1042 			 DRM_MODE_ENCODER_DAC, "CRT");
1043 
1044 	intel_connector_attach_encoder(intel_connector, &crt->base);
1045 
1046 	crt->base.type = INTEL_OUTPUT_ANALOG;
1047 	crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
1048 	if (IS_I830(dev_priv))
1049 		crt->base.pipe_mask = BIT(PIPE_A);
1050 	else
1051 		crt->base.pipe_mask = ~0;
1052 
1053 	if (DISPLAY_VER(dev_priv) == 2)
1054 		connector->interlace_allowed = 0;
1055 	else
1056 		connector->interlace_allowed = 1;
1057 	connector->doublescan_allowed = 0;
1058 
1059 	crt->adpa_reg = adpa_reg;
1060 
1061 	crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
1062 
1063 	if (I915_HAS_HOTPLUG(dev_priv) &&
1064 	    !dmi_check_system(intel_spurious_crt_detect)) {
1065 		crt->base.hpd_pin = HPD_CRT;
1066 		crt->base.hotplug = intel_encoder_hotplug;
1067 		intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
1068 	} else {
1069 		intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1070 	}
1071 
1072 	if (HAS_DDI(dev_priv)) {
1073 		crt->base.port = PORT_E;
1074 		crt->base.get_config = hsw_crt_get_config;
1075 		crt->base.get_hw_state = intel_ddi_get_hw_state;
1076 		crt->base.compute_config = hsw_crt_compute_config;
1077 		crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
1078 		crt->base.pre_enable = hsw_pre_enable_crt;
1079 		crt->base.enable = hsw_enable_crt;
1080 		crt->base.disable = hsw_disable_crt;
1081 		crt->base.post_disable = hsw_post_disable_crt;
1082 		crt->base.enable_clock = hsw_ddi_enable_clock;
1083 		crt->base.disable_clock = hsw_ddi_disable_clock;
1084 		crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled;
1085 
1086 		intel_ddi_buf_trans_init(&crt->base);
1087 	} else {
1088 		if (HAS_PCH_SPLIT(dev_priv)) {
1089 			crt->base.compute_config = pch_crt_compute_config;
1090 			crt->base.disable = pch_disable_crt;
1091 			crt->base.post_disable = pch_post_disable_crt;
1092 		} else {
1093 			crt->base.compute_config = intel_crt_compute_config;
1094 			crt->base.disable = intel_disable_crt;
1095 		}
1096 		crt->base.port = PORT_NONE;
1097 		crt->base.get_config = intel_crt_get_config;
1098 		crt->base.get_hw_state = intel_crt_get_hw_state;
1099 		crt->base.enable = intel_enable_crt;
1100 	}
1101 	intel_connector->get_hw_state = intel_connector_get_hw_state;
1102 
1103 	drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
1104 
1105 	/*
1106 	 * TODO: find a proper way to discover whether we need to set the the
1107 	 * polarity and link reversal bits or not, instead of relying on the
1108 	 * BIOS.
1109 	 */
1110 	if (HAS_PCH_LPT(dev_priv)) {
1111 		u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
1112 				 FDI_RX_LINK_REVERSAL_OVERRIDE;
1113 
1114 		dev_priv->display.fdi.rx_config = intel_de_read(dev_priv,
1115 								FDI_RX_CTL(PIPE_A)) & fdi_config;
1116 	}
1117 
1118 	intel_crt_reset(&crt->base.base);
1119 }
1120