1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dmi.h> 28 #include <linux/i2c.h> 29 #include <linux/slab.h> 30 31 #include <drm/drm_atomic_helper.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_edid.h> 34 #include <drm/drm_probe_helper.h> 35 36 #include "i915_drv.h" 37 #include "i915_irq.h" 38 #include "i915_reg.h" 39 #include "intel_connector.h" 40 #include "intel_crt.h" 41 #include "intel_crtc.h" 42 #include "intel_ddi.h" 43 #include "intel_ddi_buf_trans.h" 44 #include "intel_de.h" 45 #include "intel_display_types.h" 46 #include "intel_fdi.h" 47 #include "intel_fdi_regs.h" 48 #include "intel_fifo_underrun.h" 49 #include "intel_gmbus.h" 50 #include "intel_hotplug.h" 51 #include "intel_hotplug_irq.h" 52 #include "intel_load_detect.h" 53 #include "intel_pch_display.h" 54 #include "intel_pch_refclk.h" 55 56 /* Here's the desired hotplug mode */ 57 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ 58 ADPA_CRT_HOTPLUG_WARMUP_10MS | \ 59 ADPA_CRT_HOTPLUG_SAMPLE_4S | \ 60 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ 61 ADPA_CRT_HOTPLUG_VOLREF_325MV | \ 62 ADPA_CRT_HOTPLUG_ENABLE) 63 64 struct intel_crt { 65 struct intel_encoder base; 66 /* DPMS state is stored in the connector, which we need in the 67 * encoder's enable/disable callbacks */ 68 struct intel_connector *connector; 69 bool force_hotplug_required; 70 i915_reg_t adpa_reg; 71 }; 72 73 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) 74 { 75 return container_of(encoder, struct intel_crt, base); 76 } 77 78 static struct intel_crt *intel_attached_crt(struct intel_connector *connector) 79 { 80 return intel_encoder_to_crt(intel_attached_encoder(connector)); 81 } 82 83 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv, 84 i915_reg_t adpa_reg, enum pipe *pipe) 85 { 86 u32 val; 87 88 val = intel_de_read(dev_priv, adpa_reg); 89 90 /* asserts want to know the pipe even if the port is disabled */ 91 if (HAS_PCH_CPT(dev_priv)) 92 *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT; 93 else 94 *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT; 95 96 return val & ADPA_DAC_ENABLE; 97 } 98 99 static bool intel_crt_get_hw_state(struct intel_encoder *encoder, 100 enum pipe *pipe) 101 { 102 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 103 struct intel_crt *crt = intel_encoder_to_crt(encoder); 104 intel_wakeref_t wakeref; 105 bool ret; 106 107 wakeref = intel_display_power_get_if_enabled(dev_priv, 108 encoder->power_domain); 109 if (!wakeref) 110 return false; 111 112 ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe); 113 114 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 115 116 return ret; 117 } 118 119 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) 120 { 121 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 122 struct intel_crt *crt = intel_encoder_to_crt(encoder); 123 u32 tmp, flags = 0; 124 125 tmp = intel_de_read(dev_priv, crt->adpa_reg); 126 127 if (tmp & ADPA_HSYNC_ACTIVE_HIGH) 128 flags |= DRM_MODE_FLAG_PHSYNC; 129 else 130 flags |= DRM_MODE_FLAG_NHSYNC; 131 132 if (tmp & ADPA_VSYNC_ACTIVE_HIGH) 133 flags |= DRM_MODE_FLAG_PVSYNC; 134 else 135 flags |= DRM_MODE_FLAG_NVSYNC; 136 137 return flags; 138 } 139 140 static void intel_crt_get_config(struct intel_encoder *encoder, 141 struct intel_crtc_state *pipe_config) 142 { 143 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 144 145 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); 146 147 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; 148 } 149 150 static void hsw_crt_get_config(struct intel_encoder *encoder, 151 struct intel_crtc_state *pipe_config) 152 { 153 lpt_pch_get_config(pipe_config); 154 155 hsw_ddi_get_config(encoder, pipe_config); 156 157 pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | 158 DRM_MODE_FLAG_NHSYNC | 159 DRM_MODE_FLAG_PVSYNC | 160 DRM_MODE_FLAG_NVSYNC); 161 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); 162 } 163 164 /* Note: The caller is required to filter out dpms modes not supported by the 165 * platform. */ 166 static void intel_crt_set_dpms(struct intel_encoder *encoder, 167 const struct intel_crtc_state *crtc_state, 168 int mode) 169 { 170 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 171 struct intel_crt *crt = intel_encoder_to_crt(encoder); 172 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 173 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 174 u32 adpa; 175 176 if (DISPLAY_VER(dev_priv) >= 5) 177 adpa = ADPA_HOTPLUG_BITS; 178 else 179 adpa = 0; 180 181 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 182 adpa |= ADPA_HSYNC_ACTIVE_HIGH; 183 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 184 adpa |= ADPA_VSYNC_ACTIVE_HIGH; 185 186 /* For CPT allow 3 pipe config, for others just use A or B */ 187 if (HAS_PCH_LPT(dev_priv)) 188 ; /* Those bits don't exist here */ 189 else if (HAS_PCH_CPT(dev_priv)) 190 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe); 191 else 192 adpa |= ADPA_PIPE_SEL(crtc->pipe); 193 194 if (!HAS_PCH_SPLIT(dev_priv)) 195 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 196 197 switch (mode) { 198 case DRM_MODE_DPMS_ON: 199 adpa |= ADPA_DAC_ENABLE; 200 break; 201 case DRM_MODE_DPMS_STANDBY: 202 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; 203 break; 204 case DRM_MODE_DPMS_SUSPEND: 205 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; 206 break; 207 case DRM_MODE_DPMS_OFF: 208 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; 209 break; 210 } 211 212 intel_de_write(dev_priv, crt->adpa_reg, adpa); 213 } 214 215 static void intel_disable_crt(struct intel_atomic_state *state, 216 struct intel_encoder *encoder, 217 const struct intel_crtc_state *old_crtc_state, 218 const struct drm_connector_state *old_conn_state) 219 { 220 intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF); 221 } 222 223 static void pch_disable_crt(struct intel_atomic_state *state, 224 struct intel_encoder *encoder, 225 const struct intel_crtc_state *old_crtc_state, 226 const struct drm_connector_state *old_conn_state) 227 { 228 } 229 230 static void pch_post_disable_crt(struct intel_atomic_state *state, 231 struct intel_encoder *encoder, 232 const struct intel_crtc_state *old_crtc_state, 233 const struct drm_connector_state *old_conn_state) 234 { 235 intel_disable_crt(state, encoder, old_crtc_state, old_conn_state); 236 } 237 238 static void hsw_disable_crt(struct intel_atomic_state *state, 239 struct intel_encoder *encoder, 240 const struct intel_crtc_state *old_crtc_state, 241 const struct drm_connector_state *old_conn_state) 242 { 243 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 244 245 drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder); 246 247 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 248 } 249 250 static void hsw_post_disable_crt(struct intel_atomic_state *state, 251 struct intel_encoder *encoder, 252 const struct intel_crtc_state *old_crtc_state, 253 const struct drm_connector_state *old_conn_state) 254 { 255 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 256 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 257 258 intel_crtc_vblank_off(old_crtc_state); 259 260 intel_disable_transcoder(old_crtc_state); 261 262 intel_ddi_disable_transcoder_func(old_crtc_state); 263 264 ilk_pfit_disable(old_crtc_state); 265 266 intel_ddi_disable_transcoder_clock(old_crtc_state); 267 268 pch_post_disable_crt(state, encoder, old_crtc_state, old_conn_state); 269 270 lpt_pch_disable(state, crtc); 271 272 hsw_fdi_disable(encoder); 273 274 drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder); 275 276 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 277 } 278 279 static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state, 280 struct intel_encoder *encoder, 281 const struct intel_crtc_state *crtc_state, 282 const struct drm_connector_state *conn_state) 283 { 284 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 285 286 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder); 287 288 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 289 } 290 291 static void hsw_pre_enable_crt(struct intel_atomic_state *state, 292 struct intel_encoder *encoder, 293 const struct intel_crtc_state *crtc_state, 294 const struct drm_connector_state *conn_state) 295 { 296 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 297 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 298 enum pipe pipe = crtc->pipe; 299 300 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder); 301 302 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 303 304 hsw_fdi_link_train(encoder, crtc_state); 305 306 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 307 } 308 309 static void hsw_enable_crt(struct intel_atomic_state *state, 310 struct intel_encoder *encoder, 311 const struct intel_crtc_state *crtc_state, 312 const struct drm_connector_state *conn_state) 313 { 314 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 315 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 316 enum pipe pipe = crtc->pipe; 317 318 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder); 319 320 intel_ddi_enable_transcoder_func(encoder, crtc_state); 321 322 intel_enable_transcoder(crtc_state); 323 324 lpt_pch_enable(state, crtc); 325 326 intel_crtc_vblank_on(crtc_state); 327 328 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); 329 330 intel_crtc_wait_for_next_vblank(crtc); 331 intel_crtc_wait_for_next_vblank(crtc); 332 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 333 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 334 } 335 336 static void intel_enable_crt(struct intel_atomic_state *state, 337 struct intel_encoder *encoder, 338 const struct intel_crtc_state *crtc_state, 339 const struct drm_connector_state *conn_state) 340 { 341 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); 342 } 343 344 static enum drm_mode_status 345 intel_crt_mode_valid(struct drm_connector *connector, 346 struct drm_display_mode *mode) 347 { 348 struct drm_device *dev = connector->dev; 349 struct drm_i915_private *dev_priv = to_i915(dev); 350 int max_dotclk = dev_priv->max_dotclk_freq; 351 enum drm_mode_status status; 352 int max_clock; 353 354 status = intel_cpu_transcoder_mode_valid(dev_priv, mode); 355 if (status != MODE_OK) 356 return status; 357 358 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 359 return MODE_NO_DBLESCAN; 360 361 if (mode->clock < 25000) 362 return MODE_CLOCK_LOW; 363 364 if (HAS_PCH_LPT(dev_priv)) 365 max_clock = 180000; 366 else if (IS_VALLEYVIEW(dev_priv)) 367 /* 368 * 270 MHz due to current DPLL limits, 369 * DAC limit supposedly 355 MHz. 370 */ 371 max_clock = 270000; 372 else if (IS_DISPLAY_VER(dev_priv, 3, 4)) 373 max_clock = 400000; 374 else 375 max_clock = 350000; 376 if (mode->clock > max_clock) 377 return MODE_CLOCK_HIGH; 378 379 if (mode->clock > max_dotclk) 380 return MODE_CLOCK_HIGH; 381 382 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ 383 if (HAS_PCH_LPT(dev_priv) && 384 ilk_get_lanes_required(mode->clock, 270000, 24) > 2) 385 return MODE_CLOCK_HIGH; 386 387 /* HSW/BDW FDI limited to 4k */ 388 if (mode->hdisplay > 4096) 389 return MODE_H_ILLEGAL; 390 391 return MODE_OK; 392 } 393 394 static int intel_crt_compute_config(struct intel_encoder *encoder, 395 struct intel_crtc_state *pipe_config, 396 struct drm_connector_state *conn_state) 397 { 398 struct drm_display_mode *adjusted_mode = 399 &pipe_config->hw.adjusted_mode; 400 401 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 402 return -EINVAL; 403 404 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; 405 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 406 407 return 0; 408 } 409 410 static int pch_crt_compute_config(struct intel_encoder *encoder, 411 struct intel_crtc_state *pipe_config, 412 struct drm_connector_state *conn_state) 413 { 414 struct drm_display_mode *adjusted_mode = 415 &pipe_config->hw.adjusted_mode; 416 417 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 418 return -EINVAL; 419 420 pipe_config->has_pch_encoder = true; 421 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 422 423 return 0; 424 } 425 426 static int hsw_crt_compute_config(struct intel_encoder *encoder, 427 struct intel_crtc_state *pipe_config, 428 struct drm_connector_state *conn_state) 429 { 430 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 431 struct drm_display_mode *adjusted_mode = 432 &pipe_config->hw.adjusted_mode; 433 434 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 435 return -EINVAL; 436 437 /* HSW/BDW FDI limited to 4k */ 438 if (adjusted_mode->crtc_hdisplay > 4096 || 439 adjusted_mode->crtc_hblank_start > 4096) 440 return -EINVAL; 441 442 pipe_config->has_pch_encoder = true; 443 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 444 445 /* LPT FDI RX only supports 8bpc. */ 446 if (HAS_PCH_LPT(dev_priv)) { 447 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { 448 drm_dbg_kms(&dev_priv->drm, 449 "LPT only supports 24bpp\n"); 450 return -EINVAL; 451 } 452 453 pipe_config->pipe_bpp = 24; 454 } 455 456 /* FDI must always be 2.7 GHz */ 457 pipe_config->port_clock = 135000 * 2; 458 459 adjusted_mode->crtc_clock = lpt_iclkip(pipe_config); 460 461 return 0; 462 } 463 464 static bool ilk_crt_detect_hotplug(struct drm_connector *connector) 465 { 466 struct drm_device *dev = connector->dev; 467 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 468 struct drm_i915_private *dev_priv = to_i915(dev); 469 u32 adpa; 470 bool ret; 471 472 /* The first time through, trigger an explicit detection cycle */ 473 if (crt->force_hotplug_required) { 474 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv); 475 u32 save_adpa; 476 477 crt->force_hotplug_required = false; 478 479 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); 480 drm_dbg_kms(&dev_priv->drm, 481 "trigger hotplug detect cycle: adpa=0x%x\n", adpa); 482 483 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 484 if (turn_off_dac) 485 adpa &= ~ADPA_DAC_ENABLE; 486 487 intel_de_write(dev_priv, crt->adpa_reg, adpa); 488 489 if (intel_de_wait_for_clear(dev_priv, 490 crt->adpa_reg, 491 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 492 1000)) 493 drm_dbg_kms(&dev_priv->drm, 494 "timed out waiting for FORCE_TRIGGER"); 495 496 if (turn_off_dac) { 497 intel_de_write(dev_priv, crt->adpa_reg, save_adpa); 498 intel_de_posting_read(dev_priv, crt->adpa_reg); 499 } 500 } 501 502 /* Check the status to see if both blue and green are on now */ 503 adpa = intel_de_read(dev_priv, crt->adpa_reg); 504 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 505 ret = true; 506 else 507 ret = false; 508 drm_dbg_kms(&dev_priv->drm, "ironlake hotplug adpa=0x%x, result %d\n", 509 adpa, ret); 510 511 return ret; 512 } 513 514 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) 515 { 516 struct drm_device *dev = connector->dev; 517 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 518 struct drm_i915_private *dev_priv = to_i915(dev); 519 bool reenable_hpd; 520 u32 adpa; 521 bool ret; 522 u32 save_adpa; 523 524 /* 525 * Doing a force trigger causes a hpd interrupt to get sent, which can 526 * get us stuck in a loop if we're polling: 527 * - We enable power wells and reset the ADPA 528 * - output_poll_exec does force probe on VGA, triggering a hpd 529 * - HPD handler waits for poll to unlock dev->mode_config.mutex 530 * - output_poll_exec shuts off the ADPA, unlocks 531 * dev->mode_config.mutex 532 * - HPD handler runs, resets ADPA and brings us back to the start 533 * 534 * Just disable HPD interrupts here to prevent this 535 */ 536 reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin); 537 538 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); 539 drm_dbg_kms(&dev_priv->drm, 540 "trigger hotplug detect cycle: adpa=0x%x\n", adpa); 541 542 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 543 544 intel_de_write(dev_priv, crt->adpa_reg, adpa); 545 546 if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg, 547 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) { 548 drm_dbg_kms(&dev_priv->drm, 549 "timed out waiting for FORCE_TRIGGER"); 550 intel_de_write(dev_priv, crt->adpa_reg, save_adpa); 551 } 552 553 /* Check the status to see if both blue and green are on now */ 554 adpa = intel_de_read(dev_priv, crt->adpa_reg); 555 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 556 ret = true; 557 else 558 ret = false; 559 560 drm_dbg_kms(&dev_priv->drm, 561 "valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); 562 563 if (reenable_hpd) 564 intel_hpd_enable(dev_priv, crt->base.hpd_pin); 565 566 return ret; 567 } 568 569 static bool intel_crt_detect_hotplug(struct drm_connector *connector) 570 { 571 struct drm_device *dev = connector->dev; 572 struct drm_i915_private *dev_priv = to_i915(dev); 573 u32 stat; 574 bool ret = false; 575 int i, tries = 0; 576 577 if (HAS_PCH_SPLIT(dev_priv)) 578 return ilk_crt_detect_hotplug(connector); 579 580 if (IS_VALLEYVIEW(dev_priv)) 581 return valleyview_crt_detect_hotplug(connector); 582 583 /* 584 * On 4 series desktop, CRT detect sequence need to be done twice 585 * to get a reliable result. 586 */ 587 588 if (IS_G45(dev_priv)) 589 tries = 2; 590 else 591 tries = 1; 592 593 for (i = 0; i < tries ; i++) { 594 /* turn on the FORCE_DETECT */ 595 i915_hotplug_interrupt_update(dev_priv, 596 CRT_HOTPLUG_FORCE_DETECT, 597 CRT_HOTPLUG_FORCE_DETECT); 598 /* wait for FORCE_DETECT to go off */ 599 if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN, 600 CRT_HOTPLUG_FORCE_DETECT, 1000)) 601 drm_dbg_kms(&dev_priv->drm, 602 "timed out waiting for FORCE_DETECT to go off"); 603 } 604 605 stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT); 606 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) 607 ret = true; 608 609 /* clear the interrupt we just generated, if any */ 610 intel_de_write(dev_priv, PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); 611 612 i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); 613 614 return ret; 615 } 616 617 static const struct drm_edid *intel_crt_get_edid(struct drm_connector *connector, 618 struct i2c_adapter *i2c) 619 { 620 const struct drm_edid *drm_edid; 621 622 drm_edid = drm_edid_read_ddc(connector, i2c); 623 624 if (!drm_edid && !intel_gmbus_is_forced_bit(i2c)) { 625 drm_dbg_kms(connector->dev, 626 "CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); 627 intel_gmbus_force_bit(i2c, true); 628 drm_edid = drm_edid_read_ddc(connector, i2c); 629 intel_gmbus_force_bit(i2c, false); 630 } 631 632 return drm_edid; 633 } 634 635 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ 636 static int intel_crt_ddc_get_modes(struct drm_connector *connector, 637 struct i2c_adapter *adapter) 638 { 639 const struct drm_edid *drm_edid; 640 int ret; 641 642 drm_edid = intel_crt_get_edid(connector, adapter); 643 if (!drm_edid) 644 return 0; 645 646 ret = intel_connector_update_modes(connector, drm_edid); 647 648 drm_edid_free(drm_edid); 649 650 return ret; 651 } 652 653 static bool intel_crt_detect_ddc(struct drm_connector *connector) 654 { 655 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 656 struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev); 657 const struct drm_edid *drm_edid; 658 struct i2c_adapter *i2c; 659 bool ret = false; 660 661 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->display.vbt.crt_ddc_pin); 662 drm_edid = intel_crt_get_edid(connector, i2c); 663 664 if (drm_edid) { 665 const struct edid *edid = drm_edid_raw(drm_edid); 666 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; 667 668 /* 669 * This may be a DVI-I connector with a shared DDC 670 * link between analog and digital outputs, so we 671 * have to check the EDID input spec of the attached device. 672 */ 673 if (!is_digital) { 674 drm_dbg_kms(&dev_priv->drm, 675 "CRT detected via DDC:0x50 [EDID]\n"); 676 ret = true; 677 } else { 678 drm_dbg_kms(&dev_priv->drm, 679 "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); 680 } 681 } else { 682 drm_dbg_kms(&dev_priv->drm, 683 "CRT not detected via DDC:0x50 [no valid EDID found]\n"); 684 } 685 686 drm_edid_free(drm_edid); 687 688 return ret; 689 } 690 691 static enum drm_connector_status 692 intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe) 693 { 694 struct drm_device *dev = crt->base.base.dev; 695 struct drm_i915_private *dev_priv = to_i915(dev); 696 enum transcoder cpu_transcoder = (enum transcoder)pipe; 697 u32 save_bclrpat; 698 u32 save_vtotal; 699 u32 vtotal, vactive; 700 u32 vsample; 701 u32 vblank, vblank_start, vblank_end; 702 u32 dsl; 703 u8 st00; 704 enum drm_connector_status status; 705 706 drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n"); 707 708 save_bclrpat = intel_de_read(dev_priv, BCLRPAT(cpu_transcoder)); 709 save_vtotal = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)); 710 vblank = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder)); 711 712 vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1; 713 vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1; 714 715 vblank_start = REG_FIELD_GET(VBLANK_START_MASK, vblank) + 1; 716 vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1; 717 718 /* Set the border color to purple. */ 719 intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), 0x500050); 720 721 if (DISPLAY_VER(dev_priv) != 2) { 722 u32 transconf = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); 723 724 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), 725 transconf | TRANSCONF_FORCE_BORDER); 726 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 727 /* Wait for next Vblank to substitue 728 * border color for Color info */ 729 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe)); 730 st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE); 731 status = ((st00 & (1 << 4)) != 0) ? 732 connector_status_connected : 733 connector_status_disconnected; 734 735 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), transconf); 736 } else { 737 bool restore_vblank = false; 738 int count, detect; 739 740 /* 741 * If there isn't any border, add some. 742 * Yes, this will flicker 743 */ 744 if (vblank_start <= vactive && vblank_end >= vtotal) { 745 u32 vsync = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder)); 746 u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1; 747 748 vblank_start = vsync_start; 749 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), 750 VBLANK_START(vblank_start - 1) | 751 VBLANK_END(vblank_end - 1)); 752 restore_vblank = true; 753 } 754 /* sample in the vertical border, selecting the larger one */ 755 if (vblank_start - vactive >= vtotal - vblank_end) 756 vsample = (vblank_start + vactive) >> 1; 757 else 758 vsample = (vtotal + vblank_end) >> 1; 759 760 /* 761 * Wait for the border to be displayed 762 */ 763 while (intel_de_read(dev_priv, PIPEDSL(pipe)) >= vactive) 764 ; 765 while ((dsl = intel_de_read(dev_priv, PIPEDSL(pipe))) <= vsample) 766 ; 767 /* 768 * Watch ST00 for an entire scanline 769 */ 770 detect = 0; 771 count = 0; 772 do { 773 count++; 774 /* Read the ST00 VGA status register */ 775 st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE); 776 if (st00 & (1 << 4)) 777 detect++; 778 } while ((intel_de_read(dev_priv, PIPEDSL(pipe)) == dsl)); 779 780 /* restore vblank if necessary */ 781 if (restore_vblank) 782 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), vblank); 783 /* 784 * If more than 3/4 of the scanline detected a monitor, 785 * then it is assumed to be present. This works even on i830, 786 * where there isn't any way to force the border color across 787 * the screen 788 */ 789 status = detect * 4 > count * 3 ? 790 connector_status_connected : 791 connector_status_disconnected; 792 } 793 794 /* Restore previous settings */ 795 intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), save_bclrpat); 796 797 return status; 798 } 799 800 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id) 801 { 802 DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident); 803 return 1; 804 } 805 806 static const struct dmi_system_id intel_spurious_crt_detect[] = { 807 { 808 .callback = intel_spurious_crt_detect_dmi_callback, 809 .ident = "ACER ZGB", 810 .matches = { 811 DMI_MATCH(DMI_SYS_VENDOR, "ACER"), 812 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), 813 }, 814 }, 815 { 816 .callback = intel_spurious_crt_detect_dmi_callback, 817 .ident = "Intel DZ77BH-55K", 818 .matches = { 819 DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"), 820 DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"), 821 }, 822 }, 823 { } 824 }; 825 826 static int 827 intel_crt_detect(struct drm_connector *connector, 828 struct drm_modeset_acquire_ctx *ctx, 829 bool force) 830 { 831 struct drm_i915_private *dev_priv = to_i915(connector->dev); 832 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 833 struct intel_encoder *intel_encoder = &crt->base; 834 struct drm_atomic_state *state; 835 intel_wakeref_t wakeref; 836 int status; 837 838 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s] force=%d\n", 839 connector->base.id, connector->name, 840 force); 841 842 if (!INTEL_DISPLAY_ENABLED(dev_priv)) 843 return connector_status_disconnected; 844 845 if (dev_priv->params.load_detect_test) { 846 wakeref = intel_display_power_get(dev_priv, 847 intel_encoder->power_domain); 848 goto load_detect; 849 } 850 851 /* Skip machines without VGA that falsely report hotplug events */ 852 if (dmi_check_system(intel_spurious_crt_detect)) 853 return connector_status_disconnected; 854 855 wakeref = intel_display_power_get(dev_priv, 856 intel_encoder->power_domain); 857 858 if (I915_HAS_HOTPLUG(dev_priv)) { 859 /* We can not rely on the HPD pin always being correctly wired 860 * up, for example many KVM do not pass it through, and so 861 * only trust an assertion that the monitor is connected. 862 */ 863 if (intel_crt_detect_hotplug(connector)) { 864 drm_dbg_kms(&dev_priv->drm, 865 "CRT detected via hotplug\n"); 866 status = connector_status_connected; 867 goto out; 868 } else 869 drm_dbg_kms(&dev_priv->drm, 870 "CRT not detected via hotplug\n"); 871 } 872 873 if (intel_crt_detect_ddc(connector)) { 874 status = connector_status_connected; 875 goto out; 876 } 877 878 /* Load detection is broken on HPD capable machines. Whoever wants a 879 * broken monitor (without edid) to work behind a broken kvm (that fails 880 * to have the right resistors for HP detection) needs to fix this up. 881 * For now just bail out. */ 882 if (I915_HAS_HOTPLUG(dev_priv)) { 883 status = connector_status_disconnected; 884 goto out; 885 } 886 887 load_detect: 888 if (!force) { 889 status = connector->status; 890 goto out; 891 } 892 893 /* for pre-945g platforms use load detect */ 894 state = intel_load_detect_get_pipe(connector, ctx); 895 if (IS_ERR(state)) { 896 status = PTR_ERR(state); 897 } else if (!state) { 898 status = connector_status_unknown; 899 } else { 900 if (intel_crt_detect_ddc(connector)) 901 status = connector_status_connected; 902 else if (DISPLAY_VER(dev_priv) < 4) 903 status = intel_crt_load_detect(crt, 904 to_intel_crtc(connector->state->crtc)->pipe); 905 else if (dev_priv->params.load_detect_test) 906 status = connector_status_disconnected; 907 else 908 status = connector_status_unknown; 909 intel_load_detect_release_pipe(connector, state, ctx); 910 } 911 912 out: 913 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 914 915 /* 916 * Make sure the refs for power wells enabled during detect are 917 * dropped to avoid a new detect cycle triggered by HPD polling. 918 */ 919 intel_display_power_flush_work(dev_priv); 920 921 return status; 922 } 923 924 static int intel_crt_get_modes(struct drm_connector *connector) 925 { 926 struct drm_device *dev = connector->dev; 927 struct drm_i915_private *dev_priv = to_i915(dev); 928 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 929 struct intel_encoder *intel_encoder = &crt->base; 930 intel_wakeref_t wakeref; 931 struct i2c_adapter *i2c; 932 int ret; 933 934 wakeref = intel_display_power_get(dev_priv, 935 intel_encoder->power_domain); 936 937 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->display.vbt.crt_ddc_pin); 938 ret = intel_crt_ddc_get_modes(connector, i2c); 939 if (ret || !IS_G4X(dev_priv)) 940 goto out; 941 942 /* Try to probe digital port for output in DVI-I -> VGA mode. */ 943 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); 944 ret = intel_crt_ddc_get_modes(connector, i2c); 945 946 out: 947 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 948 949 return ret; 950 } 951 952 void intel_crt_reset(struct drm_encoder *encoder) 953 { 954 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 955 struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder)); 956 957 if (DISPLAY_VER(dev_priv) >= 5) { 958 u32 adpa; 959 960 adpa = intel_de_read(dev_priv, crt->adpa_reg); 961 adpa &= ~ADPA_CRT_HOTPLUG_MASK; 962 adpa |= ADPA_HOTPLUG_BITS; 963 intel_de_write(dev_priv, crt->adpa_reg, adpa); 964 intel_de_posting_read(dev_priv, crt->adpa_reg); 965 966 drm_dbg_kms(&dev_priv->drm, "crt adpa set to 0x%x\n", adpa); 967 crt->force_hotplug_required = true; 968 } 969 970 } 971 972 /* 973 * Routines for controlling stuff on the analog port 974 */ 975 976 static const struct drm_connector_funcs intel_crt_connector_funcs = { 977 .fill_modes = drm_helper_probe_single_connector_modes, 978 .late_register = intel_connector_register, 979 .early_unregister = intel_connector_unregister, 980 .destroy = intel_connector_destroy, 981 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 982 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 983 }; 984 985 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { 986 .detect_ctx = intel_crt_detect, 987 .mode_valid = intel_crt_mode_valid, 988 .get_modes = intel_crt_get_modes, 989 }; 990 991 static const struct drm_encoder_funcs intel_crt_enc_funcs = { 992 .reset = intel_crt_reset, 993 .destroy = intel_encoder_destroy, 994 }; 995 996 void intel_crt_init(struct drm_i915_private *dev_priv) 997 { 998 struct drm_connector *connector; 999 struct intel_crt *crt; 1000 struct intel_connector *intel_connector; 1001 i915_reg_t adpa_reg; 1002 u32 adpa; 1003 1004 if (HAS_PCH_SPLIT(dev_priv)) 1005 adpa_reg = PCH_ADPA; 1006 else if (IS_VALLEYVIEW(dev_priv)) 1007 adpa_reg = VLV_ADPA; 1008 else 1009 adpa_reg = ADPA; 1010 1011 adpa = intel_de_read(dev_priv, adpa_reg); 1012 if ((adpa & ADPA_DAC_ENABLE) == 0) { 1013 /* 1014 * On some machines (some IVB at least) CRT can be 1015 * fused off, but there's no known fuse bit to 1016 * indicate that. On these machine the ADPA register 1017 * works normally, except the DAC enable bit won't 1018 * take. So the only way to tell is attempt to enable 1019 * it and see what happens. 1020 */ 1021 intel_de_write(dev_priv, adpa_reg, 1022 adpa | ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); 1023 if ((intel_de_read(dev_priv, adpa_reg) & ADPA_DAC_ENABLE) == 0) 1024 return; 1025 intel_de_write(dev_priv, adpa_reg, adpa); 1026 } 1027 1028 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); 1029 if (!crt) 1030 return; 1031 1032 intel_connector = intel_connector_alloc(); 1033 if (!intel_connector) { 1034 kfree(crt); 1035 return; 1036 } 1037 1038 connector = &intel_connector->base; 1039 crt->connector = intel_connector; 1040 drm_connector_init(&dev_priv->drm, &intel_connector->base, 1041 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); 1042 1043 drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs, 1044 DRM_MODE_ENCODER_DAC, "CRT"); 1045 1046 intel_connector_attach_encoder(intel_connector, &crt->base); 1047 1048 crt->base.type = INTEL_OUTPUT_ANALOG; 1049 crt->base.cloneable = BIT(INTEL_OUTPUT_DVO) | BIT(INTEL_OUTPUT_HDMI); 1050 if (IS_I830(dev_priv)) 1051 crt->base.pipe_mask = BIT(PIPE_A); 1052 else 1053 crt->base.pipe_mask = ~0; 1054 1055 if (DISPLAY_VER(dev_priv) != 2) 1056 connector->interlace_allowed = true; 1057 1058 crt->adpa_reg = adpa_reg; 1059 1060 crt->base.power_domain = POWER_DOMAIN_PORT_CRT; 1061 1062 if (I915_HAS_HOTPLUG(dev_priv) && 1063 !dmi_check_system(intel_spurious_crt_detect)) { 1064 crt->base.hpd_pin = HPD_CRT; 1065 crt->base.hotplug = intel_encoder_hotplug; 1066 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 1067 } else { 1068 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1069 } 1070 1071 if (HAS_DDI(dev_priv)) { 1072 assert_port_valid(dev_priv, PORT_E); 1073 1074 crt->base.port = PORT_E; 1075 crt->base.get_config = hsw_crt_get_config; 1076 crt->base.get_hw_state = intel_ddi_get_hw_state; 1077 crt->base.compute_config = hsw_crt_compute_config; 1078 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt; 1079 crt->base.pre_enable = hsw_pre_enable_crt; 1080 crt->base.enable = hsw_enable_crt; 1081 crt->base.disable = hsw_disable_crt; 1082 crt->base.post_disable = hsw_post_disable_crt; 1083 crt->base.enable_clock = hsw_ddi_enable_clock; 1084 crt->base.disable_clock = hsw_ddi_disable_clock; 1085 crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled; 1086 1087 intel_ddi_buf_trans_init(&crt->base); 1088 } else { 1089 if (HAS_PCH_SPLIT(dev_priv)) { 1090 crt->base.compute_config = pch_crt_compute_config; 1091 crt->base.disable = pch_disable_crt; 1092 crt->base.post_disable = pch_post_disable_crt; 1093 } else { 1094 crt->base.compute_config = intel_crt_compute_config; 1095 crt->base.disable = intel_disable_crt; 1096 } 1097 crt->base.port = PORT_NONE; 1098 crt->base.get_config = intel_crt_get_config; 1099 crt->base.get_hw_state = intel_crt_get_hw_state; 1100 crt->base.enable = intel_enable_crt; 1101 } 1102 intel_connector->get_hw_state = intel_connector_get_hw_state; 1103 1104 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); 1105 1106 /* 1107 * TODO: find a proper way to discover whether we need to set the the 1108 * polarity and link reversal bits or not, instead of relying on the 1109 * BIOS. 1110 */ 1111 if (HAS_PCH_LPT(dev_priv)) { 1112 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | 1113 FDI_RX_LINK_REVERSAL_OVERRIDE; 1114 1115 dev_priv->display.fdi.rx_config = intel_de_read(dev_priv, 1116 FDI_RX_CTL(PIPE_A)) & fdi_config; 1117 } 1118 1119 intel_crt_reset(&crt->base.base); 1120 } 1121