1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *	Eric Anholt <eric@anholt.net>
25  */
26 
27 #include <linux/dmi.h>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 
31 #include <drm/drm_atomic_helper.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_edid.h>
34 #include <drm/drm_probe_helper.h>
35 
36 #include "i915_drv.h"
37 #include "intel_connector.h"
38 #include "intel_crt.h"
39 #include "intel_crtc.h"
40 #include "intel_ddi.h"
41 #include "intel_ddi_buf_trans.h"
42 #include "intel_de.h"
43 #include "intel_display_types.h"
44 #include "intel_fdi.h"
45 #include "intel_fifo_underrun.h"
46 #include "intel_gmbus.h"
47 #include "intel_hotplug.h"
48 #include "intel_pch_display.h"
49 
50 /* Here's the desired hotplug mode */
51 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |		\
52 			   ADPA_CRT_HOTPLUG_WARMUP_10MS |		\
53 			   ADPA_CRT_HOTPLUG_SAMPLE_4S |			\
54 			   ADPA_CRT_HOTPLUG_VOLTAGE_50 |		\
55 			   ADPA_CRT_HOTPLUG_VOLREF_325MV |		\
56 			   ADPA_CRT_HOTPLUG_ENABLE)
57 
58 struct intel_crt {
59 	struct intel_encoder base;
60 	/* DPMS state is stored in the connector, which we need in the
61 	 * encoder's enable/disable callbacks */
62 	struct intel_connector *connector;
63 	bool force_hotplug_required;
64 	i915_reg_t adpa_reg;
65 };
66 
67 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
68 {
69 	return container_of(encoder, struct intel_crt, base);
70 }
71 
72 static struct intel_crt *intel_attached_crt(struct intel_connector *connector)
73 {
74 	return intel_encoder_to_crt(intel_attached_encoder(connector));
75 }
76 
77 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
78 			    i915_reg_t adpa_reg, enum pipe *pipe)
79 {
80 	u32 val;
81 
82 	val = intel_de_read(dev_priv, adpa_reg);
83 
84 	/* asserts want to know the pipe even if the port is disabled */
85 	if (HAS_PCH_CPT(dev_priv))
86 		*pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT;
87 	else
88 		*pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;
89 
90 	return val & ADPA_DAC_ENABLE;
91 }
92 
93 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
94 				   enum pipe *pipe)
95 {
96 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
97 	struct intel_crt *crt = intel_encoder_to_crt(encoder);
98 	intel_wakeref_t wakeref;
99 	bool ret;
100 
101 	wakeref = intel_display_power_get_if_enabled(dev_priv,
102 						     encoder->power_domain);
103 	if (!wakeref)
104 		return false;
105 
106 	ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
107 
108 	intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
109 
110 	return ret;
111 }
112 
113 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
114 {
115 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
116 	struct intel_crt *crt = intel_encoder_to_crt(encoder);
117 	u32 tmp, flags = 0;
118 
119 	tmp = intel_de_read(dev_priv, crt->adpa_reg);
120 
121 	if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
122 		flags |= DRM_MODE_FLAG_PHSYNC;
123 	else
124 		flags |= DRM_MODE_FLAG_NHSYNC;
125 
126 	if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
127 		flags |= DRM_MODE_FLAG_PVSYNC;
128 	else
129 		flags |= DRM_MODE_FLAG_NVSYNC;
130 
131 	return flags;
132 }
133 
134 static void intel_crt_get_config(struct intel_encoder *encoder,
135 				 struct intel_crtc_state *pipe_config)
136 {
137 	pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
138 
139 	pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
140 
141 	pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
142 }
143 
144 static void hsw_crt_get_config(struct intel_encoder *encoder,
145 			       struct intel_crtc_state *pipe_config)
146 {
147 	lpt_pch_get_config(pipe_config);
148 
149 	hsw_ddi_get_config(encoder, pipe_config);
150 
151 	pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
152 					      DRM_MODE_FLAG_NHSYNC |
153 					      DRM_MODE_FLAG_PVSYNC |
154 					      DRM_MODE_FLAG_NVSYNC);
155 	pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
156 }
157 
158 /* Note: The caller is required to filter out dpms modes not supported by the
159  * platform. */
160 static void intel_crt_set_dpms(struct intel_encoder *encoder,
161 			       const struct intel_crtc_state *crtc_state,
162 			       int mode)
163 {
164 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
165 	struct intel_crt *crt = intel_encoder_to_crt(encoder);
166 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
167 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
168 	u32 adpa;
169 
170 	if (DISPLAY_VER(dev_priv) >= 5)
171 		adpa = ADPA_HOTPLUG_BITS;
172 	else
173 		adpa = 0;
174 
175 	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
176 		adpa |= ADPA_HSYNC_ACTIVE_HIGH;
177 	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
178 		adpa |= ADPA_VSYNC_ACTIVE_HIGH;
179 
180 	/* For CPT allow 3 pipe config, for others just use A or B */
181 	if (HAS_PCH_LPT(dev_priv))
182 		; /* Those bits don't exist here */
183 	else if (HAS_PCH_CPT(dev_priv))
184 		adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
185 	else
186 		adpa |= ADPA_PIPE_SEL(crtc->pipe);
187 
188 	if (!HAS_PCH_SPLIT(dev_priv))
189 		intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
190 
191 	switch (mode) {
192 	case DRM_MODE_DPMS_ON:
193 		adpa |= ADPA_DAC_ENABLE;
194 		break;
195 	case DRM_MODE_DPMS_STANDBY:
196 		adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
197 		break;
198 	case DRM_MODE_DPMS_SUSPEND:
199 		adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
200 		break;
201 	case DRM_MODE_DPMS_OFF:
202 		adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
203 		break;
204 	}
205 
206 	intel_de_write(dev_priv, crt->adpa_reg, adpa);
207 }
208 
209 static void intel_disable_crt(struct intel_atomic_state *state,
210 			      struct intel_encoder *encoder,
211 			      const struct intel_crtc_state *old_crtc_state,
212 			      const struct drm_connector_state *old_conn_state)
213 {
214 	intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
215 }
216 
217 static void pch_disable_crt(struct intel_atomic_state *state,
218 			    struct intel_encoder *encoder,
219 			    const struct intel_crtc_state *old_crtc_state,
220 			    const struct drm_connector_state *old_conn_state)
221 {
222 }
223 
224 static void pch_post_disable_crt(struct intel_atomic_state *state,
225 				 struct intel_encoder *encoder,
226 				 const struct intel_crtc_state *old_crtc_state,
227 				 const struct drm_connector_state *old_conn_state)
228 {
229 	intel_disable_crt(state, encoder, old_crtc_state, old_conn_state);
230 }
231 
232 static void hsw_disable_crt(struct intel_atomic_state *state,
233 			    struct intel_encoder *encoder,
234 			    const struct intel_crtc_state *old_crtc_state,
235 			    const struct drm_connector_state *old_conn_state)
236 {
237 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
238 
239 	drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
240 
241 	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
242 }
243 
244 static void hsw_post_disable_crt(struct intel_atomic_state *state,
245 				 struct intel_encoder *encoder,
246 				 const struct intel_crtc_state *old_crtc_state,
247 				 const struct drm_connector_state *old_conn_state)
248 {
249 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
250 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
251 
252 	intel_crtc_vblank_off(old_crtc_state);
253 
254 	intel_disable_transcoder(old_crtc_state);
255 
256 	intel_ddi_disable_transcoder_func(old_crtc_state);
257 
258 	ilk_pfit_disable(old_crtc_state);
259 
260 	intel_ddi_disable_pipe_clock(old_crtc_state);
261 
262 	pch_post_disable_crt(state, encoder, old_crtc_state, old_conn_state);
263 
264 	lpt_pch_disable(state, crtc);
265 
266 	hsw_fdi_disable(encoder);
267 
268 	drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
269 
270 	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
271 }
272 
273 static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state,
274 				   struct intel_encoder *encoder,
275 				   const struct intel_crtc_state *crtc_state,
276 				   const struct drm_connector_state *conn_state)
277 {
278 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
279 
280 	drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
281 
282 	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
283 }
284 
285 static void hsw_pre_enable_crt(struct intel_atomic_state *state,
286 			       struct intel_encoder *encoder,
287 			       const struct intel_crtc_state *crtc_state,
288 			       const struct drm_connector_state *conn_state)
289 {
290 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
291 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
292 	enum pipe pipe = crtc->pipe;
293 
294 	drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
295 
296 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
297 
298 	hsw_fdi_link_train(encoder, crtc_state);
299 
300 	intel_ddi_enable_pipe_clock(encoder, crtc_state);
301 }
302 
303 static void hsw_enable_crt(struct intel_atomic_state *state,
304 			   struct intel_encoder *encoder,
305 			   const struct intel_crtc_state *crtc_state,
306 			   const struct drm_connector_state *conn_state)
307 {
308 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
309 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
310 	enum pipe pipe = crtc->pipe;
311 
312 	drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
313 
314 	intel_ddi_enable_transcoder_func(encoder, crtc_state);
315 
316 	intel_enable_transcoder(crtc_state);
317 
318 	lpt_pch_enable(state, crtc);
319 
320 	intel_crtc_vblank_on(crtc_state);
321 
322 	intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
323 
324 	intel_crtc_wait_for_next_vblank(crtc);
325 	intel_crtc_wait_for_next_vblank(crtc);
326 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
327 	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
328 }
329 
330 static void intel_enable_crt(struct intel_atomic_state *state,
331 			     struct intel_encoder *encoder,
332 			     const struct intel_crtc_state *crtc_state,
333 			     const struct drm_connector_state *conn_state)
334 {
335 	intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
336 }
337 
338 static enum drm_mode_status
339 intel_crt_mode_valid(struct drm_connector *connector,
340 		     struct drm_display_mode *mode)
341 {
342 	struct drm_device *dev = connector->dev;
343 	struct drm_i915_private *dev_priv = to_i915(dev);
344 	int max_dotclk = dev_priv->max_dotclk_freq;
345 	int max_clock;
346 
347 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
348 		return MODE_NO_DBLESCAN;
349 
350 	if (mode->clock < 25000)
351 		return MODE_CLOCK_LOW;
352 
353 	if (HAS_PCH_LPT(dev_priv))
354 		max_clock = 180000;
355 	else if (IS_VALLEYVIEW(dev_priv))
356 		/*
357 		 * 270 MHz due to current DPLL limits,
358 		 * DAC limit supposedly 355 MHz.
359 		 */
360 		max_clock = 270000;
361 	else if (IS_DISPLAY_VER(dev_priv, 3, 4))
362 		max_clock = 400000;
363 	else
364 		max_clock = 350000;
365 	if (mode->clock > max_clock)
366 		return MODE_CLOCK_HIGH;
367 
368 	if (mode->clock > max_dotclk)
369 		return MODE_CLOCK_HIGH;
370 
371 	/* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
372 	if (HAS_PCH_LPT(dev_priv) &&
373 	    ilk_get_lanes_required(mode->clock, 270000, 24) > 2)
374 		return MODE_CLOCK_HIGH;
375 
376 	/* HSW/BDW FDI limited to 4k */
377 	if (mode->hdisplay > 4096)
378 		return MODE_H_ILLEGAL;
379 
380 	return MODE_OK;
381 }
382 
383 static int intel_crt_compute_config(struct intel_encoder *encoder,
384 				    struct intel_crtc_state *pipe_config,
385 				    struct drm_connector_state *conn_state)
386 {
387 	struct drm_display_mode *adjusted_mode =
388 		&pipe_config->hw.adjusted_mode;
389 
390 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
391 		return -EINVAL;
392 
393 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
394 
395 	return 0;
396 }
397 
398 static int pch_crt_compute_config(struct intel_encoder *encoder,
399 				  struct intel_crtc_state *pipe_config,
400 				  struct drm_connector_state *conn_state)
401 {
402 	struct drm_display_mode *adjusted_mode =
403 		&pipe_config->hw.adjusted_mode;
404 
405 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
406 		return -EINVAL;
407 
408 	pipe_config->has_pch_encoder = true;
409 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
410 
411 	return 0;
412 }
413 
414 static int hsw_crt_compute_config(struct intel_encoder *encoder,
415 				  struct intel_crtc_state *pipe_config,
416 				  struct drm_connector_state *conn_state)
417 {
418 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
419 	struct drm_display_mode *adjusted_mode =
420 		&pipe_config->hw.adjusted_mode;
421 
422 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
423 		return -EINVAL;
424 
425 	/* HSW/BDW FDI limited to 4k */
426 	if (adjusted_mode->crtc_hdisplay > 4096 ||
427 	    adjusted_mode->crtc_hblank_start > 4096)
428 		return -EINVAL;
429 
430 	pipe_config->has_pch_encoder = true;
431 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
432 
433 	/* LPT FDI RX only supports 8bpc. */
434 	if (HAS_PCH_LPT(dev_priv)) {
435 		if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
436 			drm_dbg_kms(&dev_priv->drm,
437 				    "LPT only supports 24bpp\n");
438 			return -EINVAL;
439 		}
440 
441 		pipe_config->pipe_bpp = 24;
442 	}
443 
444 	/* FDI must always be 2.7 GHz */
445 	pipe_config->port_clock = 135000 * 2;
446 
447 	return 0;
448 }
449 
450 static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
451 {
452 	struct drm_device *dev = connector->dev;
453 	struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
454 	struct drm_i915_private *dev_priv = to_i915(dev);
455 	u32 adpa;
456 	bool ret;
457 
458 	/* The first time through, trigger an explicit detection cycle */
459 	if (crt->force_hotplug_required) {
460 		bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
461 		u32 save_adpa;
462 
463 		crt->force_hotplug_required = false;
464 
465 		save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
466 		drm_dbg_kms(&dev_priv->drm,
467 			    "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
468 
469 		adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
470 		if (turn_off_dac)
471 			adpa &= ~ADPA_DAC_ENABLE;
472 
473 		intel_de_write(dev_priv, crt->adpa_reg, adpa);
474 
475 		if (intel_de_wait_for_clear(dev_priv,
476 					    crt->adpa_reg,
477 					    ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
478 					    1000))
479 			drm_dbg_kms(&dev_priv->drm,
480 				    "timed out waiting for FORCE_TRIGGER");
481 
482 		if (turn_off_dac) {
483 			intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
484 			intel_de_posting_read(dev_priv, crt->adpa_reg);
485 		}
486 	}
487 
488 	/* Check the status to see if both blue and green are on now */
489 	adpa = intel_de_read(dev_priv, crt->adpa_reg);
490 	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
491 		ret = true;
492 	else
493 		ret = false;
494 	drm_dbg_kms(&dev_priv->drm, "ironlake hotplug adpa=0x%x, result %d\n",
495 		    adpa, ret);
496 
497 	return ret;
498 }
499 
500 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
501 {
502 	struct drm_device *dev = connector->dev;
503 	struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
504 	struct drm_i915_private *dev_priv = to_i915(dev);
505 	bool reenable_hpd;
506 	u32 adpa;
507 	bool ret;
508 	u32 save_adpa;
509 
510 	/*
511 	 * Doing a force trigger causes a hpd interrupt to get sent, which can
512 	 * get us stuck in a loop if we're polling:
513 	 *  - We enable power wells and reset the ADPA
514 	 *  - output_poll_exec does force probe on VGA, triggering a hpd
515 	 *  - HPD handler waits for poll to unlock dev->mode_config.mutex
516 	 *  - output_poll_exec shuts off the ADPA, unlocks
517 	 *    dev->mode_config.mutex
518 	 *  - HPD handler runs, resets ADPA and brings us back to the start
519 	 *
520 	 * Just disable HPD interrupts here to prevent this
521 	 */
522 	reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
523 
524 	save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
525 	drm_dbg_kms(&dev_priv->drm,
526 		    "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
527 
528 	adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
529 
530 	intel_de_write(dev_priv, crt->adpa_reg, adpa);
531 
532 	if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg,
533 				    ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) {
534 		drm_dbg_kms(&dev_priv->drm,
535 			    "timed out waiting for FORCE_TRIGGER");
536 		intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
537 	}
538 
539 	/* Check the status to see if both blue and green are on now */
540 	adpa = intel_de_read(dev_priv, crt->adpa_reg);
541 	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
542 		ret = true;
543 	else
544 		ret = false;
545 
546 	drm_dbg_kms(&dev_priv->drm,
547 		    "valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
548 
549 	if (reenable_hpd)
550 		intel_hpd_enable(dev_priv, crt->base.hpd_pin);
551 
552 	return ret;
553 }
554 
555 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
556 {
557 	struct drm_device *dev = connector->dev;
558 	struct drm_i915_private *dev_priv = to_i915(dev);
559 	u32 stat;
560 	bool ret = false;
561 	int i, tries = 0;
562 
563 	if (HAS_PCH_SPLIT(dev_priv))
564 		return ilk_crt_detect_hotplug(connector);
565 
566 	if (IS_VALLEYVIEW(dev_priv))
567 		return valleyview_crt_detect_hotplug(connector);
568 
569 	/*
570 	 * On 4 series desktop, CRT detect sequence need to be done twice
571 	 * to get a reliable result.
572 	 */
573 
574 	if (IS_G45(dev_priv))
575 		tries = 2;
576 	else
577 		tries = 1;
578 
579 	for (i = 0; i < tries ; i++) {
580 		/* turn on the FORCE_DETECT */
581 		i915_hotplug_interrupt_update(dev_priv,
582 					      CRT_HOTPLUG_FORCE_DETECT,
583 					      CRT_HOTPLUG_FORCE_DETECT);
584 		/* wait for FORCE_DETECT to go off */
585 		if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN,
586 					    CRT_HOTPLUG_FORCE_DETECT, 1000))
587 			drm_dbg_kms(&dev_priv->drm,
588 				    "timed out waiting for FORCE_DETECT to go off");
589 	}
590 
591 	stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT);
592 	if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
593 		ret = true;
594 
595 	/* clear the interrupt we just generated, if any */
596 	intel_de_write(dev_priv, PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
597 
598 	i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
599 
600 	return ret;
601 }
602 
603 static struct edid *intel_crt_get_edid(struct drm_connector *connector,
604 				struct i2c_adapter *i2c)
605 {
606 	struct edid *edid;
607 
608 	edid = drm_get_edid(connector, i2c);
609 
610 	if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
611 		drm_dbg_kms(connector->dev,
612 			    "CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
613 		intel_gmbus_force_bit(i2c, true);
614 		edid = drm_get_edid(connector, i2c);
615 		intel_gmbus_force_bit(i2c, false);
616 	}
617 
618 	return edid;
619 }
620 
621 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
622 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
623 				struct i2c_adapter *adapter)
624 {
625 	struct edid *edid;
626 	int ret;
627 
628 	edid = intel_crt_get_edid(connector, adapter);
629 	if (!edid)
630 		return 0;
631 
632 	ret = intel_connector_update_modes(connector, edid);
633 	kfree(edid);
634 
635 	return ret;
636 }
637 
638 static bool intel_crt_detect_ddc(struct drm_connector *connector)
639 {
640 	struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
641 	struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
642 	struct edid *edid;
643 	struct i2c_adapter *i2c;
644 	bool ret = false;
645 
646 	BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
647 
648 	i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
649 	edid = intel_crt_get_edid(connector, i2c);
650 
651 	if (edid) {
652 		bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
653 
654 		/*
655 		 * This may be a DVI-I connector with a shared DDC
656 		 * link between analog and digital outputs, so we
657 		 * have to check the EDID input spec of the attached device.
658 		 */
659 		if (!is_digital) {
660 			drm_dbg_kms(&dev_priv->drm,
661 				    "CRT detected via DDC:0x50 [EDID]\n");
662 			ret = true;
663 		} else {
664 			drm_dbg_kms(&dev_priv->drm,
665 				    "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
666 		}
667 	} else {
668 		drm_dbg_kms(&dev_priv->drm,
669 			    "CRT not detected via DDC:0x50 [no valid EDID found]\n");
670 	}
671 
672 	kfree(edid);
673 
674 	return ret;
675 }
676 
677 static enum drm_connector_status
678 intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
679 {
680 	struct drm_device *dev = crt->base.base.dev;
681 	struct drm_i915_private *dev_priv = to_i915(dev);
682 	struct intel_uncore *uncore = &dev_priv->uncore;
683 	u32 save_bclrpat;
684 	u32 save_vtotal;
685 	u32 vtotal, vactive;
686 	u32 vsample;
687 	u32 vblank, vblank_start, vblank_end;
688 	u32 dsl;
689 	i915_reg_t bclrpat_reg, vtotal_reg,
690 		vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
691 	u8 st00;
692 	enum drm_connector_status status;
693 
694 	drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n");
695 
696 	bclrpat_reg = BCLRPAT(pipe);
697 	vtotal_reg = VTOTAL(pipe);
698 	vblank_reg = VBLANK(pipe);
699 	vsync_reg = VSYNC(pipe);
700 	pipeconf_reg = PIPECONF(pipe);
701 	pipe_dsl_reg = PIPEDSL(pipe);
702 
703 	save_bclrpat = intel_uncore_read(uncore, bclrpat_reg);
704 	save_vtotal = intel_uncore_read(uncore, vtotal_reg);
705 	vblank = intel_uncore_read(uncore, vblank_reg);
706 
707 	vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
708 	vactive = (save_vtotal & 0x7ff) + 1;
709 
710 	vblank_start = (vblank & 0xfff) + 1;
711 	vblank_end = ((vblank >> 16) & 0xfff) + 1;
712 
713 	/* Set the border color to purple. */
714 	intel_uncore_write(uncore, bclrpat_reg, 0x500050);
715 
716 	if (DISPLAY_VER(dev_priv) != 2) {
717 		u32 pipeconf = intel_uncore_read(uncore, pipeconf_reg);
718 		intel_uncore_write(uncore,
719 				   pipeconf_reg,
720 				   pipeconf | PIPECONF_FORCE_BORDER);
721 		intel_uncore_posting_read(uncore, pipeconf_reg);
722 		/* Wait for next Vblank to substitue
723 		 * border color for Color info */
724 		intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
725 		st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE);
726 		status = ((st00 & (1 << 4)) != 0) ?
727 			connector_status_connected :
728 			connector_status_disconnected;
729 
730 		intel_uncore_write(uncore, pipeconf_reg, pipeconf);
731 	} else {
732 		bool restore_vblank = false;
733 		int count, detect;
734 
735 		/*
736 		* If there isn't any border, add some.
737 		* Yes, this will flicker
738 		*/
739 		if (vblank_start <= vactive && vblank_end >= vtotal) {
740 			u32 vsync = intel_de_read(dev_priv, vsync_reg);
741 			u32 vsync_start = (vsync & 0xffff) + 1;
742 
743 			vblank_start = vsync_start;
744 			intel_uncore_write(uncore,
745 					   vblank_reg,
746 					   (vblank_start - 1) |
747 					   ((vblank_end - 1) << 16));
748 			restore_vblank = true;
749 		}
750 		/* sample in the vertical border, selecting the larger one */
751 		if (vblank_start - vactive >= vtotal - vblank_end)
752 			vsample = (vblank_start + vactive) >> 1;
753 		else
754 			vsample = (vtotal + vblank_end) >> 1;
755 
756 		/*
757 		 * Wait for the border to be displayed
758 		 */
759 		while (intel_uncore_read(uncore, pipe_dsl_reg) >= vactive)
760 			;
761 		while ((dsl = intel_uncore_read(uncore, pipe_dsl_reg)) <=
762 		       vsample)
763 			;
764 		/*
765 		 * Watch ST00 for an entire scanline
766 		 */
767 		detect = 0;
768 		count = 0;
769 		do {
770 			count++;
771 			/* Read the ST00 VGA status register */
772 			st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE);
773 			if (st00 & (1 << 4))
774 				detect++;
775 		} while ((intel_uncore_read(uncore, pipe_dsl_reg) == dsl));
776 
777 		/* restore vblank if necessary */
778 		if (restore_vblank)
779 			intel_uncore_write(uncore, vblank_reg, vblank);
780 		/*
781 		 * If more than 3/4 of the scanline detected a monitor,
782 		 * then it is assumed to be present. This works even on i830,
783 		 * where there isn't any way to force the border color across
784 		 * the screen
785 		 */
786 		status = detect * 4 > count * 3 ?
787 			 connector_status_connected :
788 			 connector_status_disconnected;
789 	}
790 
791 	/* Restore previous settings */
792 	intel_uncore_write(uncore, bclrpat_reg, save_bclrpat);
793 
794 	return status;
795 }
796 
797 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id)
798 {
799 	DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident);
800 	return 1;
801 }
802 
803 static const struct dmi_system_id intel_spurious_crt_detect[] = {
804 	{
805 		.callback = intel_spurious_crt_detect_dmi_callback,
806 		.ident = "ACER ZGB",
807 		.matches = {
808 			DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
809 			DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
810 		},
811 	},
812 	{
813 		.callback = intel_spurious_crt_detect_dmi_callback,
814 		.ident = "Intel DZ77BH-55K",
815 		.matches = {
816 			DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"),
817 			DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
818 		},
819 	},
820 	{ }
821 };
822 
823 static int
824 intel_crt_detect(struct drm_connector *connector,
825 		 struct drm_modeset_acquire_ctx *ctx,
826 		 bool force)
827 {
828 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
829 	struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
830 	struct intel_encoder *intel_encoder = &crt->base;
831 	intel_wakeref_t wakeref;
832 	int status, ret;
833 	struct intel_load_detect_pipe tmp;
834 
835 	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s] force=%d\n",
836 		    connector->base.id, connector->name,
837 		    force);
838 
839 	if (!INTEL_DISPLAY_ENABLED(dev_priv))
840 		return connector_status_disconnected;
841 
842 	if (dev_priv->params.load_detect_test) {
843 		wakeref = intel_display_power_get(dev_priv,
844 						  intel_encoder->power_domain);
845 		goto load_detect;
846 	}
847 
848 	/* Skip machines without VGA that falsely report hotplug events */
849 	if (dmi_check_system(intel_spurious_crt_detect))
850 		return connector_status_disconnected;
851 
852 	wakeref = intel_display_power_get(dev_priv,
853 					  intel_encoder->power_domain);
854 
855 	if (I915_HAS_HOTPLUG(dev_priv)) {
856 		/* We can not rely on the HPD pin always being correctly wired
857 		 * up, for example many KVM do not pass it through, and so
858 		 * only trust an assertion that the monitor is connected.
859 		 */
860 		if (intel_crt_detect_hotplug(connector)) {
861 			drm_dbg_kms(&dev_priv->drm,
862 				    "CRT detected via hotplug\n");
863 			status = connector_status_connected;
864 			goto out;
865 		} else
866 			drm_dbg_kms(&dev_priv->drm,
867 				    "CRT not detected via hotplug\n");
868 	}
869 
870 	if (intel_crt_detect_ddc(connector)) {
871 		status = connector_status_connected;
872 		goto out;
873 	}
874 
875 	/* Load detection is broken on HPD capable machines. Whoever wants a
876 	 * broken monitor (without edid) to work behind a broken kvm (that fails
877 	 * to have the right resistors for HP detection) needs to fix this up.
878 	 * For now just bail out. */
879 	if (I915_HAS_HOTPLUG(dev_priv)) {
880 		status = connector_status_disconnected;
881 		goto out;
882 	}
883 
884 load_detect:
885 	if (!force) {
886 		status = connector->status;
887 		goto out;
888 	}
889 
890 	/* for pre-945g platforms use load detect */
891 	ret = intel_get_load_detect_pipe(connector, &tmp, ctx);
892 	if (ret > 0) {
893 		if (intel_crt_detect_ddc(connector))
894 			status = connector_status_connected;
895 		else if (DISPLAY_VER(dev_priv) < 4)
896 			status = intel_crt_load_detect(crt,
897 				to_intel_crtc(connector->state->crtc)->pipe);
898 		else if (dev_priv->params.load_detect_test)
899 			status = connector_status_disconnected;
900 		else
901 			status = connector_status_unknown;
902 		intel_release_load_detect_pipe(connector, &tmp, ctx);
903 	} else if (ret == 0) {
904 		status = connector_status_unknown;
905 	} else {
906 		status = ret;
907 	}
908 
909 out:
910 	intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
911 
912 	/*
913 	 * Make sure the refs for power wells enabled during detect are
914 	 * dropped to avoid a new detect cycle triggered by HPD polling.
915 	 */
916 	intel_display_power_flush_work(dev_priv);
917 
918 	return status;
919 }
920 
921 static int intel_crt_get_modes(struct drm_connector *connector)
922 {
923 	struct drm_device *dev = connector->dev;
924 	struct drm_i915_private *dev_priv = to_i915(dev);
925 	struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
926 	struct intel_encoder *intel_encoder = &crt->base;
927 	intel_wakeref_t wakeref;
928 	struct i2c_adapter *i2c;
929 	int ret;
930 
931 	wakeref = intel_display_power_get(dev_priv,
932 					  intel_encoder->power_domain);
933 
934 	i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
935 	ret = intel_crt_ddc_get_modes(connector, i2c);
936 	if (ret || !IS_G4X(dev_priv))
937 		goto out;
938 
939 	/* Try to probe digital port for output in DVI-I -> VGA mode. */
940 	i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
941 	ret = intel_crt_ddc_get_modes(connector, i2c);
942 
943 out:
944 	intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
945 
946 	return ret;
947 }
948 
949 void intel_crt_reset(struct drm_encoder *encoder)
950 {
951 	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
952 	struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
953 
954 	if (DISPLAY_VER(dev_priv) >= 5) {
955 		u32 adpa;
956 
957 		adpa = intel_de_read(dev_priv, crt->adpa_reg);
958 		adpa &= ~ADPA_CRT_HOTPLUG_MASK;
959 		adpa |= ADPA_HOTPLUG_BITS;
960 		intel_de_write(dev_priv, crt->adpa_reg, adpa);
961 		intel_de_posting_read(dev_priv, crt->adpa_reg);
962 
963 		drm_dbg_kms(&dev_priv->drm, "crt adpa set to 0x%x\n", adpa);
964 		crt->force_hotplug_required = true;
965 	}
966 
967 }
968 
969 /*
970  * Routines for controlling stuff on the analog port
971  */
972 
973 static const struct drm_connector_funcs intel_crt_connector_funcs = {
974 	.fill_modes = drm_helper_probe_single_connector_modes,
975 	.late_register = intel_connector_register,
976 	.early_unregister = intel_connector_unregister,
977 	.destroy = intel_connector_destroy,
978 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
979 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
980 };
981 
982 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
983 	.detect_ctx = intel_crt_detect,
984 	.mode_valid = intel_crt_mode_valid,
985 	.get_modes = intel_crt_get_modes,
986 };
987 
988 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
989 	.reset = intel_crt_reset,
990 	.destroy = intel_encoder_destroy,
991 };
992 
993 void intel_crt_init(struct drm_i915_private *dev_priv)
994 {
995 	struct drm_connector *connector;
996 	struct intel_crt *crt;
997 	struct intel_connector *intel_connector;
998 	i915_reg_t adpa_reg;
999 	u32 adpa;
1000 
1001 	if (HAS_PCH_SPLIT(dev_priv))
1002 		adpa_reg = PCH_ADPA;
1003 	else if (IS_VALLEYVIEW(dev_priv))
1004 		adpa_reg = VLV_ADPA;
1005 	else
1006 		adpa_reg = ADPA;
1007 
1008 	adpa = intel_de_read(dev_priv, adpa_reg);
1009 	if ((adpa & ADPA_DAC_ENABLE) == 0) {
1010 		/*
1011 		 * On some machines (some IVB at least) CRT can be
1012 		 * fused off, but there's no known fuse bit to
1013 		 * indicate that. On these machine the ADPA register
1014 		 * works normally, except the DAC enable bit won't
1015 		 * take. So the only way to tell is attempt to enable
1016 		 * it and see what happens.
1017 		 */
1018 		intel_de_write(dev_priv, adpa_reg,
1019 			       adpa | ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
1020 		if ((intel_de_read(dev_priv, adpa_reg) & ADPA_DAC_ENABLE) == 0)
1021 			return;
1022 		intel_de_write(dev_priv, adpa_reg, adpa);
1023 	}
1024 
1025 	crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
1026 	if (!crt)
1027 		return;
1028 
1029 	intel_connector = intel_connector_alloc();
1030 	if (!intel_connector) {
1031 		kfree(crt);
1032 		return;
1033 	}
1034 
1035 	connector = &intel_connector->base;
1036 	crt->connector = intel_connector;
1037 	drm_connector_init(&dev_priv->drm, &intel_connector->base,
1038 			   &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
1039 
1040 	drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
1041 			 DRM_MODE_ENCODER_DAC, "CRT");
1042 
1043 	intel_connector_attach_encoder(intel_connector, &crt->base);
1044 
1045 	crt->base.type = INTEL_OUTPUT_ANALOG;
1046 	crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
1047 	if (IS_I830(dev_priv))
1048 		crt->base.pipe_mask = BIT(PIPE_A);
1049 	else
1050 		crt->base.pipe_mask = ~0;
1051 
1052 	if (DISPLAY_VER(dev_priv) == 2)
1053 		connector->interlace_allowed = 0;
1054 	else
1055 		connector->interlace_allowed = 1;
1056 	connector->doublescan_allowed = 0;
1057 
1058 	crt->adpa_reg = adpa_reg;
1059 
1060 	crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
1061 
1062 	if (I915_HAS_HOTPLUG(dev_priv) &&
1063 	    !dmi_check_system(intel_spurious_crt_detect)) {
1064 		crt->base.hpd_pin = HPD_CRT;
1065 		crt->base.hotplug = intel_encoder_hotplug;
1066 		intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
1067 	} else {
1068 		intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1069 	}
1070 
1071 	if (HAS_DDI(dev_priv)) {
1072 		crt->base.port = PORT_E;
1073 		crt->base.get_config = hsw_crt_get_config;
1074 		crt->base.get_hw_state = intel_ddi_get_hw_state;
1075 		crt->base.compute_config = hsw_crt_compute_config;
1076 		crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
1077 		crt->base.pre_enable = hsw_pre_enable_crt;
1078 		crt->base.enable = hsw_enable_crt;
1079 		crt->base.disable = hsw_disable_crt;
1080 		crt->base.post_disable = hsw_post_disable_crt;
1081 		crt->base.enable_clock = hsw_ddi_enable_clock;
1082 		crt->base.disable_clock = hsw_ddi_disable_clock;
1083 		crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled;
1084 
1085 		intel_ddi_buf_trans_init(&crt->base);
1086 	} else {
1087 		if (HAS_PCH_SPLIT(dev_priv)) {
1088 			crt->base.compute_config = pch_crt_compute_config;
1089 			crt->base.disable = pch_disable_crt;
1090 			crt->base.post_disable = pch_post_disable_crt;
1091 		} else {
1092 			crt->base.compute_config = intel_crt_compute_config;
1093 			crt->base.disable = intel_disable_crt;
1094 		}
1095 		crt->base.port = PORT_NONE;
1096 		crt->base.get_config = intel_crt_get_config;
1097 		crt->base.get_hw_state = intel_crt_get_hw_state;
1098 		crt->base.enable = intel_enable_crt;
1099 	}
1100 	intel_connector->get_hw_state = intel_connector_get_hw_state;
1101 
1102 	drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
1103 
1104 	/*
1105 	 * TODO: find a proper way to discover whether we need to set the the
1106 	 * polarity and link reversal bits or not, instead of relying on the
1107 	 * BIOS.
1108 	 */
1109 	if (HAS_PCH_LPT(dev_priv)) {
1110 		u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
1111 				 FDI_RX_LINK_REVERSAL_OVERRIDE;
1112 
1113 		dev_priv->fdi_rx_config = intel_de_read(dev_priv,
1114 							FDI_RX_CTL(PIPE_A)) & fdi_config;
1115 	}
1116 
1117 	intel_crt_reset(&crt->base.base);
1118 }
1119