1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dmi.h> 28 #include <linux/i2c.h> 29 #include <linux/slab.h> 30 31 #include <drm/drm_atomic_helper.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_edid.h> 34 #include <drm/drm_probe_helper.h> 35 #include <drm/i915_drm.h> 36 37 #include "i915_drv.h" 38 #include "intel_connector.h" 39 #include "intel_crt.h" 40 #include "intel_ddi.h" 41 #include "intel_display_types.h" 42 #include "intel_fifo_underrun.h" 43 #include "intel_gmbus.h" 44 #include "intel_hotplug.h" 45 46 /* Here's the desired hotplug mode */ 47 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ 48 ADPA_CRT_HOTPLUG_WARMUP_10MS | \ 49 ADPA_CRT_HOTPLUG_SAMPLE_4S | \ 50 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ 51 ADPA_CRT_HOTPLUG_VOLREF_325MV | \ 52 ADPA_CRT_HOTPLUG_ENABLE) 53 54 struct intel_crt { 55 struct intel_encoder base; 56 /* DPMS state is stored in the connector, which we need in the 57 * encoder's enable/disable callbacks */ 58 struct intel_connector *connector; 59 bool force_hotplug_required; 60 i915_reg_t adpa_reg; 61 }; 62 63 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) 64 { 65 return container_of(encoder, struct intel_crt, base); 66 } 67 68 static struct intel_crt *intel_attached_crt(struct intel_connector *connector) 69 { 70 return intel_encoder_to_crt(intel_attached_encoder(connector)); 71 } 72 73 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv, 74 i915_reg_t adpa_reg, enum pipe *pipe) 75 { 76 u32 val; 77 78 val = intel_de_read(dev_priv, adpa_reg); 79 80 /* asserts want to know the pipe even if the port is disabled */ 81 if (HAS_PCH_CPT(dev_priv)) 82 *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT; 83 else 84 *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT; 85 86 return val & ADPA_DAC_ENABLE; 87 } 88 89 static bool intel_crt_get_hw_state(struct intel_encoder *encoder, 90 enum pipe *pipe) 91 { 92 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 93 struct intel_crt *crt = intel_encoder_to_crt(encoder); 94 intel_wakeref_t wakeref; 95 bool ret; 96 97 wakeref = intel_display_power_get_if_enabled(dev_priv, 98 encoder->power_domain); 99 if (!wakeref) 100 return false; 101 102 ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe); 103 104 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 105 106 return ret; 107 } 108 109 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) 110 { 111 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 112 struct intel_crt *crt = intel_encoder_to_crt(encoder); 113 u32 tmp, flags = 0; 114 115 tmp = intel_de_read(dev_priv, crt->adpa_reg); 116 117 if (tmp & ADPA_HSYNC_ACTIVE_HIGH) 118 flags |= DRM_MODE_FLAG_PHSYNC; 119 else 120 flags |= DRM_MODE_FLAG_NHSYNC; 121 122 if (tmp & ADPA_VSYNC_ACTIVE_HIGH) 123 flags |= DRM_MODE_FLAG_PVSYNC; 124 else 125 flags |= DRM_MODE_FLAG_NVSYNC; 126 127 return flags; 128 } 129 130 static void intel_crt_get_config(struct intel_encoder *encoder, 131 struct intel_crtc_state *pipe_config) 132 { 133 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 134 135 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); 136 137 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; 138 } 139 140 static void hsw_crt_get_config(struct intel_encoder *encoder, 141 struct intel_crtc_state *pipe_config) 142 { 143 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 144 145 intel_ddi_get_config(encoder, pipe_config); 146 147 pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | 148 DRM_MODE_FLAG_NHSYNC | 149 DRM_MODE_FLAG_PVSYNC | 150 DRM_MODE_FLAG_NVSYNC); 151 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); 152 153 pipe_config->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); 154 } 155 156 /* Note: The caller is required to filter out dpms modes not supported by the 157 * platform. */ 158 static void intel_crt_set_dpms(struct intel_encoder *encoder, 159 const struct intel_crtc_state *crtc_state, 160 int mode) 161 { 162 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 163 struct intel_crt *crt = intel_encoder_to_crt(encoder); 164 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 165 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 166 u32 adpa; 167 168 if (INTEL_GEN(dev_priv) >= 5) 169 adpa = ADPA_HOTPLUG_BITS; 170 else 171 adpa = 0; 172 173 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 174 adpa |= ADPA_HSYNC_ACTIVE_HIGH; 175 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 176 adpa |= ADPA_VSYNC_ACTIVE_HIGH; 177 178 /* For CPT allow 3 pipe config, for others just use A or B */ 179 if (HAS_PCH_LPT(dev_priv)) 180 ; /* Those bits don't exist here */ 181 else if (HAS_PCH_CPT(dev_priv)) 182 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe); 183 else 184 adpa |= ADPA_PIPE_SEL(crtc->pipe); 185 186 if (!HAS_PCH_SPLIT(dev_priv)) 187 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 188 189 switch (mode) { 190 case DRM_MODE_DPMS_ON: 191 adpa |= ADPA_DAC_ENABLE; 192 break; 193 case DRM_MODE_DPMS_STANDBY: 194 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; 195 break; 196 case DRM_MODE_DPMS_SUSPEND: 197 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; 198 break; 199 case DRM_MODE_DPMS_OFF: 200 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; 201 break; 202 } 203 204 intel_de_write(dev_priv, crt->adpa_reg, adpa); 205 } 206 207 static void intel_disable_crt(struct intel_encoder *encoder, 208 const struct intel_crtc_state *old_crtc_state, 209 const struct drm_connector_state *old_conn_state) 210 { 211 intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF); 212 } 213 214 static void pch_disable_crt(struct intel_encoder *encoder, 215 const struct intel_crtc_state *old_crtc_state, 216 const struct drm_connector_state *old_conn_state) 217 { 218 } 219 220 static void pch_post_disable_crt(struct intel_encoder *encoder, 221 const struct intel_crtc_state *old_crtc_state, 222 const struct drm_connector_state *old_conn_state) 223 { 224 intel_disable_crt(encoder, old_crtc_state, old_conn_state); 225 } 226 227 static void hsw_disable_crt(struct intel_encoder *encoder, 228 const struct intel_crtc_state *old_crtc_state, 229 const struct drm_connector_state *old_conn_state) 230 { 231 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 232 233 drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder); 234 235 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 236 } 237 238 static void hsw_post_disable_crt(struct intel_encoder *encoder, 239 const struct intel_crtc_state *old_crtc_state, 240 const struct drm_connector_state *old_conn_state) 241 { 242 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 243 244 intel_crtc_vblank_off(old_crtc_state); 245 246 intel_disable_pipe(old_crtc_state); 247 248 intel_ddi_disable_transcoder_func(old_crtc_state); 249 250 ilk_pfit_disable(old_crtc_state); 251 252 intel_ddi_disable_pipe_clock(old_crtc_state); 253 254 pch_post_disable_crt(encoder, old_crtc_state, old_conn_state); 255 256 lpt_disable_pch_transcoder(dev_priv); 257 lpt_disable_iclkip(dev_priv); 258 259 intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state); 260 261 drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder); 262 263 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 264 } 265 266 static void hsw_pre_pll_enable_crt(struct intel_encoder *encoder, 267 const struct intel_crtc_state *crtc_state, 268 const struct drm_connector_state *conn_state) 269 { 270 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 271 272 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder); 273 274 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 275 } 276 277 static void hsw_pre_enable_crt(struct intel_encoder *encoder, 278 const struct intel_crtc_state *crtc_state, 279 const struct drm_connector_state *conn_state) 280 { 281 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 282 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 283 enum pipe pipe = crtc->pipe; 284 285 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder); 286 287 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 288 289 hsw_fdi_link_train(encoder, crtc_state); 290 291 intel_ddi_enable_pipe_clock(crtc_state); 292 } 293 294 static void hsw_enable_crt(struct intel_encoder *encoder, 295 const struct intel_crtc_state *crtc_state, 296 const struct drm_connector_state *conn_state) 297 { 298 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 299 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 300 enum pipe pipe = crtc->pipe; 301 302 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder); 303 304 intel_enable_pipe(crtc_state); 305 306 lpt_pch_enable(crtc_state); 307 308 intel_crtc_vblank_on(crtc_state); 309 310 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); 311 312 intel_wait_for_vblank(dev_priv, pipe); 313 intel_wait_for_vblank(dev_priv, pipe); 314 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 315 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 316 } 317 318 static void intel_enable_crt(struct intel_encoder *encoder, 319 const struct intel_crtc_state *crtc_state, 320 const struct drm_connector_state *conn_state) 321 { 322 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); 323 } 324 325 static enum drm_mode_status 326 intel_crt_mode_valid(struct drm_connector *connector, 327 struct drm_display_mode *mode) 328 { 329 struct drm_device *dev = connector->dev; 330 struct drm_i915_private *dev_priv = to_i915(dev); 331 int max_dotclk = dev_priv->max_dotclk_freq; 332 int max_clock; 333 334 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 335 return MODE_NO_DBLESCAN; 336 337 if (mode->clock < 25000) 338 return MODE_CLOCK_LOW; 339 340 if (HAS_PCH_LPT(dev_priv)) 341 max_clock = 180000; 342 else if (IS_VALLEYVIEW(dev_priv)) 343 /* 344 * 270 MHz due to current DPLL limits, 345 * DAC limit supposedly 355 MHz. 346 */ 347 max_clock = 270000; 348 else if (IS_GEN_RANGE(dev_priv, 3, 4)) 349 max_clock = 400000; 350 else 351 max_clock = 350000; 352 if (mode->clock > max_clock) 353 return MODE_CLOCK_HIGH; 354 355 if (mode->clock > max_dotclk) 356 return MODE_CLOCK_HIGH; 357 358 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ 359 if (HAS_PCH_LPT(dev_priv) && 360 ilk_get_lanes_required(mode->clock, 270000, 24) > 2) 361 return MODE_CLOCK_HIGH; 362 363 /* HSW/BDW FDI limited to 4k */ 364 if (mode->hdisplay > 4096) 365 return MODE_H_ILLEGAL; 366 367 return MODE_OK; 368 } 369 370 static int intel_crt_compute_config(struct intel_encoder *encoder, 371 struct intel_crtc_state *pipe_config, 372 struct drm_connector_state *conn_state) 373 { 374 struct drm_display_mode *adjusted_mode = 375 &pipe_config->hw.adjusted_mode; 376 377 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 378 return -EINVAL; 379 380 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 381 382 return 0; 383 } 384 385 static int pch_crt_compute_config(struct intel_encoder *encoder, 386 struct intel_crtc_state *pipe_config, 387 struct drm_connector_state *conn_state) 388 { 389 struct drm_display_mode *adjusted_mode = 390 &pipe_config->hw.adjusted_mode; 391 392 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 393 return -EINVAL; 394 395 pipe_config->has_pch_encoder = true; 396 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 397 398 return 0; 399 } 400 401 static int hsw_crt_compute_config(struct intel_encoder *encoder, 402 struct intel_crtc_state *pipe_config, 403 struct drm_connector_state *conn_state) 404 { 405 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 406 struct drm_display_mode *adjusted_mode = 407 &pipe_config->hw.adjusted_mode; 408 409 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 410 return -EINVAL; 411 412 /* HSW/BDW FDI limited to 4k */ 413 if (adjusted_mode->crtc_hdisplay > 4096 || 414 adjusted_mode->crtc_hblank_start > 4096) 415 return -EINVAL; 416 417 pipe_config->has_pch_encoder = true; 418 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 419 420 /* LPT FDI RX only supports 8bpc. */ 421 if (HAS_PCH_LPT(dev_priv)) { 422 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { 423 drm_dbg_kms(&dev_priv->drm, 424 "LPT only supports 24bpp\n"); 425 return -EINVAL; 426 } 427 428 pipe_config->pipe_bpp = 24; 429 } 430 431 /* FDI must always be 2.7 GHz */ 432 pipe_config->port_clock = 135000 * 2; 433 434 return 0; 435 } 436 437 static bool ilk_crt_detect_hotplug(struct drm_connector *connector) 438 { 439 struct drm_device *dev = connector->dev; 440 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 441 struct drm_i915_private *dev_priv = to_i915(dev); 442 u32 adpa; 443 bool ret; 444 445 /* The first time through, trigger an explicit detection cycle */ 446 if (crt->force_hotplug_required) { 447 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv); 448 u32 save_adpa; 449 450 crt->force_hotplug_required = false; 451 452 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); 453 drm_dbg_kms(&dev_priv->drm, 454 "trigger hotplug detect cycle: adpa=0x%x\n", adpa); 455 456 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 457 if (turn_off_dac) 458 adpa &= ~ADPA_DAC_ENABLE; 459 460 intel_de_write(dev_priv, crt->adpa_reg, adpa); 461 462 if (intel_de_wait_for_clear(dev_priv, 463 crt->adpa_reg, 464 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 465 1000)) 466 drm_dbg_kms(&dev_priv->drm, 467 "timed out waiting for FORCE_TRIGGER"); 468 469 if (turn_off_dac) { 470 intel_de_write(dev_priv, crt->adpa_reg, save_adpa); 471 intel_de_posting_read(dev_priv, crt->adpa_reg); 472 } 473 } 474 475 /* Check the status to see if both blue and green are on now */ 476 adpa = intel_de_read(dev_priv, crt->adpa_reg); 477 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 478 ret = true; 479 else 480 ret = false; 481 drm_dbg_kms(&dev_priv->drm, "ironlake hotplug adpa=0x%x, result %d\n", 482 adpa, ret); 483 484 return ret; 485 } 486 487 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) 488 { 489 struct drm_device *dev = connector->dev; 490 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 491 struct drm_i915_private *dev_priv = to_i915(dev); 492 bool reenable_hpd; 493 u32 adpa; 494 bool ret; 495 u32 save_adpa; 496 497 /* 498 * Doing a force trigger causes a hpd interrupt to get sent, which can 499 * get us stuck in a loop if we're polling: 500 * - We enable power wells and reset the ADPA 501 * - output_poll_exec does force probe on VGA, triggering a hpd 502 * - HPD handler waits for poll to unlock dev->mode_config.mutex 503 * - output_poll_exec shuts off the ADPA, unlocks 504 * dev->mode_config.mutex 505 * - HPD handler runs, resets ADPA and brings us back to the start 506 * 507 * Just disable HPD interrupts here to prevent this 508 */ 509 reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin); 510 511 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); 512 drm_dbg_kms(&dev_priv->drm, 513 "trigger hotplug detect cycle: adpa=0x%x\n", adpa); 514 515 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 516 517 intel_de_write(dev_priv, crt->adpa_reg, adpa); 518 519 if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg, 520 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) { 521 drm_dbg_kms(&dev_priv->drm, 522 "timed out waiting for FORCE_TRIGGER"); 523 intel_de_write(dev_priv, crt->adpa_reg, save_adpa); 524 } 525 526 /* Check the status to see if both blue and green are on now */ 527 adpa = intel_de_read(dev_priv, crt->adpa_reg); 528 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 529 ret = true; 530 else 531 ret = false; 532 533 drm_dbg_kms(&dev_priv->drm, 534 "valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); 535 536 if (reenable_hpd) 537 intel_hpd_enable(dev_priv, crt->base.hpd_pin); 538 539 return ret; 540 } 541 542 static bool intel_crt_detect_hotplug(struct drm_connector *connector) 543 { 544 struct drm_device *dev = connector->dev; 545 struct drm_i915_private *dev_priv = to_i915(dev); 546 u32 stat; 547 bool ret = false; 548 int i, tries = 0; 549 550 if (HAS_PCH_SPLIT(dev_priv)) 551 return ilk_crt_detect_hotplug(connector); 552 553 if (IS_VALLEYVIEW(dev_priv)) 554 return valleyview_crt_detect_hotplug(connector); 555 556 /* 557 * On 4 series desktop, CRT detect sequence need to be done twice 558 * to get a reliable result. 559 */ 560 561 if (IS_G45(dev_priv)) 562 tries = 2; 563 else 564 tries = 1; 565 566 for (i = 0; i < tries ; i++) { 567 /* turn on the FORCE_DETECT */ 568 i915_hotplug_interrupt_update(dev_priv, 569 CRT_HOTPLUG_FORCE_DETECT, 570 CRT_HOTPLUG_FORCE_DETECT); 571 /* wait for FORCE_DETECT to go off */ 572 if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN, 573 CRT_HOTPLUG_FORCE_DETECT, 1000)) 574 drm_dbg_kms(&dev_priv->drm, 575 "timed out waiting for FORCE_DETECT to go off"); 576 } 577 578 stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT); 579 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) 580 ret = true; 581 582 /* clear the interrupt we just generated, if any */ 583 intel_de_write(dev_priv, PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); 584 585 i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); 586 587 return ret; 588 } 589 590 static struct edid *intel_crt_get_edid(struct drm_connector *connector, 591 struct i2c_adapter *i2c) 592 { 593 struct edid *edid; 594 595 edid = drm_get_edid(connector, i2c); 596 597 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 598 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); 599 intel_gmbus_force_bit(i2c, true); 600 edid = drm_get_edid(connector, i2c); 601 intel_gmbus_force_bit(i2c, false); 602 } 603 604 return edid; 605 } 606 607 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ 608 static int intel_crt_ddc_get_modes(struct drm_connector *connector, 609 struct i2c_adapter *adapter) 610 { 611 struct edid *edid; 612 int ret; 613 614 edid = intel_crt_get_edid(connector, adapter); 615 if (!edid) 616 return 0; 617 618 ret = intel_connector_update_modes(connector, edid); 619 kfree(edid); 620 621 return ret; 622 } 623 624 static bool intel_crt_detect_ddc(struct drm_connector *connector) 625 { 626 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 627 struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev); 628 struct edid *edid; 629 struct i2c_adapter *i2c; 630 bool ret = false; 631 632 BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); 633 634 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 635 edid = intel_crt_get_edid(connector, i2c); 636 637 if (edid) { 638 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; 639 640 /* 641 * This may be a DVI-I connector with a shared DDC 642 * link between analog and digital outputs, so we 643 * have to check the EDID input spec of the attached device. 644 */ 645 if (!is_digital) { 646 drm_dbg_kms(&dev_priv->drm, 647 "CRT detected via DDC:0x50 [EDID]\n"); 648 ret = true; 649 } else { 650 drm_dbg_kms(&dev_priv->drm, 651 "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); 652 } 653 } else { 654 drm_dbg_kms(&dev_priv->drm, 655 "CRT not detected via DDC:0x50 [no valid EDID found]\n"); 656 } 657 658 kfree(edid); 659 660 return ret; 661 } 662 663 static enum drm_connector_status 664 intel_crt_load_detect(struct intel_crt *crt, u32 pipe) 665 { 666 struct drm_device *dev = crt->base.base.dev; 667 struct drm_i915_private *dev_priv = to_i915(dev); 668 struct intel_uncore *uncore = &dev_priv->uncore; 669 u32 save_bclrpat; 670 u32 save_vtotal; 671 u32 vtotal, vactive; 672 u32 vsample; 673 u32 vblank, vblank_start, vblank_end; 674 u32 dsl; 675 i915_reg_t bclrpat_reg, vtotal_reg, 676 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg; 677 u8 st00; 678 enum drm_connector_status status; 679 680 drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n"); 681 682 bclrpat_reg = BCLRPAT(pipe); 683 vtotal_reg = VTOTAL(pipe); 684 vblank_reg = VBLANK(pipe); 685 vsync_reg = VSYNC(pipe); 686 pipeconf_reg = PIPECONF(pipe); 687 pipe_dsl_reg = PIPEDSL(pipe); 688 689 save_bclrpat = intel_uncore_read(uncore, bclrpat_reg); 690 save_vtotal = intel_uncore_read(uncore, vtotal_reg); 691 vblank = intel_uncore_read(uncore, vblank_reg); 692 693 vtotal = ((save_vtotal >> 16) & 0xfff) + 1; 694 vactive = (save_vtotal & 0x7ff) + 1; 695 696 vblank_start = (vblank & 0xfff) + 1; 697 vblank_end = ((vblank >> 16) & 0xfff) + 1; 698 699 /* Set the border color to purple. */ 700 intel_uncore_write(uncore, bclrpat_reg, 0x500050); 701 702 if (!IS_GEN(dev_priv, 2)) { 703 u32 pipeconf = intel_uncore_read(uncore, pipeconf_reg); 704 intel_uncore_write(uncore, 705 pipeconf_reg, 706 pipeconf | PIPECONF_FORCE_BORDER); 707 intel_uncore_posting_read(uncore, pipeconf_reg); 708 /* Wait for next Vblank to substitue 709 * border color for Color info */ 710 intel_wait_for_vblank(dev_priv, pipe); 711 st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE); 712 status = ((st00 & (1 << 4)) != 0) ? 713 connector_status_connected : 714 connector_status_disconnected; 715 716 intel_uncore_write(uncore, pipeconf_reg, pipeconf); 717 } else { 718 bool restore_vblank = false; 719 int count, detect; 720 721 /* 722 * If there isn't any border, add some. 723 * Yes, this will flicker 724 */ 725 if (vblank_start <= vactive && vblank_end >= vtotal) { 726 u32 vsync = intel_de_read(dev_priv, vsync_reg); 727 u32 vsync_start = (vsync & 0xffff) + 1; 728 729 vblank_start = vsync_start; 730 intel_uncore_write(uncore, 731 vblank_reg, 732 (vblank_start - 1) | 733 ((vblank_end - 1) << 16)); 734 restore_vblank = true; 735 } 736 /* sample in the vertical border, selecting the larger one */ 737 if (vblank_start - vactive >= vtotal - vblank_end) 738 vsample = (vblank_start + vactive) >> 1; 739 else 740 vsample = (vtotal + vblank_end) >> 1; 741 742 /* 743 * Wait for the border to be displayed 744 */ 745 while (intel_uncore_read(uncore, pipe_dsl_reg) >= vactive) 746 ; 747 while ((dsl = intel_uncore_read(uncore, pipe_dsl_reg)) <= 748 vsample) 749 ; 750 /* 751 * Watch ST00 for an entire scanline 752 */ 753 detect = 0; 754 count = 0; 755 do { 756 count++; 757 /* Read the ST00 VGA status register */ 758 st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE); 759 if (st00 & (1 << 4)) 760 detect++; 761 } while ((intel_uncore_read(uncore, pipe_dsl_reg) == dsl)); 762 763 /* restore vblank if necessary */ 764 if (restore_vblank) 765 intel_uncore_write(uncore, vblank_reg, vblank); 766 /* 767 * If more than 3/4 of the scanline detected a monitor, 768 * then it is assumed to be present. This works even on i830, 769 * where there isn't any way to force the border color across 770 * the screen 771 */ 772 status = detect * 4 > count * 3 ? 773 connector_status_connected : 774 connector_status_disconnected; 775 } 776 777 /* Restore previous settings */ 778 intel_uncore_write(uncore, bclrpat_reg, save_bclrpat); 779 780 return status; 781 } 782 783 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id) 784 { 785 DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident); 786 return 1; 787 } 788 789 static const struct dmi_system_id intel_spurious_crt_detect[] = { 790 { 791 .callback = intel_spurious_crt_detect_dmi_callback, 792 .ident = "ACER ZGB", 793 .matches = { 794 DMI_MATCH(DMI_SYS_VENDOR, "ACER"), 795 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), 796 }, 797 }, 798 { 799 .callback = intel_spurious_crt_detect_dmi_callback, 800 .ident = "Intel DZ77BH-55K", 801 .matches = { 802 DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"), 803 DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"), 804 }, 805 }, 806 { } 807 }; 808 809 static int 810 intel_crt_detect(struct drm_connector *connector, 811 struct drm_modeset_acquire_ctx *ctx, 812 bool force) 813 { 814 struct drm_i915_private *dev_priv = to_i915(connector->dev); 815 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 816 struct intel_encoder *intel_encoder = &crt->base; 817 intel_wakeref_t wakeref; 818 int status, ret; 819 struct intel_load_detect_pipe tmp; 820 821 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s] force=%d\n", 822 connector->base.id, connector->name, 823 force); 824 825 if (i915_modparams.load_detect_test) { 826 wakeref = intel_display_power_get(dev_priv, 827 intel_encoder->power_domain); 828 goto load_detect; 829 } 830 831 /* Skip machines without VGA that falsely report hotplug events */ 832 if (dmi_check_system(intel_spurious_crt_detect)) 833 return connector_status_disconnected; 834 835 wakeref = intel_display_power_get(dev_priv, 836 intel_encoder->power_domain); 837 838 if (I915_HAS_HOTPLUG(dev_priv)) { 839 /* We can not rely on the HPD pin always being correctly wired 840 * up, for example many KVM do not pass it through, and so 841 * only trust an assertion that the monitor is connected. 842 */ 843 if (intel_crt_detect_hotplug(connector)) { 844 drm_dbg_kms(&dev_priv->drm, 845 "CRT detected via hotplug\n"); 846 status = connector_status_connected; 847 goto out; 848 } else 849 drm_dbg_kms(&dev_priv->drm, 850 "CRT not detected via hotplug\n"); 851 } 852 853 if (intel_crt_detect_ddc(connector)) { 854 status = connector_status_connected; 855 goto out; 856 } 857 858 /* Load detection is broken on HPD capable machines. Whoever wants a 859 * broken monitor (without edid) to work behind a broken kvm (that fails 860 * to have the right resistors for HP detection) needs to fix this up. 861 * For now just bail out. */ 862 if (I915_HAS_HOTPLUG(dev_priv)) { 863 status = connector_status_disconnected; 864 goto out; 865 } 866 867 load_detect: 868 if (!force) { 869 status = connector->status; 870 goto out; 871 } 872 873 /* for pre-945g platforms use load detect */ 874 ret = intel_get_load_detect_pipe(connector, &tmp, ctx); 875 if (ret > 0) { 876 if (intel_crt_detect_ddc(connector)) 877 status = connector_status_connected; 878 else if (INTEL_GEN(dev_priv) < 4) 879 status = intel_crt_load_detect(crt, 880 to_intel_crtc(connector->state->crtc)->pipe); 881 else if (i915_modparams.load_detect_test) 882 status = connector_status_disconnected; 883 else 884 status = connector_status_unknown; 885 intel_release_load_detect_pipe(connector, &tmp, ctx); 886 } else if (ret == 0) { 887 status = connector_status_unknown; 888 } else { 889 status = ret; 890 } 891 892 out: 893 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 894 895 /* 896 * Make sure the refs for power wells enabled during detect are 897 * dropped to avoid a new detect cycle triggered by HPD polling. 898 */ 899 intel_display_power_flush_work(dev_priv); 900 901 return status; 902 } 903 904 static int intel_crt_get_modes(struct drm_connector *connector) 905 { 906 struct drm_device *dev = connector->dev; 907 struct drm_i915_private *dev_priv = to_i915(dev); 908 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 909 struct intel_encoder *intel_encoder = &crt->base; 910 intel_wakeref_t wakeref; 911 struct i2c_adapter *i2c; 912 int ret; 913 914 wakeref = intel_display_power_get(dev_priv, 915 intel_encoder->power_domain); 916 917 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 918 ret = intel_crt_ddc_get_modes(connector, i2c); 919 if (ret || !IS_G4X(dev_priv)) 920 goto out; 921 922 /* Try to probe digital port for output in DVI-I -> VGA mode. */ 923 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); 924 ret = intel_crt_ddc_get_modes(connector, i2c); 925 926 out: 927 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 928 929 return ret; 930 } 931 932 void intel_crt_reset(struct drm_encoder *encoder) 933 { 934 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 935 struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder)); 936 937 if (INTEL_GEN(dev_priv) >= 5) { 938 u32 adpa; 939 940 adpa = intel_de_read(dev_priv, crt->adpa_reg); 941 adpa &= ~ADPA_CRT_HOTPLUG_MASK; 942 adpa |= ADPA_HOTPLUG_BITS; 943 intel_de_write(dev_priv, crt->adpa_reg, adpa); 944 intel_de_posting_read(dev_priv, crt->adpa_reg); 945 946 drm_dbg_kms(&dev_priv->drm, "crt adpa set to 0x%x\n", adpa); 947 crt->force_hotplug_required = true; 948 } 949 950 } 951 952 /* 953 * Routines for controlling stuff on the analog port 954 */ 955 956 static const struct drm_connector_funcs intel_crt_connector_funcs = { 957 .fill_modes = drm_helper_probe_single_connector_modes, 958 .late_register = intel_connector_register, 959 .early_unregister = intel_connector_unregister, 960 .destroy = intel_connector_destroy, 961 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 962 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 963 }; 964 965 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { 966 .detect_ctx = intel_crt_detect, 967 .mode_valid = intel_crt_mode_valid, 968 .get_modes = intel_crt_get_modes, 969 }; 970 971 static const struct drm_encoder_funcs intel_crt_enc_funcs = { 972 .reset = intel_crt_reset, 973 .destroy = intel_encoder_destroy, 974 }; 975 976 void intel_crt_init(struct drm_i915_private *dev_priv) 977 { 978 struct drm_connector *connector; 979 struct intel_crt *crt; 980 struct intel_connector *intel_connector; 981 i915_reg_t adpa_reg; 982 u32 adpa; 983 984 if (HAS_PCH_SPLIT(dev_priv)) 985 adpa_reg = PCH_ADPA; 986 else if (IS_VALLEYVIEW(dev_priv)) 987 adpa_reg = VLV_ADPA; 988 else 989 adpa_reg = ADPA; 990 991 adpa = intel_de_read(dev_priv, adpa_reg); 992 if ((adpa & ADPA_DAC_ENABLE) == 0) { 993 /* 994 * On some machines (some IVB at least) CRT can be 995 * fused off, but there's no known fuse bit to 996 * indicate that. On these machine the ADPA register 997 * works normally, except the DAC enable bit won't 998 * take. So the only way to tell is attempt to enable 999 * it and see what happens. 1000 */ 1001 intel_de_write(dev_priv, adpa_reg, 1002 adpa | ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); 1003 if ((intel_de_read(dev_priv, adpa_reg) & ADPA_DAC_ENABLE) == 0) 1004 return; 1005 intel_de_write(dev_priv, adpa_reg, adpa); 1006 } 1007 1008 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); 1009 if (!crt) 1010 return; 1011 1012 intel_connector = intel_connector_alloc(); 1013 if (!intel_connector) { 1014 kfree(crt); 1015 return; 1016 } 1017 1018 connector = &intel_connector->base; 1019 crt->connector = intel_connector; 1020 drm_connector_init(&dev_priv->drm, &intel_connector->base, 1021 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); 1022 1023 drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs, 1024 DRM_MODE_ENCODER_DAC, "CRT"); 1025 1026 intel_connector_attach_encoder(intel_connector, &crt->base); 1027 1028 crt->base.type = INTEL_OUTPUT_ANALOG; 1029 crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); 1030 if (IS_I830(dev_priv)) 1031 crt->base.pipe_mask = BIT(PIPE_A); 1032 else 1033 crt->base.pipe_mask = ~0; 1034 1035 if (IS_GEN(dev_priv, 2)) 1036 connector->interlace_allowed = 0; 1037 else 1038 connector->interlace_allowed = 1; 1039 connector->doublescan_allowed = 0; 1040 1041 crt->adpa_reg = adpa_reg; 1042 1043 crt->base.power_domain = POWER_DOMAIN_PORT_CRT; 1044 1045 if (I915_HAS_HOTPLUG(dev_priv) && 1046 !dmi_check_system(intel_spurious_crt_detect)) { 1047 crt->base.hpd_pin = HPD_CRT; 1048 crt->base.hotplug = intel_encoder_hotplug; 1049 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 1050 } else { 1051 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1052 } 1053 1054 if (HAS_DDI(dev_priv)) { 1055 crt->base.port = PORT_E; 1056 crt->base.get_config = hsw_crt_get_config; 1057 crt->base.get_hw_state = intel_ddi_get_hw_state; 1058 crt->base.compute_config = hsw_crt_compute_config; 1059 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt; 1060 crt->base.pre_enable = hsw_pre_enable_crt; 1061 crt->base.enable = hsw_enable_crt; 1062 crt->base.disable = hsw_disable_crt; 1063 crt->base.post_disable = hsw_post_disable_crt; 1064 } else { 1065 if (HAS_PCH_SPLIT(dev_priv)) { 1066 crt->base.compute_config = pch_crt_compute_config; 1067 crt->base.disable = pch_disable_crt; 1068 crt->base.post_disable = pch_post_disable_crt; 1069 } else { 1070 crt->base.compute_config = intel_crt_compute_config; 1071 crt->base.disable = intel_disable_crt; 1072 } 1073 crt->base.port = PORT_NONE; 1074 crt->base.get_config = intel_crt_get_config; 1075 crt->base.get_hw_state = intel_crt_get_hw_state; 1076 crt->base.enable = intel_enable_crt; 1077 } 1078 intel_connector->get_hw_state = intel_connector_get_hw_state; 1079 1080 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); 1081 1082 /* 1083 * TODO: find a proper way to discover whether we need to set the the 1084 * polarity and link reversal bits or not, instead of relying on the 1085 * BIOS. 1086 */ 1087 if (HAS_PCH_LPT(dev_priv)) { 1088 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | 1089 FDI_RX_LINK_REVERSAL_OVERRIDE; 1090 1091 dev_priv->fdi_rx_config = intel_de_read(dev_priv, 1092 FDI_RX_CTL(PIPE_A)) & fdi_config; 1093 } 1094 1095 intel_crt_reset(&crt->base.base); 1096 } 1097