1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2018 Intel Corporation
4  */
5 
6 #include "intel_combo_phy.h"
7 #include "intel_display_types.h"
8 
9 #define for_each_combo_phy(__dev_priv, __phy) \
10 	for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++)	\
11 		for_each_if(intel_phy_is_combo(__dev_priv, __phy))
12 
13 #define for_each_combo_phy_reverse(__dev_priv, __phy) \
14 	for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
15 		for_each_if(intel_phy_is_combo(__dev_priv, __phy))
16 
17 enum {
18 	PROCMON_0_85V_DOT_0,
19 	PROCMON_0_95V_DOT_0,
20 	PROCMON_0_95V_DOT_1,
21 	PROCMON_1_05V_DOT_0,
22 	PROCMON_1_05V_DOT_1,
23 };
24 
25 static const struct cnl_procmon {
26 	u32 dw1, dw9, dw10;
27 } cnl_procmon_values[] = {
28 	[PROCMON_0_85V_DOT_0] =
29 		{ .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
30 	[PROCMON_0_95V_DOT_0] =
31 		{ .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, },
32 	[PROCMON_0_95V_DOT_1] =
33 		{ .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, },
34 	[PROCMON_1_05V_DOT_0] =
35 		{ .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, },
36 	[PROCMON_1_05V_DOT_1] =
37 		{ .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
38 };
39 
40 /*
41  * CNL has just one set of registers, while gen11 has a set for each combo PHY.
42  * The CNL registers are equivalent to the gen11 PHY A registers, that's why we
43  * call the ICL macros even though the function has CNL on its name.
44  */
45 static const struct cnl_procmon *
46 cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
47 {
48 	const struct cnl_procmon *procmon;
49 	u32 val;
50 
51 	val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy));
52 	switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
53 	default:
54 		MISSING_CASE(val);
55 		fallthrough;
56 	case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:
57 		procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0];
58 		break;
59 	case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0:
60 		procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0];
61 		break;
62 	case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1:
63 		procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1];
64 		break;
65 	case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0:
66 		procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0];
67 		break;
68 	case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1:
69 		procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1];
70 		break;
71 	}
72 
73 	return procmon;
74 }
75 
76 static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
77 				       enum phy phy)
78 {
79 	const struct cnl_procmon *procmon;
80 	u32 val;
81 
82 	procmon = cnl_get_procmon_ref_values(dev_priv, phy);
83 
84 	val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy));
85 	val &= ~((0xff << 16) | 0xff);
86 	val |= procmon->dw1;
87 	intel_de_write(dev_priv, ICL_PORT_COMP_DW1(phy), val);
88 
89 	intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9);
90 	intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10);
91 }
92 
93 static bool check_phy_reg(struct drm_i915_private *dev_priv,
94 			  enum phy phy, i915_reg_t reg, u32 mask,
95 			  u32 expected_val)
96 {
97 	u32 val = intel_de_read(dev_priv, reg);
98 
99 	if ((val & mask) != expected_val) {
100 		drm_dbg(&dev_priv->drm,
101 			"Combo PHY %c reg %08x state mismatch: "
102 			"current %08x mask %08x expected %08x\n",
103 			phy_name(phy),
104 			reg.reg, val, mask, expected_val);
105 		return false;
106 	}
107 
108 	return true;
109 }
110 
111 static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
112 					  enum phy phy)
113 {
114 	const struct cnl_procmon *procmon;
115 	bool ret;
116 
117 	procmon = cnl_get_procmon_ref_values(dev_priv, phy);
118 
119 	ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy),
120 			    (0xff << 16) | 0xff, procmon->dw1);
121 	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy),
122 			     -1U, procmon->dw9);
123 	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy),
124 			     -1U, procmon->dw10);
125 
126 	return ret;
127 }
128 
129 static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv)
130 {
131 	return !(intel_de_read(dev_priv, CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) &&
132 		(intel_de_read(dev_priv, CNL_PORT_COMP_DW0) & COMP_INIT);
133 }
134 
135 static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv)
136 {
137 	enum phy phy = PHY_A;
138 	bool ret;
139 
140 	if (!cnl_combo_phy_enabled(dev_priv))
141 		return false;
142 
143 	ret = cnl_verify_procmon_ref_values(dev_priv, phy);
144 
145 	ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5,
146 			     CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
147 
148 	return ret;
149 }
150 
151 static void cnl_combo_phys_init(struct drm_i915_private *dev_priv)
152 {
153 	u32 val;
154 
155 	val = intel_de_read(dev_priv, CHICKEN_MISC_2);
156 	val &= ~CNL_COMP_PWR_DOWN;
157 	intel_de_write(dev_priv, CHICKEN_MISC_2, val);
158 
159 	/* Dummy PORT_A to get the correct CNL register from the ICL macro */
160 	cnl_set_procmon_ref_values(dev_priv, PHY_A);
161 
162 	val = intel_de_read(dev_priv, CNL_PORT_COMP_DW0);
163 	val |= COMP_INIT;
164 	intel_de_write(dev_priv, CNL_PORT_COMP_DW0, val);
165 
166 	val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5);
167 	val |= CL_POWER_DOWN_ENABLE;
168 	intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val);
169 }
170 
171 static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv)
172 {
173 	u32 val;
174 
175 	if (!cnl_combo_phy_verify_state(dev_priv))
176 		drm_warn(&dev_priv->drm,
177 			 "Combo PHY HW state changed unexpectedly.\n");
178 
179 	val = intel_de_read(dev_priv, CHICKEN_MISC_2);
180 	val |= CNL_COMP_PWR_DOWN;
181 	intel_de_write(dev_priv, CHICKEN_MISC_2, val);
182 }
183 
184 static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
185 {
186 	/*
187 	 * Some platforms only expect PHY_MISC to be programmed for PHY-A and
188 	 * PHY-B and may not even have instances of the register for the
189 	 * other combo PHY's.
190 	 *
191 	 * ADL-S technically has three instances of PHY_MISC, but only requires
192 	 * that we program it for PHY A.
193 	 */
194 
195 	if (IS_ALDERLAKE_S(i915))
196 		return phy == PHY_A;
197 	else if (IS_JSL_EHL(i915) ||
198 		 IS_ROCKETLAKE(i915) ||
199 		 IS_DG1(i915))
200 		return phy < PHY_C;
201 
202 	return true;
203 }
204 
205 static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
206 				  enum phy phy)
207 {
208 	/* The PHY C added by EHL has no PHY_MISC register */
209 	if (!has_phy_misc(dev_priv, phy))
210 		return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT;
211 	else
212 		return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) &
213 			 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
214 			(intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT);
215 }
216 
217 static bool ehl_vbt_ddi_d_present(struct drm_i915_private *i915)
218 {
219 	bool ddi_a_present = intel_bios_is_port_present(i915, PORT_A);
220 	bool ddi_d_present = intel_bios_is_port_present(i915, PORT_D);
221 	bool dsi_present = intel_bios_is_dsi_present(i915, NULL);
222 
223 	/*
224 	 * VBT's 'dvo port' field for child devices references the DDI, not
225 	 * the PHY.  So if combo PHY A is wired up to drive an external
226 	 * display, we should see a child device present on PORT_D and
227 	 * nothing on PORT_A and no DSI.
228 	 */
229 	if (ddi_d_present && !ddi_a_present && !dsi_present)
230 		return true;
231 
232 	/*
233 	 * If we encounter a VBT that claims to have an external display on
234 	 * DDI-D _and_ an internal display on DDI-A/DSI leave an error message
235 	 * in the log and let the internal display win.
236 	 */
237 	if (ddi_d_present)
238 		drm_err(&i915->drm,
239 			"VBT claims to have both internal and external displays on PHY A.  Configuring for internal.\n");
240 
241 	return false;
242 }
243 
244 static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)
245 {
246 	/*
247 	 * Certain PHYs are connected to compensation resistors and act
248 	 * as masters to other PHYs.
249 	 *
250 	 * ICL,TGL:
251 	 *   A(master) -> B(slave), C(slave)
252 	 * RKL,DG1:
253 	 *   A(master) -> B(slave)
254 	 *   C(master) -> D(slave)
255 	 * ADL-S:
256 	 *   A(master) -> B(slave), C(slave)
257 	 *   D(master) -> E(slave)
258 	 *
259 	 * We must set the IREFGEN bit for any PHY acting as a master
260 	 * to another PHY.
261 	 */
262 	if (phy == PHY_A)
263 		return true;
264 	else if (IS_ALDERLAKE_S(dev_priv))
265 		return phy == PHY_D;
266 	else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
267 		return phy == PHY_C;
268 
269 	return false;
270 }
271 
272 static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
273 				       enum phy phy)
274 {
275 	bool ret = true;
276 	u32 expected_val = 0;
277 
278 	if (!icl_combo_phy_enabled(dev_priv, phy))
279 		return false;
280 
281 	if (DISPLAY_VER(dev_priv) >= 12) {
282 		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN0(phy),
283 				     ICL_PORT_TX_DW8_ODCC_CLK_SEL |
284 				     ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK,
285 				     ICL_PORT_TX_DW8_ODCC_CLK_SEL |
286 				     ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2);
287 
288 		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN0(phy),
289 				     DCC_MODE_SELECT_MASK,
290 				     DCC_MODE_SELECT_CONTINUOSLY);
291 	}
292 
293 	ret &= cnl_verify_procmon_ref_values(dev_priv, phy);
294 
295 	if (phy_is_master(dev_priv, phy)) {
296 		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
297 				     IREFGEN, IREFGEN);
298 
299 		if (IS_JSL_EHL(dev_priv)) {
300 			if (ehl_vbt_ddi_d_present(dev_priv))
301 				expected_val = ICL_PHY_MISC_MUX_DDID;
302 
303 			ret &= check_phy_reg(dev_priv, phy, ICL_PHY_MISC(phy),
304 					     ICL_PHY_MISC_MUX_DDID,
305 					     expected_val);
306 		}
307 	}
308 
309 	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy),
310 			     CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
311 
312 	return ret;
313 }
314 
315 void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
316 				    enum phy phy, bool is_dsi,
317 				    int lane_count, bool lane_reversal)
318 {
319 	u8 lane_mask;
320 	u32 val;
321 
322 	if (is_dsi) {
323 		drm_WARN_ON(&dev_priv->drm, lane_reversal);
324 
325 		switch (lane_count) {
326 		case 1:
327 			lane_mask = PWR_DOWN_LN_3_1_0;
328 			break;
329 		case 2:
330 			lane_mask = PWR_DOWN_LN_3_1;
331 			break;
332 		case 3:
333 			lane_mask = PWR_DOWN_LN_3;
334 			break;
335 		default:
336 			MISSING_CASE(lane_count);
337 			fallthrough;
338 		case 4:
339 			lane_mask = PWR_UP_ALL_LANES;
340 			break;
341 		}
342 	} else {
343 		switch (lane_count) {
344 		case 1:
345 			lane_mask = lane_reversal ? PWR_DOWN_LN_2_1_0 :
346 						    PWR_DOWN_LN_3_2_1;
347 			break;
348 		case 2:
349 			lane_mask = lane_reversal ? PWR_DOWN_LN_1_0 :
350 						    PWR_DOWN_LN_3_2;
351 			break;
352 		default:
353 			MISSING_CASE(lane_count);
354 			fallthrough;
355 		case 4:
356 			lane_mask = PWR_UP_ALL_LANES;
357 			break;
358 		}
359 	}
360 
361 	val = intel_de_read(dev_priv, ICL_PORT_CL_DW10(phy));
362 	val &= ~PWR_DOWN_LN_MASK;
363 	val |= lane_mask << PWR_DOWN_LN_SHIFT;
364 	intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val);
365 }
366 
367 static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
368 {
369 	enum phy phy;
370 
371 	for_each_combo_phy(dev_priv, phy) {
372 		u32 val;
373 
374 		if (icl_combo_phy_verify_state(dev_priv, phy)) {
375 			drm_dbg(&dev_priv->drm,
376 				"Combo PHY %c already enabled, won't reprogram it.\n",
377 				phy_name(phy));
378 			continue;
379 		}
380 
381 		if (!has_phy_misc(dev_priv, phy))
382 			goto skip_phy_misc;
383 
384 		/*
385 		 * EHL's combo PHY A can be hooked up to either an external
386 		 * display (via DDI-D) or an internal display (via DDI-A or
387 		 * the DSI DPHY).  This is a motherboard design decision that
388 		 * can't be changed on the fly, so initialize the PHY's mux
389 		 * based on whether our VBT indicates the presence of any
390 		 * "internal" child devices.
391 		 */
392 		val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
393 		if (IS_JSL_EHL(dev_priv) && phy == PHY_A) {
394 			val &= ~ICL_PHY_MISC_MUX_DDID;
395 
396 			if (ehl_vbt_ddi_d_present(dev_priv))
397 				val |= ICL_PHY_MISC_MUX_DDID;
398 		}
399 
400 		val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
401 		intel_de_write(dev_priv, ICL_PHY_MISC(phy), val);
402 
403 skip_phy_misc:
404 		if (DISPLAY_VER(dev_priv) >= 12) {
405 			val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN0(phy));
406 			val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK;
407 			val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL;
408 			val |= ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2;
409 			intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val);
410 
411 			val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
412 			val &= ~DCC_MODE_SELECT_MASK;
413 			val |= DCC_MODE_SELECT_CONTINUOSLY;
414 			intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
415 		}
416 
417 		cnl_set_procmon_ref_values(dev_priv, phy);
418 
419 		if (phy_is_master(dev_priv, phy)) {
420 			val = intel_de_read(dev_priv, ICL_PORT_COMP_DW8(phy));
421 			val |= IREFGEN;
422 			intel_de_write(dev_priv, ICL_PORT_COMP_DW8(phy), val);
423 		}
424 
425 		val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy));
426 		val |= COMP_INIT;
427 		intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val);
428 
429 		val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
430 		val |= CL_POWER_DOWN_ENABLE;
431 		intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
432 	}
433 }
434 
435 static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
436 {
437 	enum phy phy;
438 
439 	for_each_combo_phy_reverse(dev_priv, phy) {
440 		u32 val;
441 
442 		if (phy == PHY_A &&
443 		    !icl_combo_phy_verify_state(dev_priv, phy)) {
444 			if (IS_TIGERLAKE(dev_priv) || IS_DG1(dev_priv)) {
445 				/*
446 				 * A known problem with old ifwi:
447 				 * https://gitlab.freedesktop.org/drm/intel/-/issues/2411
448 				 * Suppress the warning for CI. Remove ASAP!
449 				 */
450 				drm_dbg_kms(&dev_priv->drm,
451 					    "Combo PHY %c HW state changed unexpectedly\n",
452 					    phy_name(phy));
453 			} else {
454 				drm_warn(&dev_priv->drm,
455 					 "Combo PHY %c HW state changed unexpectedly\n",
456 					 phy_name(phy));
457 			}
458 		}
459 
460 		if (!has_phy_misc(dev_priv, phy))
461 			goto skip_phy_misc;
462 
463 		val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
464 		val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
465 		intel_de_write(dev_priv, ICL_PHY_MISC(phy), val);
466 
467 skip_phy_misc:
468 		val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy));
469 		val &= ~COMP_INIT;
470 		intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val);
471 	}
472 }
473 
474 void intel_combo_phy_init(struct drm_i915_private *i915)
475 {
476 	if (DISPLAY_VER(i915) >= 11)
477 		icl_combo_phys_init(i915);
478 	else if (IS_CANNONLAKE(i915))
479 		cnl_combo_phys_init(i915);
480 }
481 
482 void intel_combo_phy_uninit(struct drm_i915_private *i915)
483 {
484 	if (DISPLAY_VER(i915) >= 11)
485 		icl_combo_phys_uninit(i915);
486 	else if (IS_CANNONLAKE(i915))
487 		cnl_combo_phys_uninit(i915);
488 }
489