1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2018 Intel Corporation 4 */ 5 6 #include "intel_combo_phy.h" 7 #include "intel_combo_phy_regs.h" 8 #include "intel_de.h" 9 #include "intel_display_types.h" 10 11 #define for_each_combo_phy(__dev_priv, __phy) \ 12 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ 13 for_each_if(intel_phy_is_combo(__dev_priv, __phy)) 14 15 #define for_each_combo_phy_reverse(__dev_priv, __phy) \ 16 for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \ 17 for_each_if(intel_phy_is_combo(__dev_priv, __phy)) 18 19 enum { 20 PROCMON_0_85V_DOT_0, 21 PROCMON_0_95V_DOT_0, 22 PROCMON_0_95V_DOT_1, 23 PROCMON_1_05V_DOT_0, 24 PROCMON_1_05V_DOT_1, 25 }; 26 27 static const struct icl_procmon { 28 const char *name; 29 u32 dw1, dw9, dw10; 30 } icl_procmon_values[] = { 31 [PROCMON_0_85V_DOT_0] = { 32 .name = "0.85V dot0 (low-voltage)", 33 .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, 34 }, 35 [PROCMON_0_95V_DOT_0] = { 36 .name = "0.95V dot0", 37 .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, 38 }, 39 [PROCMON_0_95V_DOT_1] = { 40 .name = "0.95V dot1", 41 .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, 42 }, 43 [PROCMON_1_05V_DOT_0] = { 44 .name = "1.05V dot0", 45 .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, 46 }, 47 [PROCMON_1_05V_DOT_1] = { 48 .name = "1.05V dot1", 49 .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, 50 }, 51 }; 52 53 static const struct icl_procmon * 54 icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) 55 { 56 u32 val; 57 58 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); 59 switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) { 60 default: 61 MISSING_CASE(val); 62 fallthrough; 63 case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0: 64 return &icl_procmon_values[PROCMON_0_85V_DOT_0]; 65 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0: 66 return &icl_procmon_values[PROCMON_0_95V_DOT_0]; 67 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1: 68 return &icl_procmon_values[PROCMON_0_95V_DOT_1]; 69 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0: 70 return &icl_procmon_values[PROCMON_1_05V_DOT_0]; 71 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1: 72 return &icl_procmon_values[PROCMON_1_05V_DOT_1]; 73 } 74 } 75 76 static void icl_set_procmon_ref_values(struct drm_i915_private *dev_priv, 77 enum phy phy) 78 { 79 const struct icl_procmon *procmon; 80 u32 val; 81 82 procmon = icl_get_procmon_ref_values(dev_priv, phy); 83 84 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy)); 85 val &= ~((0xff << 16) | 0xff); 86 val |= procmon->dw1; 87 intel_de_write(dev_priv, ICL_PORT_COMP_DW1(phy), val); 88 89 intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9); 90 intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10); 91 } 92 93 static bool check_phy_reg(struct drm_i915_private *dev_priv, 94 enum phy phy, i915_reg_t reg, u32 mask, 95 u32 expected_val) 96 { 97 u32 val = intel_de_read(dev_priv, reg); 98 99 if ((val & mask) != expected_val) { 100 drm_dbg(&dev_priv->drm, 101 "Combo PHY %c reg %08x state mismatch: " 102 "current %08x mask %08x expected %08x\n", 103 phy_name(phy), 104 reg.reg, val, mask, expected_val); 105 return false; 106 } 107 108 return true; 109 } 110 111 static bool icl_verify_procmon_ref_values(struct drm_i915_private *dev_priv, 112 enum phy phy) 113 { 114 const struct icl_procmon *procmon; 115 bool ret; 116 117 procmon = icl_get_procmon_ref_values(dev_priv, phy); 118 119 drm_dbg_kms(&dev_priv->drm, 120 "Combo PHY %c Voltage/Process Info : %s\n", 121 phy_name(phy), procmon->name); 122 123 ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy), 124 (0xff << 16) | 0xff, procmon->dw1); 125 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy), 126 -1U, procmon->dw9); 127 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy), 128 -1U, procmon->dw10); 129 130 return ret; 131 } 132 133 static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy) 134 { 135 /* 136 * Some platforms only expect PHY_MISC to be programmed for PHY-A and 137 * PHY-B and may not even have instances of the register for the 138 * other combo PHY's. 139 * 140 * ADL-S technically has three instances of PHY_MISC, but only requires 141 * that we program it for PHY A. 142 */ 143 144 if (IS_ALDERLAKE_S(i915)) 145 return phy == PHY_A; 146 else if (IS_JSL_EHL(i915) || 147 IS_ROCKETLAKE(i915) || 148 IS_DG1(i915)) 149 return phy < PHY_C; 150 151 return true; 152 } 153 154 static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv, 155 enum phy phy) 156 { 157 /* The PHY C added by EHL has no PHY_MISC register */ 158 if (!has_phy_misc(dev_priv, phy)) 159 return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT; 160 else 161 return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) & 162 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) && 163 (intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT); 164 } 165 166 static bool ehl_vbt_ddi_d_present(struct drm_i915_private *i915) 167 { 168 bool ddi_a_present = intel_bios_is_port_present(i915, PORT_A); 169 bool ddi_d_present = intel_bios_is_port_present(i915, PORT_D); 170 bool dsi_present = intel_bios_is_dsi_present(i915, NULL); 171 172 /* 173 * VBT's 'dvo port' field for child devices references the DDI, not 174 * the PHY. So if combo PHY A is wired up to drive an external 175 * display, we should see a child device present on PORT_D and 176 * nothing on PORT_A and no DSI. 177 */ 178 if (ddi_d_present && !ddi_a_present && !dsi_present) 179 return true; 180 181 /* 182 * If we encounter a VBT that claims to have an external display on 183 * DDI-D _and_ an internal display on DDI-A/DSI leave an error message 184 * in the log and let the internal display win. 185 */ 186 if (ddi_d_present) 187 drm_err(&i915->drm, 188 "VBT claims to have both internal and external displays on PHY A. Configuring for internal.\n"); 189 190 return false; 191 } 192 193 static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy) 194 { 195 /* 196 * Certain PHYs are connected to compensation resistors and act 197 * as masters to other PHYs. 198 * 199 * ICL,TGL: 200 * A(master) -> B(slave), C(slave) 201 * RKL,DG1: 202 * A(master) -> B(slave) 203 * C(master) -> D(slave) 204 * ADL-S: 205 * A(master) -> B(slave), C(slave) 206 * D(master) -> E(slave) 207 * 208 * We must set the IREFGEN bit for any PHY acting as a master 209 * to another PHY. 210 */ 211 if (phy == PHY_A) 212 return true; 213 else if (IS_ALDERLAKE_S(dev_priv)) 214 return phy == PHY_D; 215 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 216 return phy == PHY_C; 217 218 return false; 219 } 220 221 static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, 222 enum phy phy) 223 { 224 bool ret = true; 225 u32 expected_val = 0; 226 227 if (!icl_combo_phy_enabled(dev_priv, phy)) 228 return false; 229 230 if (DISPLAY_VER(dev_priv) >= 12) { 231 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN(0, phy), 232 ICL_PORT_TX_DW8_ODCC_CLK_SEL | 233 ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 234 ICL_PORT_TX_DW8_ODCC_CLK_SEL | 235 ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2); 236 237 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy), 238 DCC_MODE_SELECT_MASK, 239 DCC_MODE_SELECT_CONTINUOSLY); 240 } 241 242 ret &= icl_verify_procmon_ref_values(dev_priv, phy); 243 244 if (phy_is_master(dev_priv, phy)) { 245 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy), 246 IREFGEN, IREFGEN); 247 248 if (IS_JSL_EHL(dev_priv)) { 249 if (ehl_vbt_ddi_d_present(dev_priv)) 250 expected_val = ICL_PHY_MISC_MUX_DDID; 251 252 ret &= check_phy_reg(dev_priv, phy, ICL_PHY_MISC(phy), 253 ICL_PHY_MISC_MUX_DDID, 254 expected_val); 255 } 256 } 257 258 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy), 259 CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE); 260 261 return ret; 262 } 263 264 void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, 265 enum phy phy, bool is_dsi, 266 int lane_count, bool lane_reversal) 267 { 268 u8 lane_mask; 269 u32 val; 270 271 if (is_dsi) { 272 drm_WARN_ON(&dev_priv->drm, lane_reversal); 273 274 switch (lane_count) { 275 case 1: 276 lane_mask = PWR_DOWN_LN_3_1_0; 277 break; 278 case 2: 279 lane_mask = PWR_DOWN_LN_3_1; 280 break; 281 case 3: 282 lane_mask = PWR_DOWN_LN_3; 283 break; 284 default: 285 MISSING_CASE(lane_count); 286 fallthrough; 287 case 4: 288 lane_mask = PWR_UP_ALL_LANES; 289 break; 290 } 291 } else { 292 switch (lane_count) { 293 case 1: 294 lane_mask = lane_reversal ? PWR_DOWN_LN_2_1_0 : 295 PWR_DOWN_LN_3_2_1; 296 break; 297 case 2: 298 lane_mask = lane_reversal ? PWR_DOWN_LN_1_0 : 299 PWR_DOWN_LN_3_2; 300 break; 301 default: 302 MISSING_CASE(lane_count); 303 fallthrough; 304 case 4: 305 lane_mask = PWR_UP_ALL_LANES; 306 break; 307 } 308 } 309 310 val = intel_de_read(dev_priv, ICL_PORT_CL_DW10(phy)); 311 val &= ~PWR_DOWN_LN_MASK; 312 val |= lane_mask; 313 intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val); 314 } 315 316 static void icl_combo_phys_init(struct drm_i915_private *dev_priv) 317 { 318 enum phy phy; 319 320 for_each_combo_phy(dev_priv, phy) { 321 u32 val; 322 323 if (icl_combo_phy_verify_state(dev_priv, phy)) { 324 drm_dbg(&dev_priv->drm, 325 "Combo PHY %c already enabled, won't reprogram it.\n", 326 phy_name(phy)); 327 continue; 328 } 329 330 if (!has_phy_misc(dev_priv, phy)) 331 goto skip_phy_misc; 332 333 /* 334 * EHL's combo PHY A can be hooked up to either an external 335 * display (via DDI-D) or an internal display (via DDI-A or 336 * the DSI DPHY). This is a motherboard design decision that 337 * can't be changed on the fly, so initialize the PHY's mux 338 * based on whether our VBT indicates the presence of any 339 * "internal" child devices. 340 */ 341 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); 342 if (IS_JSL_EHL(dev_priv) && phy == PHY_A) { 343 val &= ~ICL_PHY_MISC_MUX_DDID; 344 345 if (ehl_vbt_ddi_d_present(dev_priv)) 346 val |= ICL_PHY_MISC_MUX_DDID; 347 } 348 349 val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; 350 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); 351 352 skip_phy_misc: 353 if (DISPLAY_VER(dev_priv) >= 12) { 354 val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN(0, phy)); 355 val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK; 356 val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL; 357 val |= ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2; 358 intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val); 359 360 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 361 val &= ~DCC_MODE_SELECT_MASK; 362 val |= DCC_MODE_SELECT_CONTINUOSLY; 363 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 364 } 365 366 icl_set_procmon_ref_values(dev_priv, phy); 367 368 if (phy_is_master(dev_priv, phy)) { 369 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW8(phy)); 370 val |= IREFGEN; 371 intel_de_write(dev_priv, ICL_PORT_COMP_DW8(phy), val); 372 } 373 374 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)); 375 val |= COMP_INIT; 376 intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val); 377 378 val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 379 val |= CL_POWER_DOWN_ENABLE; 380 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); 381 } 382 } 383 384 static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv) 385 { 386 enum phy phy; 387 388 for_each_combo_phy_reverse(dev_priv, phy) { 389 u32 val; 390 391 if (phy == PHY_A && 392 !icl_combo_phy_verify_state(dev_priv, phy)) { 393 if (IS_TIGERLAKE(dev_priv) || IS_DG1(dev_priv)) { 394 /* 395 * A known problem with old ifwi: 396 * https://gitlab.freedesktop.org/drm/intel/-/issues/2411 397 * Suppress the warning for CI. Remove ASAP! 398 */ 399 drm_dbg_kms(&dev_priv->drm, 400 "Combo PHY %c HW state changed unexpectedly\n", 401 phy_name(phy)); 402 } else { 403 drm_warn(&dev_priv->drm, 404 "Combo PHY %c HW state changed unexpectedly\n", 405 phy_name(phy)); 406 } 407 } 408 409 if (!has_phy_misc(dev_priv, phy)) 410 goto skip_phy_misc; 411 412 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); 413 val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; 414 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); 415 416 skip_phy_misc: 417 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)); 418 val &= ~COMP_INIT; 419 intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val); 420 } 421 } 422 423 void intel_combo_phy_init(struct drm_i915_private *i915) 424 { 425 icl_combo_phys_init(i915); 426 } 427 428 void intel_combo_phy_uninit(struct drm_i915_private *i915) 429 { 430 icl_combo_phys_uninit(i915); 431 } 432