1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2018 Intel Corporation 4 */ 5 6 #include "intel_combo_phy.h" 7 #include "intel_display_types.h" 8 9 #define for_each_combo_phy(__dev_priv, __phy) \ 10 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ 11 for_each_if(intel_phy_is_combo(__dev_priv, __phy)) 12 13 #define for_each_combo_phy_reverse(__dev_priv, __phy) \ 14 for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \ 15 for_each_if(intel_phy_is_combo(__dev_priv, __phy)) 16 17 enum { 18 PROCMON_0_85V_DOT_0, 19 PROCMON_0_95V_DOT_0, 20 PROCMON_0_95V_DOT_1, 21 PROCMON_1_05V_DOT_0, 22 PROCMON_1_05V_DOT_1, 23 }; 24 25 static const struct cnl_procmon { 26 u32 dw1, dw9, dw10; 27 } cnl_procmon_values[] = { 28 [PROCMON_0_85V_DOT_0] = 29 { .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, }, 30 [PROCMON_0_95V_DOT_0] = 31 { .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, }, 32 [PROCMON_0_95V_DOT_1] = 33 { .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, }, 34 [PROCMON_1_05V_DOT_0] = 35 { .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, }, 36 [PROCMON_1_05V_DOT_1] = 37 { .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, }, 38 }; 39 40 /* 41 * CNL has just one set of registers, while gen11 has a set for each combo PHY. 42 * The CNL registers are equivalent to the gen11 PHY A registers, that's why we 43 * call the ICL macros even though the function has CNL on its name. 44 */ 45 static const struct cnl_procmon * 46 cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) 47 { 48 const struct cnl_procmon *procmon; 49 u32 val; 50 51 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); 52 switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) { 53 default: 54 MISSING_CASE(val); 55 /* fall through */ 56 case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0: 57 procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0]; 58 break; 59 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0: 60 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0]; 61 break; 62 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1: 63 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1]; 64 break; 65 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0: 66 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0]; 67 break; 68 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1: 69 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1]; 70 break; 71 } 72 73 return procmon; 74 } 75 76 static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv, 77 enum phy phy) 78 { 79 const struct cnl_procmon *procmon; 80 u32 val; 81 82 procmon = cnl_get_procmon_ref_values(dev_priv, phy); 83 84 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy)); 85 val &= ~((0xff << 16) | 0xff); 86 val |= procmon->dw1; 87 intel_de_write(dev_priv, ICL_PORT_COMP_DW1(phy), val); 88 89 intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9); 90 intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10); 91 } 92 93 static bool check_phy_reg(struct drm_i915_private *dev_priv, 94 enum phy phy, i915_reg_t reg, u32 mask, 95 u32 expected_val) 96 { 97 u32 val = intel_de_read(dev_priv, reg); 98 99 if ((val & mask) != expected_val) { 100 drm_dbg(&dev_priv->drm, 101 "Combo PHY %c reg %08x state mismatch: " 102 "current %08x mask %08x expected %08x\n", 103 phy_name(phy), 104 reg.reg, val, mask, expected_val); 105 return false; 106 } 107 108 return true; 109 } 110 111 static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv, 112 enum phy phy) 113 { 114 const struct cnl_procmon *procmon; 115 bool ret; 116 117 procmon = cnl_get_procmon_ref_values(dev_priv, phy); 118 119 ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy), 120 (0xff << 16) | 0xff, procmon->dw1); 121 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy), 122 -1U, procmon->dw9); 123 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy), 124 -1U, procmon->dw10); 125 126 return ret; 127 } 128 129 static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv) 130 { 131 return !(intel_de_read(dev_priv, CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) && 132 (intel_de_read(dev_priv, CNL_PORT_COMP_DW0) & COMP_INIT); 133 } 134 135 static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv) 136 { 137 enum phy phy = PHY_A; 138 bool ret; 139 140 if (!cnl_combo_phy_enabled(dev_priv)) 141 return false; 142 143 ret = cnl_verify_procmon_ref_values(dev_priv, phy); 144 145 ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5, 146 CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE); 147 148 return ret; 149 } 150 151 static void cnl_combo_phys_init(struct drm_i915_private *dev_priv) 152 { 153 u32 val; 154 155 val = intel_de_read(dev_priv, CHICKEN_MISC_2); 156 val &= ~CNL_COMP_PWR_DOWN; 157 intel_de_write(dev_priv, CHICKEN_MISC_2, val); 158 159 /* Dummy PORT_A to get the correct CNL register from the ICL macro */ 160 cnl_set_procmon_ref_values(dev_priv, PHY_A); 161 162 val = intel_de_read(dev_priv, CNL_PORT_COMP_DW0); 163 val |= COMP_INIT; 164 intel_de_write(dev_priv, CNL_PORT_COMP_DW0, val); 165 166 val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5); 167 val |= CL_POWER_DOWN_ENABLE; 168 intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val); 169 } 170 171 static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv) 172 { 173 u32 val; 174 175 if (!cnl_combo_phy_verify_state(dev_priv)) 176 drm_warn(&dev_priv->drm, 177 "Combo PHY HW state changed unexpectedly.\n"); 178 179 val = intel_de_read(dev_priv, CHICKEN_MISC_2); 180 val |= CNL_COMP_PWR_DOWN; 181 intel_de_write(dev_priv, CHICKEN_MISC_2, val); 182 } 183 184 static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy) 185 { 186 /* 187 * Some platforms only expect PHY_MISC to be programmed for PHY-A and 188 * PHY-B and may not even have instances of the register for the 189 * other combo PHY's. 190 */ 191 if (IS_ELKHARTLAKE(i915) || 192 IS_ROCKETLAKE(i915)) 193 return phy < PHY_C; 194 195 return true; 196 } 197 198 static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv, 199 enum phy phy) 200 { 201 /* The PHY C added by EHL has no PHY_MISC register */ 202 if (!has_phy_misc(dev_priv, phy)) 203 return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT; 204 else 205 return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) & 206 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) && 207 (intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT); 208 } 209 210 static bool ehl_vbt_ddi_d_present(struct drm_i915_private *i915) 211 { 212 bool ddi_a_present = intel_bios_is_port_present(i915, PORT_A); 213 bool ddi_d_present = intel_bios_is_port_present(i915, PORT_D); 214 bool dsi_present = intel_bios_is_dsi_present(i915, NULL); 215 216 /* 217 * VBT's 'dvo port' field for child devices references the DDI, not 218 * the PHY. So if combo PHY A is wired up to drive an external 219 * display, we should see a child device present on PORT_D and 220 * nothing on PORT_A and no DSI. 221 */ 222 if (ddi_d_present && !ddi_a_present && !dsi_present) 223 return true; 224 225 /* 226 * If we encounter a VBT that claims to have an external display on 227 * DDI-D _and_ an internal display on DDI-A/DSI leave an error message 228 * in the log and let the internal display win. 229 */ 230 if (ddi_d_present) 231 drm_err(&i915->drm, 232 "VBT claims to have both internal and external displays on PHY A. Configuring for internal.\n"); 233 234 return false; 235 } 236 237 static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, 238 enum phy phy) 239 { 240 bool ret; 241 u32 expected_val = 0; 242 243 if (!icl_combo_phy_enabled(dev_priv, phy)) 244 return false; 245 246 ret = cnl_verify_procmon_ref_values(dev_priv, phy); 247 248 if (phy == PHY_A) { 249 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy), 250 IREFGEN, IREFGEN); 251 252 if (IS_ELKHARTLAKE(dev_priv)) { 253 if (ehl_vbt_ddi_d_present(dev_priv)) 254 expected_val = ICL_PHY_MISC_MUX_DDID; 255 256 ret &= check_phy_reg(dev_priv, phy, ICL_PHY_MISC(phy), 257 ICL_PHY_MISC_MUX_DDID, 258 expected_val); 259 } 260 } 261 262 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy), 263 CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE); 264 265 return ret; 266 } 267 268 void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, 269 enum phy phy, bool is_dsi, 270 int lane_count, bool lane_reversal) 271 { 272 u8 lane_mask; 273 u32 val; 274 275 if (is_dsi) { 276 drm_WARN_ON(&dev_priv->drm, lane_reversal); 277 278 switch (lane_count) { 279 case 1: 280 lane_mask = PWR_DOWN_LN_3_1_0; 281 break; 282 case 2: 283 lane_mask = PWR_DOWN_LN_3_1; 284 break; 285 case 3: 286 lane_mask = PWR_DOWN_LN_3; 287 break; 288 default: 289 MISSING_CASE(lane_count); 290 /* fall-through */ 291 case 4: 292 lane_mask = PWR_UP_ALL_LANES; 293 break; 294 } 295 } else { 296 switch (lane_count) { 297 case 1: 298 lane_mask = lane_reversal ? PWR_DOWN_LN_2_1_0 : 299 PWR_DOWN_LN_3_2_1; 300 break; 301 case 2: 302 lane_mask = lane_reversal ? PWR_DOWN_LN_1_0 : 303 PWR_DOWN_LN_3_2; 304 break; 305 default: 306 MISSING_CASE(lane_count); 307 /* fall-through */ 308 case 4: 309 lane_mask = PWR_UP_ALL_LANES; 310 break; 311 } 312 } 313 314 val = intel_de_read(dev_priv, ICL_PORT_CL_DW10(phy)); 315 val &= ~PWR_DOWN_LN_MASK; 316 val |= lane_mask << PWR_DOWN_LN_SHIFT; 317 intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val); 318 } 319 320 static void icl_combo_phys_init(struct drm_i915_private *dev_priv) 321 { 322 enum phy phy; 323 324 for_each_combo_phy(dev_priv, phy) { 325 u32 val; 326 327 if (icl_combo_phy_verify_state(dev_priv, phy)) { 328 drm_dbg(&dev_priv->drm, 329 "Combo PHY %c already enabled, won't reprogram it.\n", 330 phy_name(phy)); 331 continue; 332 } 333 334 if (!has_phy_misc(dev_priv, phy)) 335 goto skip_phy_misc; 336 337 /* 338 * EHL's combo PHY A can be hooked up to either an external 339 * display (via DDI-D) or an internal display (via DDI-A or 340 * the DSI DPHY). This is a motherboard design decision that 341 * can't be changed on the fly, so initialize the PHY's mux 342 * based on whether our VBT indicates the presence of any 343 * "internal" child devices. 344 */ 345 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); 346 if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_A) { 347 val &= ~ICL_PHY_MISC_MUX_DDID; 348 349 if (ehl_vbt_ddi_d_present(dev_priv)) 350 val |= ICL_PHY_MISC_MUX_DDID; 351 } 352 353 val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; 354 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); 355 356 skip_phy_misc: 357 cnl_set_procmon_ref_values(dev_priv, phy); 358 359 if (phy == PHY_A) { 360 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW8(phy)); 361 val |= IREFGEN; 362 intel_de_write(dev_priv, ICL_PORT_COMP_DW8(phy), val); 363 } 364 365 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)); 366 val |= COMP_INIT; 367 intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val); 368 369 val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 370 val |= CL_POWER_DOWN_ENABLE; 371 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); 372 } 373 } 374 375 static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv) 376 { 377 enum phy phy; 378 379 for_each_combo_phy_reverse(dev_priv, phy) { 380 u32 val; 381 382 if (phy == PHY_A && 383 !icl_combo_phy_verify_state(dev_priv, phy)) 384 drm_warn(&dev_priv->drm, 385 "Combo PHY %c HW state changed unexpectedly\n", 386 phy_name(phy)); 387 388 if (!has_phy_misc(dev_priv, phy)) 389 goto skip_phy_misc; 390 391 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); 392 val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; 393 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); 394 395 skip_phy_misc: 396 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)); 397 val &= ~COMP_INIT; 398 intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val); 399 } 400 } 401 402 void intel_combo_phy_init(struct drm_i915_private *i915) 403 { 404 if (INTEL_GEN(i915) >= 11) 405 icl_combo_phys_init(i915); 406 else if (IS_CANNONLAKE(i915)) 407 cnl_combo_phys_init(i915); 408 } 409 410 void intel_combo_phy_uninit(struct drm_i915_private *i915) 411 { 412 if (INTEL_GEN(i915) >= 11) 413 icl_combo_phys_uninit(i915); 414 else if (IS_CANNONLAKE(i915)) 415 cnl_combo_phys_uninit(i915); 416 } 417