1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include "intel_color.h" 26 #include "intel_de.h" 27 #include "intel_display_types.h" 28 #include "intel_dpll.h" 29 #include "intel_dsi.h" 30 31 #define CTM_COEFF_SIGN (1ULL << 63) 32 33 #define CTM_COEFF_1_0 (1ULL << 32) 34 #define CTM_COEFF_2_0 (CTM_COEFF_1_0 << 1) 35 #define CTM_COEFF_4_0 (CTM_COEFF_2_0 << 1) 36 #define CTM_COEFF_8_0 (CTM_COEFF_4_0 << 1) 37 #define CTM_COEFF_0_5 (CTM_COEFF_1_0 >> 1) 38 #define CTM_COEFF_0_25 (CTM_COEFF_0_5 >> 1) 39 #define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1) 40 41 #define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255) 42 43 #define CTM_COEFF_NEGATIVE(coeff) (((coeff) & CTM_COEFF_SIGN) != 0) 44 #define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1)) 45 46 #define LEGACY_LUT_LENGTH 256 47 48 /* 49 * ILK+ csc matrix: 50 * 51 * |R/Cr| | c0 c1 c2 | ( |R/Cr| |preoff0| ) |postoff0| 52 * |G/Y | = | c3 c4 c5 | x ( |G/Y | + |preoff1| ) + |postoff1| 53 * |B/Cb| | c6 c7 c8 | ( |B/Cb| |preoff2| ) |postoff2| 54 * 55 * ILK/SNB don't have explicit post offsets, and instead 56 * CSC_MODE_YUV_TO_RGB and CSC_BLACK_SCREEN_OFFSET are used: 57 * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=0 -> 1/2, 0, 1/2 58 * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/2, 1/16, 1/2 59 * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=0 -> 0, 0, 0 60 * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/16, 1/16, 1/16 61 */ 62 63 /* 64 * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point 65 * format). This macro takes the coefficient we want transformed and the 66 * number of fractional bits. 67 * 68 * We only have a 9 bits precision window which slides depending on the value 69 * of the CTM coefficient and we write the value from bit 3. We also round the 70 * value. 71 */ 72 #define ILK_CSC_COEFF_FP(coeff, fbits) \ 73 (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8) 74 75 #define ILK_CSC_COEFF_LIMITED_RANGE 0x0dc0 76 #define ILK_CSC_COEFF_1_0 0x7800 77 78 #define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255) 79 80 /* Nop pre/post offsets */ 81 static const u16 ilk_csc_off_zero[3] = {}; 82 83 /* Identity matrix */ 84 static const u16 ilk_csc_coeff_identity[9] = { 85 ILK_CSC_COEFF_1_0, 0, 0, 86 0, ILK_CSC_COEFF_1_0, 0, 87 0, 0, ILK_CSC_COEFF_1_0, 88 }; 89 90 /* Limited range RGB post offsets */ 91 static const u16 ilk_csc_postoff_limited_range[3] = { 92 ILK_CSC_POSTOFF_LIMITED_RANGE, 93 ILK_CSC_POSTOFF_LIMITED_RANGE, 94 ILK_CSC_POSTOFF_LIMITED_RANGE, 95 }; 96 97 /* Full range RGB -> limited range RGB matrix */ 98 static const u16 ilk_csc_coeff_limited_range[9] = { 99 ILK_CSC_COEFF_LIMITED_RANGE, 0, 0, 100 0, ILK_CSC_COEFF_LIMITED_RANGE, 0, 101 0, 0, ILK_CSC_COEFF_LIMITED_RANGE, 102 }; 103 104 /* BT.709 full range RGB -> limited range YCbCr matrix */ 105 static const u16 ilk_csc_coeff_rgb_to_ycbcr[9] = { 106 0x1e08, 0x9cc0, 0xb528, 107 0x2ba8, 0x09d8, 0x37e8, 108 0xbce8, 0x9ad8, 0x1e08, 109 }; 110 111 /* Limited range YCbCr post offsets */ 112 static const u16 ilk_csc_postoff_rgb_to_ycbcr[3] = { 113 0x0800, 0x0100, 0x0800, 114 }; 115 116 static bool lut_is_legacy(const struct drm_property_blob *lut) 117 { 118 return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH; 119 } 120 121 static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state) 122 { 123 return !crtc_state->hw.degamma_lut && 124 !crtc_state->hw.ctm && 125 crtc_state->hw.gamma_lut && 126 lut_is_legacy(crtc_state->hw.gamma_lut); 127 } 128 129 /* 130 * When using limited range, multiply the matrix given by userspace by 131 * the matrix that we would use for the limited range. 132 */ 133 static u64 *ctm_mult_by_limited(u64 *result, const u64 *input) 134 { 135 int i; 136 137 for (i = 0; i < 9; i++) { 138 u64 user_coeff = input[i]; 139 u32 limited_coeff = CTM_COEFF_LIMITED_RANGE; 140 u32 abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff), 0, 141 CTM_COEFF_4_0 - 1) >> 2; 142 143 /* 144 * By scaling every co-efficient with limited range (16-235) 145 * vs full range (0-255) the final o/p will be scaled down to 146 * fit in the limited range supported by the panel. 147 */ 148 result[i] = mul_u32_u32(limited_coeff, abs_coeff) >> 30; 149 result[i] |= user_coeff & CTM_COEFF_SIGN; 150 } 151 152 return result; 153 } 154 155 static void ilk_update_pipe_csc(struct intel_crtc *crtc, 156 const u16 preoff[3], 157 const u16 coeff[9], 158 const u16 postoff[3]) 159 { 160 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 161 enum pipe pipe = crtc->pipe; 162 163 intel_de_write(dev_priv, PIPE_CSC_PREOFF_HI(pipe), preoff[0]); 164 intel_de_write(dev_priv, PIPE_CSC_PREOFF_ME(pipe), preoff[1]); 165 intel_de_write(dev_priv, PIPE_CSC_PREOFF_LO(pipe), preoff[2]); 166 167 intel_de_write(dev_priv, PIPE_CSC_COEFF_RY_GY(pipe), 168 coeff[0] << 16 | coeff[1]); 169 intel_de_write(dev_priv, PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16); 170 171 intel_de_write(dev_priv, PIPE_CSC_COEFF_RU_GU(pipe), 172 coeff[3] << 16 | coeff[4]); 173 intel_de_write(dev_priv, PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16); 174 175 intel_de_write(dev_priv, PIPE_CSC_COEFF_RV_GV(pipe), 176 coeff[6] << 16 | coeff[7]); 177 intel_de_write(dev_priv, PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16); 178 179 if (DISPLAY_VER(dev_priv) >= 7) { 180 intel_de_write(dev_priv, PIPE_CSC_POSTOFF_HI(pipe), 181 postoff[0]); 182 intel_de_write(dev_priv, PIPE_CSC_POSTOFF_ME(pipe), 183 postoff[1]); 184 intel_de_write(dev_priv, PIPE_CSC_POSTOFF_LO(pipe), 185 postoff[2]); 186 } 187 } 188 189 static void icl_update_output_csc(struct intel_crtc *crtc, 190 const u16 preoff[3], 191 const u16 coeff[9], 192 const u16 postoff[3]) 193 { 194 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 195 enum pipe pipe = crtc->pipe; 196 197 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_HI(pipe), preoff[0]); 198 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_ME(pipe), preoff[1]); 199 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]); 200 201 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe), 202 coeff[0] << 16 | coeff[1]); 203 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BY(pipe), 204 coeff[2] << 16); 205 206 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe), 207 coeff[3] << 16 | coeff[4]); 208 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BU(pipe), 209 coeff[5] << 16); 210 211 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe), 212 coeff[6] << 16 | coeff[7]); 213 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BV(pipe), 214 coeff[8] << 16); 215 216 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]); 217 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]); 218 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), postoff[2]); 219 } 220 221 static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state) 222 { 223 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 224 225 /* 226 * FIXME if there's a gamma LUT after the CSC, we should 227 * do the range compression using the gamma LUT instead. 228 */ 229 return crtc_state->limited_color_range && 230 (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) || 231 IS_DISPLAY_VER(dev_priv, 9, 10)); 232 } 233 234 static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state, 235 u16 coeffs[9]) 236 { 237 const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data; 238 const u64 *input; 239 u64 temp[9]; 240 int i; 241 242 if (ilk_csc_limited_range(crtc_state)) 243 input = ctm_mult_by_limited(temp, ctm->matrix); 244 else 245 input = ctm->matrix; 246 247 /* 248 * Convert fixed point S31.32 input to format supported by the 249 * hardware. 250 */ 251 for (i = 0; i < 9; i++) { 252 u64 abs_coeff = ((1ULL << 63) - 1) & input[i]; 253 254 /* 255 * Clamp input value to min/max supported by 256 * hardware. 257 */ 258 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1); 259 260 coeffs[i] = 0; 261 262 /* sign bit */ 263 if (CTM_COEFF_NEGATIVE(input[i])) 264 coeffs[i] |= 1 << 15; 265 266 if (abs_coeff < CTM_COEFF_0_125) 267 coeffs[i] |= (3 << 12) | 268 ILK_CSC_COEFF_FP(abs_coeff, 12); 269 else if (abs_coeff < CTM_COEFF_0_25) 270 coeffs[i] |= (2 << 12) | 271 ILK_CSC_COEFF_FP(abs_coeff, 11); 272 else if (abs_coeff < CTM_COEFF_0_5) 273 coeffs[i] |= (1 << 12) | 274 ILK_CSC_COEFF_FP(abs_coeff, 10); 275 else if (abs_coeff < CTM_COEFF_1_0) 276 coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9); 277 else if (abs_coeff < CTM_COEFF_2_0) 278 coeffs[i] |= (7 << 12) | 279 ILK_CSC_COEFF_FP(abs_coeff, 8); 280 else 281 coeffs[i] |= (6 << 12) | 282 ILK_CSC_COEFF_FP(abs_coeff, 7); 283 } 284 } 285 286 static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state) 287 { 288 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 289 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 290 bool limited_color_range = ilk_csc_limited_range(crtc_state); 291 292 if (crtc_state->hw.ctm) { 293 u16 coeff[9]; 294 295 ilk_csc_convert_ctm(crtc_state, coeff); 296 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeff, 297 limited_color_range ? 298 ilk_csc_postoff_limited_range : 299 ilk_csc_off_zero); 300 } else if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) { 301 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, 302 ilk_csc_coeff_rgb_to_ycbcr, 303 ilk_csc_postoff_rgb_to_ycbcr); 304 } else if (limited_color_range) { 305 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, 306 ilk_csc_coeff_limited_range, 307 ilk_csc_postoff_limited_range); 308 } else if (crtc_state->csc_enable) { 309 /* 310 * On GLK both pipe CSC and degamma LUT are controlled 311 * by csc_enable. Hence for the cases where the degama 312 * LUT is needed but CSC is not we need to load an 313 * identity matrix. 314 */ 315 drm_WARN_ON(&dev_priv->drm, !IS_GEMINILAKE(dev_priv)); 316 317 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, 318 ilk_csc_coeff_identity, 319 ilk_csc_off_zero); 320 } 321 322 intel_de_write(dev_priv, PIPE_CSC_MODE(crtc->pipe), 323 crtc_state->csc_mode); 324 } 325 326 static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state) 327 { 328 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 329 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 330 331 if (crtc_state->hw.ctm) { 332 u16 coeff[9]; 333 334 ilk_csc_convert_ctm(crtc_state, coeff); 335 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, 336 coeff, ilk_csc_off_zero); 337 } 338 339 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) { 340 icl_update_output_csc(crtc, ilk_csc_off_zero, 341 ilk_csc_coeff_rgb_to_ycbcr, 342 ilk_csc_postoff_rgb_to_ycbcr); 343 } else if (crtc_state->limited_color_range) { 344 icl_update_output_csc(crtc, ilk_csc_off_zero, 345 ilk_csc_coeff_limited_range, 346 ilk_csc_postoff_limited_range); 347 } 348 349 intel_de_write(dev_priv, PIPE_CSC_MODE(crtc->pipe), 350 crtc_state->csc_mode); 351 } 352 353 static void chv_load_cgm_csc(struct intel_crtc *crtc, 354 const struct drm_property_blob *blob) 355 { 356 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 357 const struct drm_color_ctm *ctm = blob->data; 358 enum pipe pipe = crtc->pipe; 359 u16 coeffs[9]; 360 int i; 361 362 for (i = 0; i < ARRAY_SIZE(coeffs); i++) { 363 u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i]; 364 365 /* Round coefficient. */ 366 abs_coeff += 1 << (32 - 13); 367 /* Clamp to hardware limits. */ 368 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1); 369 370 coeffs[i] = 0; 371 372 /* Write coefficients in S3.12 format. */ 373 if (ctm->matrix[i] & (1ULL << 63)) 374 coeffs[i] |= 1 << 15; 375 376 coeffs[i] |= ((abs_coeff >> 32) & 7) << 12; 377 coeffs[i] |= (abs_coeff >> 20) & 0xfff; 378 } 379 380 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF01(pipe), 381 coeffs[1] << 16 | coeffs[0]); 382 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF23(pipe), 383 coeffs[3] << 16 | coeffs[2]); 384 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF45(pipe), 385 coeffs[5] << 16 | coeffs[4]); 386 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF67(pipe), 387 coeffs[7] << 16 | coeffs[6]); 388 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF8(pipe), 389 coeffs[8]); 390 } 391 392 /* convert hw value with given bit_precision to lut property val */ 393 static u32 intel_color_lut_pack(u32 val, int bit_precision) 394 { 395 u32 max = 0xffff >> (16 - bit_precision); 396 397 val = clamp_val(val, 0, max); 398 399 if (bit_precision < 16) 400 val <<= 16 - bit_precision; 401 402 return val; 403 } 404 405 static u32 i9xx_lut_8(const struct drm_color_lut *color) 406 { 407 return drm_color_lut_extract(color->red, 8) << 16 | 408 drm_color_lut_extract(color->green, 8) << 8 | 409 drm_color_lut_extract(color->blue, 8); 410 } 411 412 static void i9xx_lut_8_pack(struct drm_color_lut *entry, u32 val) 413 { 414 entry->red = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_RED_MASK, val), 8); 415 entry->green = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_GREEN_MASK, val), 8); 416 entry->blue = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_BLUE_MASK, val), 8); 417 } 418 419 /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */ 420 static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color) 421 { 422 return (color->red & 0xff) << 16 | 423 (color->green & 0xff) << 8 | 424 (color->blue & 0xff); 425 } 426 427 /* i965+ "10.6" interpolated format "odd DW" (high 8 bits) */ 428 static u32 i965_lut_10p6_udw(const struct drm_color_lut *color) 429 { 430 return (color->red >> 8) << 16 | 431 (color->green >> 8) << 8 | 432 (color->blue >> 8); 433 } 434 435 static void i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) 436 { 437 entry->red = REG_FIELD_GET(PALETTE_RED_MASK, udw) << 8 | 438 REG_FIELD_GET(PALETTE_RED_MASK, ldw); 439 entry->green = REG_FIELD_GET(PALETTE_GREEN_MASK, udw) << 8 | 440 REG_FIELD_GET(PALETTE_GREEN_MASK, ldw); 441 entry->blue = REG_FIELD_GET(PALETTE_BLUE_MASK, udw) << 8 | 442 REG_FIELD_GET(PALETTE_BLUE_MASK, ldw); 443 } 444 445 static u16 i965_lut_11p6_max_pack(u32 val) 446 { 447 /* PIPEGCMAX is 11.6, clamp to 10.6 */ 448 return clamp_val(val, 0, 0xffff); 449 } 450 451 static u32 ilk_lut_10(const struct drm_color_lut *color) 452 { 453 return drm_color_lut_extract(color->red, 10) << 20 | 454 drm_color_lut_extract(color->green, 10) << 10 | 455 drm_color_lut_extract(color->blue, 10); 456 } 457 458 static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val) 459 { 460 entry->red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_RED_MASK, val), 10); 461 entry->green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_GREEN_MASK, val), 10); 462 entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10); 463 } 464 465 static void icl_lut_multi_seg_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) 466 { 467 entry->red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, udw) << 6 | 468 REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, ldw); 469 entry->green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, udw) << 6 | 470 REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, ldw); 471 entry->blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, udw) << 6 | 472 REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw); 473 } 474 475 static void i9xx_color_commit(const struct intel_crtc_state *crtc_state) 476 { 477 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 478 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 479 enum pipe pipe = crtc->pipe; 480 u32 val; 481 482 val = intel_de_read(dev_priv, PIPECONF(pipe)); 483 val &= ~PIPECONF_GAMMA_MODE_MASK_I9XX; 484 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 485 intel_de_write(dev_priv, PIPECONF(pipe), val); 486 } 487 488 static void ilk_color_commit(const struct intel_crtc_state *crtc_state) 489 { 490 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 491 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 492 enum pipe pipe = crtc->pipe; 493 u32 val; 494 495 val = intel_de_read(dev_priv, PIPECONF(pipe)); 496 val &= ~PIPECONF_GAMMA_MODE_MASK_ILK; 497 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 498 intel_de_write(dev_priv, PIPECONF(pipe), val); 499 500 ilk_load_csc_matrix(crtc_state); 501 } 502 503 static void hsw_color_commit(const struct intel_crtc_state *crtc_state) 504 { 505 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 506 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 507 508 intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe), 509 crtc_state->gamma_mode); 510 511 ilk_load_csc_matrix(crtc_state); 512 } 513 514 static void skl_color_commit(const struct intel_crtc_state *crtc_state) 515 { 516 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 517 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 518 enum pipe pipe = crtc->pipe; 519 u32 val = 0; 520 521 /* 522 * We don't (yet) allow userspace to control the pipe background color, 523 * so force it to black, but apply pipe gamma and CSC appropriately 524 * so that its handling will match how we program our planes. 525 */ 526 if (crtc_state->gamma_enable) 527 val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE; 528 if (crtc_state->csc_enable) 529 val |= SKL_BOTTOM_COLOR_CSC_ENABLE; 530 intel_de_write(dev_priv, SKL_BOTTOM_COLOR(pipe), val); 531 532 intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe), 533 crtc_state->gamma_mode); 534 535 if (DISPLAY_VER(dev_priv) >= 11) 536 icl_load_csc_matrix(crtc_state); 537 else 538 ilk_load_csc_matrix(crtc_state); 539 } 540 541 static void i9xx_load_lut_8(struct intel_crtc *crtc, 542 const struct drm_property_blob *blob) 543 { 544 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 545 const struct drm_color_lut *lut; 546 enum pipe pipe = crtc->pipe; 547 int i; 548 549 if (!blob) 550 return; 551 552 lut = blob->data; 553 554 for (i = 0; i < 256; i++) 555 intel_de_write(dev_priv, PALETTE(pipe, i), 556 i9xx_lut_8(&lut[i])); 557 } 558 559 static void i9xx_load_luts(const struct intel_crtc_state *crtc_state) 560 { 561 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 562 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 563 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 564 565 assert_pll_enabled(dev_priv, crtc->pipe); 566 567 i9xx_load_lut_8(crtc, gamma_lut); 568 } 569 570 static void i965_load_lut_10p6(struct intel_crtc *crtc, 571 const struct drm_property_blob *blob) 572 { 573 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 574 const struct drm_color_lut *lut = blob->data; 575 int i, lut_size = drm_color_lut_size(blob); 576 enum pipe pipe = crtc->pipe; 577 578 for (i = 0; i < lut_size - 1; i++) { 579 intel_de_write(dev_priv, PALETTE(pipe, 2 * i + 0), 580 i965_lut_10p6_ldw(&lut[i])); 581 intel_de_write(dev_priv, PALETTE(pipe, 2 * i + 1), 582 i965_lut_10p6_udw(&lut[i])); 583 } 584 585 intel_de_write(dev_priv, PIPEGCMAX(pipe, 0), lut[i].red); 586 intel_de_write(dev_priv, PIPEGCMAX(pipe, 1), lut[i].green); 587 intel_de_write(dev_priv, PIPEGCMAX(pipe, 2), lut[i].blue); 588 } 589 590 static void i965_load_luts(const struct intel_crtc_state *crtc_state) 591 { 592 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 593 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 594 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 595 596 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 597 assert_dsi_pll_enabled(dev_priv); 598 else 599 assert_pll_enabled(dev_priv, crtc->pipe); 600 601 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) 602 i9xx_load_lut_8(crtc, gamma_lut); 603 else 604 i965_load_lut_10p6(crtc, gamma_lut); 605 } 606 607 static void ilk_load_lut_8(struct intel_crtc *crtc, 608 const struct drm_property_blob *blob) 609 { 610 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 611 const struct drm_color_lut *lut; 612 enum pipe pipe = crtc->pipe; 613 int i; 614 615 if (!blob) 616 return; 617 618 lut = blob->data; 619 620 for (i = 0; i < 256; i++) 621 intel_de_write(dev_priv, LGC_PALETTE(pipe, i), 622 i9xx_lut_8(&lut[i])); 623 } 624 625 static void ilk_load_lut_10(struct intel_crtc *crtc, 626 const struct drm_property_blob *blob) 627 { 628 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 629 const struct drm_color_lut *lut = blob->data; 630 int i, lut_size = drm_color_lut_size(blob); 631 enum pipe pipe = crtc->pipe; 632 633 for (i = 0; i < lut_size; i++) 634 intel_de_write(dev_priv, PREC_PALETTE(pipe, i), 635 ilk_lut_10(&lut[i])); 636 } 637 638 static void ilk_load_luts(const struct intel_crtc_state *crtc_state) 639 { 640 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 641 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 642 643 switch (crtc_state->gamma_mode) { 644 case GAMMA_MODE_MODE_8BIT: 645 ilk_load_lut_8(crtc, gamma_lut); 646 break; 647 case GAMMA_MODE_MODE_10BIT: 648 ilk_load_lut_10(crtc, gamma_lut); 649 break; 650 default: 651 MISSING_CASE(crtc_state->gamma_mode); 652 break; 653 } 654 } 655 656 static int ivb_lut_10_size(u32 prec_index) 657 { 658 if (prec_index & PAL_PREC_SPLIT_MODE) 659 return 512; 660 else 661 return 1024; 662 } 663 664 /* 665 * IVB/HSW Bspec / PAL_PREC_INDEX: 666 * "Restriction : Index auto increment mode is not 667 * supported and must not be enabled." 668 */ 669 static void ivb_load_lut_10(struct intel_crtc *crtc, 670 const struct drm_property_blob *blob, 671 u32 prec_index) 672 { 673 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 674 int hw_lut_size = ivb_lut_10_size(prec_index); 675 const struct drm_color_lut *lut = blob->data; 676 int i, lut_size = drm_color_lut_size(blob); 677 enum pipe pipe = crtc->pipe; 678 679 for (i = 0; i < hw_lut_size; i++) { 680 /* We discard half the user entries in split gamma mode */ 681 const struct drm_color_lut *entry = 682 &lut[i * (lut_size - 1) / (hw_lut_size - 1)]; 683 684 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), prec_index++); 685 intel_de_write(dev_priv, PREC_PAL_DATA(pipe), 686 ilk_lut_10(entry)); 687 } 688 689 /* 690 * Reset the index, otherwise it prevents the legacy palette to be 691 * written properly. 692 */ 693 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0); 694 } 695 696 /* On BDW+ the index auto increment mode actually works */ 697 static void bdw_load_lut_10(struct intel_crtc *crtc, 698 const struct drm_property_blob *blob, 699 u32 prec_index) 700 { 701 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 702 int hw_lut_size = ivb_lut_10_size(prec_index); 703 const struct drm_color_lut *lut = blob->data; 704 int i, lut_size = drm_color_lut_size(blob); 705 enum pipe pipe = crtc->pipe; 706 707 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 708 prec_index | PAL_PREC_AUTO_INCREMENT); 709 710 for (i = 0; i < hw_lut_size; i++) { 711 /* We discard half the user entries in split gamma mode */ 712 const struct drm_color_lut *entry = 713 &lut[i * (lut_size - 1) / (hw_lut_size - 1)]; 714 715 intel_de_write(dev_priv, PREC_PAL_DATA(pipe), 716 ilk_lut_10(entry)); 717 } 718 719 /* 720 * Reset the index, otherwise it prevents the legacy palette to be 721 * written properly. 722 */ 723 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0); 724 } 725 726 static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state) 727 { 728 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 729 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 730 enum pipe pipe = crtc->pipe; 731 732 /* Program the max register to clamp values > 1.0. */ 733 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16); 734 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16); 735 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16); 736 737 /* 738 * Program the gc max 2 register to clamp values > 1.0. 739 * ToDo: Extend the ABI to be able to program values 740 * from 3.0 to 7.0 741 */ 742 if (DISPLAY_VER(dev_priv) >= 10) { 743 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0), 744 1 << 16); 745 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1), 746 1 << 16); 747 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 2), 748 1 << 16); 749 } 750 } 751 752 static void ivb_load_luts(const struct intel_crtc_state *crtc_state) 753 { 754 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 755 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 756 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut; 757 const struct drm_property_blob *blob = gamma_lut ?: degamma_lut; 758 759 switch (crtc_state->gamma_mode) { 760 case GAMMA_MODE_MODE_8BIT: 761 ilk_load_lut_8(crtc, blob); 762 break; 763 case GAMMA_MODE_MODE_SPLIT: 764 ivb_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE | 765 PAL_PREC_INDEX_VALUE(0)); 766 ivb_load_lut_ext_max(crtc_state); 767 ivb_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE | 768 PAL_PREC_INDEX_VALUE(512)); 769 break; 770 case GAMMA_MODE_MODE_10BIT: 771 ivb_load_lut_10(crtc, blob, 772 PAL_PREC_INDEX_VALUE(0)); 773 ivb_load_lut_ext_max(crtc_state); 774 break; 775 default: 776 MISSING_CASE(crtc_state->gamma_mode); 777 break; 778 } 779 } 780 781 static void bdw_load_luts(const struct intel_crtc_state *crtc_state) 782 { 783 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 784 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 785 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut; 786 const struct drm_property_blob *blob = gamma_lut ?: degamma_lut; 787 788 switch (crtc_state->gamma_mode) { 789 case GAMMA_MODE_MODE_8BIT: 790 ilk_load_lut_8(crtc, blob); 791 break; 792 case GAMMA_MODE_MODE_SPLIT: 793 bdw_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE | 794 PAL_PREC_INDEX_VALUE(0)); 795 ivb_load_lut_ext_max(crtc_state); 796 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE | 797 PAL_PREC_INDEX_VALUE(512)); 798 break; 799 case GAMMA_MODE_MODE_10BIT: 800 801 bdw_load_lut_10(crtc, blob, 802 PAL_PREC_INDEX_VALUE(0)); 803 ivb_load_lut_ext_max(crtc_state); 804 break; 805 default: 806 MISSING_CASE(crtc_state->gamma_mode); 807 break; 808 } 809 } 810 811 static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state) 812 { 813 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 814 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 815 enum pipe pipe = crtc->pipe; 816 int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; 817 const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data; 818 819 /* 820 * When setting the auto-increment bit, the hardware seems to 821 * ignore the index bits, so we need to reset it to index 0 822 * separately. 823 */ 824 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0); 825 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 826 PRE_CSC_GAMC_AUTO_INCREMENT); 827 828 for (i = 0; i < lut_size; i++) { 829 /* 830 * First 33 entries represent range from 0 to 1.0 831 * 34th and 35th entry will represent extended range 832 * inputs 3.0 and 7.0 respectively, currently clamped 833 * at 1.0. Since the precision is 16bit, the user 834 * value can be directly filled to register. 835 * The pipe degamma table in GLK+ onwards doesn't 836 * support different values per channel, so this just 837 * programs green value which will be equal to Red and 838 * Blue into the lut registers. 839 * ToDo: Extend to max 7.0. Enable 32 bit input value 840 * as compared to just 16 to achieve this. 841 */ 842 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 843 lut[i].green); 844 } 845 846 /* Clamp values > 1.0. */ 847 while (i++ < 35) 848 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16); 849 850 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0); 851 } 852 853 static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_state) 854 { 855 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 856 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 857 enum pipe pipe = crtc->pipe; 858 int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; 859 860 /* 861 * When setting the auto-increment bit, the hardware seems to 862 * ignore the index bits, so we need to reset it to index 0 863 * separately. 864 */ 865 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0); 866 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 867 PRE_CSC_GAMC_AUTO_INCREMENT); 868 869 for (i = 0; i < lut_size; i++) { 870 u32 v = (i << 16) / (lut_size - 1); 871 872 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), v); 873 } 874 875 /* Clamp values > 1.0. */ 876 while (i++ < 35) 877 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16); 878 879 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0); 880 } 881 882 static void glk_load_luts(const struct intel_crtc_state *crtc_state) 883 { 884 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 885 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 886 887 /* 888 * On GLK+ both pipe CSC and degamma LUT are controlled 889 * by csc_enable. Hence for the cases where the CSC is 890 * needed but degamma LUT is not we need to load a 891 * linear degamma LUT. In fact we'll just always load 892 * the degama LUT so that we don't have to reload 893 * it every time the pipe CSC is being enabled. 894 */ 895 if (crtc_state->hw.degamma_lut) 896 glk_load_degamma_lut(crtc_state); 897 else 898 glk_load_degamma_lut_linear(crtc_state); 899 900 switch (crtc_state->gamma_mode) { 901 case GAMMA_MODE_MODE_8BIT: 902 ilk_load_lut_8(crtc, gamma_lut); 903 break; 904 case GAMMA_MODE_MODE_10BIT: 905 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0)); 906 ivb_load_lut_ext_max(crtc_state); 907 break; 908 default: 909 MISSING_CASE(crtc_state->gamma_mode); 910 break; 911 } 912 } 913 914 /* ilk+ "12.4" interpolated format (high 10 bits) */ 915 static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color) 916 { 917 return (color->red >> 6) << 20 | (color->green >> 6) << 10 | 918 (color->blue >> 6); 919 } 920 921 /* ilk+ "12.4" interpolated format (low 6 bits) */ 922 static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color) 923 { 924 return (color->red & 0x3f) << 24 | (color->green & 0x3f) << 14 | 925 (color->blue & 0x3f) << 4; 926 } 927 928 static void 929 icl_load_gcmax(const struct intel_crtc_state *crtc_state, 930 const struct drm_color_lut *color) 931 { 932 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 933 enum pipe pipe = crtc->pipe; 934 935 /* FIXME LUT entries are 16 bit only, so we can prog 0xFFFF max */ 936 intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red); 937 intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green); 938 intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue); 939 } 940 941 static void 942 icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state) 943 { 944 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 945 const struct drm_property_blob *blob = crtc_state->hw.gamma_lut; 946 const struct drm_color_lut *lut = blob->data; 947 enum pipe pipe = crtc->pipe; 948 int i; 949 950 /* 951 * Program Super Fine segment (let's call it seg1)... 952 * 953 * Super Fine segment's step is 1/(8 * 128 * 256) and it has 954 * 9 entries, corresponding to values 0, 1/(8 * 128 * 256), 955 * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256). 956 */ 957 intel_dsb_reg_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe), 958 PAL_PREC_AUTO_INCREMENT); 959 960 for (i = 0; i < 9; i++) { 961 const struct drm_color_lut *entry = &lut[i]; 962 963 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe), 964 ilk_lut_12p4_ldw(entry)); 965 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe), 966 ilk_lut_12p4_udw(entry)); 967 } 968 } 969 970 static void 971 icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state) 972 { 973 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 974 const struct drm_property_blob *blob = crtc_state->hw.gamma_lut; 975 const struct drm_color_lut *lut = blob->data; 976 const struct drm_color_lut *entry; 977 enum pipe pipe = crtc->pipe; 978 int i; 979 980 /* 981 * Program Fine segment (let's call it seg2)... 982 * 983 * Fine segment's step is 1/(128 * 256) i.e. 1/(128 * 256), 2/(128 * 256) 984 * ... 256/(128 * 256). So in order to program fine segment of LUT we 985 * need to pick every 8th entry in the LUT, and program 256 indexes. 986 * 987 * PAL_PREC_INDEX[0] and PAL_PREC_INDEX[1] map to seg2[1], 988 * seg2[0] being unused by the hardware. 989 */ 990 intel_dsb_reg_write(crtc_state, PREC_PAL_INDEX(pipe), 991 PAL_PREC_AUTO_INCREMENT); 992 for (i = 1; i < 257; i++) { 993 entry = &lut[i * 8]; 994 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), 995 ilk_lut_12p4_ldw(entry)); 996 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), 997 ilk_lut_12p4_udw(entry)); 998 } 999 1000 /* 1001 * Program Coarse segment (let's call it seg3)... 1002 * 1003 * Coarse segment starts from index 0 and it's step is 1/256 ie 0, 1004 * 1/256, 2/256 ... 256/256. As per the description of each entry in LUT 1005 * above, we need to pick every (8 * 128)th entry in LUT, and 1006 * program 256 of those. 1007 * 1008 * Spec is not very clear about if entries seg3[0] and seg3[1] are 1009 * being used or not, but we still need to program these to advance 1010 * the index. 1011 */ 1012 for (i = 0; i < 256; i++) { 1013 entry = &lut[i * 8 * 128]; 1014 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), 1015 ilk_lut_12p4_ldw(entry)); 1016 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), 1017 ilk_lut_12p4_udw(entry)); 1018 } 1019 1020 /* The last entry in the LUT is to be programmed in GCMAX */ 1021 entry = &lut[256 * 8 * 128]; 1022 icl_load_gcmax(crtc_state, entry); 1023 ivb_load_lut_ext_max(crtc_state); 1024 } 1025 1026 static void icl_load_luts(const struct intel_crtc_state *crtc_state) 1027 { 1028 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 1029 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1030 1031 if (crtc_state->hw.degamma_lut) 1032 glk_load_degamma_lut(crtc_state); 1033 1034 switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { 1035 case GAMMA_MODE_MODE_8BIT: 1036 ilk_load_lut_8(crtc, gamma_lut); 1037 break; 1038 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: 1039 icl_program_gamma_superfine_segment(crtc_state); 1040 icl_program_gamma_multi_segment(crtc_state); 1041 break; 1042 case GAMMA_MODE_MODE_10BIT: 1043 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0)); 1044 ivb_load_lut_ext_max(crtc_state); 1045 break; 1046 default: 1047 MISSING_CASE(crtc_state->gamma_mode); 1048 break; 1049 } 1050 1051 intel_dsb_commit(crtc_state); 1052 } 1053 1054 static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color) 1055 { 1056 return drm_color_lut_extract(color->green, 14) << 16 | 1057 drm_color_lut_extract(color->blue, 14); 1058 } 1059 1060 static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color) 1061 { 1062 return drm_color_lut_extract(color->red, 14); 1063 } 1064 1065 static void chv_load_cgm_degamma(struct intel_crtc *crtc, 1066 const struct drm_property_blob *blob) 1067 { 1068 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1069 const struct drm_color_lut *lut = blob->data; 1070 int i, lut_size = drm_color_lut_size(blob); 1071 enum pipe pipe = crtc->pipe; 1072 1073 for (i = 0; i < lut_size; i++) { 1074 intel_de_write(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 0), 1075 chv_cgm_degamma_ldw(&lut[i])); 1076 intel_de_write(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 1), 1077 chv_cgm_degamma_udw(&lut[i])); 1078 } 1079 } 1080 1081 static u32 chv_cgm_gamma_ldw(const struct drm_color_lut *color) 1082 { 1083 return drm_color_lut_extract(color->green, 10) << 16 | 1084 drm_color_lut_extract(color->blue, 10); 1085 } 1086 1087 static u32 chv_cgm_gamma_udw(const struct drm_color_lut *color) 1088 { 1089 return drm_color_lut_extract(color->red, 10); 1090 } 1091 1092 static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) 1093 { 1094 entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK, ldw), 10); 1095 entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK, ldw), 10); 1096 entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, udw), 10); 1097 } 1098 1099 static void chv_load_cgm_gamma(struct intel_crtc *crtc, 1100 const struct drm_property_blob *blob) 1101 { 1102 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1103 const struct drm_color_lut *lut = blob->data; 1104 int i, lut_size = drm_color_lut_size(blob); 1105 enum pipe pipe = crtc->pipe; 1106 1107 for (i = 0; i < lut_size; i++) { 1108 intel_de_write(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0), 1109 chv_cgm_gamma_ldw(&lut[i])); 1110 intel_de_write(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1), 1111 chv_cgm_gamma_udw(&lut[i])); 1112 } 1113 } 1114 1115 static void chv_load_luts(const struct intel_crtc_state *crtc_state) 1116 { 1117 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1118 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1119 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut; 1120 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 1121 const struct drm_property_blob *ctm = crtc_state->hw.ctm; 1122 1123 if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) 1124 chv_load_cgm_csc(crtc, ctm); 1125 1126 if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA) 1127 chv_load_cgm_degamma(crtc, degamma_lut); 1128 1129 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) 1130 chv_load_cgm_gamma(crtc, gamma_lut); 1131 else 1132 i965_load_luts(crtc_state); 1133 1134 intel_de_write(dev_priv, CGM_PIPE_MODE(crtc->pipe), 1135 crtc_state->cgm_mode); 1136 } 1137 1138 void intel_color_load_luts(const struct intel_crtc_state *crtc_state) 1139 { 1140 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1141 1142 dev_priv->color_funcs->load_luts(crtc_state); 1143 } 1144 1145 void intel_color_commit(const struct intel_crtc_state *crtc_state) 1146 { 1147 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1148 1149 dev_priv->color_funcs->color_commit(crtc_state); 1150 } 1151 1152 static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state) 1153 { 1154 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 1155 struct intel_atomic_state *state = 1156 to_intel_atomic_state(new_crtc_state->uapi.state); 1157 const struct intel_crtc_state *old_crtc_state = 1158 intel_atomic_get_old_crtc_state(state, crtc); 1159 1160 return !old_crtc_state->hw.gamma_lut && 1161 !old_crtc_state->hw.degamma_lut; 1162 } 1163 1164 static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state) 1165 { 1166 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 1167 struct intel_atomic_state *state = 1168 to_intel_atomic_state(new_crtc_state->uapi.state); 1169 const struct intel_crtc_state *old_crtc_state = 1170 intel_atomic_get_old_crtc_state(state, crtc); 1171 1172 /* 1173 * CGM_PIPE_MODE is itself single buffered. We'd have to 1174 * somehow split it out from chv_load_luts() if we wanted 1175 * the ability to preload the CGM LUTs/CSC without tearing. 1176 */ 1177 if (old_crtc_state->cgm_mode || new_crtc_state->cgm_mode) 1178 return false; 1179 1180 return !old_crtc_state->hw.gamma_lut; 1181 } 1182 1183 static bool glk_can_preload_luts(const struct intel_crtc_state *new_crtc_state) 1184 { 1185 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 1186 struct intel_atomic_state *state = 1187 to_intel_atomic_state(new_crtc_state->uapi.state); 1188 const struct intel_crtc_state *old_crtc_state = 1189 intel_atomic_get_old_crtc_state(state, crtc); 1190 1191 /* 1192 * The hardware degamma is active whenever the pipe 1193 * CSC is active. Thus even if the old state has no 1194 * software degamma we need to avoid clobbering the 1195 * linear hardware degamma mid scanout. 1196 */ 1197 return !old_crtc_state->csc_enable && 1198 !old_crtc_state->hw.gamma_lut; 1199 } 1200 1201 int intel_color_check(struct intel_crtc_state *crtc_state) 1202 { 1203 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1204 1205 return dev_priv->color_funcs->color_check(crtc_state); 1206 } 1207 1208 void intel_color_get_config(struct intel_crtc_state *crtc_state) 1209 { 1210 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1211 1212 if (dev_priv->color_funcs->read_luts) 1213 dev_priv->color_funcs->read_luts(crtc_state); 1214 } 1215 1216 static bool need_plane_update(struct intel_plane *plane, 1217 const struct intel_crtc_state *crtc_state) 1218 { 1219 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1220 1221 /* 1222 * On pre-SKL the pipe gamma enable and pipe csc enable for 1223 * the pipe bottom color are configured via the primary plane. 1224 * We have to reconfigure that even if the plane is inactive. 1225 */ 1226 return crtc_state->active_planes & BIT(plane->id) || 1227 (DISPLAY_VER(dev_priv) < 9 && 1228 plane->id == PLANE_PRIMARY); 1229 } 1230 1231 static int 1232 intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state) 1233 { 1234 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 1235 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1236 struct intel_atomic_state *state = 1237 to_intel_atomic_state(new_crtc_state->uapi.state); 1238 const struct intel_crtc_state *old_crtc_state = 1239 intel_atomic_get_old_crtc_state(state, crtc); 1240 struct intel_plane *plane; 1241 1242 if (!new_crtc_state->hw.active || 1243 drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) 1244 return 0; 1245 1246 if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable && 1247 new_crtc_state->csc_enable == old_crtc_state->csc_enable) 1248 return 0; 1249 1250 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 1251 struct intel_plane_state *plane_state; 1252 1253 if (!need_plane_update(plane, new_crtc_state)) 1254 continue; 1255 1256 plane_state = intel_atomic_get_plane_state(state, plane); 1257 if (IS_ERR(plane_state)) 1258 return PTR_ERR(plane_state); 1259 1260 new_crtc_state->update_planes |= BIT(plane->id); 1261 } 1262 1263 return 0; 1264 } 1265 1266 static int check_lut_size(const struct drm_property_blob *lut, int expected) 1267 { 1268 int len; 1269 1270 if (!lut) 1271 return 0; 1272 1273 len = drm_color_lut_size(lut); 1274 if (len != expected) { 1275 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n", 1276 len, expected); 1277 return -EINVAL; 1278 } 1279 1280 return 0; 1281 } 1282 1283 static int check_luts(const struct intel_crtc_state *crtc_state) 1284 { 1285 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1286 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 1287 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut; 1288 int gamma_length, degamma_length; 1289 u32 gamma_tests, degamma_tests; 1290 1291 /* Always allow legacy gamma LUT with no further checking. */ 1292 if (crtc_state_is_legacy_gamma(crtc_state)) 1293 return 0; 1294 1295 /* C8 relies on its palette being stored in the legacy LUT */ 1296 if (crtc_state->c8_planes) { 1297 drm_dbg_kms(&dev_priv->drm, 1298 "C8 pixelformat requires the legacy LUT\n"); 1299 return -EINVAL; 1300 } 1301 1302 degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size; 1303 gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size; 1304 degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests; 1305 gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests; 1306 1307 if (check_lut_size(degamma_lut, degamma_length) || 1308 check_lut_size(gamma_lut, gamma_length)) 1309 return -EINVAL; 1310 1311 if (drm_color_lut_check(degamma_lut, degamma_tests) || 1312 drm_color_lut_check(gamma_lut, gamma_tests)) 1313 return -EINVAL; 1314 1315 return 0; 1316 } 1317 1318 static u32 i9xx_gamma_mode(struct intel_crtc_state *crtc_state) 1319 { 1320 if (!crtc_state->gamma_enable || 1321 crtc_state_is_legacy_gamma(crtc_state)) 1322 return GAMMA_MODE_MODE_8BIT; 1323 else 1324 return GAMMA_MODE_MODE_10BIT; /* i965+ only */ 1325 } 1326 1327 static int i9xx_color_check(struct intel_crtc_state *crtc_state) 1328 { 1329 int ret; 1330 1331 ret = check_luts(crtc_state); 1332 if (ret) 1333 return ret; 1334 1335 crtc_state->gamma_enable = 1336 crtc_state->hw.gamma_lut && 1337 !crtc_state->c8_planes; 1338 1339 crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state); 1340 1341 ret = intel_color_add_affected_planes(crtc_state); 1342 if (ret) 1343 return ret; 1344 1345 crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 1346 1347 return 0; 1348 } 1349 1350 static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state) 1351 { 1352 u32 cgm_mode = 0; 1353 1354 if (crtc_state_is_legacy_gamma(crtc_state)) 1355 return 0; 1356 1357 if (crtc_state->hw.degamma_lut) 1358 cgm_mode |= CGM_PIPE_MODE_DEGAMMA; 1359 if (crtc_state->hw.ctm) 1360 cgm_mode |= CGM_PIPE_MODE_CSC; 1361 if (crtc_state->hw.gamma_lut) 1362 cgm_mode |= CGM_PIPE_MODE_GAMMA; 1363 1364 return cgm_mode; 1365 } 1366 1367 /* 1368 * CHV color pipeline: 1369 * u0.10 -> CGM degamma -> u0.14 -> CGM csc -> u0.14 -> CGM gamma -> 1370 * u0.10 -> WGC csc -> u0.10 -> pipe gamma -> u0.10 1371 * 1372 * We always bypass the WGC csc and use the CGM csc 1373 * instead since it has degamma and better precision. 1374 */ 1375 static int chv_color_check(struct intel_crtc_state *crtc_state) 1376 { 1377 int ret; 1378 1379 ret = check_luts(crtc_state); 1380 if (ret) 1381 return ret; 1382 1383 /* 1384 * Pipe gamma will be used only for the legacy LUT. 1385 * Otherwise we bypass it and use the CGM gamma instead. 1386 */ 1387 crtc_state->gamma_enable = 1388 crtc_state_is_legacy_gamma(crtc_state) && 1389 !crtc_state->c8_planes; 1390 1391 crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT; 1392 1393 crtc_state->cgm_mode = chv_cgm_mode(crtc_state); 1394 1395 ret = intel_color_add_affected_planes(crtc_state); 1396 if (ret) 1397 return ret; 1398 1399 crtc_state->preload_luts = chv_can_preload_luts(crtc_state); 1400 1401 return 0; 1402 } 1403 1404 static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state) 1405 { 1406 if (!crtc_state->gamma_enable || 1407 crtc_state_is_legacy_gamma(crtc_state)) 1408 return GAMMA_MODE_MODE_8BIT; 1409 else 1410 return GAMMA_MODE_MODE_10BIT; 1411 } 1412 1413 static u32 ilk_csc_mode(const struct intel_crtc_state *crtc_state) 1414 { 1415 /* 1416 * CSC comes after the LUT in RGB->YCbCr mode. 1417 * RGB->YCbCr needs the limited range offsets added to 1418 * the output. RGB limited range output is handled by 1419 * the hw automagically elsewhere. 1420 */ 1421 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 1422 return CSC_BLACK_SCREEN_OFFSET; 1423 1424 return CSC_MODE_YUV_TO_RGB | 1425 CSC_POSITION_BEFORE_GAMMA; 1426 } 1427 1428 static int ilk_color_check(struct intel_crtc_state *crtc_state) 1429 { 1430 int ret; 1431 1432 ret = check_luts(crtc_state); 1433 if (ret) 1434 return ret; 1435 1436 crtc_state->gamma_enable = 1437 crtc_state->hw.gamma_lut && 1438 !crtc_state->c8_planes; 1439 1440 /* 1441 * We don't expose the ctm on ilk/snb currently, also RGB 1442 * limited range output is handled by the hw automagically. 1443 */ 1444 crtc_state->csc_enable = 1445 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB; 1446 1447 crtc_state->gamma_mode = ilk_gamma_mode(crtc_state); 1448 1449 crtc_state->csc_mode = ilk_csc_mode(crtc_state); 1450 1451 ret = intel_color_add_affected_planes(crtc_state); 1452 if (ret) 1453 return ret; 1454 1455 crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 1456 1457 return 0; 1458 } 1459 1460 static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state) 1461 { 1462 if (!crtc_state->gamma_enable || 1463 crtc_state_is_legacy_gamma(crtc_state)) 1464 return GAMMA_MODE_MODE_8BIT; 1465 else if (crtc_state->hw.gamma_lut && 1466 crtc_state->hw.degamma_lut) 1467 return GAMMA_MODE_MODE_SPLIT; 1468 else 1469 return GAMMA_MODE_MODE_10BIT; 1470 } 1471 1472 static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state) 1473 { 1474 bool limited_color_range = ilk_csc_limited_range(crtc_state); 1475 1476 /* 1477 * CSC comes after the LUT in degamma, RGB->YCbCr, 1478 * and RGB full->limited range mode. 1479 */ 1480 if (crtc_state->hw.degamma_lut || 1481 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || 1482 limited_color_range) 1483 return 0; 1484 1485 return CSC_POSITION_BEFORE_GAMMA; 1486 } 1487 1488 static int ivb_color_check(struct intel_crtc_state *crtc_state) 1489 { 1490 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1491 bool limited_color_range = ilk_csc_limited_range(crtc_state); 1492 int ret; 1493 1494 ret = check_luts(crtc_state); 1495 if (ret) 1496 return ret; 1497 1498 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB && 1499 crtc_state->hw.ctm) { 1500 drm_dbg_kms(&dev_priv->drm, 1501 "YCBCR and CTM together are not possible\n"); 1502 return -EINVAL; 1503 } 1504 1505 crtc_state->gamma_enable = 1506 (crtc_state->hw.gamma_lut || 1507 crtc_state->hw.degamma_lut) && 1508 !crtc_state->c8_planes; 1509 1510 crtc_state->csc_enable = 1511 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || 1512 crtc_state->hw.ctm || limited_color_range; 1513 1514 crtc_state->gamma_mode = ivb_gamma_mode(crtc_state); 1515 1516 crtc_state->csc_mode = ivb_csc_mode(crtc_state); 1517 1518 ret = intel_color_add_affected_planes(crtc_state); 1519 if (ret) 1520 return ret; 1521 1522 crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 1523 1524 return 0; 1525 } 1526 1527 static u32 glk_gamma_mode(const struct intel_crtc_state *crtc_state) 1528 { 1529 if (!crtc_state->gamma_enable || 1530 crtc_state_is_legacy_gamma(crtc_state)) 1531 return GAMMA_MODE_MODE_8BIT; 1532 else 1533 return GAMMA_MODE_MODE_10BIT; 1534 } 1535 1536 static int glk_color_check(struct intel_crtc_state *crtc_state) 1537 { 1538 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1539 int ret; 1540 1541 ret = check_luts(crtc_state); 1542 if (ret) 1543 return ret; 1544 1545 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB && 1546 crtc_state->hw.ctm) { 1547 drm_dbg_kms(&dev_priv->drm, 1548 "YCBCR and CTM together are not possible\n"); 1549 return -EINVAL; 1550 } 1551 1552 crtc_state->gamma_enable = 1553 crtc_state->hw.gamma_lut && 1554 !crtc_state->c8_planes; 1555 1556 /* On GLK+ degamma LUT is controlled by csc_enable */ 1557 crtc_state->csc_enable = 1558 crtc_state->hw.degamma_lut || 1559 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || 1560 crtc_state->hw.ctm || crtc_state->limited_color_range; 1561 1562 crtc_state->gamma_mode = glk_gamma_mode(crtc_state); 1563 1564 crtc_state->csc_mode = 0; 1565 1566 ret = intel_color_add_affected_planes(crtc_state); 1567 if (ret) 1568 return ret; 1569 1570 crtc_state->preload_luts = glk_can_preload_luts(crtc_state); 1571 1572 return 0; 1573 } 1574 1575 static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state) 1576 { 1577 u32 gamma_mode = 0; 1578 1579 if (crtc_state->hw.degamma_lut) 1580 gamma_mode |= PRE_CSC_GAMMA_ENABLE; 1581 1582 if (crtc_state->hw.gamma_lut && 1583 !crtc_state->c8_planes) 1584 gamma_mode |= POST_CSC_GAMMA_ENABLE; 1585 1586 if (!crtc_state->hw.gamma_lut || 1587 crtc_state_is_legacy_gamma(crtc_state)) 1588 gamma_mode |= GAMMA_MODE_MODE_8BIT; 1589 else 1590 gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED; 1591 1592 return gamma_mode; 1593 } 1594 1595 static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state) 1596 { 1597 u32 csc_mode = 0; 1598 1599 if (crtc_state->hw.ctm) 1600 csc_mode |= ICL_CSC_ENABLE; 1601 1602 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || 1603 crtc_state->limited_color_range) 1604 csc_mode |= ICL_OUTPUT_CSC_ENABLE; 1605 1606 return csc_mode; 1607 } 1608 1609 static int icl_color_check(struct intel_crtc_state *crtc_state) 1610 { 1611 int ret; 1612 1613 ret = check_luts(crtc_state); 1614 if (ret) 1615 return ret; 1616 1617 crtc_state->gamma_mode = icl_gamma_mode(crtc_state); 1618 1619 crtc_state->csc_mode = icl_csc_mode(crtc_state); 1620 1621 crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 1622 1623 return 0; 1624 } 1625 1626 static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state) 1627 { 1628 if (!crtc_state->gamma_enable) 1629 return 0; 1630 1631 switch (crtc_state->gamma_mode) { 1632 case GAMMA_MODE_MODE_8BIT: 1633 return 8; 1634 case GAMMA_MODE_MODE_10BIT: 1635 return 16; 1636 default: 1637 MISSING_CASE(crtc_state->gamma_mode); 1638 return 0; 1639 } 1640 } 1641 1642 static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state) 1643 { 1644 if (!crtc_state->gamma_enable) 1645 return 0; 1646 1647 if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0) 1648 return 0; 1649 1650 switch (crtc_state->gamma_mode) { 1651 case GAMMA_MODE_MODE_8BIT: 1652 return 8; 1653 case GAMMA_MODE_MODE_10BIT: 1654 return 10; 1655 default: 1656 MISSING_CASE(crtc_state->gamma_mode); 1657 return 0; 1658 } 1659 } 1660 1661 static int chv_gamma_precision(const struct intel_crtc_state *crtc_state) 1662 { 1663 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) 1664 return 10; 1665 else 1666 return i9xx_gamma_precision(crtc_state); 1667 } 1668 1669 static int glk_gamma_precision(const struct intel_crtc_state *crtc_state) 1670 { 1671 if (!crtc_state->gamma_enable) 1672 return 0; 1673 1674 switch (crtc_state->gamma_mode) { 1675 case GAMMA_MODE_MODE_8BIT: 1676 return 8; 1677 case GAMMA_MODE_MODE_10BIT: 1678 return 10; 1679 default: 1680 MISSING_CASE(crtc_state->gamma_mode); 1681 return 0; 1682 } 1683 } 1684 1685 static int icl_gamma_precision(const struct intel_crtc_state *crtc_state) 1686 { 1687 if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0) 1688 return 0; 1689 1690 switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { 1691 case GAMMA_MODE_MODE_8BIT: 1692 return 8; 1693 case GAMMA_MODE_MODE_10BIT: 1694 return 10; 1695 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: 1696 return 16; 1697 default: 1698 MISSING_CASE(crtc_state->gamma_mode); 1699 return 0; 1700 } 1701 } 1702 1703 int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state) 1704 { 1705 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1706 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1707 1708 if (HAS_GMCH(dev_priv)) { 1709 if (IS_CHERRYVIEW(dev_priv)) 1710 return chv_gamma_precision(crtc_state); 1711 else 1712 return i9xx_gamma_precision(crtc_state); 1713 } else { 1714 if (DISPLAY_VER(dev_priv) >= 11) 1715 return icl_gamma_precision(crtc_state); 1716 else if (DISPLAY_VER(dev_priv) == 10) 1717 return glk_gamma_precision(crtc_state); 1718 else if (IS_IRONLAKE(dev_priv)) 1719 return ilk_gamma_precision(crtc_state); 1720 } 1721 1722 return 0; 1723 } 1724 1725 static bool err_check(struct drm_color_lut *lut1, 1726 struct drm_color_lut *lut2, u32 err) 1727 { 1728 return ((abs((long)lut2->red - lut1->red)) <= err) && 1729 ((abs((long)lut2->blue - lut1->blue)) <= err) && 1730 ((abs((long)lut2->green - lut1->green)) <= err); 1731 } 1732 1733 static bool intel_color_lut_entries_equal(struct drm_color_lut *lut1, 1734 struct drm_color_lut *lut2, 1735 int lut_size, u32 err) 1736 { 1737 int i; 1738 1739 for (i = 0; i < lut_size; i++) { 1740 if (!err_check(&lut1[i], &lut2[i], err)) 1741 return false; 1742 } 1743 1744 return true; 1745 } 1746 1747 bool intel_color_lut_equal(struct drm_property_blob *blob1, 1748 struct drm_property_blob *blob2, 1749 u32 gamma_mode, u32 bit_precision) 1750 { 1751 struct drm_color_lut *lut1, *lut2; 1752 int lut_size1, lut_size2; 1753 u32 err; 1754 1755 if (!blob1 != !blob2) 1756 return false; 1757 1758 if (!blob1) 1759 return true; 1760 1761 lut_size1 = drm_color_lut_size(blob1); 1762 lut_size2 = drm_color_lut_size(blob2); 1763 1764 /* check sw and hw lut size */ 1765 if (lut_size1 != lut_size2) 1766 return false; 1767 1768 lut1 = blob1->data; 1769 lut2 = blob2->data; 1770 1771 err = 0xffff >> bit_precision; 1772 1773 /* check sw and hw lut entry to be equal */ 1774 switch (gamma_mode & GAMMA_MODE_MODE_MASK) { 1775 case GAMMA_MODE_MODE_8BIT: 1776 case GAMMA_MODE_MODE_10BIT: 1777 if (!intel_color_lut_entries_equal(lut1, lut2, 1778 lut_size2, err)) 1779 return false; 1780 break; 1781 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: 1782 if (!intel_color_lut_entries_equal(lut1, lut2, 1783 9, err)) 1784 return false; 1785 break; 1786 default: 1787 MISSING_CASE(gamma_mode); 1788 return false; 1789 } 1790 1791 return true; 1792 } 1793 1794 static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc) 1795 { 1796 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1797 enum pipe pipe = crtc->pipe; 1798 struct drm_property_blob *blob; 1799 struct drm_color_lut *lut; 1800 int i; 1801 1802 blob = drm_property_create_blob(&dev_priv->drm, 1803 sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH, 1804 NULL); 1805 if (IS_ERR(blob)) 1806 return NULL; 1807 1808 lut = blob->data; 1809 1810 for (i = 0; i < LEGACY_LUT_LENGTH; i++) { 1811 u32 val = intel_de_read(dev_priv, PALETTE(pipe, i)); 1812 1813 i9xx_lut_8_pack(&lut[i], val); 1814 } 1815 1816 return blob; 1817 } 1818 1819 static void i9xx_read_luts(struct intel_crtc_state *crtc_state) 1820 { 1821 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1822 1823 if (!crtc_state->gamma_enable) 1824 return; 1825 1826 crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc); 1827 } 1828 1829 static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc) 1830 { 1831 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1832 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; 1833 enum pipe pipe = crtc->pipe; 1834 struct drm_property_blob *blob; 1835 struct drm_color_lut *lut; 1836 1837 blob = drm_property_create_blob(&dev_priv->drm, 1838 sizeof(struct drm_color_lut) * lut_size, 1839 NULL); 1840 if (IS_ERR(blob)) 1841 return NULL; 1842 1843 lut = blob->data; 1844 1845 for (i = 0; i < lut_size - 1; i++) { 1846 u32 ldw = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 0)); 1847 u32 udw = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 1)); 1848 1849 i965_lut_10p6_pack(&lut[i], ldw, udw); 1850 } 1851 1852 lut[i].red = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 0))); 1853 lut[i].green = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 1))); 1854 lut[i].blue = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 2))); 1855 1856 return blob; 1857 } 1858 1859 static void i965_read_luts(struct intel_crtc_state *crtc_state) 1860 { 1861 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1862 1863 if (!crtc_state->gamma_enable) 1864 return; 1865 1866 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) 1867 crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc); 1868 else 1869 crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc); 1870 } 1871 1872 static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc) 1873 { 1874 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1875 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; 1876 enum pipe pipe = crtc->pipe; 1877 struct drm_property_blob *blob; 1878 struct drm_color_lut *lut; 1879 1880 blob = drm_property_create_blob(&dev_priv->drm, 1881 sizeof(struct drm_color_lut) * lut_size, 1882 NULL); 1883 if (IS_ERR(blob)) 1884 return NULL; 1885 1886 lut = blob->data; 1887 1888 for (i = 0; i < lut_size; i++) { 1889 u32 ldw = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0)); 1890 u32 udw = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1)); 1891 1892 chv_cgm_gamma_pack(&lut[i], ldw, udw); 1893 } 1894 1895 return blob; 1896 } 1897 1898 static void chv_read_luts(struct intel_crtc_state *crtc_state) 1899 { 1900 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1901 1902 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) 1903 crtc_state->hw.gamma_lut = chv_read_cgm_gamma(crtc); 1904 else 1905 i965_read_luts(crtc_state); 1906 } 1907 1908 static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc) 1909 { 1910 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1911 enum pipe pipe = crtc->pipe; 1912 struct drm_property_blob *blob; 1913 struct drm_color_lut *lut; 1914 int i; 1915 1916 blob = drm_property_create_blob(&dev_priv->drm, 1917 sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH, 1918 NULL); 1919 if (IS_ERR(blob)) 1920 return NULL; 1921 1922 lut = blob->data; 1923 1924 for (i = 0; i < LEGACY_LUT_LENGTH; i++) { 1925 u32 val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i)); 1926 1927 i9xx_lut_8_pack(&lut[i], val); 1928 } 1929 1930 return blob; 1931 } 1932 1933 static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc) 1934 { 1935 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1936 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; 1937 enum pipe pipe = crtc->pipe; 1938 struct drm_property_blob *blob; 1939 struct drm_color_lut *lut; 1940 1941 blob = drm_property_create_blob(&dev_priv->drm, 1942 sizeof(struct drm_color_lut) * lut_size, 1943 NULL); 1944 if (IS_ERR(blob)) 1945 return NULL; 1946 1947 lut = blob->data; 1948 1949 for (i = 0; i < lut_size; i++) { 1950 u32 val = intel_de_read(dev_priv, PREC_PALETTE(pipe, i)); 1951 1952 ilk_lut_10_pack(&lut[i], val); 1953 } 1954 1955 return blob; 1956 } 1957 1958 static void ilk_read_luts(struct intel_crtc_state *crtc_state) 1959 { 1960 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1961 1962 if (!crtc_state->gamma_enable) 1963 return; 1964 1965 if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0) 1966 return; 1967 1968 switch (crtc_state->gamma_mode) { 1969 case GAMMA_MODE_MODE_8BIT: 1970 crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc); 1971 break; 1972 case GAMMA_MODE_MODE_10BIT: 1973 crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc); 1974 break; 1975 default: 1976 MISSING_CASE(crtc_state->gamma_mode); 1977 break; 1978 } 1979 } 1980 1981 /* On BDW+ the index auto increment mode actually works */ 1982 static struct drm_property_blob *bdw_read_lut_10(struct intel_crtc *crtc, 1983 u32 prec_index) 1984 { 1985 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1986 int i, hw_lut_size = ivb_lut_10_size(prec_index); 1987 int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; 1988 enum pipe pipe = crtc->pipe; 1989 struct drm_property_blob *blob; 1990 struct drm_color_lut *lut; 1991 1992 drm_WARN_ON(&dev_priv->drm, lut_size != hw_lut_size); 1993 1994 blob = drm_property_create_blob(&dev_priv->drm, 1995 sizeof(struct drm_color_lut) * lut_size, 1996 NULL); 1997 if (IS_ERR(blob)) 1998 return NULL; 1999 2000 lut = blob->data; 2001 2002 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 2003 prec_index | PAL_PREC_AUTO_INCREMENT); 2004 2005 for (i = 0; i < lut_size; i++) { 2006 u32 val = intel_de_read(dev_priv, PREC_PAL_DATA(pipe)); 2007 2008 ilk_lut_10_pack(&lut[i], val); 2009 } 2010 2011 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0); 2012 2013 return blob; 2014 } 2015 2016 static void glk_read_luts(struct intel_crtc_state *crtc_state) 2017 { 2018 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2019 2020 if (!crtc_state->gamma_enable) 2021 return; 2022 2023 switch (crtc_state->gamma_mode) { 2024 case GAMMA_MODE_MODE_8BIT: 2025 crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc); 2026 break; 2027 case GAMMA_MODE_MODE_10BIT: 2028 crtc_state->hw.gamma_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0)); 2029 break; 2030 default: 2031 MISSING_CASE(crtc_state->gamma_mode); 2032 break; 2033 } 2034 } 2035 2036 static struct drm_property_blob * 2037 icl_read_lut_multi_segment(struct intel_crtc *crtc) 2038 { 2039 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2040 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; 2041 enum pipe pipe = crtc->pipe; 2042 struct drm_property_blob *blob; 2043 struct drm_color_lut *lut; 2044 2045 blob = drm_property_create_blob(&dev_priv->drm, 2046 sizeof(struct drm_color_lut) * lut_size, 2047 NULL); 2048 if (IS_ERR(blob)) 2049 return NULL; 2050 2051 lut = blob->data; 2052 2053 intel_de_write(dev_priv, PREC_PAL_MULTI_SEG_INDEX(pipe), 2054 PAL_PREC_AUTO_INCREMENT); 2055 2056 for (i = 0; i < 9; i++) { 2057 u32 ldw = intel_de_read(dev_priv, PREC_PAL_MULTI_SEG_DATA(pipe)); 2058 u32 udw = intel_de_read(dev_priv, PREC_PAL_MULTI_SEG_DATA(pipe)); 2059 2060 icl_lut_multi_seg_pack(&lut[i], ldw, udw); 2061 } 2062 2063 intel_de_write(dev_priv, PREC_PAL_MULTI_SEG_INDEX(pipe), 0); 2064 2065 /* 2066 * FIXME readouts from PAL_PREC_DATA register aren't giving 2067 * correct values in the case of fine and coarse segments. 2068 * Restricting readouts only for super fine segment as of now. 2069 */ 2070 2071 return blob; 2072 } 2073 2074 static void icl_read_luts(struct intel_crtc_state *crtc_state) 2075 { 2076 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2077 2078 if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0) 2079 return; 2080 2081 switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { 2082 case GAMMA_MODE_MODE_8BIT: 2083 crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc); 2084 break; 2085 case GAMMA_MODE_MODE_10BIT: 2086 crtc_state->hw.gamma_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0)); 2087 break; 2088 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: 2089 crtc_state->hw.gamma_lut = icl_read_lut_multi_segment(crtc); 2090 break; 2091 default: 2092 MISSING_CASE(crtc_state->gamma_mode); 2093 break; 2094 } 2095 } 2096 2097 static const struct intel_color_funcs chv_color_funcs = { 2098 .color_check = chv_color_check, 2099 .color_commit = i9xx_color_commit, 2100 .load_luts = chv_load_luts, 2101 .read_luts = chv_read_luts, 2102 }; 2103 2104 static const struct intel_color_funcs i965_color_funcs = { 2105 .color_check = i9xx_color_check, 2106 .color_commit = i9xx_color_commit, 2107 .load_luts = i965_load_luts, 2108 .read_luts = i965_read_luts, 2109 }; 2110 2111 static const struct intel_color_funcs i9xx_color_funcs = { 2112 .color_check = i9xx_color_check, 2113 .color_commit = i9xx_color_commit, 2114 .load_luts = i9xx_load_luts, 2115 .read_luts = i9xx_read_luts, 2116 }; 2117 2118 static const struct intel_color_funcs icl_color_funcs = { 2119 .color_check = icl_color_check, 2120 .color_commit = skl_color_commit, 2121 .load_luts = icl_load_luts, 2122 .read_luts = icl_read_luts, 2123 }; 2124 2125 static const struct intel_color_funcs glk_color_funcs = { 2126 .color_check = glk_color_check, 2127 .color_commit = skl_color_commit, 2128 .load_luts = glk_load_luts, 2129 .read_luts = glk_read_luts, 2130 }; 2131 2132 static const struct intel_color_funcs skl_color_funcs = { 2133 .color_check = ivb_color_check, 2134 .color_commit = skl_color_commit, 2135 .load_luts = bdw_load_luts, 2136 .read_luts = NULL, 2137 }; 2138 2139 static const struct intel_color_funcs bdw_color_funcs = { 2140 .color_check = ivb_color_check, 2141 .color_commit = hsw_color_commit, 2142 .load_luts = bdw_load_luts, 2143 .read_luts = NULL, 2144 }; 2145 2146 static const struct intel_color_funcs hsw_color_funcs = { 2147 .color_check = ivb_color_check, 2148 .color_commit = hsw_color_commit, 2149 .load_luts = ivb_load_luts, 2150 .read_luts = NULL, 2151 }; 2152 2153 static const struct intel_color_funcs ivb_color_funcs = { 2154 .color_check = ivb_color_check, 2155 .color_commit = ilk_color_commit, 2156 .load_luts = ivb_load_luts, 2157 .read_luts = NULL, 2158 }; 2159 2160 static const struct intel_color_funcs ilk_color_funcs = { 2161 .color_check = ilk_color_check, 2162 .color_commit = ilk_color_commit, 2163 .load_luts = ilk_load_luts, 2164 .read_luts = ilk_read_luts, 2165 }; 2166 2167 void intel_color_init(struct intel_crtc *crtc) 2168 { 2169 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2170 bool has_ctm = INTEL_INFO(dev_priv)->color.degamma_lut_size != 0; 2171 2172 drm_mode_crtc_set_gamma_size(&crtc->base, 256); 2173 2174 if (HAS_GMCH(dev_priv)) { 2175 if (IS_CHERRYVIEW(dev_priv)) { 2176 dev_priv->color_funcs = &chv_color_funcs; 2177 } else if (DISPLAY_VER(dev_priv) >= 4) { 2178 dev_priv->color_funcs = &i965_color_funcs; 2179 } else { 2180 dev_priv->color_funcs = &i9xx_color_funcs; 2181 } 2182 } else { 2183 if (DISPLAY_VER(dev_priv) >= 11) 2184 dev_priv->color_funcs = &icl_color_funcs; 2185 else if (DISPLAY_VER(dev_priv) == 10) 2186 dev_priv->color_funcs = &glk_color_funcs; 2187 else if (DISPLAY_VER(dev_priv) == 9) 2188 dev_priv->color_funcs = &skl_color_funcs; 2189 else if (DISPLAY_VER(dev_priv) == 8) 2190 dev_priv->color_funcs = &bdw_color_funcs; 2191 else if (DISPLAY_VER(dev_priv) == 7) { 2192 if (IS_HASWELL(dev_priv)) 2193 dev_priv->color_funcs = &hsw_color_funcs; 2194 else 2195 dev_priv->color_funcs = &ivb_color_funcs; 2196 } else 2197 dev_priv->color_funcs = &ilk_color_funcs; 2198 } 2199 2200 drm_crtc_enable_color_mgmt(&crtc->base, 2201 INTEL_INFO(dev_priv)->color.degamma_lut_size, 2202 has_ctm, 2203 INTEL_INFO(dev_priv)->color.gamma_lut_size); 2204 } 2205