1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include "intel_color.h" 26 #include "intel_de.h" 27 #include "intel_display_types.h" 28 #include "intel_dpll.h" 29 #include "vlv_dsi_pll.h" 30 31 struct intel_color_funcs { 32 int (*color_check)(struct intel_crtc_state *crtc_state); 33 /* 34 * Program non-arming double buffered color management registers 35 * before vblank evasion. The registers should then latch after 36 * the arming register is written (by color_commit_arm()) during 37 * the next vblank start, alongside any other double buffered 38 * registers involved with the same commit. This hook is optional. 39 */ 40 void (*color_commit_noarm)(const struct intel_crtc_state *crtc_state); 41 /* 42 * Program arming double buffered color management registers 43 * during vblank evasion. The registers (and whatever other registers 44 * they arm that were written by color_commit_noarm) should then latch 45 * during the next vblank start, alongside any other double buffered 46 * registers involved with the same commit. 47 */ 48 void (*color_commit_arm)(const struct intel_crtc_state *crtc_state); 49 /* 50 * Load LUTs (and other single buffered color management 51 * registers). Will (hopefully) be called during the vblank 52 * following the latching of any double buffered registers 53 * involved with the same commit. 54 */ 55 void (*load_luts)(const struct intel_crtc_state *crtc_state); 56 void (*read_luts)(struct intel_crtc_state *crtc_state); 57 }; 58 59 #define CTM_COEFF_SIGN (1ULL << 63) 60 61 #define CTM_COEFF_1_0 (1ULL << 32) 62 #define CTM_COEFF_2_0 (CTM_COEFF_1_0 << 1) 63 #define CTM_COEFF_4_0 (CTM_COEFF_2_0 << 1) 64 #define CTM_COEFF_8_0 (CTM_COEFF_4_0 << 1) 65 #define CTM_COEFF_0_5 (CTM_COEFF_1_0 >> 1) 66 #define CTM_COEFF_0_25 (CTM_COEFF_0_5 >> 1) 67 #define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1) 68 69 #define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255) 70 71 #define CTM_COEFF_NEGATIVE(coeff) (((coeff) & CTM_COEFF_SIGN) != 0) 72 #define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1)) 73 74 #define LEGACY_LUT_LENGTH 256 75 76 /* 77 * ILK+ csc matrix: 78 * 79 * |R/Cr| | c0 c1 c2 | ( |R/Cr| |preoff0| ) |postoff0| 80 * |G/Y | = | c3 c4 c5 | x ( |G/Y | + |preoff1| ) + |postoff1| 81 * |B/Cb| | c6 c7 c8 | ( |B/Cb| |preoff2| ) |postoff2| 82 * 83 * ILK/SNB don't have explicit post offsets, and instead 84 * CSC_MODE_YUV_TO_RGB and CSC_BLACK_SCREEN_OFFSET are used: 85 * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=0 -> 1/2, 0, 1/2 86 * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/2, 1/16, 1/2 87 * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=0 -> 0, 0, 0 88 * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/16, 1/16, 1/16 89 */ 90 91 /* 92 * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point 93 * format). This macro takes the coefficient we want transformed and the 94 * number of fractional bits. 95 * 96 * We only have a 9 bits precision window which slides depending on the value 97 * of the CTM coefficient and we write the value from bit 3. We also round the 98 * value. 99 */ 100 #define ILK_CSC_COEFF_FP(coeff, fbits) \ 101 (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8) 102 103 #define ILK_CSC_COEFF_LIMITED_RANGE 0x0dc0 104 #define ILK_CSC_COEFF_1_0 0x7800 105 106 #define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255) 107 108 /* Nop pre/post offsets */ 109 static const u16 ilk_csc_off_zero[3] = {}; 110 111 /* Identity matrix */ 112 static const u16 ilk_csc_coeff_identity[9] = { 113 ILK_CSC_COEFF_1_0, 0, 0, 114 0, ILK_CSC_COEFF_1_0, 0, 115 0, 0, ILK_CSC_COEFF_1_0, 116 }; 117 118 /* Limited range RGB post offsets */ 119 static const u16 ilk_csc_postoff_limited_range[3] = { 120 ILK_CSC_POSTOFF_LIMITED_RANGE, 121 ILK_CSC_POSTOFF_LIMITED_RANGE, 122 ILK_CSC_POSTOFF_LIMITED_RANGE, 123 }; 124 125 /* Full range RGB -> limited range RGB matrix */ 126 static const u16 ilk_csc_coeff_limited_range[9] = { 127 ILK_CSC_COEFF_LIMITED_RANGE, 0, 0, 128 0, ILK_CSC_COEFF_LIMITED_RANGE, 0, 129 0, 0, ILK_CSC_COEFF_LIMITED_RANGE, 130 }; 131 132 /* BT.709 full range RGB -> limited range YCbCr matrix */ 133 static const u16 ilk_csc_coeff_rgb_to_ycbcr[9] = { 134 0x1e08, 0x9cc0, 0xb528, 135 0x2ba8, 0x09d8, 0x37e8, 136 0xbce8, 0x9ad8, 0x1e08, 137 }; 138 139 /* Limited range YCbCr post offsets */ 140 static const u16 ilk_csc_postoff_rgb_to_ycbcr[3] = { 141 0x0800, 0x0100, 0x0800, 142 }; 143 144 static bool lut_is_legacy(const struct drm_property_blob *lut) 145 { 146 return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH; 147 } 148 149 static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state) 150 { 151 return !crtc_state->hw.degamma_lut && 152 !crtc_state->hw.ctm && 153 crtc_state->hw.gamma_lut && 154 lut_is_legacy(crtc_state->hw.gamma_lut); 155 } 156 157 /* 158 * When using limited range, multiply the matrix given by userspace by 159 * the matrix that we would use for the limited range. 160 */ 161 static u64 *ctm_mult_by_limited(u64 *result, const u64 *input) 162 { 163 int i; 164 165 for (i = 0; i < 9; i++) { 166 u64 user_coeff = input[i]; 167 u32 limited_coeff = CTM_COEFF_LIMITED_RANGE; 168 u32 abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff), 0, 169 CTM_COEFF_4_0 - 1) >> 2; 170 171 /* 172 * By scaling every co-efficient with limited range (16-235) 173 * vs full range (0-255) the final o/p will be scaled down to 174 * fit in the limited range supported by the panel. 175 */ 176 result[i] = mul_u32_u32(limited_coeff, abs_coeff) >> 30; 177 result[i] |= user_coeff & CTM_COEFF_SIGN; 178 } 179 180 return result; 181 } 182 183 static void ilk_update_pipe_csc(struct intel_crtc *crtc, 184 const u16 preoff[3], 185 const u16 coeff[9], 186 const u16 postoff[3]) 187 { 188 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 189 enum pipe pipe = crtc->pipe; 190 191 intel_de_write_fw(dev_priv, PIPE_CSC_PREOFF_HI(pipe), preoff[0]); 192 intel_de_write_fw(dev_priv, PIPE_CSC_PREOFF_ME(pipe), preoff[1]); 193 intel_de_write_fw(dev_priv, PIPE_CSC_PREOFF_LO(pipe), preoff[2]); 194 195 intel_de_write_fw(dev_priv, PIPE_CSC_COEFF_RY_GY(pipe), 196 coeff[0] << 16 | coeff[1]); 197 intel_de_write_fw(dev_priv, PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16); 198 199 intel_de_write_fw(dev_priv, PIPE_CSC_COEFF_RU_GU(pipe), 200 coeff[3] << 16 | coeff[4]); 201 intel_de_write_fw(dev_priv, PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16); 202 203 intel_de_write_fw(dev_priv, PIPE_CSC_COEFF_RV_GV(pipe), 204 coeff[6] << 16 | coeff[7]); 205 intel_de_write_fw(dev_priv, PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16); 206 207 if (DISPLAY_VER(dev_priv) >= 7) { 208 intel_de_write_fw(dev_priv, PIPE_CSC_POSTOFF_HI(pipe), 209 postoff[0]); 210 intel_de_write_fw(dev_priv, PIPE_CSC_POSTOFF_ME(pipe), 211 postoff[1]); 212 intel_de_write_fw(dev_priv, PIPE_CSC_POSTOFF_LO(pipe), 213 postoff[2]); 214 } 215 } 216 217 static void icl_update_output_csc(struct intel_crtc *crtc, 218 const u16 preoff[3], 219 const u16 coeff[9], 220 const u16 postoff[3]) 221 { 222 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 223 enum pipe pipe = crtc->pipe; 224 225 intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_PREOFF_HI(pipe), preoff[0]); 226 intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_PREOFF_ME(pipe), preoff[1]); 227 intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]); 228 229 intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe), 230 coeff[0] << 16 | coeff[1]); 231 intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_COEFF_BY(pipe), 232 coeff[2] << 16); 233 234 intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe), 235 coeff[3] << 16 | coeff[4]); 236 intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_COEFF_BU(pipe), 237 coeff[5] << 16); 238 239 intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe), 240 coeff[6] << 16 | coeff[7]); 241 intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_COEFF_BV(pipe), 242 coeff[8] << 16); 243 244 intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]); 245 intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]); 246 intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), postoff[2]); 247 } 248 249 static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state) 250 { 251 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 252 253 /* 254 * FIXME if there's a gamma LUT after the CSC, we should 255 * do the range compression using the gamma LUT instead. 256 */ 257 return crtc_state->limited_color_range && 258 (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) || 259 IS_DISPLAY_VER(dev_priv, 9, 10)); 260 } 261 262 static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state, 263 u16 coeffs[9]) 264 { 265 const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data; 266 const u64 *input; 267 u64 temp[9]; 268 int i; 269 270 if (ilk_csc_limited_range(crtc_state)) 271 input = ctm_mult_by_limited(temp, ctm->matrix); 272 else 273 input = ctm->matrix; 274 275 /* 276 * Convert fixed point S31.32 input to format supported by the 277 * hardware. 278 */ 279 for (i = 0; i < 9; i++) { 280 u64 abs_coeff = ((1ULL << 63) - 1) & input[i]; 281 282 /* 283 * Clamp input value to min/max supported by 284 * hardware. 285 */ 286 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1); 287 288 coeffs[i] = 0; 289 290 /* sign bit */ 291 if (CTM_COEFF_NEGATIVE(input[i])) 292 coeffs[i] |= 1 << 15; 293 294 if (abs_coeff < CTM_COEFF_0_125) 295 coeffs[i] |= (3 << 12) | 296 ILK_CSC_COEFF_FP(abs_coeff, 12); 297 else if (abs_coeff < CTM_COEFF_0_25) 298 coeffs[i] |= (2 << 12) | 299 ILK_CSC_COEFF_FP(abs_coeff, 11); 300 else if (abs_coeff < CTM_COEFF_0_5) 301 coeffs[i] |= (1 << 12) | 302 ILK_CSC_COEFF_FP(abs_coeff, 10); 303 else if (abs_coeff < CTM_COEFF_1_0) 304 coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9); 305 else if (abs_coeff < CTM_COEFF_2_0) 306 coeffs[i] |= (7 << 12) | 307 ILK_CSC_COEFF_FP(abs_coeff, 8); 308 else 309 coeffs[i] |= (6 << 12) | 310 ILK_CSC_COEFF_FP(abs_coeff, 7); 311 } 312 } 313 314 static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state) 315 { 316 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 317 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 318 bool limited_color_range = ilk_csc_limited_range(crtc_state); 319 320 if (crtc_state->hw.ctm) { 321 u16 coeff[9]; 322 323 ilk_csc_convert_ctm(crtc_state, coeff); 324 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeff, 325 limited_color_range ? 326 ilk_csc_postoff_limited_range : 327 ilk_csc_off_zero); 328 } else if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) { 329 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, 330 ilk_csc_coeff_rgb_to_ycbcr, 331 ilk_csc_postoff_rgb_to_ycbcr); 332 } else if (limited_color_range) { 333 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, 334 ilk_csc_coeff_limited_range, 335 ilk_csc_postoff_limited_range); 336 } else if (crtc_state->csc_enable) { 337 /* 338 * On GLK both pipe CSC and degamma LUT are controlled 339 * by csc_enable. Hence for the cases where the degama 340 * LUT is needed but CSC is not we need to load an 341 * identity matrix. 342 */ 343 drm_WARN_ON(&dev_priv->drm, !IS_GEMINILAKE(dev_priv)); 344 345 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, 346 ilk_csc_coeff_identity, 347 ilk_csc_off_zero); 348 } 349 } 350 351 static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state) 352 { 353 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 354 355 if (crtc_state->hw.ctm) { 356 u16 coeff[9]; 357 358 ilk_csc_convert_ctm(crtc_state, coeff); 359 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, 360 coeff, ilk_csc_off_zero); 361 } 362 363 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) { 364 icl_update_output_csc(crtc, ilk_csc_off_zero, 365 ilk_csc_coeff_rgb_to_ycbcr, 366 ilk_csc_postoff_rgb_to_ycbcr); 367 } else if (crtc_state->limited_color_range) { 368 icl_update_output_csc(crtc, ilk_csc_off_zero, 369 ilk_csc_coeff_limited_range, 370 ilk_csc_postoff_limited_range); 371 } 372 } 373 374 static void chv_load_cgm_csc(struct intel_crtc *crtc, 375 const struct drm_property_blob *blob) 376 { 377 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 378 const struct drm_color_ctm *ctm = blob->data; 379 enum pipe pipe = crtc->pipe; 380 u16 coeffs[9]; 381 int i; 382 383 for (i = 0; i < ARRAY_SIZE(coeffs); i++) { 384 u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i]; 385 386 /* Round coefficient. */ 387 abs_coeff += 1 << (32 - 13); 388 /* Clamp to hardware limits. */ 389 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1); 390 391 coeffs[i] = 0; 392 393 /* Write coefficients in S3.12 format. */ 394 if (ctm->matrix[i] & (1ULL << 63)) 395 coeffs[i] |= 1 << 15; 396 397 coeffs[i] |= ((abs_coeff >> 32) & 7) << 12; 398 coeffs[i] |= (abs_coeff >> 20) & 0xfff; 399 } 400 401 intel_de_write_fw(dev_priv, CGM_PIPE_CSC_COEFF01(pipe), 402 coeffs[1] << 16 | coeffs[0]); 403 intel_de_write_fw(dev_priv, CGM_PIPE_CSC_COEFF23(pipe), 404 coeffs[3] << 16 | coeffs[2]); 405 intel_de_write_fw(dev_priv, CGM_PIPE_CSC_COEFF45(pipe), 406 coeffs[5] << 16 | coeffs[4]); 407 intel_de_write_fw(dev_priv, CGM_PIPE_CSC_COEFF67(pipe), 408 coeffs[7] << 16 | coeffs[6]); 409 intel_de_write_fw(dev_priv, CGM_PIPE_CSC_COEFF8(pipe), 410 coeffs[8]); 411 } 412 413 /* convert hw value with given bit_precision to lut property val */ 414 static u32 intel_color_lut_pack(u32 val, int bit_precision) 415 { 416 u32 max = 0xffff >> (16 - bit_precision); 417 418 val = clamp_val(val, 0, max); 419 420 if (bit_precision < 16) 421 val <<= 16 - bit_precision; 422 423 return val; 424 } 425 426 static u32 i9xx_lut_8(const struct drm_color_lut *color) 427 { 428 return drm_color_lut_extract(color->red, 8) << 16 | 429 drm_color_lut_extract(color->green, 8) << 8 | 430 drm_color_lut_extract(color->blue, 8); 431 } 432 433 static void i9xx_lut_8_pack(struct drm_color_lut *entry, u32 val) 434 { 435 entry->red = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_RED_MASK, val), 8); 436 entry->green = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_GREEN_MASK, val), 8); 437 entry->blue = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_BLUE_MASK, val), 8); 438 } 439 440 /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */ 441 static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color) 442 { 443 return (color->red & 0xff) << 16 | 444 (color->green & 0xff) << 8 | 445 (color->blue & 0xff); 446 } 447 448 /* i965+ "10.6" interpolated format "odd DW" (high 8 bits) */ 449 static u32 i965_lut_10p6_udw(const struct drm_color_lut *color) 450 { 451 return (color->red >> 8) << 16 | 452 (color->green >> 8) << 8 | 453 (color->blue >> 8); 454 } 455 456 static void i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) 457 { 458 entry->red = REG_FIELD_GET(PALETTE_RED_MASK, udw) << 8 | 459 REG_FIELD_GET(PALETTE_RED_MASK, ldw); 460 entry->green = REG_FIELD_GET(PALETTE_GREEN_MASK, udw) << 8 | 461 REG_FIELD_GET(PALETTE_GREEN_MASK, ldw); 462 entry->blue = REG_FIELD_GET(PALETTE_BLUE_MASK, udw) << 8 | 463 REG_FIELD_GET(PALETTE_BLUE_MASK, ldw); 464 } 465 466 static u16 i965_lut_11p6_max_pack(u32 val) 467 { 468 /* PIPEGCMAX is 11.6, clamp to 10.6 */ 469 return clamp_val(val, 0, 0xffff); 470 } 471 472 static u32 ilk_lut_10(const struct drm_color_lut *color) 473 { 474 return drm_color_lut_extract(color->red, 10) << 20 | 475 drm_color_lut_extract(color->green, 10) << 10 | 476 drm_color_lut_extract(color->blue, 10); 477 } 478 479 static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val) 480 { 481 entry->red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_RED_MASK, val), 10); 482 entry->green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_GREEN_MASK, val), 10); 483 entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10); 484 } 485 486 static void icl_lut_multi_seg_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) 487 { 488 entry->red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, udw) << 6 | 489 REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, ldw); 490 entry->green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, udw) << 6 | 491 REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, ldw); 492 entry->blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, udw) << 6 | 493 REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw); 494 } 495 496 static void icl_color_commit_noarm(const struct intel_crtc_state *crtc_state) 497 { 498 icl_load_csc_matrix(crtc_state); 499 } 500 501 static void ilk_color_commit_noarm(const struct intel_crtc_state *crtc_state) 502 { 503 ilk_load_csc_matrix(crtc_state); 504 } 505 506 static void i9xx_color_commit_arm(const struct intel_crtc_state *crtc_state) 507 { 508 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 509 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 510 enum pipe pipe = crtc->pipe; 511 u32 val; 512 513 val = intel_de_read(dev_priv, PIPECONF(pipe)); 514 val &= ~PIPECONF_GAMMA_MODE_MASK_I9XX; 515 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 516 intel_de_write(dev_priv, PIPECONF(pipe), val); 517 } 518 519 static void ilk_color_commit_arm(const struct intel_crtc_state *crtc_state) 520 { 521 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 522 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 523 enum pipe pipe = crtc->pipe; 524 u32 val; 525 526 val = intel_de_read(dev_priv, PIPECONF(pipe)); 527 val &= ~PIPECONF_GAMMA_MODE_MASK_ILK; 528 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 529 intel_de_write(dev_priv, PIPECONF(pipe), val); 530 531 intel_de_write_fw(dev_priv, PIPE_CSC_MODE(pipe), 532 crtc_state->csc_mode); 533 } 534 535 static void hsw_color_commit_arm(const struct intel_crtc_state *crtc_state) 536 { 537 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 538 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 539 540 intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe), 541 crtc_state->gamma_mode); 542 543 intel_de_write_fw(dev_priv, PIPE_CSC_MODE(crtc->pipe), 544 crtc_state->csc_mode); 545 } 546 547 static void skl_color_commit_arm(const struct intel_crtc_state *crtc_state) 548 { 549 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 550 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 551 enum pipe pipe = crtc->pipe; 552 u32 val = 0; 553 554 /* 555 * We don't (yet) allow userspace to control the pipe background color, 556 * so force it to black, but apply pipe gamma and CSC appropriately 557 * so that its handling will match how we program our planes. 558 */ 559 if (crtc_state->gamma_enable) 560 val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE; 561 if (crtc_state->csc_enable) 562 val |= SKL_BOTTOM_COLOR_CSC_ENABLE; 563 intel_de_write(dev_priv, SKL_BOTTOM_COLOR(pipe), val); 564 565 intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe), 566 crtc_state->gamma_mode); 567 568 intel_de_write_fw(dev_priv, PIPE_CSC_MODE(crtc->pipe), 569 crtc_state->csc_mode); 570 } 571 572 static void i9xx_load_lut_8(struct intel_crtc *crtc, 573 const struct drm_property_blob *blob) 574 { 575 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 576 const struct drm_color_lut *lut; 577 enum pipe pipe = crtc->pipe; 578 int i; 579 580 if (!blob) 581 return; 582 583 lut = blob->data; 584 585 for (i = 0; i < 256; i++) 586 intel_de_write_fw(dev_priv, PALETTE(pipe, i), 587 i9xx_lut_8(&lut[i])); 588 } 589 590 static void i9xx_load_luts(const struct intel_crtc_state *crtc_state) 591 { 592 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 593 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 594 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 595 596 assert_pll_enabled(dev_priv, crtc->pipe); 597 598 i9xx_load_lut_8(crtc, gamma_lut); 599 } 600 601 static void i965_load_lut_10p6(struct intel_crtc *crtc, 602 const struct drm_property_blob *blob) 603 { 604 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 605 const struct drm_color_lut *lut = blob->data; 606 int i, lut_size = drm_color_lut_size(blob); 607 enum pipe pipe = crtc->pipe; 608 609 for (i = 0; i < lut_size - 1; i++) { 610 intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 0), 611 i965_lut_10p6_ldw(&lut[i])); 612 intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 1), 613 i965_lut_10p6_udw(&lut[i])); 614 } 615 616 intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 0), lut[i].red); 617 intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 1), lut[i].green); 618 intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 2), lut[i].blue); 619 } 620 621 static void i965_load_luts(const struct intel_crtc_state *crtc_state) 622 { 623 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 624 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 625 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 626 627 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 628 assert_dsi_pll_enabled(dev_priv); 629 else 630 assert_pll_enabled(dev_priv, crtc->pipe); 631 632 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) 633 i9xx_load_lut_8(crtc, gamma_lut); 634 else 635 i965_load_lut_10p6(crtc, gamma_lut); 636 } 637 638 static void ilk_load_lut_8(struct intel_crtc *crtc, 639 const struct drm_property_blob *blob) 640 { 641 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 642 const struct drm_color_lut *lut; 643 enum pipe pipe = crtc->pipe; 644 int i; 645 646 if (!blob) 647 return; 648 649 lut = blob->data; 650 651 for (i = 0; i < 256; i++) 652 intel_de_write_fw(dev_priv, LGC_PALETTE(pipe, i), 653 i9xx_lut_8(&lut[i])); 654 } 655 656 static void ilk_load_lut_10(struct intel_crtc *crtc, 657 const struct drm_property_blob *blob) 658 { 659 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 660 const struct drm_color_lut *lut = blob->data; 661 int i, lut_size = drm_color_lut_size(blob); 662 enum pipe pipe = crtc->pipe; 663 664 for (i = 0; i < lut_size; i++) 665 intel_de_write_fw(dev_priv, PREC_PALETTE(pipe, i), 666 ilk_lut_10(&lut[i])); 667 } 668 669 static void ilk_load_luts(const struct intel_crtc_state *crtc_state) 670 { 671 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 672 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 673 674 switch (crtc_state->gamma_mode) { 675 case GAMMA_MODE_MODE_8BIT: 676 ilk_load_lut_8(crtc, gamma_lut); 677 break; 678 case GAMMA_MODE_MODE_10BIT: 679 ilk_load_lut_10(crtc, gamma_lut); 680 break; 681 default: 682 MISSING_CASE(crtc_state->gamma_mode); 683 break; 684 } 685 } 686 687 static int ivb_lut_10_size(u32 prec_index) 688 { 689 if (prec_index & PAL_PREC_SPLIT_MODE) 690 return 512; 691 else 692 return 1024; 693 } 694 695 /* 696 * IVB/HSW Bspec / PAL_PREC_INDEX: 697 * "Restriction : Index auto increment mode is not 698 * supported and must not be enabled." 699 */ 700 static void ivb_load_lut_10(struct intel_crtc *crtc, 701 const struct drm_property_blob *blob, 702 u32 prec_index) 703 { 704 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 705 int hw_lut_size = ivb_lut_10_size(prec_index); 706 const struct drm_color_lut *lut = blob->data; 707 int i, lut_size = drm_color_lut_size(blob); 708 enum pipe pipe = crtc->pipe; 709 710 for (i = 0; i < hw_lut_size; i++) { 711 /* We discard half the user entries in split gamma mode */ 712 const struct drm_color_lut *entry = 713 &lut[i * (lut_size - 1) / (hw_lut_size - 1)]; 714 715 intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe), prec_index++); 716 intel_de_write_fw(dev_priv, PREC_PAL_DATA(pipe), 717 ilk_lut_10(entry)); 718 } 719 720 /* 721 * Reset the index, otherwise it prevents the legacy palette to be 722 * written properly. 723 */ 724 intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe), 0); 725 } 726 727 /* On BDW+ the index auto increment mode actually works */ 728 static void bdw_load_lut_10(struct intel_crtc *crtc, 729 const struct drm_property_blob *blob, 730 u32 prec_index) 731 { 732 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 733 int hw_lut_size = ivb_lut_10_size(prec_index); 734 const struct drm_color_lut *lut = blob->data; 735 int i, lut_size = drm_color_lut_size(blob); 736 enum pipe pipe = crtc->pipe; 737 738 intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe), 739 prec_index | PAL_PREC_AUTO_INCREMENT); 740 741 for (i = 0; i < hw_lut_size; i++) { 742 /* We discard half the user entries in split gamma mode */ 743 const struct drm_color_lut *entry = 744 &lut[i * (lut_size - 1) / (hw_lut_size - 1)]; 745 746 intel_de_write_fw(dev_priv, PREC_PAL_DATA(pipe), 747 ilk_lut_10(entry)); 748 } 749 750 /* 751 * Reset the index, otherwise it prevents the legacy palette to be 752 * written properly. 753 */ 754 intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe), 0); 755 } 756 757 static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state) 758 { 759 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 760 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 761 enum pipe pipe = crtc->pipe; 762 763 /* Program the max register to clamp values > 1.0. */ 764 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16); 765 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16); 766 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16); 767 768 /* 769 * Program the gc max 2 register to clamp values > 1.0. 770 * ToDo: Extend the ABI to be able to program values 771 * from 3.0 to 7.0 772 */ 773 if (DISPLAY_VER(dev_priv) >= 10) { 774 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0), 775 1 << 16); 776 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1), 777 1 << 16); 778 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 2), 779 1 << 16); 780 } 781 } 782 783 static void ivb_load_luts(const struct intel_crtc_state *crtc_state) 784 { 785 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 786 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 787 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut; 788 const struct drm_property_blob *blob = gamma_lut ?: degamma_lut; 789 790 switch (crtc_state->gamma_mode) { 791 case GAMMA_MODE_MODE_8BIT: 792 ilk_load_lut_8(crtc, blob); 793 break; 794 case GAMMA_MODE_MODE_SPLIT: 795 ivb_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE | 796 PAL_PREC_INDEX_VALUE(0)); 797 ivb_load_lut_ext_max(crtc_state); 798 ivb_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE | 799 PAL_PREC_INDEX_VALUE(512)); 800 break; 801 case GAMMA_MODE_MODE_10BIT: 802 ivb_load_lut_10(crtc, blob, 803 PAL_PREC_INDEX_VALUE(0)); 804 ivb_load_lut_ext_max(crtc_state); 805 break; 806 default: 807 MISSING_CASE(crtc_state->gamma_mode); 808 break; 809 } 810 } 811 812 static void bdw_load_luts(const struct intel_crtc_state *crtc_state) 813 { 814 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 815 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 816 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut; 817 const struct drm_property_blob *blob = gamma_lut ?: degamma_lut; 818 819 switch (crtc_state->gamma_mode) { 820 case GAMMA_MODE_MODE_8BIT: 821 ilk_load_lut_8(crtc, blob); 822 break; 823 case GAMMA_MODE_MODE_SPLIT: 824 bdw_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE | 825 PAL_PREC_INDEX_VALUE(0)); 826 ivb_load_lut_ext_max(crtc_state); 827 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE | 828 PAL_PREC_INDEX_VALUE(512)); 829 break; 830 case GAMMA_MODE_MODE_10BIT: 831 832 bdw_load_lut_10(crtc, blob, 833 PAL_PREC_INDEX_VALUE(0)); 834 ivb_load_lut_ext_max(crtc_state); 835 break; 836 default: 837 MISSING_CASE(crtc_state->gamma_mode); 838 break; 839 } 840 } 841 842 static int glk_degamma_lut_size(struct drm_i915_private *i915) 843 { 844 if (DISPLAY_VER(i915) >= 13) 845 return 131; 846 else 847 return 35; 848 } 849 850 static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state) 851 { 852 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 853 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 854 enum pipe pipe = crtc->pipe; 855 int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; 856 const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data; 857 858 /* 859 * When setting the auto-increment bit, the hardware seems to 860 * ignore the index bits, so we need to reset it to index 0 861 * separately. 862 */ 863 intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0); 864 intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 865 PRE_CSC_GAMC_AUTO_INCREMENT); 866 867 for (i = 0; i < lut_size; i++) { 868 /* 869 * First lut_size entries represent range from 0 to 1.0 870 * 3 additional lut entries will represent extended range 871 * inputs 3.0 and 7.0 respectively, currently clamped 872 * at 1.0. Since the precision is 16bit, the user 873 * value can be directly filled to register. 874 * The pipe degamma table in GLK+ onwards doesn't 875 * support different values per channel, so this just 876 * programs green value which will be equal to Red and 877 * Blue into the lut registers. 878 * ToDo: Extend to max 7.0. Enable 32 bit input value 879 * as compared to just 16 to achieve this. 880 */ 881 intel_de_write_fw(dev_priv, PRE_CSC_GAMC_DATA(pipe), 882 lut[i].green); 883 } 884 885 /* Clamp values > 1.0. */ 886 while (i++ < glk_degamma_lut_size(dev_priv)) 887 intel_de_write_fw(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16); 888 889 intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0); 890 } 891 892 static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_state) 893 { 894 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 895 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 896 enum pipe pipe = crtc->pipe; 897 int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; 898 899 /* 900 * When setting the auto-increment bit, the hardware seems to 901 * ignore the index bits, so we need to reset it to index 0 902 * separately. 903 */ 904 intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0); 905 intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 906 PRE_CSC_GAMC_AUTO_INCREMENT); 907 908 for (i = 0; i < lut_size; i++) { 909 u32 v = (i << 16) / (lut_size - 1); 910 911 intel_de_write_fw(dev_priv, PRE_CSC_GAMC_DATA(pipe), v); 912 } 913 914 /* Clamp values > 1.0. */ 915 while (i++ < 35) 916 intel_de_write_fw(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16); 917 918 intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0); 919 } 920 921 static void glk_load_luts(const struct intel_crtc_state *crtc_state) 922 { 923 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 924 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 925 926 /* 927 * On GLK+ both pipe CSC and degamma LUT are controlled 928 * by csc_enable. Hence for the cases where the CSC is 929 * needed but degamma LUT is not we need to load a 930 * linear degamma LUT. In fact we'll just always load 931 * the degama LUT so that we don't have to reload 932 * it every time the pipe CSC is being enabled. 933 */ 934 if (crtc_state->hw.degamma_lut) 935 glk_load_degamma_lut(crtc_state); 936 else 937 glk_load_degamma_lut_linear(crtc_state); 938 939 switch (crtc_state->gamma_mode) { 940 case GAMMA_MODE_MODE_8BIT: 941 ilk_load_lut_8(crtc, gamma_lut); 942 break; 943 case GAMMA_MODE_MODE_10BIT: 944 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0)); 945 ivb_load_lut_ext_max(crtc_state); 946 break; 947 default: 948 MISSING_CASE(crtc_state->gamma_mode); 949 break; 950 } 951 } 952 953 /* ilk+ "12.4" interpolated format (high 10 bits) */ 954 static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color) 955 { 956 return (color->red >> 6) << 20 | (color->green >> 6) << 10 | 957 (color->blue >> 6); 958 } 959 960 /* ilk+ "12.4" interpolated format (low 6 bits) */ 961 static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color) 962 { 963 return (color->red & 0x3f) << 24 | (color->green & 0x3f) << 14 | 964 (color->blue & 0x3f) << 4; 965 } 966 967 static void 968 icl_load_gcmax(const struct intel_crtc_state *crtc_state, 969 const struct drm_color_lut *color) 970 { 971 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 972 enum pipe pipe = crtc->pipe; 973 974 /* FIXME LUT entries are 16 bit only, so we can prog 0xFFFF max */ 975 intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red); 976 intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green); 977 intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue); 978 } 979 980 static void 981 icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state) 982 { 983 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 984 const struct drm_property_blob *blob = crtc_state->hw.gamma_lut; 985 const struct drm_color_lut *lut = blob->data; 986 enum pipe pipe = crtc->pipe; 987 int i; 988 989 /* 990 * Program Super Fine segment (let's call it seg1)... 991 * 992 * Super Fine segment's step is 1/(8 * 128 * 256) and it has 993 * 9 entries, corresponding to values 0, 1/(8 * 128 * 256), 994 * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256). 995 */ 996 intel_dsb_reg_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe), 997 PAL_PREC_AUTO_INCREMENT); 998 999 for (i = 0; i < 9; i++) { 1000 const struct drm_color_lut *entry = &lut[i]; 1001 1002 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe), 1003 ilk_lut_12p4_ldw(entry)); 1004 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe), 1005 ilk_lut_12p4_udw(entry)); 1006 } 1007 } 1008 1009 static void 1010 icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state) 1011 { 1012 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1013 const struct drm_property_blob *blob = crtc_state->hw.gamma_lut; 1014 const struct drm_color_lut *lut = blob->data; 1015 const struct drm_color_lut *entry; 1016 enum pipe pipe = crtc->pipe; 1017 int i; 1018 1019 /* 1020 * Program Fine segment (let's call it seg2)... 1021 * 1022 * Fine segment's step is 1/(128 * 256) i.e. 1/(128 * 256), 2/(128 * 256) 1023 * ... 256/(128 * 256). So in order to program fine segment of LUT we 1024 * need to pick every 8th entry in the LUT, and program 256 indexes. 1025 * 1026 * PAL_PREC_INDEX[0] and PAL_PREC_INDEX[1] map to seg2[1], 1027 * seg2[0] being unused by the hardware. 1028 */ 1029 intel_dsb_reg_write(crtc_state, PREC_PAL_INDEX(pipe), 1030 PAL_PREC_AUTO_INCREMENT); 1031 for (i = 1; i < 257; i++) { 1032 entry = &lut[i * 8]; 1033 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), 1034 ilk_lut_12p4_ldw(entry)); 1035 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), 1036 ilk_lut_12p4_udw(entry)); 1037 } 1038 1039 /* 1040 * Program Coarse segment (let's call it seg3)... 1041 * 1042 * Coarse segment starts from index 0 and it's step is 1/256 ie 0, 1043 * 1/256, 2/256 ... 256/256. As per the description of each entry in LUT 1044 * above, we need to pick every (8 * 128)th entry in LUT, and 1045 * program 256 of those. 1046 * 1047 * Spec is not very clear about if entries seg3[0] and seg3[1] are 1048 * being used or not, but we still need to program these to advance 1049 * the index. 1050 */ 1051 for (i = 0; i < 256; i++) { 1052 entry = &lut[i * 8 * 128]; 1053 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), 1054 ilk_lut_12p4_ldw(entry)); 1055 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), 1056 ilk_lut_12p4_udw(entry)); 1057 } 1058 1059 /* The last entry in the LUT is to be programmed in GCMAX */ 1060 entry = &lut[256 * 8 * 128]; 1061 icl_load_gcmax(crtc_state, entry); 1062 ivb_load_lut_ext_max(crtc_state); 1063 } 1064 1065 static void icl_load_luts(const struct intel_crtc_state *crtc_state) 1066 { 1067 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 1068 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1069 1070 if (crtc_state->hw.degamma_lut) 1071 glk_load_degamma_lut(crtc_state); 1072 1073 switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { 1074 case GAMMA_MODE_MODE_8BIT: 1075 ilk_load_lut_8(crtc, gamma_lut); 1076 break; 1077 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: 1078 icl_program_gamma_superfine_segment(crtc_state); 1079 icl_program_gamma_multi_segment(crtc_state); 1080 break; 1081 case GAMMA_MODE_MODE_10BIT: 1082 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0)); 1083 ivb_load_lut_ext_max(crtc_state); 1084 break; 1085 default: 1086 MISSING_CASE(crtc_state->gamma_mode); 1087 break; 1088 } 1089 1090 intel_dsb_commit(crtc_state); 1091 } 1092 1093 static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color) 1094 { 1095 return drm_color_lut_extract(color->green, 14) << 16 | 1096 drm_color_lut_extract(color->blue, 14); 1097 } 1098 1099 static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color) 1100 { 1101 return drm_color_lut_extract(color->red, 14); 1102 } 1103 1104 static void chv_load_cgm_degamma(struct intel_crtc *crtc, 1105 const struct drm_property_blob *blob) 1106 { 1107 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1108 const struct drm_color_lut *lut = blob->data; 1109 int i, lut_size = drm_color_lut_size(blob); 1110 enum pipe pipe = crtc->pipe; 1111 1112 for (i = 0; i < lut_size; i++) { 1113 intel_de_write_fw(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 0), 1114 chv_cgm_degamma_ldw(&lut[i])); 1115 intel_de_write_fw(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 1), 1116 chv_cgm_degamma_udw(&lut[i])); 1117 } 1118 } 1119 1120 static u32 chv_cgm_gamma_ldw(const struct drm_color_lut *color) 1121 { 1122 return drm_color_lut_extract(color->green, 10) << 16 | 1123 drm_color_lut_extract(color->blue, 10); 1124 } 1125 1126 static u32 chv_cgm_gamma_udw(const struct drm_color_lut *color) 1127 { 1128 return drm_color_lut_extract(color->red, 10); 1129 } 1130 1131 static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) 1132 { 1133 entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK, ldw), 10); 1134 entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK, ldw), 10); 1135 entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, udw), 10); 1136 } 1137 1138 static void chv_load_cgm_gamma(struct intel_crtc *crtc, 1139 const struct drm_property_blob *blob) 1140 { 1141 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1142 const struct drm_color_lut *lut = blob->data; 1143 int i, lut_size = drm_color_lut_size(blob); 1144 enum pipe pipe = crtc->pipe; 1145 1146 for (i = 0; i < lut_size; i++) { 1147 intel_de_write_fw(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0), 1148 chv_cgm_gamma_ldw(&lut[i])); 1149 intel_de_write_fw(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1), 1150 chv_cgm_gamma_udw(&lut[i])); 1151 } 1152 } 1153 1154 static void chv_load_luts(const struct intel_crtc_state *crtc_state) 1155 { 1156 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1157 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1158 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut; 1159 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 1160 const struct drm_property_blob *ctm = crtc_state->hw.ctm; 1161 1162 if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) 1163 chv_load_cgm_csc(crtc, ctm); 1164 1165 if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA) 1166 chv_load_cgm_degamma(crtc, degamma_lut); 1167 1168 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) 1169 chv_load_cgm_gamma(crtc, gamma_lut); 1170 else 1171 i965_load_luts(crtc_state); 1172 1173 intel_de_write_fw(dev_priv, CGM_PIPE_MODE(crtc->pipe), 1174 crtc_state->cgm_mode); 1175 } 1176 1177 void intel_color_load_luts(const struct intel_crtc_state *crtc_state) 1178 { 1179 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1180 1181 dev_priv->color_funcs->load_luts(crtc_state); 1182 } 1183 1184 void intel_color_commit_noarm(const struct intel_crtc_state *crtc_state) 1185 { 1186 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1187 1188 if (dev_priv->color_funcs->color_commit_noarm) 1189 dev_priv->color_funcs->color_commit_noarm(crtc_state); 1190 } 1191 1192 void intel_color_commit_arm(const struct intel_crtc_state *crtc_state) 1193 { 1194 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1195 1196 dev_priv->color_funcs->color_commit_arm(crtc_state); 1197 } 1198 1199 static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state) 1200 { 1201 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 1202 struct intel_atomic_state *state = 1203 to_intel_atomic_state(new_crtc_state->uapi.state); 1204 const struct intel_crtc_state *old_crtc_state = 1205 intel_atomic_get_old_crtc_state(state, crtc); 1206 1207 return !old_crtc_state->hw.gamma_lut && 1208 !old_crtc_state->hw.degamma_lut; 1209 } 1210 1211 static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state) 1212 { 1213 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 1214 struct intel_atomic_state *state = 1215 to_intel_atomic_state(new_crtc_state->uapi.state); 1216 const struct intel_crtc_state *old_crtc_state = 1217 intel_atomic_get_old_crtc_state(state, crtc); 1218 1219 /* 1220 * CGM_PIPE_MODE is itself single buffered. We'd have to 1221 * somehow split it out from chv_load_luts() if we wanted 1222 * the ability to preload the CGM LUTs/CSC without tearing. 1223 */ 1224 if (old_crtc_state->cgm_mode || new_crtc_state->cgm_mode) 1225 return false; 1226 1227 return !old_crtc_state->hw.gamma_lut; 1228 } 1229 1230 static bool glk_can_preload_luts(const struct intel_crtc_state *new_crtc_state) 1231 { 1232 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 1233 struct intel_atomic_state *state = 1234 to_intel_atomic_state(new_crtc_state->uapi.state); 1235 const struct intel_crtc_state *old_crtc_state = 1236 intel_atomic_get_old_crtc_state(state, crtc); 1237 1238 /* 1239 * The hardware degamma is active whenever the pipe 1240 * CSC is active. Thus even if the old state has no 1241 * software degamma we need to avoid clobbering the 1242 * linear hardware degamma mid scanout. 1243 */ 1244 return !old_crtc_state->csc_enable && 1245 !old_crtc_state->hw.gamma_lut; 1246 } 1247 1248 int intel_color_check(struct intel_crtc_state *crtc_state) 1249 { 1250 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1251 1252 return dev_priv->color_funcs->color_check(crtc_state); 1253 } 1254 1255 void intel_color_get_config(struct intel_crtc_state *crtc_state) 1256 { 1257 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1258 1259 if (dev_priv->color_funcs->read_luts) 1260 dev_priv->color_funcs->read_luts(crtc_state); 1261 } 1262 1263 static bool need_plane_update(struct intel_plane *plane, 1264 const struct intel_crtc_state *crtc_state) 1265 { 1266 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1267 1268 /* 1269 * On pre-SKL the pipe gamma enable and pipe csc enable for 1270 * the pipe bottom color are configured via the primary plane. 1271 * We have to reconfigure that even if the plane is inactive. 1272 */ 1273 return crtc_state->active_planes & BIT(plane->id) || 1274 (DISPLAY_VER(dev_priv) < 9 && 1275 plane->id == PLANE_PRIMARY); 1276 } 1277 1278 static int 1279 intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state) 1280 { 1281 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 1282 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1283 struct intel_atomic_state *state = 1284 to_intel_atomic_state(new_crtc_state->uapi.state); 1285 const struct intel_crtc_state *old_crtc_state = 1286 intel_atomic_get_old_crtc_state(state, crtc); 1287 struct intel_plane *plane; 1288 1289 if (!new_crtc_state->hw.active || 1290 drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) 1291 return 0; 1292 1293 if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable && 1294 new_crtc_state->csc_enable == old_crtc_state->csc_enable) 1295 return 0; 1296 1297 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 1298 struct intel_plane_state *plane_state; 1299 1300 if (!need_plane_update(plane, new_crtc_state)) 1301 continue; 1302 1303 plane_state = intel_atomic_get_plane_state(state, plane); 1304 if (IS_ERR(plane_state)) 1305 return PTR_ERR(plane_state); 1306 1307 new_crtc_state->update_planes |= BIT(plane->id); 1308 } 1309 1310 return 0; 1311 } 1312 1313 static int check_lut_size(const struct drm_property_blob *lut, int expected) 1314 { 1315 int len; 1316 1317 if (!lut) 1318 return 0; 1319 1320 len = drm_color_lut_size(lut); 1321 if (len != expected) { 1322 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n", 1323 len, expected); 1324 return -EINVAL; 1325 } 1326 1327 return 0; 1328 } 1329 1330 static int check_luts(const struct intel_crtc_state *crtc_state) 1331 { 1332 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1333 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 1334 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut; 1335 int gamma_length, degamma_length; 1336 u32 gamma_tests, degamma_tests; 1337 1338 /* Always allow legacy gamma LUT with no further checking. */ 1339 if (crtc_state_is_legacy_gamma(crtc_state)) 1340 return 0; 1341 1342 /* C8 relies on its palette being stored in the legacy LUT */ 1343 if (crtc_state->c8_planes) { 1344 drm_dbg_kms(&dev_priv->drm, 1345 "C8 pixelformat requires the legacy LUT\n"); 1346 return -EINVAL; 1347 } 1348 1349 degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size; 1350 gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size; 1351 degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests; 1352 gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests; 1353 1354 if (check_lut_size(degamma_lut, degamma_length) || 1355 check_lut_size(gamma_lut, gamma_length)) 1356 return -EINVAL; 1357 1358 if (drm_color_lut_check(degamma_lut, degamma_tests) || 1359 drm_color_lut_check(gamma_lut, gamma_tests)) 1360 return -EINVAL; 1361 1362 return 0; 1363 } 1364 1365 static u32 i9xx_gamma_mode(struct intel_crtc_state *crtc_state) 1366 { 1367 if (!crtc_state->gamma_enable || 1368 crtc_state_is_legacy_gamma(crtc_state)) 1369 return GAMMA_MODE_MODE_8BIT; 1370 else 1371 return GAMMA_MODE_MODE_10BIT; /* i965+ only */ 1372 } 1373 1374 static int i9xx_color_check(struct intel_crtc_state *crtc_state) 1375 { 1376 int ret; 1377 1378 ret = check_luts(crtc_state); 1379 if (ret) 1380 return ret; 1381 1382 crtc_state->gamma_enable = 1383 crtc_state->hw.gamma_lut && 1384 !crtc_state->c8_planes; 1385 1386 crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state); 1387 1388 ret = intel_color_add_affected_planes(crtc_state); 1389 if (ret) 1390 return ret; 1391 1392 crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 1393 1394 return 0; 1395 } 1396 1397 static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state) 1398 { 1399 u32 cgm_mode = 0; 1400 1401 if (crtc_state_is_legacy_gamma(crtc_state)) 1402 return 0; 1403 1404 if (crtc_state->hw.degamma_lut) 1405 cgm_mode |= CGM_PIPE_MODE_DEGAMMA; 1406 if (crtc_state->hw.ctm) 1407 cgm_mode |= CGM_PIPE_MODE_CSC; 1408 if (crtc_state->hw.gamma_lut) 1409 cgm_mode |= CGM_PIPE_MODE_GAMMA; 1410 1411 return cgm_mode; 1412 } 1413 1414 /* 1415 * CHV color pipeline: 1416 * u0.10 -> CGM degamma -> u0.14 -> CGM csc -> u0.14 -> CGM gamma -> 1417 * u0.10 -> WGC csc -> u0.10 -> pipe gamma -> u0.10 1418 * 1419 * We always bypass the WGC csc and use the CGM csc 1420 * instead since it has degamma and better precision. 1421 */ 1422 static int chv_color_check(struct intel_crtc_state *crtc_state) 1423 { 1424 int ret; 1425 1426 ret = check_luts(crtc_state); 1427 if (ret) 1428 return ret; 1429 1430 /* 1431 * Pipe gamma will be used only for the legacy LUT. 1432 * Otherwise we bypass it and use the CGM gamma instead. 1433 */ 1434 crtc_state->gamma_enable = 1435 crtc_state_is_legacy_gamma(crtc_state) && 1436 !crtc_state->c8_planes; 1437 1438 crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT; 1439 1440 crtc_state->cgm_mode = chv_cgm_mode(crtc_state); 1441 1442 ret = intel_color_add_affected_planes(crtc_state); 1443 if (ret) 1444 return ret; 1445 1446 crtc_state->preload_luts = chv_can_preload_luts(crtc_state); 1447 1448 return 0; 1449 } 1450 1451 static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state) 1452 { 1453 if (!crtc_state->gamma_enable || 1454 crtc_state_is_legacy_gamma(crtc_state)) 1455 return GAMMA_MODE_MODE_8BIT; 1456 else 1457 return GAMMA_MODE_MODE_10BIT; 1458 } 1459 1460 static u32 ilk_csc_mode(const struct intel_crtc_state *crtc_state) 1461 { 1462 /* 1463 * CSC comes after the LUT in RGB->YCbCr mode. 1464 * RGB->YCbCr needs the limited range offsets added to 1465 * the output. RGB limited range output is handled by 1466 * the hw automagically elsewhere. 1467 */ 1468 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 1469 return CSC_BLACK_SCREEN_OFFSET; 1470 1471 return CSC_MODE_YUV_TO_RGB | 1472 CSC_POSITION_BEFORE_GAMMA; 1473 } 1474 1475 static int ilk_color_check(struct intel_crtc_state *crtc_state) 1476 { 1477 int ret; 1478 1479 ret = check_luts(crtc_state); 1480 if (ret) 1481 return ret; 1482 1483 crtc_state->gamma_enable = 1484 crtc_state->hw.gamma_lut && 1485 !crtc_state->c8_planes; 1486 1487 /* 1488 * We don't expose the ctm on ilk/snb currently, also RGB 1489 * limited range output is handled by the hw automagically. 1490 */ 1491 crtc_state->csc_enable = 1492 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB; 1493 1494 crtc_state->gamma_mode = ilk_gamma_mode(crtc_state); 1495 1496 crtc_state->csc_mode = ilk_csc_mode(crtc_state); 1497 1498 ret = intel_color_add_affected_planes(crtc_state); 1499 if (ret) 1500 return ret; 1501 1502 crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 1503 1504 return 0; 1505 } 1506 1507 static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state) 1508 { 1509 if (!crtc_state->gamma_enable || 1510 crtc_state_is_legacy_gamma(crtc_state)) 1511 return GAMMA_MODE_MODE_8BIT; 1512 else if (crtc_state->hw.gamma_lut && 1513 crtc_state->hw.degamma_lut) 1514 return GAMMA_MODE_MODE_SPLIT; 1515 else 1516 return GAMMA_MODE_MODE_10BIT; 1517 } 1518 1519 static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state) 1520 { 1521 bool limited_color_range = ilk_csc_limited_range(crtc_state); 1522 1523 /* 1524 * CSC comes after the LUT in degamma, RGB->YCbCr, 1525 * and RGB full->limited range mode. 1526 */ 1527 if (crtc_state->hw.degamma_lut || 1528 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || 1529 limited_color_range) 1530 return 0; 1531 1532 return CSC_POSITION_BEFORE_GAMMA; 1533 } 1534 1535 static int ivb_color_check(struct intel_crtc_state *crtc_state) 1536 { 1537 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1538 bool limited_color_range = ilk_csc_limited_range(crtc_state); 1539 int ret; 1540 1541 ret = check_luts(crtc_state); 1542 if (ret) 1543 return ret; 1544 1545 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB && 1546 crtc_state->hw.ctm) { 1547 drm_dbg_kms(&dev_priv->drm, 1548 "YCBCR and CTM together are not possible\n"); 1549 return -EINVAL; 1550 } 1551 1552 crtc_state->gamma_enable = 1553 (crtc_state->hw.gamma_lut || 1554 crtc_state->hw.degamma_lut) && 1555 !crtc_state->c8_planes; 1556 1557 crtc_state->csc_enable = 1558 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || 1559 crtc_state->hw.ctm || limited_color_range; 1560 1561 crtc_state->gamma_mode = ivb_gamma_mode(crtc_state); 1562 1563 crtc_state->csc_mode = ivb_csc_mode(crtc_state); 1564 1565 ret = intel_color_add_affected_planes(crtc_state); 1566 if (ret) 1567 return ret; 1568 1569 crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 1570 1571 return 0; 1572 } 1573 1574 static u32 glk_gamma_mode(const struct intel_crtc_state *crtc_state) 1575 { 1576 if (!crtc_state->gamma_enable || 1577 crtc_state_is_legacy_gamma(crtc_state)) 1578 return GAMMA_MODE_MODE_8BIT; 1579 else 1580 return GAMMA_MODE_MODE_10BIT; 1581 } 1582 1583 static int glk_color_check(struct intel_crtc_state *crtc_state) 1584 { 1585 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1586 int ret; 1587 1588 ret = check_luts(crtc_state); 1589 if (ret) 1590 return ret; 1591 1592 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB && 1593 crtc_state->hw.ctm) { 1594 drm_dbg_kms(&dev_priv->drm, 1595 "YCBCR and CTM together are not possible\n"); 1596 return -EINVAL; 1597 } 1598 1599 crtc_state->gamma_enable = 1600 crtc_state->hw.gamma_lut && 1601 !crtc_state->c8_planes; 1602 1603 /* On GLK+ degamma LUT is controlled by csc_enable */ 1604 crtc_state->csc_enable = 1605 crtc_state->hw.degamma_lut || 1606 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || 1607 crtc_state->hw.ctm || crtc_state->limited_color_range; 1608 1609 crtc_state->gamma_mode = glk_gamma_mode(crtc_state); 1610 1611 crtc_state->csc_mode = 0; 1612 1613 ret = intel_color_add_affected_planes(crtc_state); 1614 if (ret) 1615 return ret; 1616 1617 crtc_state->preload_luts = glk_can_preload_luts(crtc_state); 1618 1619 return 0; 1620 } 1621 1622 static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state) 1623 { 1624 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1625 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1626 u32 gamma_mode = 0; 1627 1628 if (crtc_state->hw.degamma_lut) 1629 gamma_mode |= PRE_CSC_GAMMA_ENABLE; 1630 1631 if (crtc_state->hw.gamma_lut && 1632 !crtc_state->c8_planes) 1633 gamma_mode |= POST_CSC_GAMMA_ENABLE; 1634 1635 if (!crtc_state->hw.gamma_lut || 1636 crtc_state_is_legacy_gamma(crtc_state)) 1637 gamma_mode |= GAMMA_MODE_MODE_8BIT; 1638 /* 1639 * Enable 10bit gamma for D13 1640 * ToDo: Extend to Logarithmic Gamma once the new UAPI 1641 * is acccepted and implemented by a userspace consumer 1642 */ 1643 else if (DISPLAY_VER(i915) >= 13) 1644 gamma_mode |= GAMMA_MODE_MODE_10BIT; 1645 else 1646 gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED; 1647 1648 return gamma_mode; 1649 } 1650 1651 static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state) 1652 { 1653 u32 csc_mode = 0; 1654 1655 if (crtc_state->hw.ctm) 1656 csc_mode |= ICL_CSC_ENABLE; 1657 1658 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || 1659 crtc_state->limited_color_range) 1660 csc_mode |= ICL_OUTPUT_CSC_ENABLE; 1661 1662 return csc_mode; 1663 } 1664 1665 static int icl_color_check(struct intel_crtc_state *crtc_state) 1666 { 1667 int ret; 1668 1669 ret = check_luts(crtc_state); 1670 if (ret) 1671 return ret; 1672 1673 crtc_state->gamma_mode = icl_gamma_mode(crtc_state); 1674 1675 crtc_state->csc_mode = icl_csc_mode(crtc_state); 1676 1677 crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 1678 1679 return 0; 1680 } 1681 1682 static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state) 1683 { 1684 if (!crtc_state->gamma_enable) 1685 return 0; 1686 1687 switch (crtc_state->gamma_mode) { 1688 case GAMMA_MODE_MODE_8BIT: 1689 return 8; 1690 case GAMMA_MODE_MODE_10BIT: 1691 return 16; 1692 default: 1693 MISSING_CASE(crtc_state->gamma_mode); 1694 return 0; 1695 } 1696 } 1697 1698 static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state) 1699 { 1700 if (!crtc_state->gamma_enable) 1701 return 0; 1702 1703 if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0) 1704 return 0; 1705 1706 switch (crtc_state->gamma_mode) { 1707 case GAMMA_MODE_MODE_8BIT: 1708 return 8; 1709 case GAMMA_MODE_MODE_10BIT: 1710 return 10; 1711 default: 1712 MISSING_CASE(crtc_state->gamma_mode); 1713 return 0; 1714 } 1715 } 1716 1717 static int chv_gamma_precision(const struct intel_crtc_state *crtc_state) 1718 { 1719 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) 1720 return 10; 1721 else 1722 return i9xx_gamma_precision(crtc_state); 1723 } 1724 1725 static int glk_gamma_precision(const struct intel_crtc_state *crtc_state) 1726 { 1727 if (!crtc_state->gamma_enable) 1728 return 0; 1729 1730 switch (crtc_state->gamma_mode) { 1731 case GAMMA_MODE_MODE_8BIT: 1732 return 8; 1733 case GAMMA_MODE_MODE_10BIT: 1734 return 10; 1735 default: 1736 MISSING_CASE(crtc_state->gamma_mode); 1737 return 0; 1738 } 1739 } 1740 1741 static int icl_gamma_precision(const struct intel_crtc_state *crtc_state) 1742 { 1743 if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0) 1744 return 0; 1745 1746 switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { 1747 case GAMMA_MODE_MODE_8BIT: 1748 return 8; 1749 case GAMMA_MODE_MODE_10BIT: 1750 return 10; 1751 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: 1752 return 16; 1753 default: 1754 MISSING_CASE(crtc_state->gamma_mode); 1755 return 0; 1756 } 1757 } 1758 1759 int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state) 1760 { 1761 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1762 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1763 1764 if (HAS_GMCH(dev_priv)) { 1765 if (IS_CHERRYVIEW(dev_priv)) 1766 return chv_gamma_precision(crtc_state); 1767 else 1768 return i9xx_gamma_precision(crtc_state); 1769 } else { 1770 if (DISPLAY_VER(dev_priv) >= 11) 1771 return icl_gamma_precision(crtc_state); 1772 else if (DISPLAY_VER(dev_priv) == 10) 1773 return glk_gamma_precision(crtc_state); 1774 else if (IS_IRONLAKE(dev_priv)) 1775 return ilk_gamma_precision(crtc_state); 1776 } 1777 1778 return 0; 1779 } 1780 1781 static bool err_check(struct drm_color_lut *lut1, 1782 struct drm_color_lut *lut2, u32 err) 1783 { 1784 return ((abs((long)lut2->red - lut1->red)) <= err) && 1785 ((abs((long)lut2->blue - lut1->blue)) <= err) && 1786 ((abs((long)lut2->green - lut1->green)) <= err); 1787 } 1788 1789 static bool intel_color_lut_entries_equal(struct drm_color_lut *lut1, 1790 struct drm_color_lut *lut2, 1791 int lut_size, u32 err) 1792 { 1793 int i; 1794 1795 for (i = 0; i < lut_size; i++) { 1796 if (!err_check(&lut1[i], &lut2[i], err)) 1797 return false; 1798 } 1799 1800 return true; 1801 } 1802 1803 bool intel_color_lut_equal(struct drm_property_blob *blob1, 1804 struct drm_property_blob *blob2, 1805 u32 gamma_mode, u32 bit_precision) 1806 { 1807 struct drm_color_lut *lut1, *lut2; 1808 int lut_size1, lut_size2; 1809 u32 err; 1810 1811 if (!blob1 != !blob2) 1812 return false; 1813 1814 if (!blob1) 1815 return true; 1816 1817 lut_size1 = drm_color_lut_size(blob1); 1818 lut_size2 = drm_color_lut_size(blob2); 1819 1820 /* check sw and hw lut size */ 1821 if (lut_size1 != lut_size2) 1822 return false; 1823 1824 lut1 = blob1->data; 1825 lut2 = blob2->data; 1826 1827 err = 0xffff >> bit_precision; 1828 1829 /* check sw and hw lut entry to be equal */ 1830 switch (gamma_mode & GAMMA_MODE_MODE_MASK) { 1831 case GAMMA_MODE_MODE_8BIT: 1832 case GAMMA_MODE_MODE_10BIT: 1833 if (!intel_color_lut_entries_equal(lut1, lut2, 1834 lut_size2, err)) 1835 return false; 1836 break; 1837 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: 1838 if (!intel_color_lut_entries_equal(lut1, lut2, 1839 9, err)) 1840 return false; 1841 break; 1842 default: 1843 MISSING_CASE(gamma_mode); 1844 return false; 1845 } 1846 1847 return true; 1848 } 1849 1850 static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc) 1851 { 1852 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1853 enum pipe pipe = crtc->pipe; 1854 struct drm_property_blob *blob; 1855 struct drm_color_lut *lut; 1856 int i; 1857 1858 blob = drm_property_create_blob(&dev_priv->drm, 1859 sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH, 1860 NULL); 1861 if (IS_ERR(blob)) 1862 return NULL; 1863 1864 lut = blob->data; 1865 1866 for (i = 0; i < LEGACY_LUT_LENGTH; i++) { 1867 u32 val = intel_de_read_fw(dev_priv, PALETTE(pipe, i)); 1868 1869 i9xx_lut_8_pack(&lut[i], val); 1870 } 1871 1872 return blob; 1873 } 1874 1875 static void i9xx_read_luts(struct intel_crtc_state *crtc_state) 1876 { 1877 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1878 1879 if (!crtc_state->gamma_enable) 1880 return; 1881 1882 crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc); 1883 } 1884 1885 static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc) 1886 { 1887 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1888 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; 1889 enum pipe pipe = crtc->pipe; 1890 struct drm_property_blob *blob; 1891 struct drm_color_lut *lut; 1892 1893 blob = drm_property_create_blob(&dev_priv->drm, 1894 sizeof(struct drm_color_lut) * lut_size, 1895 NULL); 1896 if (IS_ERR(blob)) 1897 return NULL; 1898 1899 lut = blob->data; 1900 1901 for (i = 0; i < lut_size - 1; i++) { 1902 u32 ldw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 0)); 1903 u32 udw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 1)); 1904 1905 i965_lut_10p6_pack(&lut[i], ldw, udw); 1906 } 1907 1908 lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(pipe, 0))); 1909 lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(pipe, 1))); 1910 lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(pipe, 2))); 1911 1912 return blob; 1913 } 1914 1915 static void i965_read_luts(struct intel_crtc_state *crtc_state) 1916 { 1917 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1918 1919 if (!crtc_state->gamma_enable) 1920 return; 1921 1922 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) 1923 crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc); 1924 else 1925 crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc); 1926 } 1927 1928 static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc) 1929 { 1930 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1931 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; 1932 enum pipe pipe = crtc->pipe; 1933 struct drm_property_blob *blob; 1934 struct drm_color_lut *lut; 1935 1936 blob = drm_property_create_blob(&dev_priv->drm, 1937 sizeof(struct drm_color_lut) * lut_size, 1938 NULL); 1939 if (IS_ERR(blob)) 1940 return NULL; 1941 1942 lut = blob->data; 1943 1944 for (i = 0; i < lut_size; i++) { 1945 u32 ldw = intel_de_read_fw(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0)); 1946 u32 udw = intel_de_read_fw(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1)); 1947 1948 chv_cgm_gamma_pack(&lut[i], ldw, udw); 1949 } 1950 1951 return blob; 1952 } 1953 1954 static void chv_read_luts(struct intel_crtc_state *crtc_state) 1955 { 1956 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1957 1958 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) 1959 crtc_state->hw.gamma_lut = chv_read_cgm_gamma(crtc); 1960 else 1961 i965_read_luts(crtc_state); 1962 } 1963 1964 static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc) 1965 { 1966 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1967 enum pipe pipe = crtc->pipe; 1968 struct drm_property_blob *blob; 1969 struct drm_color_lut *lut; 1970 int i; 1971 1972 blob = drm_property_create_blob(&dev_priv->drm, 1973 sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH, 1974 NULL); 1975 if (IS_ERR(blob)) 1976 return NULL; 1977 1978 lut = blob->data; 1979 1980 for (i = 0; i < LEGACY_LUT_LENGTH; i++) { 1981 u32 val = intel_de_read_fw(dev_priv, LGC_PALETTE(pipe, i)); 1982 1983 i9xx_lut_8_pack(&lut[i], val); 1984 } 1985 1986 return blob; 1987 } 1988 1989 static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc) 1990 { 1991 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1992 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; 1993 enum pipe pipe = crtc->pipe; 1994 struct drm_property_blob *blob; 1995 struct drm_color_lut *lut; 1996 1997 blob = drm_property_create_blob(&dev_priv->drm, 1998 sizeof(struct drm_color_lut) * lut_size, 1999 NULL); 2000 if (IS_ERR(blob)) 2001 return NULL; 2002 2003 lut = blob->data; 2004 2005 for (i = 0; i < lut_size; i++) { 2006 u32 val = intel_de_read_fw(dev_priv, PREC_PALETTE(pipe, i)); 2007 2008 ilk_lut_10_pack(&lut[i], val); 2009 } 2010 2011 return blob; 2012 } 2013 2014 static void ilk_read_luts(struct intel_crtc_state *crtc_state) 2015 { 2016 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2017 2018 if (!crtc_state->gamma_enable) 2019 return; 2020 2021 if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0) 2022 return; 2023 2024 switch (crtc_state->gamma_mode) { 2025 case GAMMA_MODE_MODE_8BIT: 2026 crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc); 2027 break; 2028 case GAMMA_MODE_MODE_10BIT: 2029 crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc); 2030 break; 2031 default: 2032 MISSING_CASE(crtc_state->gamma_mode); 2033 break; 2034 } 2035 } 2036 2037 /* On BDW+ the index auto increment mode actually works */ 2038 static struct drm_property_blob *bdw_read_lut_10(struct intel_crtc *crtc, 2039 u32 prec_index) 2040 { 2041 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2042 int i, hw_lut_size = ivb_lut_10_size(prec_index); 2043 int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; 2044 enum pipe pipe = crtc->pipe; 2045 struct drm_property_blob *blob; 2046 struct drm_color_lut *lut; 2047 2048 drm_WARN_ON(&dev_priv->drm, lut_size != hw_lut_size); 2049 2050 blob = drm_property_create_blob(&dev_priv->drm, 2051 sizeof(struct drm_color_lut) * lut_size, 2052 NULL); 2053 if (IS_ERR(blob)) 2054 return NULL; 2055 2056 lut = blob->data; 2057 2058 intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe), 2059 prec_index | PAL_PREC_AUTO_INCREMENT); 2060 2061 for (i = 0; i < lut_size; i++) { 2062 u32 val = intel_de_read_fw(dev_priv, PREC_PAL_DATA(pipe)); 2063 2064 ilk_lut_10_pack(&lut[i], val); 2065 } 2066 2067 intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe), 0); 2068 2069 return blob; 2070 } 2071 2072 static void glk_read_luts(struct intel_crtc_state *crtc_state) 2073 { 2074 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2075 2076 if (!crtc_state->gamma_enable) 2077 return; 2078 2079 switch (crtc_state->gamma_mode) { 2080 case GAMMA_MODE_MODE_8BIT: 2081 crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc); 2082 break; 2083 case GAMMA_MODE_MODE_10BIT: 2084 crtc_state->hw.gamma_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0)); 2085 break; 2086 default: 2087 MISSING_CASE(crtc_state->gamma_mode); 2088 break; 2089 } 2090 } 2091 2092 static struct drm_property_blob * 2093 icl_read_lut_multi_segment(struct intel_crtc *crtc) 2094 { 2095 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2096 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; 2097 enum pipe pipe = crtc->pipe; 2098 struct drm_property_blob *blob; 2099 struct drm_color_lut *lut; 2100 2101 blob = drm_property_create_blob(&dev_priv->drm, 2102 sizeof(struct drm_color_lut) * lut_size, 2103 NULL); 2104 if (IS_ERR(blob)) 2105 return NULL; 2106 2107 lut = blob->data; 2108 2109 intel_de_write_fw(dev_priv, PREC_PAL_MULTI_SEG_INDEX(pipe), 2110 PAL_PREC_AUTO_INCREMENT); 2111 2112 for (i = 0; i < 9; i++) { 2113 u32 ldw = intel_de_read_fw(dev_priv, PREC_PAL_MULTI_SEG_DATA(pipe)); 2114 u32 udw = intel_de_read_fw(dev_priv, PREC_PAL_MULTI_SEG_DATA(pipe)); 2115 2116 icl_lut_multi_seg_pack(&lut[i], ldw, udw); 2117 } 2118 2119 intel_de_write_fw(dev_priv, PREC_PAL_MULTI_SEG_INDEX(pipe), 0); 2120 2121 /* 2122 * FIXME readouts from PAL_PREC_DATA register aren't giving 2123 * correct values in the case of fine and coarse segments. 2124 * Restricting readouts only for super fine segment as of now. 2125 */ 2126 2127 return blob; 2128 } 2129 2130 static void icl_read_luts(struct intel_crtc_state *crtc_state) 2131 { 2132 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2133 2134 if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0) 2135 return; 2136 2137 switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { 2138 case GAMMA_MODE_MODE_8BIT: 2139 crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc); 2140 break; 2141 case GAMMA_MODE_MODE_10BIT: 2142 crtc_state->hw.gamma_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0)); 2143 break; 2144 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: 2145 crtc_state->hw.gamma_lut = icl_read_lut_multi_segment(crtc); 2146 break; 2147 default: 2148 MISSING_CASE(crtc_state->gamma_mode); 2149 break; 2150 } 2151 } 2152 2153 static const struct intel_color_funcs chv_color_funcs = { 2154 .color_check = chv_color_check, 2155 .color_commit_arm = i9xx_color_commit_arm, 2156 .load_luts = chv_load_luts, 2157 .read_luts = chv_read_luts, 2158 }; 2159 2160 static const struct intel_color_funcs i965_color_funcs = { 2161 .color_check = i9xx_color_check, 2162 .color_commit_arm = i9xx_color_commit_arm, 2163 .load_luts = i965_load_luts, 2164 .read_luts = i965_read_luts, 2165 }; 2166 2167 static const struct intel_color_funcs i9xx_color_funcs = { 2168 .color_check = i9xx_color_check, 2169 .color_commit_arm = i9xx_color_commit_arm, 2170 .load_luts = i9xx_load_luts, 2171 .read_luts = i9xx_read_luts, 2172 }; 2173 2174 static const struct intel_color_funcs icl_color_funcs = { 2175 .color_check = icl_color_check, 2176 .color_commit_noarm = icl_color_commit_noarm, 2177 .color_commit_arm = skl_color_commit_arm, 2178 .load_luts = icl_load_luts, 2179 .read_luts = icl_read_luts, 2180 }; 2181 2182 static const struct intel_color_funcs glk_color_funcs = { 2183 .color_check = glk_color_check, 2184 .color_commit_noarm = ilk_color_commit_noarm, 2185 .color_commit_arm = skl_color_commit_arm, 2186 .load_luts = glk_load_luts, 2187 .read_luts = glk_read_luts, 2188 }; 2189 2190 static const struct intel_color_funcs skl_color_funcs = { 2191 .color_check = ivb_color_check, 2192 .color_commit_noarm = ilk_color_commit_noarm, 2193 .color_commit_arm = skl_color_commit_arm, 2194 .load_luts = bdw_load_luts, 2195 .read_luts = NULL, 2196 }; 2197 2198 static const struct intel_color_funcs bdw_color_funcs = { 2199 .color_check = ivb_color_check, 2200 .color_commit_noarm = ilk_color_commit_noarm, 2201 .color_commit_arm = hsw_color_commit_arm, 2202 .load_luts = bdw_load_luts, 2203 .read_luts = NULL, 2204 }; 2205 2206 static const struct intel_color_funcs hsw_color_funcs = { 2207 .color_check = ivb_color_check, 2208 .color_commit_noarm = ilk_color_commit_noarm, 2209 .color_commit_arm = hsw_color_commit_arm, 2210 .load_luts = ivb_load_luts, 2211 .read_luts = NULL, 2212 }; 2213 2214 static const struct intel_color_funcs ivb_color_funcs = { 2215 .color_check = ivb_color_check, 2216 .color_commit_noarm = ilk_color_commit_noarm, 2217 .color_commit_arm = ilk_color_commit_arm, 2218 .load_luts = ivb_load_luts, 2219 .read_luts = NULL, 2220 }; 2221 2222 static const struct intel_color_funcs ilk_color_funcs = { 2223 .color_check = ilk_color_check, 2224 .color_commit_noarm = ilk_color_commit_noarm, 2225 .color_commit_arm = ilk_color_commit_arm, 2226 .load_luts = ilk_load_luts, 2227 .read_luts = ilk_read_luts, 2228 }; 2229 2230 void intel_color_init(struct intel_crtc *crtc) 2231 { 2232 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2233 bool has_ctm = INTEL_INFO(dev_priv)->color.degamma_lut_size != 0; 2234 2235 drm_mode_crtc_set_gamma_size(&crtc->base, 256); 2236 2237 if (HAS_GMCH(dev_priv)) { 2238 if (IS_CHERRYVIEW(dev_priv)) { 2239 dev_priv->color_funcs = &chv_color_funcs; 2240 } else if (DISPLAY_VER(dev_priv) >= 4) { 2241 dev_priv->color_funcs = &i965_color_funcs; 2242 } else { 2243 dev_priv->color_funcs = &i9xx_color_funcs; 2244 } 2245 } else { 2246 if (DISPLAY_VER(dev_priv) >= 11) 2247 dev_priv->color_funcs = &icl_color_funcs; 2248 else if (DISPLAY_VER(dev_priv) == 10) 2249 dev_priv->color_funcs = &glk_color_funcs; 2250 else if (DISPLAY_VER(dev_priv) == 9) 2251 dev_priv->color_funcs = &skl_color_funcs; 2252 else if (DISPLAY_VER(dev_priv) == 8) 2253 dev_priv->color_funcs = &bdw_color_funcs; 2254 else if (DISPLAY_VER(dev_priv) == 7) { 2255 if (IS_HASWELL(dev_priv)) 2256 dev_priv->color_funcs = &hsw_color_funcs; 2257 else 2258 dev_priv->color_funcs = &ivb_color_funcs; 2259 } else 2260 dev_priv->color_funcs = &ilk_color_funcs; 2261 } 2262 2263 drm_crtc_enable_color_mgmt(&crtc->base, 2264 INTEL_INFO(dev_priv)->color.degamma_lut_size, 2265 has_ctm, 2266 INTEL_INFO(dev_priv)->color.gamma_lut_size); 2267 } 2268