1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include "intel_color.h" 26 #include "intel_de.h" 27 #include "intel_display_types.h" 28 #include "intel_dpll.h" 29 #include "vlv_dsi_pll.h" 30 31 struct intel_color_funcs { 32 int (*color_check)(struct intel_crtc_state *crtc_state); 33 /* 34 * Program double buffered color management registers during 35 * vblank evasion. The registers should then latch during the 36 * next vblank start, alongside any other double buffered registers 37 * involved with the same commit. 38 */ 39 void (*color_commit)(const struct intel_crtc_state *crtc_state); 40 /* 41 * Load LUTs (and other single buffered color management 42 * registers). Will (hopefully) be called during the vblank 43 * following the latching of any double buffered registers 44 * involved with the same commit. 45 */ 46 void (*load_luts)(const struct intel_crtc_state *crtc_state); 47 void (*read_luts)(struct intel_crtc_state *crtc_state); 48 }; 49 50 #define CTM_COEFF_SIGN (1ULL << 63) 51 52 #define CTM_COEFF_1_0 (1ULL << 32) 53 #define CTM_COEFF_2_0 (CTM_COEFF_1_0 << 1) 54 #define CTM_COEFF_4_0 (CTM_COEFF_2_0 << 1) 55 #define CTM_COEFF_8_0 (CTM_COEFF_4_0 << 1) 56 #define CTM_COEFF_0_5 (CTM_COEFF_1_0 >> 1) 57 #define CTM_COEFF_0_25 (CTM_COEFF_0_5 >> 1) 58 #define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1) 59 60 #define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255) 61 62 #define CTM_COEFF_NEGATIVE(coeff) (((coeff) & CTM_COEFF_SIGN) != 0) 63 #define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1)) 64 65 #define LEGACY_LUT_LENGTH 256 66 67 /* 68 * ILK+ csc matrix: 69 * 70 * |R/Cr| | c0 c1 c2 | ( |R/Cr| |preoff0| ) |postoff0| 71 * |G/Y | = | c3 c4 c5 | x ( |G/Y | + |preoff1| ) + |postoff1| 72 * |B/Cb| | c6 c7 c8 | ( |B/Cb| |preoff2| ) |postoff2| 73 * 74 * ILK/SNB don't have explicit post offsets, and instead 75 * CSC_MODE_YUV_TO_RGB and CSC_BLACK_SCREEN_OFFSET are used: 76 * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=0 -> 1/2, 0, 1/2 77 * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/2, 1/16, 1/2 78 * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=0 -> 0, 0, 0 79 * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/16, 1/16, 1/16 80 */ 81 82 /* 83 * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point 84 * format). This macro takes the coefficient we want transformed and the 85 * number of fractional bits. 86 * 87 * We only have a 9 bits precision window which slides depending on the value 88 * of the CTM coefficient and we write the value from bit 3. We also round the 89 * value. 90 */ 91 #define ILK_CSC_COEFF_FP(coeff, fbits) \ 92 (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8) 93 94 #define ILK_CSC_COEFF_LIMITED_RANGE 0x0dc0 95 #define ILK_CSC_COEFF_1_0 0x7800 96 97 #define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255) 98 99 /* Nop pre/post offsets */ 100 static const u16 ilk_csc_off_zero[3] = {}; 101 102 /* Identity matrix */ 103 static const u16 ilk_csc_coeff_identity[9] = { 104 ILK_CSC_COEFF_1_0, 0, 0, 105 0, ILK_CSC_COEFF_1_0, 0, 106 0, 0, ILK_CSC_COEFF_1_0, 107 }; 108 109 /* Limited range RGB post offsets */ 110 static const u16 ilk_csc_postoff_limited_range[3] = { 111 ILK_CSC_POSTOFF_LIMITED_RANGE, 112 ILK_CSC_POSTOFF_LIMITED_RANGE, 113 ILK_CSC_POSTOFF_LIMITED_RANGE, 114 }; 115 116 /* Full range RGB -> limited range RGB matrix */ 117 static const u16 ilk_csc_coeff_limited_range[9] = { 118 ILK_CSC_COEFF_LIMITED_RANGE, 0, 0, 119 0, ILK_CSC_COEFF_LIMITED_RANGE, 0, 120 0, 0, ILK_CSC_COEFF_LIMITED_RANGE, 121 }; 122 123 /* BT.709 full range RGB -> limited range YCbCr matrix */ 124 static const u16 ilk_csc_coeff_rgb_to_ycbcr[9] = { 125 0x1e08, 0x9cc0, 0xb528, 126 0x2ba8, 0x09d8, 0x37e8, 127 0xbce8, 0x9ad8, 0x1e08, 128 }; 129 130 /* Limited range YCbCr post offsets */ 131 static const u16 ilk_csc_postoff_rgb_to_ycbcr[3] = { 132 0x0800, 0x0100, 0x0800, 133 }; 134 135 static bool lut_is_legacy(const struct drm_property_blob *lut) 136 { 137 return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH; 138 } 139 140 static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state) 141 { 142 return !crtc_state->hw.degamma_lut && 143 !crtc_state->hw.ctm && 144 crtc_state->hw.gamma_lut && 145 lut_is_legacy(crtc_state->hw.gamma_lut); 146 } 147 148 /* 149 * When using limited range, multiply the matrix given by userspace by 150 * the matrix that we would use for the limited range. 151 */ 152 static u64 *ctm_mult_by_limited(u64 *result, const u64 *input) 153 { 154 int i; 155 156 for (i = 0; i < 9; i++) { 157 u64 user_coeff = input[i]; 158 u32 limited_coeff = CTM_COEFF_LIMITED_RANGE; 159 u32 abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff), 0, 160 CTM_COEFF_4_0 - 1) >> 2; 161 162 /* 163 * By scaling every co-efficient with limited range (16-235) 164 * vs full range (0-255) the final o/p will be scaled down to 165 * fit in the limited range supported by the panel. 166 */ 167 result[i] = mul_u32_u32(limited_coeff, abs_coeff) >> 30; 168 result[i] |= user_coeff & CTM_COEFF_SIGN; 169 } 170 171 return result; 172 } 173 174 static void ilk_update_pipe_csc(struct intel_crtc *crtc, 175 const u16 preoff[3], 176 const u16 coeff[9], 177 const u16 postoff[3]) 178 { 179 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 180 enum pipe pipe = crtc->pipe; 181 182 intel_de_write_fw(dev_priv, PIPE_CSC_PREOFF_HI(pipe), preoff[0]); 183 intel_de_write_fw(dev_priv, PIPE_CSC_PREOFF_ME(pipe), preoff[1]); 184 intel_de_write_fw(dev_priv, PIPE_CSC_PREOFF_LO(pipe), preoff[2]); 185 186 intel_de_write_fw(dev_priv, PIPE_CSC_COEFF_RY_GY(pipe), 187 coeff[0] << 16 | coeff[1]); 188 intel_de_write_fw(dev_priv, PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16); 189 190 intel_de_write_fw(dev_priv, PIPE_CSC_COEFF_RU_GU(pipe), 191 coeff[3] << 16 | coeff[4]); 192 intel_de_write_fw(dev_priv, PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16); 193 194 intel_de_write_fw(dev_priv, PIPE_CSC_COEFF_RV_GV(pipe), 195 coeff[6] << 16 | coeff[7]); 196 intel_de_write_fw(dev_priv, PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16); 197 198 if (DISPLAY_VER(dev_priv) >= 7) { 199 intel_de_write_fw(dev_priv, PIPE_CSC_POSTOFF_HI(pipe), 200 postoff[0]); 201 intel_de_write_fw(dev_priv, PIPE_CSC_POSTOFF_ME(pipe), 202 postoff[1]); 203 intel_de_write_fw(dev_priv, PIPE_CSC_POSTOFF_LO(pipe), 204 postoff[2]); 205 } 206 } 207 208 static void icl_update_output_csc(struct intel_crtc *crtc, 209 const u16 preoff[3], 210 const u16 coeff[9], 211 const u16 postoff[3]) 212 { 213 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 214 enum pipe pipe = crtc->pipe; 215 216 intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_PREOFF_HI(pipe), preoff[0]); 217 intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_PREOFF_ME(pipe), preoff[1]); 218 intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]); 219 220 intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe), 221 coeff[0] << 16 | coeff[1]); 222 intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_COEFF_BY(pipe), 223 coeff[2] << 16); 224 225 intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe), 226 coeff[3] << 16 | coeff[4]); 227 intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_COEFF_BU(pipe), 228 coeff[5] << 16); 229 230 intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe), 231 coeff[6] << 16 | coeff[7]); 232 intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_COEFF_BV(pipe), 233 coeff[8] << 16); 234 235 intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]); 236 intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]); 237 intel_de_write_fw(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), postoff[2]); 238 } 239 240 static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state) 241 { 242 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 243 244 /* 245 * FIXME if there's a gamma LUT after the CSC, we should 246 * do the range compression using the gamma LUT instead. 247 */ 248 return crtc_state->limited_color_range && 249 (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) || 250 IS_DISPLAY_VER(dev_priv, 9, 10)); 251 } 252 253 static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state, 254 u16 coeffs[9]) 255 { 256 const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data; 257 const u64 *input; 258 u64 temp[9]; 259 int i; 260 261 if (ilk_csc_limited_range(crtc_state)) 262 input = ctm_mult_by_limited(temp, ctm->matrix); 263 else 264 input = ctm->matrix; 265 266 /* 267 * Convert fixed point S31.32 input to format supported by the 268 * hardware. 269 */ 270 for (i = 0; i < 9; i++) { 271 u64 abs_coeff = ((1ULL << 63) - 1) & input[i]; 272 273 /* 274 * Clamp input value to min/max supported by 275 * hardware. 276 */ 277 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1); 278 279 coeffs[i] = 0; 280 281 /* sign bit */ 282 if (CTM_COEFF_NEGATIVE(input[i])) 283 coeffs[i] |= 1 << 15; 284 285 if (abs_coeff < CTM_COEFF_0_125) 286 coeffs[i] |= (3 << 12) | 287 ILK_CSC_COEFF_FP(abs_coeff, 12); 288 else if (abs_coeff < CTM_COEFF_0_25) 289 coeffs[i] |= (2 << 12) | 290 ILK_CSC_COEFF_FP(abs_coeff, 11); 291 else if (abs_coeff < CTM_COEFF_0_5) 292 coeffs[i] |= (1 << 12) | 293 ILK_CSC_COEFF_FP(abs_coeff, 10); 294 else if (abs_coeff < CTM_COEFF_1_0) 295 coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9); 296 else if (abs_coeff < CTM_COEFF_2_0) 297 coeffs[i] |= (7 << 12) | 298 ILK_CSC_COEFF_FP(abs_coeff, 8); 299 else 300 coeffs[i] |= (6 << 12) | 301 ILK_CSC_COEFF_FP(abs_coeff, 7); 302 } 303 } 304 305 static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state) 306 { 307 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 308 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 309 bool limited_color_range = ilk_csc_limited_range(crtc_state); 310 311 if (crtc_state->hw.ctm) { 312 u16 coeff[9]; 313 314 ilk_csc_convert_ctm(crtc_state, coeff); 315 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeff, 316 limited_color_range ? 317 ilk_csc_postoff_limited_range : 318 ilk_csc_off_zero); 319 } else if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) { 320 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, 321 ilk_csc_coeff_rgb_to_ycbcr, 322 ilk_csc_postoff_rgb_to_ycbcr); 323 } else if (limited_color_range) { 324 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, 325 ilk_csc_coeff_limited_range, 326 ilk_csc_postoff_limited_range); 327 } else if (crtc_state->csc_enable) { 328 /* 329 * On GLK both pipe CSC and degamma LUT are controlled 330 * by csc_enable. Hence for the cases where the degama 331 * LUT is needed but CSC is not we need to load an 332 * identity matrix. 333 */ 334 drm_WARN_ON(&dev_priv->drm, !IS_GEMINILAKE(dev_priv)); 335 336 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, 337 ilk_csc_coeff_identity, 338 ilk_csc_off_zero); 339 } 340 341 intel_de_write_fw(dev_priv, PIPE_CSC_MODE(crtc->pipe), 342 crtc_state->csc_mode); 343 } 344 345 static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state) 346 { 347 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 348 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 349 350 if (crtc_state->hw.ctm) { 351 u16 coeff[9]; 352 353 ilk_csc_convert_ctm(crtc_state, coeff); 354 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, 355 coeff, ilk_csc_off_zero); 356 } 357 358 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) { 359 icl_update_output_csc(crtc, ilk_csc_off_zero, 360 ilk_csc_coeff_rgb_to_ycbcr, 361 ilk_csc_postoff_rgb_to_ycbcr); 362 } else if (crtc_state->limited_color_range) { 363 icl_update_output_csc(crtc, ilk_csc_off_zero, 364 ilk_csc_coeff_limited_range, 365 ilk_csc_postoff_limited_range); 366 } 367 368 intel_de_write_fw(dev_priv, PIPE_CSC_MODE(crtc->pipe), 369 crtc_state->csc_mode); 370 } 371 372 static void chv_load_cgm_csc(struct intel_crtc *crtc, 373 const struct drm_property_blob *blob) 374 { 375 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 376 const struct drm_color_ctm *ctm = blob->data; 377 enum pipe pipe = crtc->pipe; 378 u16 coeffs[9]; 379 int i; 380 381 for (i = 0; i < ARRAY_SIZE(coeffs); i++) { 382 u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i]; 383 384 /* Round coefficient. */ 385 abs_coeff += 1 << (32 - 13); 386 /* Clamp to hardware limits. */ 387 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1); 388 389 coeffs[i] = 0; 390 391 /* Write coefficients in S3.12 format. */ 392 if (ctm->matrix[i] & (1ULL << 63)) 393 coeffs[i] |= 1 << 15; 394 395 coeffs[i] |= ((abs_coeff >> 32) & 7) << 12; 396 coeffs[i] |= (abs_coeff >> 20) & 0xfff; 397 } 398 399 intel_de_write_fw(dev_priv, CGM_PIPE_CSC_COEFF01(pipe), 400 coeffs[1] << 16 | coeffs[0]); 401 intel_de_write_fw(dev_priv, CGM_PIPE_CSC_COEFF23(pipe), 402 coeffs[3] << 16 | coeffs[2]); 403 intel_de_write_fw(dev_priv, CGM_PIPE_CSC_COEFF45(pipe), 404 coeffs[5] << 16 | coeffs[4]); 405 intel_de_write_fw(dev_priv, CGM_PIPE_CSC_COEFF67(pipe), 406 coeffs[7] << 16 | coeffs[6]); 407 intel_de_write_fw(dev_priv, CGM_PIPE_CSC_COEFF8(pipe), 408 coeffs[8]); 409 } 410 411 /* convert hw value with given bit_precision to lut property val */ 412 static u32 intel_color_lut_pack(u32 val, int bit_precision) 413 { 414 u32 max = 0xffff >> (16 - bit_precision); 415 416 val = clamp_val(val, 0, max); 417 418 if (bit_precision < 16) 419 val <<= 16 - bit_precision; 420 421 return val; 422 } 423 424 static u32 i9xx_lut_8(const struct drm_color_lut *color) 425 { 426 return drm_color_lut_extract(color->red, 8) << 16 | 427 drm_color_lut_extract(color->green, 8) << 8 | 428 drm_color_lut_extract(color->blue, 8); 429 } 430 431 static void i9xx_lut_8_pack(struct drm_color_lut *entry, u32 val) 432 { 433 entry->red = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_RED_MASK, val), 8); 434 entry->green = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_GREEN_MASK, val), 8); 435 entry->blue = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_BLUE_MASK, val), 8); 436 } 437 438 /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */ 439 static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color) 440 { 441 return (color->red & 0xff) << 16 | 442 (color->green & 0xff) << 8 | 443 (color->blue & 0xff); 444 } 445 446 /* i965+ "10.6" interpolated format "odd DW" (high 8 bits) */ 447 static u32 i965_lut_10p6_udw(const struct drm_color_lut *color) 448 { 449 return (color->red >> 8) << 16 | 450 (color->green >> 8) << 8 | 451 (color->blue >> 8); 452 } 453 454 static void i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) 455 { 456 entry->red = REG_FIELD_GET(PALETTE_RED_MASK, udw) << 8 | 457 REG_FIELD_GET(PALETTE_RED_MASK, ldw); 458 entry->green = REG_FIELD_GET(PALETTE_GREEN_MASK, udw) << 8 | 459 REG_FIELD_GET(PALETTE_GREEN_MASK, ldw); 460 entry->blue = REG_FIELD_GET(PALETTE_BLUE_MASK, udw) << 8 | 461 REG_FIELD_GET(PALETTE_BLUE_MASK, ldw); 462 } 463 464 static u16 i965_lut_11p6_max_pack(u32 val) 465 { 466 /* PIPEGCMAX is 11.6, clamp to 10.6 */ 467 return clamp_val(val, 0, 0xffff); 468 } 469 470 static u32 ilk_lut_10(const struct drm_color_lut *color) 471 { 472 return drm_color_lut_extract(color->red, 10) << 20 | 473 drm_color_lut_extract(color->green, 10) << 10 | 474 drm_color_lut_extract(color->blue, 10); 475 } 476 477 static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val) 478 { 479 entry->red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_RED_MASK, val), 10); 480 entry->green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_GREEN_MASK, val), 10); 481 entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10); 482 } 483 484 static void icl_lut_multi_seg_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) 485 { 486 entry->red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, udw) << 6 | 487 REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, ldw); 488 entry->green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, udw) << 6 | 489 REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, ldw); 490 entry->blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, udw) << 6 | 491 REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw); 492 } 493 494 static void i9xx_color_commit(const struct intel_crtc_state *crtc_state) 495 { 496 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 497 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 498 enum pipe pipe = crtc->pipe; 499 u32 val; 500 501 val = intel_de_read(dev_priv, PIPECONF(pipe)); 502 val &= ~PIPECONF_GAMMA_MODE_MASK_I9XX; 503 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 504 intel_de_write(dev_priv, PIPECONF(pipe), val); 505 } 506 507 static void ilk_color_commit(const struct intel_crtc_state *crtc_state) 508 { 509 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 510 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 511 enum pipe pipe = crtc->pipe; 512 u32 val; 513 514 val = intel_de_read(dev_priv, PIPECONF(pipe)); 515 val &= ~PIPECONF_GAMMA_MODE_MASK_ILK; 516 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 517 intel_de_write(dev_priv, PIPECONF(pipe), val); 518 519 ilk_load_csc_matrix(crtc_state); 520 } 521 522 static void hsw_color_commit(const struct intel_crtc_state *crtc_state) 523 { 524 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 525 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 526 527 intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe), 528 crtc_state->gamma_mode); 529 530 ilk_load_csc_matrix(crtc_state); 531 } 532 533 static void skl_color_commit(const struct intel_crtc_state *crtc_state) 534 { 535 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 536 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 537 enum pipe pipe = crtc->pipe; 538 u32 val = 0; 539 540 /* 541 * We don't (yet) allow userspace to control the pipe background color, 542 * so force it to black, but apply pipe gamma and CSC appropriately 543 * so that its handling will match how we program our planes. 544 */ 545 if (crtc_state->gamma_enable) 546 val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE; 547 if (crtc_state->csc_enable) 548 val |= SKL_BOTTOM_COLOR_CSC_ENABLE; 549 intel_de_write(dev_priv, SKL_BOTTOM_COLOR(pipe), val); 550 551 intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe), 552 crtc_state->gamma_mode); 553 554 if (DISPLAY_VER(dev_priv) >= 11) 555 icl_load_csc_matrix(crtc_state); 556 else 557 ilk_load_csc_matrix(crtc_state); 558 } 559 560 static void i9xx_load_lut_8(struct intel_crtc *crtc, 561 const struct drm_property_blob *blob) 562 { 563 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 564 const struct drm_color_lut *lut; 565 enum pipe pipe = crtc->pipe; 566 int i; 567 568 if (!blob) 569 return; 570 571 lut = blob->data; 572 573 for (i = 0; i < 256; i++) 574 intel_de_write_fw(dev_priv, PALETTE(pipe, i), 575 i9xx_lut_8(&lut[i])); 576 } 577 578 static void i9xx_load_luts(const struct intel_crtc_state *crtc_state) 579 { 580 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 581 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 582 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 583 584 assert_pll_enabled(dev_priv, crtc->pipe); 585 586 i9xx_load_lut_8(crtc, gamma_lut); 587 } 588 589 static void i965_load_lut_10p6(struct intel_crtc *crtc, 590 const struct drm_property_blob *blob) 591 { 592 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 593 const struct drm_color_lut *lut = blob->data; 594 int i, lut_size = drm_color_lut_size(blob); 595 enum pipe pipe = crtc->pipe; 596 597 for (i = 0; i < lut_size - 1; i++) { 598 intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 0), 599 i965_lut_10p6_ldw(&lut[i])); 600 intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 1), 601 i965_lut_10p6_udw(&lut[i])); 602 } 603 604 intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 0), lut[i].red); 605 intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 1), lut[i].green); 606 intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 2), lut[i].blue); 607 } 608 609 static void i965_load_luts(const struct intel_crtc_state *crtc_state) 610 { 611 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 612 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 613 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 614 615 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 616 assert_dsi_pll_enabled(dev_priv); 617 else 618 assert_pll_enabled(dev_priv, crtc->pipe); 619 620 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) 621 i9xx_load_lut_8(crtc, gamma_lut); 622 else 623 i965_load_lut_10p6(crtc, gamma_lut); 624 } 625 626 static void ilk_load_lut_8(struct intel_crtc *crtc, 627 const struct drm_property_blob *blob) 628 { 629 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 630 const struct drm_color_lut *lut; 631 enum pipe pipe = crtc->pipe; 632 int i; 633 634 if (!blob) 635 return; 636 637 lut = blob->data; 638 639 for (i = 0; i < 256; i++) 640 intel_de_write_fw(dev_priv, LGC_PALETTE(pipe, i), 641 i9xx_lut_8(&lut[i])); 642 } 643 644 static void ilk_load_lut_10(struct intel_crtc *crtc, 645 const struct drm_property_blob *blob) 646 { 647 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 648 const struct drm_color_lut *lut = blob->data; 649 int i, lut_size = drm_color_lut_size(blob); 650 enum pipe pipe = crtc->pipe; 651 652 for (i = 0; i < lut_size; i++) 653 intel_de_write_fw(dev_priv, PREC_PALETTE(pipe, i), 654 ilk_lut_10(&lut[i])); 655 } 656 657 static void ilk_load_luts(const struct intel_crtc_state *crtc_state) 658 { 659 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 660 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 661 662 switch (crtc_state->gamma_mode) { 663 case GAMMA_MODE_MODE_8BIT: 664 ilk_load_lut_8(crtc, gamma_lut); 665 break; 666 case GAMMA_MODE_MODE_10BIT: 667 ilk_load_lut_10(crtc, gamma_lut); 668 break; 669 default: 670 MISSING_CASE(crtc_state->gamma_mode); 671 break; 672 } 673 } 674 675 static int ivb_lut_10_size(u32 prec_index) 676 { 677 if (prec_index & PAL_PREC_SPLIT_MODE) 678 return 512; 679 else 680 return 1024; 681 } 682 683 /* 684 * IVB/HSW Bspec / PAL_PREC_INDEX: 685 * "Restriction : Index auto increment mode is not 686 * supported and must not be enabled." 687 */ 688 static void ivb_load_lut_10(struct intel_crtc *crtc, 689 const struct drm_property_blob *blob, 690 u32 prec_index) 691 { 692 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 693 int hw_lut_size = ivb_lut_10_size(prec_index); 694 const struct drm_color_lut *lut = blob->data; 695 int i, lut_size = drm_color_lut_size(blob); 696 enum pipe pipe = crtc->pipe; 697 698 for (i = 0; i < hw_lut_size; i++) { 699 /* We discard half the user entries in split gamma mode */ 700 const struct drm_color_lut *entry = 701 &lut[i * (lut_size - 1) / (hw_lut_size - 1)]; 702 703 intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe), prec_index++); 704 intel_de_write_fw(dev_priv, PREC_PAL_DATA(pipe), 705 ilk_lut_10(entry)); 706 } 707 708 /* 709 * Reset the index, otherwise it prevents the legacy palette to be 710 * written properly. 711 */ 712 intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe), 0); 713 } 714 715 /* On BDW+ the index auto increment mode actually works */ 716 static void bdw_load_lut_10(struct intel_crtc *crtc, 717 const struct drm_property_blob *blob, 718 u32 prec_index) 719 { 720 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 721 int hw_lut_size = ivb_lut_10_size(prec_index); 722 const struct drm_color_lut *lut = blob->data; 723 int i, lut_size = drm_color_lut_size(blob); 724 enum pipe pipe = crtc->pipe; 725 726 intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe), 727 prec_index | PAL_PREC_AUTO_INCREMENT); 728 729 for (i = 0; i < hw_lut_size; i++) { 730 /* We discard half the user entries in split gamma mode */ 731 const struct drm_color_lut *entry = 732 &lut[i * (lut_size - 1) / (hw_lut_size - 1)]; 733 734 intel_de_write_fw(dev_priv, PREC_PAL_DATA(pipe), 735 ilk_lut_10(entry)); 736 } 737 738 /* 739 * Reset the index, otherwise it prevents the legacy palette to be 740 * written properly. 741 */ 742 intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe), 0); 743 } 744 745 static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state) 746 { 747 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 748 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 749 enum pipe pipe = crtc->pipe; 750 751 /* Program the max register to clamp values > 1.0. */ 752 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16); 753 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16); 754 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16); 755 756 /* 757 * Program the gc max 2 register to clamp values > 1.0. 758 * ToDo: Extend the ABI to be able to program values 759 * from 3.0 to 7.0 760 */ 761 if (DISPLAY_VER(dev_priv) >= 10) { 762 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0), 763 1 << 16); 764 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1), 765 1 << 16); 766 intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 2), 767 1 << 16); 768 } 769 } 770 771 static void ivb_load_luts(const struct intel_crtc_state *crtc_state) 772 { 773 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 774 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 775 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut; 776 const struct drm_property_blob *blob = gamma_lut ?: degamma_lut; 777 778 switch (crtc_state->gamma_mode) { 779 case GAMMA_MODE_MODE_8BIT: 780 ilk_load_lut_8(crtc, blob); 781 break; 782 case GAMMA_MODE_MODE_SPLIT: 783 ivb_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE | 784 PAL_PREC_INDEX_VALUE(0)); 785 ivb_load_lut_ext_max(crtc_state); 786 ivb_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE | 787 PAL_PREC_INDEX_VALUE(512)); 788 break; 789 case GAMMA_MODE_MODE_10BIT: 790 ivb_load_lut_10(crtc, blob, 791 PAL_PREC_INDEX_VALUE(0)); 792 ivb_load_lut_ext_max(crtc_state); 793 break; 794 default: 795 MISSING_CASE(crtc_state->gamma_mode); 796 break; 797 } 798 } 799 800 static void bdw_load_luts(const struct intel_crtc_state *crtc_state) 801 { 802 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 803 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 804 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut; 805 const struct drm_property_blob *blob = gamma_lut ?: degamma_lut; 806 807 switch (crtc_state->gamma_mode) { 808 case GAMMA_MODE_MODE_8BIT: 809 ilk_load_lut_8(crtc, blob); 810 break; 811 case GAMMA_MODE_MODE_SPLIT: 812 bdw_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE | 813 PAL_PREC_INDEX_VALUE(0)); 814 ivb_load_lut_ext_max(crtc_state); 815 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE | 816 PAL_PREC_INDEX_VALUE(512)); 817 break; 818 case GAMMA_MODE_MODE_10BIT: 819 820 bdw_load_lut_10(crtc, blob, 821 PAL_PREC_INDEX_VALUE(0)); 822 ivb_load_lut_ext_max(crtc_state); 823 break; 824 default: 825 MISSING_CASE(crtc_state->gamma_mode); 826 break; 827 } 828 } 829 830 static int glk_degamma_lut_size(struct drm_i915_private *i915) 831 { 832 if (DISPLAY_VER(i915) >= 13) 833 return 131; 834 else 835 return 35; 836 } 837 838 static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state) 839 { 840 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 841 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 842 enum pipe pipe = crtc->pipe; 843 int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; 844 const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data; 845 846 /* 847 * When setting the auto-increment bit, the hardware seems to 848 * ignore the index bits, so we need to reset it to index 0 849 * separately. 850 */ 851 intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0); 852 intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 853 PRE_CSC_GAMC_AUTO_INCREMENT); 854 855 for (i = 0; i < lut_size; i++) { 856 /* 857 * First lut_size entries represent range from 0 to 1.0 858 * 3 additional lut entries will represent extended range 859 * inputs 3.0 and 7.0 respectively, currently clamped 860 * at 1.0. Since the precision is 16bit, the user 861 * value can be directly filled to register. 862 * The pipe degamma table in GLK+ onwards doesn't 863 * support different values per channel, so this just 864 * programs green value which will be equal to Red and 865 * Blue into the lut registers. 866 * ToDo: Extend to max 7.0. Enable 32 bit input value 867 * as compared to just 16 to achieve this. 868 */ 869 intel_de_write_fw(dev_priv, PRE_CSC_GAMC_DATA(pipe), 870 lut[i].green); 871 } 872 873 /* Clamp values > 1.0. */ 874 while (i++ < glk_degamma_lut_size(dev_priv)) 875 intel_de_write_fw(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16); 876 877 intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0); 878 } 879 880 static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_state) 881 { 882 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 883 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 884 enum pipe pipe = crtc->pipe; 885 int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; 886 887 /* 888 * When setting the auto-increment bit, the hardware seems to 889 * ignore the index bits, so we need to reset it to index 0 890 * separately. 891 */ 892 intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0); 893 intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 894 PRE_CSC_GAMC_AUTO_INCREMENT); 895 896 for (i = 0; i < lut_size; i++) { 897 u32 v = (i << 16) / (lut_size - 1); 898 899 intel_de_write_fw(dev_priv, PRE_CSC_GAMC_DATA(pipe), v); 900 } 901 902 /* Clamp values > 1.0. */ 903 while (i++ < 35) 904 intel_de_write_fw(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16); 905 906 intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0); 907 } 908 909 static void glk_load_luts(const struct intel_crtc_state *crtc_state) 910 { 911 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 912 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 913 914 /* 915 * On GLK+ both pipe CSC and degamma LUT are controlled 916 * by csc_enable. Hence for the cases where the CSC is 917 * needed but degamma LUT is not we need to load a 918 * linear degamma LUT. In fact we'll just always load 919 * the degama LUT so that we don't have to reload 920 * it every time the pipe CSC is being enabled. 921 */ 922 if (crtc_state->hw.degamma_lut) 923 glk_load_degamma_lut(crtc_state); 924 else 925 glk_load_degamma_lut_linear(crtc_state); 926 927 switch (crtc_state->gamma_mode) { 928 case GAMMA_MODE_MODE_8BIT: 929 ilk_load_lut_8(crtc, gamma_lut); 930 break; 931 case GAMMA_MODE_MODE_10BIT: 932 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0)); 933 ivb_load_lut_ext_max(crtc_state); 934 break; 935 default: 936 MISSING_CASE(crtc_state->gamma_mode); 937 break; 938 } 939 } 940 941 /* ilk+ "12.4" interpolated format (high 10 bits) */ 942 static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color) 943 { 944 return (color->red >> 6) << 20 | (color->green >> 6) << 10 | 945 (color->blue >> 6); 946 } 947 948 /* ilk+ "12.4" interpolated format (low 6 bits) */ 949 static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color) 950 { 951 return (color->red & 0x3f) << 24 | (color->green & 0x3f) << 14 | 952 (color->blue & 0x3f) << 4; 953 } 954 955 static void 956 icl_load_gcmax(const struct intel_crtc_state *crtc_state, 957 const struct drm_color_lut *color) 958 { 959 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 960 enum pipe pipe = crtc->pipe; 961 962 /* FIXME LUT entries are 16 bit only, so we can prog 0xFFFF max */ 963 intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red); 964 intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green); 965 intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue); 966 } 967 968 static void 969 icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state) 970 { 971 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 972 const struct drm_property_blob *blob = crtc_state->hw.gamma_lut; 973 const struct drm_color_lut *lut = blob->data; 974 enum pipe pipe = crtc->pipe; 975 int i; 976 977 /* 978 * Program Super Fine segment (let's call it seg1)... 979 * 980 * Super Fine segment's step is 1/(8 * 128 * 256) and it has 981 * 9 entries, corresponding to values 0, 1/(8 * 128 * 256), 982 * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256). 983 */ 984 intel_dsb_reg_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe), 985 PAL_PREC_AUTO_INCREMENT); 986 987 for (i = 0; i < 9; i++) { 988 const struct drm_color_lut *entry = &lut[i]; 989 990 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe), 991 ilk_lut_12p4_ldw(entry)); 992 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe), 993 ilk_lut_12p4_udw(entry)); 994 } 995 } 996 997 static void 998 icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state) 999 { 1000 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1001 const struct drm_property_blob *blob = crtc_state->hw.gamma_lut; 1002 const struct drm_color_lut *lut = blob->data; 1003 const struct drm_color_lut *entry; 1004 enum pipe pipe = crtc->pipe; 1005 int i; 1006 1007 /* 1008 * Program Fine segment (let's call it seg2)... 1009 * 1010 * Fine segment's step is 1/(128 * 256) i.e. 1/(128 * 256), 2/(128 * 256) 1011 * ... 256/(128 * 256). So in order to program fine segment of LUT we 1012 * need to pick every 8th entry in the LUT, and program 256 indexes. 1013 * 1014 * PAL_PREC_INDEX[0] and PAL_PREC_INDEX[1] map to seg2[1], 1015 * seg2[0] being unused by the hardware. 1016 */ 1017 intel_dsb_reg_write(crtc_state, PREC_PAL_INDEX(pipe), 1018 PAL_PREC_AUTO_INCREMENT); 1019 for (i = 1; i < 257; i++) { 1020 entry = &lut[i * 8]; 1021 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), 1022 ilk_lut_12p4_ldw(entry)); 1023 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), 1024 ilk_lut_12p4_udw(entry)); 1025 } 1026 1027 /* 1028 * Program Coarse segment (let's call it seg3)... 1029 * 1030 * Coarse segment starts from index 0 and it's step is 1/256 ie 0, 1031 * 1/256, 2/256 ... 256/256. As per the description of each entry in LUT 1032 * above, we need to pick every (8 * 128)th entry in LUT, and 1033 * program 256 of those. 1034 * 1035 * Spec is not very clear about if entries seg3[0] and seg3[1] are 1036 * being used or not, but we still need to program these to advance 1037 * the index. 1038 */ 1039 for (i = 0; i < 256; i++) { 1040 entry = &lut[i * 8 * 128]; 1041 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), 1042 ilk_lut_12p4_ldw(entry)); 1043 intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), 1044 ilk_lut_12p4_udw(entry)); 1045 } 1046 1047 /* The last entry in the LUT is to be programmed in GCMAX */ 1048 entry = &lut[256 * 8 * 128]; 1049 icl_load_gcmax(crtc_state, entry); 1050 ivb_load_lut_ext_max(crtc_state); 1051 } 1052 1053 static void icl_load_luts(const struct intel_crtc_state *crtc_state) 1054 { 1055 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 1056 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1057 1058 if (crtc_state->hw.degamma_lut) 1059 glk_load_degamma_lut(crtc_state); 1060 1061 switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { 1062 case GAMMA_MODE_MODE_8BIT: 1063 ilk_load_lut_8(crtc, gamma_lut); 1064 break; 1065 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: 1066 icl_program_gamma_superfine_segment(crtc_state); 1067 icl_program_gamma_multi_segment(crtc_state); 1068 break; 1069 case GAMMA_MODE_MODE_10BIT: 1070 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0)); 1071 ivb_load_lut_ext_max(crtc_state); 1072 break; 1073 default: 1074 MISSING_CASE(crtc_state->gamma_mode); 1075 break; 1076 } 1077 1078 intel_dsb_commit(crtc_state); 1079 } 1080 1081 static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color) 1082 { 1083 return drm_color_lut_extract(color->green, 14) << 16 | 1084 drm_color_lut_extract(color->blue, 14); 1085 } 1086 1087 static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color) 1088 { 1089 return drm_color_lut_extract(color->red, 14); 1090 } 1091 1092 static void chv_load_cgm_degamma(struct intel_crtc *crtc, 1093 const struct drm_property_blob *blob) 1094 { 1095 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1096 const struct drm_color_lut *lut = blob->data; 1097 int i, lut_size = drm_color_lut_size(blob); 1098 enum pipe pipe = crtc->pipe; 1099 1100 for (i = 0; i < lut_size; i++) { 1101 intel_de_write_fw(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 0), 1102 chv_cgm_degamma_ldw(&lut[i])); 1103 intel_de_write_fw(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 1), 1104 chv_cgm_degamma_udw(&lut[i])); 1105 } 1106 } 1107 1108 static u32 chv_cgm_gamma_ldw(const struct drm_color_lut *color) 1109 { 1110 return drm_color_lut_extract(color->green, 10) << 16 | 1111 drm_color_lut_extract(color->blue, 10); 1112 } 1113 1114 static u32 chv_cgm_gamma_udw(const struct drm_color_lut *color) 1115 { 1116 return drm_color_lut_extract(color->red, 10); 1117 } 1118 1119 static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) 1120 { 1121 entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK, ldw), 10); 1122 entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK, ldw), 10); 1123 entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, udw), 10); 1124 } 1125 1126 static void chv_load_cgm_gamma(struct intel_crtc *crtc, 1127 const struct drm_property_blob *blob) 1128 { 1129 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1130 const struct drm_color_lut *lut = blob->data; 1131 int i, lut_size = drm_color_lut_size(blob); 1132 enum pipe pipe = crtc->pipe; 1133 1134 for (i = 0; i < lut_size; i++) { 1135 intel_de_write_fw(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0), 1136 chv_cgm_gamma_ldw(&lut[i])); 1137 intel_de_write_fw(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1), 1138 chv_cgm_gamma_udw(&lut[i])); 1139 } 1140 } 1141 1142 static void chv_load_luts(const struct intel_crtc_state *crtc_state) 1143 { 1144 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1145 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1146 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut; 1147 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 1148 const struct drm_property_blob *ctm = crtc_state->hw.ctm; 1149 1150 if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) 1151 chv_load_cgm_csc(crtc, ctm); 1152 1153 if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA) 1154 chv_load_cgm_degamma(crtc, degamma_lut); 1155 1156 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) 1157 chv_load_cgm_gamma(crtc, gamma_lut); 1158 else 1159 i965_load_luts(crtc_state); 1160 1161 intel_de_write_fw(dev_priv, CGM_PIPE_MODE(crtc->pipe), 1162 crtc_state->cgm_mode); 1163 } 1164 1165 void intel_color_load_luts(const struct intel_crtc_state *crtc_state) 1166 { 1167 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1168 1169 dev_priv->color_funcs->load_luts(crtc_state); 1170 } 1171 1172 void intel_color_commit(const struct intel_crtc_state *crtc_state) 1173 { 1174 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1175 1176 dev_priv->color_funcs->color_commit(crtc_state); 1177 } 1178 1179 static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state) 1180 { 1181 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 1182 struct intel_atomic_state *state = 1183 to_intel_atomic_state(new_crtc_state->uapi.state); 1184 const struct intel_crtc_state *old_crtc_state = 1185 intel_atomic_get_old_crtc_state(state, crtc); 1186 1187 return !old_crtc_state->hw.gamma_lut && 1188 !old_crtc_state->hw.degamma_lut; 1189 } 1190 1191 static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state) 1192 { 1193 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 1194 struct intel_atomic_state *state = 1195 to_intel_atomic_state(new_crtc_state->uapi.state); 1196 const struct intel_crtc_state *old_crtc_state = 1197 intel_atomic_get_old_crtc_state(state, crtc); 1198 1199 /* 1200 * CGM_PIPE_MODE is itself single buffered. We'd have to 1201 * somehow split it out from chv_load_luts() if we wanted 1202 * the ability to preload the CGM LUTs/CSC without tearing. 1203 */ 1204 if (old_crtc_state->cgm_mode || new_crtc_state->cgm_mode) 1205 return false; 1206 1207 return !old_crtc_state->hw.gamma_lut; 1208 } 1209 1210 static bool glk_can_preload_luts(const struct intel_crtc_state *new_crtc_state) 1211 { 1212 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 1213 struct intel_atomic_state *state = 1214 to_intel_atomic_state(new_crtc_state->uapi.state); 1215 const struct intel_crtc_state *old_crtc_state = 1216 intel_atomic_get_old_crtc_state(state, crtc); 1217 1218 /* 1219 * The hardware degamma is active whenever the pipe 1220 * CSC is active. Thus even if the old state has no 1221 * software degamma we need to avoid clobbering the 1222 * linear hardware degamma mid scanout. 1223 */ 1224 return !old_crtc_state->csc_enable && 1225 !old_crtc_state->hw.gamma_lut; 1226 } 1227 1228 int intel_color_check(struct intel_crtc_state *crtc_state) 1229 { 1230 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1231 1232 return dev_priv->color_funcs->color_check(crtc_state); 1233 } 1234 1235 void intel_color_get_config(struct intel_crtc_state *crtc_state) 1236 { 1237 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1238 1239 if (dev_priv->color_funcs->read_luts) 1240 dev_priv->color_funcs->read_luts(crtc_state); 1241 } 1242 1243 static bool need_plane_update(struct intel_plane *plane, 1244 const struct intel_crtc_state *crtc_state) 1245 { 1246 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1247 1248 /* 1249 * On pre-SKL the pipe gamma enable and pipe csc enable for 1250 * the pipe bottom color are configured via the primary plane. 1251 * We have to reconfigure that even if the plane is inactive. 1252 */ 1253 return crtc_state->active_planes & BIT(plane->id) || 1254 (DISPLAY_VER(dev_priv) < 9 && 1255 plane->id == PLANE_PRIMARY); 1256 } 1257 1258 static int 1259 intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state) 1260 { 1261 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 1262 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1263 struct intel_atomic_state *state = 1264 to_intel_atomic_state(new_crtc_state->uapi.state); 1265 const struct intel_crtc_state *old_crtc_state = 1266 intel_atomic_get_old_crtc_state(state, crtc); 1267 struct intel_plane *plane; 1268 1269 if (!new_crtc_state->hw.active || 1270 drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) 1271 return 0; 1272 1273 if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable && 1274 new_crtc_state->csc_enable == old_crtc_state->csc_enable) 1275 return 0; 1276 1277 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 1278 struct intel_plane_state *plane_state; 1279 1280 if (!need_plane_update(plane, new_crtc_state)) 1281 continue; 1282 1283 plane_state = intel_atomic_get_plane_state(state, plane); 1284 if (IS_ERR(plane_state)) 1285 return PTR_ERR(plane_state); 1286 1287 new_crtc_state->update_planes |= BIT(plane->id); 1288 } 1289 1290 return 0; 1291 } 1292 1293 static int check_lut_size(const struct drm_property_blob *lut, int expected) 1294 { 1295 int len; 1296 1297 if (!lut) 1298 return 0; 1299 1300 len = drm_color_lut_size(lut); 1301 if (len != expected) { 1302 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n", 1303 len, expected); 1304 return -EINVAL; 1305 } 1306 1307 return 0; 1308 } 1309 1310 static int check_luts(const struct intel_crtc_state *crtc_state) 1311 { 1312 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1313 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 1314 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut; 1315 int gamma_length, degamma_length; 1316 u32 gamma_tests, degamma_tests; 1317 1318 /* Always allow legacy gamma LUT with no further checking. */ 1319 if (crtc_state_is_legacy_gamma(crtc_state)) 1320 return 0; 1321 1322 /* C8 relies on its palette being stored in the legacy LUT */ 1323 if (crtc_state->c8_planes) { 1324 drm_dbg_kms(&dev_priv->drm, 1325 "C8 pixelformat requires the legacy LUT\n"); 1326 return -EINVAL; 1327 } 1328 1329 degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size; 1330 gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size; 1331 degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests; 1332 gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests; 1333 1334 if (check_lut_size(degamma_lut, degamma_length) || 1335 check_lut_size(gamma_lut, gamma_length)) 1336 return -EINVAL; 1337 1338 if (drm_color_lut_check(degamma_lut, degamma_tests) || 1339 drm_color_lut_check(gamma_lut, gamma_tests)) 1340 return -EINVAL; 1341 1342 return 0; 1343 } 1344 1345 static u32 i9xx_gamma_mode(struct intel_crtc_state *crtc_state) 1346 { 1347 if (!crtc_state->gamma_enable || 1348 crtc_state_is_legacy_gamma(crtc_state)) 1349 return GAMMA_MODE_MODE_8BIT; 1350 else 1351 return GAMMA_MODE_MODE_10BIT; /* i965+ only */ 1352 } 1353 1354 static int i9xx_color_check(struct intel_crtc_state *crtc_state) 1355 { 1356 int ret; 1357 1358 ret = check_luts(crtc_state); 1359 if (ret) 1360 return ret; 1361 1362 crtc_state->gamma_enable = 1363 crtc_state->hw.gamma_lut && 1364 !crtc_state->c8_planes; 1365 1366 crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state); 1367 1368 ret = intel_color_add_affected_planes(crtc_state); 1369 if (ret) 1370 return ret; 1371 1372 crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 1373 1374 return 0; 1375 } 1376 1377 static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state) 1378 { 1379 u32 cgm_mode = 0; 1380 1381 if (crtc_state_is_legacy_gamma(crtc_state)) 1382 return 0; 1383 1384 if (crtc_state->hw.degamma_lut) 1385 cgm_mode |= CGM_PIPE_MODE_DEGAMMA; 1386 if (crtc_state->hw.ctm) 1387 cgm_mode |= CGM_PIPE_MODE_CSC; 1388 if (crtc_state->hw.gamma_lut) 1389 cgm_mode |= CGM_PIPE_MODE_GAMMA; 1390 1391 return cgm_mode; 1392 } 1393 1394 /* 1395 * CHV color pipeline: 1396 * u0.10 -> CGM degamma -> u0.14 -> CGM csc -> u0.14 -> CGM gamma -> 1397 * u0.10 -> WGC csc -> u0.10 -> pipe gamma -> u0.10 1398 * 1399 * We always bypass the WGC csc and use the CGM csc 1400 * instead since it has degamma and better precision. 1401 */ 1402 static int chv_color_check(struct intel_crtc_state *crtc_state) 1403 { 1404 int ret; 1405 1406 ret = check_luts(crtc_state); 1407 if (ret) 1408 return ret; 1409 1410 /* 1411 * Pipe gamma will be used only for the legacy LUT. 1412 * Otherwise we bypass it and use the CGM gamma instead. 1413 */ 1414 crtc_state->gamma_enable = 1415 crtc_state_is_legacy_gamma(crtc_state) && 1416 !crtc_state->c8_planes; 1417 1418 crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT; 1419 1420 crtc_state->cgm_mode = chv_cgm_mode(crtc_state); 1421 1422 ret = intel_color_add_affected_planes(crtc_state); 1423 if (ret) 1424 return ret; 1425 1426 crtc_state->preload_luts = chv_can_preload_luts(crtc_state); 1427 1428 return 0; 1429 } 1430 1431 static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state) 1432 { 1433 if (!crtc_state->gamma_enable || 1434 crtc_state_is_legacy_gamma(crtc_state)) 1435 return GAMMA_MODE_MODE_8BIT; 1436 else 1437 return GAMMA_MODE_MODE_10BIT; 1438 } 1439 1440 static u32 ilk_csc_mode(const struct intel_crtc_state *crtc_state) 1441 { 1442 /* 1443 * CSC comes after the LUT in RGB->YCbCr mode. 1444 * RGB->YCbCr needs the limited range offsets added to 1445 * the output. RGB limited range output is handled by 1446 * the hw automagically elsewhere. 1447 */ 1448 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 1449 return CSC_BLACK_SCREEN_OFFSET; 1450 1451 return CSC_MODE_YUV_TO_RGB | 1452 CSC_POSITION_BEFORE_GAMMA; 1453 } 1454 1455 static int ilk_color_check(struct intel_crtc_state *crtc_state) 1456 { 1457 int ret; 1458 1459 ret = check_luts(crtc_state); 1460 if (ret) 1461 return ret; 1462 1463 crtc_state->gamma_enable = 1464 crtc_state->hw.gamma_lut && 1465 !crtc_state->c8_planes; 1466 1467 /* 1468 * We don't expose the ctm on ilk/snb currently, also RGB 1469 * limited range output is handled by the hw automagically. 1470 */ 1471 crtc_state->csc_enable = 1472 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB; 1473 1474 crtc_state->gamma_mode = ilk_gamma_mode(crtc_state); 1475 1476 crtc_state->csc_mode = ilk_csc_mode(crtc_state); 1477 1478 ret = intel_color_add_affected_planes(crtc_state); 1479 if (ret) 1480 return ret; 1481 1482 crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 1483 1484 return 0; 1485 } 1486 1487 static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state) 1488 { 1489 if (!crtc_state->gamma_enable || 1490 crtc_state_is_legacy_gamma(crtc_state)) 1491 return GAMMA_MODE_MODE_8BIT; 1492 else if (crtc_state->hw.gamma_lut && 1493 crtc_state->hw.degamma_lut) 1494 return GAMMA_MODE_MODE_SPLIT; 1495 else 1496 return GAMMA_MODE_MODE_10BIT; 1497 } 1498 1499 static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state) 1500 { 1501 bool limited_color_range = ilk_csc_limited_range(crtc_state); 1502 1503 /* 1504 * CSC comes after the LUT in degamma, RGB->YCbCr, 1505 * and RGB full->limited range mode. 1506 */ 1507 if (crtc_state->hw.degamma_lut || 1508 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || 1509 limited_color_range) 1510 return 0; 1511 1512 return CSC_POSITION_BEFORE_GAMMA; 1513 } 1514 1515 static int ivb_color_check(struct intel_crtc_state *crtc_state) 1516 { 1517 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1518 bool limited_color_range = ilk_csc_limited_range(crtc_state); 1519 int ret; 1520 1521 ret = check_luts(crtc_state); 1522 if (ret) 1523 return ret; 1524 1525 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB && 1526 crtc_state->hw.ctm) { 1527 drm_dbg_kms(&dev_priv->drm, 1528 "YCBCR and CTM together are not possible\n"); 1529 return -EINVAL; 1530 } 1531 1532 crtc_state->gamma_enable = 1533 (crtc_state->hw.gamma_lut || 1534 crtc_state->hw.degamma_lut) && 1535 !crtc_state->c8_planes; 1536 1537 crtc_state->csc_enable = 1538 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || 1539 crtc_state->hw.ctm || limited_color_range; 1540 1541 crtc_state->gamma_mode = ivb_gamma_mode(crtc_state); 1542 1543 crtc_state->csc_mode = ivb_csc_mode(crtc_state); 1544 1545 ret = intel_color_add_affected_planes(crtc_state); 1546 if (ret) 1547 return ret; 1548 1549 crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 1550 1551 return 0; 1552 } 1553 1554 static u32 glk_gamma_mode(const struct intel_crtc_state *crtc_state) 1555 { 1556 if (!crtc_state->gamma_enable || 1557 crtc_state_is_legacy_gamma(crtc_state)) 1558 return GAMMA_MODE_MODE_8BIT; 1559 else 1560 return GAMMA_MODE_MODE_10BIT; 1561 } 1562 1563 static int glk_color_check(struct intel_crtc_state *crtc_state) 1564 { 1565 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1566 int ret; 1567 1568 ret = check_luts(crtc_state); 1569 if (ret) 1570 return ret; 1571 1572 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB && 1573 crtc_state->hw.ctm) { 1574 drm_dbg_kms(&dev_priv->drm, 1575 "YCBCR and CTM together are not possible\n"); 1576 return -EINVAL; 1577 } 1578 1579 crtc_state->gamma_enable = 1580 crtc_state->hw.gamma_lut && 1581 !crtc_state->c8_planes; 1582 1583 /* On GLK+ degamma LUT is controlled by csc_enable */ 1584 crtc_state->csc_enable = 1585 crtc_state->hw.degamma_lut || 1586 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || 1587 crtc_state->hw.ctm || crtc_state->limited_color_range; 1588 1589 crtc_state->gamma_mode = glk_gamma_mode(crtc_state); 1590 1591 crtc_state->csc_mode = 0; 1592 1593 ret = intel_color_add_affected_planes(crtc_state); 1594 if (ret) 1595 return ret; 1596 1597 crtc_state->preload_luts = glk_can_preload_luts(crtc_state); 1598 1599 return 0; 1600 } 1601 1602 static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state) 1603 { 1604 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1605 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1606 u32 gamma_mode = 0; 1607 1608 if (crtc_state->hw.degamma_lut) 1609 gamma_mode |= PRE_CSC_GAMMA_ENABLE; 1610 1611 if (crtc_state->hw.gamma_lut && 1612 !crtc_state->c8_planes) 1613 gamma_mode |= POST_CSC_GAMMA_ENABLE; 1614 1615 if (!crtc_state->hw.gamma_lut || 1616 crtc_state_is_legacy_gamma(crtc_state)) 1617 gamma_mode |= GAMMA_MODE_MODE_8BIT; 1618 /* 1619 * Enable 10bit gamma for D13 1620 * ToDo: Extend to Logarithmic Gamma once the new UAPI 1621 * is acccepted and implemented by a userspace consumer 1622 */ 1623 else if (DISPLAY_VER(i915) >= 13) 1624 gamma_mode |= GAMMA_MODE_MODE_10BIT; 1625 else 1626 gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED; 1627 1628 return gamma_mode; 1629 } 1630 1631 static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state) 1632 { 1633 u32 csc_mode = 0; 1634 1635 if (crtc_state->hw.ctm) 1636 csc_mode |= ICL_CSC_ENABLE; 1637 1638 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || 1639 crtc_state->limited_color_range) 1640 csc_mode |= ICL_OUTPUT_CSC_ENABLE; 1641 1642 return csc_mode; 1643 } 1644 1645 static int icl_color_check(struct intel_crtc_state *crtc_state) 1646 { 1647 int ret; 1648 1649 ret = check_luts(crtc_state); 1650 if (ret) 1651 return ret; 1652 1653 crtc_state->gamma_mode = icl_gamma_mode(crtc_state); 1654 1655 crtc_state->csc_mode = icl_csc_mode(crtc_state); 1656 1657 crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 1658 1659 return 0; 1660 } 1661 1662 static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state) 1663 { 1664 if (!crtc_state->gamma_enable) 1665 return 0; 1666 1667 switch (crtc_state->gamma_mode) { 1668 case GAMMA_MODE_MODE_8BIT: 1669 return 8; 1670 case GAMMA_MODE_MODE_10BIT: 1671 return 16; 1672 default: 1673 MISSING_CASE(crtc_state->gamma_mode); 1674 return 0; 1675 } 1676 } 1677 1678 static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state) 1679 { 1680 if (!crtc_state->gamma_enable) 1681 return 0; 1682 1683 if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0) 1684 return 0; 1685 1686 switch (crtc_state->gamma_mode) { 1687 case GAMMA_MODE_MODE_8BIT: 1688 return 8; 1689 case GAMMA_MODE_MODE_10BIT: 1690 return 10; 1691 default: 1692 MISSING_CASE(crtc_state->gamma_mode); 1693 return 0; 1694 } 1695 } 1696 1697 static int chv_gamma_precision(const struct intel_crtc_state *crtc_state) 1698 { 1699 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) 1700 return 10; 1701 else 1702 return i9xx_gamma_precision(crtc_state); 1703 } 1704 1705 static int glk_gamma_precision(const struct intel_crtc_state *crtc_state) 1706 { 1707 if (!crtc_state->gamma_enable) 1708 return 0; 1709 1710 switch (crtc_state->gamma_mode) { 1711 case GAMMA_MODE_MODE_8BIT: 1712 return 8; 1713 case GAMMA_MODE_MODE_10BIT: 1714 return 10; 1715 default: 1716 MISSING_CASE(crtc_state->gamma_mode); 1717 return 0; 1718 } 1719 } 1720 1721 static int icl_gamma_precision(const struct intel_crtc_state *crtc_state) 1722 { 1723 if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0) 1724 return 0; 1725 1726 switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { 1727 case GAMMA_MODE_MODE_8BIT: 1728 return 8; 1729 case GAMMA_MODE_MODE_10BIT: 1730 return 10; 1731 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: 1732 return 16; 1733 default: 1734 MISSING_CASE(crtc_state->gamma_mode); 1735 return 0; 1736 } 1737 } 1738 1739 int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state) 1740 { 1741 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1742 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1743 1744 if (HAS_GMCH(dev_priv)) { 1745 if (IS_CHERRYVIEW(dev_priv)) 1746 return chv_gamma_precision(crtc_state); 1747 else 1748 return i9xx_gamma_precision(crtc_state); 1749 } else { 1750 if (DISPLAY_VER(dev_priv) >= 11) 1751 return icl_gamma_precision(crtc_state); 1752 else if (DISPLAY_VER(dev_priv) == 10) 1753 return glk_gamma_precision(crtc_state); 1754 else if (IS_IRONLAKE(dev_priv)) 1755 return ilk_gamma_precision(crtc_state); 1756 } 1757 1758 return 0; 1759 } 1760 1761 static bool err_check(struct drm_color_lut *lut1, 1762 struct drm_color_lut *lut2, u32 err) 1763 { 1764 return ((abs((long)lut2->red - lut1->red)) <= err) && 1765 ((abs((long)lut2->blue - lut1->blue)) <= err) && 1766 ((abs((long)lut2->green - lut1->green)) <= err); 1767 } 1768 1769 static bool intel_color_lut_entries_equal(struct drm_color_lut *lut1, 1770 struct drm_color_lut *lut2, 1771 int lut_size, u32 err) 1772 { 1773 int i; 1774 1775 for (i = 0; i < lut_size; i++) { 1776 if (!err_check(&lut1[i], &lut2[i], err)) 1777 return false; 1778 } 1779 1780 return true; 1781 } 1782 1783 bool intel_color_lut_equal(struct drm_property_blob *blob1, 1784 struct drm_property_blob *blob2, 1785 u32 gamma_mode, u32 bit_precision) 1786 { 1787 struct drm_color_lut *lut1, *lut2; 1788 int lut_size1, lut_size2; 1789 u32 err; 1790 1791 if (!blob1 != !blob2) 1792 return false; 1793 1794 if (!blob1) 1795 return true; 1796 1797 lut_size1 = drm_color_lut_size(blob1); 1798 lut_size2 = drm_color_lut_size(blob2); 1799 1800 /* check sw and hw lut size */ 1801 if (lut_size1 != lut_size2) 1802 return false; 1803 1804 lut1 = blob1->data; 1805 lut2 = blob2->data; 1806 1807 err = 0xffff >> bit_precision; 1808 1809 /* check sw and hw lut entry to be equal */ 1810 switch (gamma_mode & GAMMA_MODE_MODE_MASK) { 1811 case GAMMA_MODE_MODE_8BIT: 1812 case GAMMA_MODE_MODE_10BIT: 1813 if (!intel_color_lut_entries_equal(lut1, lut2, 1814 lut_size2, err)) 1815 return false; 1816 break; 1817 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: 1818 if (!intel_color_lut_entries_equal(lut1, lut2, 1819 9, err)) 1820 return false; 1821 break; 1822 default: 1823 MISSING_CASE(gamma_mode); 1824 return false; 1825 } 1826 1827 return true; 1828 } 1829 1830 static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc) 1831 { 1832 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1833 enum pipe pipe = crtc->pipe; 1834 struct drm_property_blob *blob; 1835 struct drm_color_lut *lut; 1836 int i; 1837 1838 blob = drm_property_create_blob(&dev_priv->drm, 1839 sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH, 1840 NULL); 1841 if (IS_ERR(blob)) 1842 return NULL; 1843 1844 lut = blob->data; 1845 1846 for (i = 0; i < LEGACY_LUT_LENGTH; i++) { 1847 u32 val = intel_de_read_fw(dev_priv, PALETTE(pipe, i)); 1848 1849 i9xx_lut_8_pack(&lut[i], val); 1850 } 1851 1852 return blob; 1853 } 1854 1855 static void i9xx_read_luts(struct intel_crtc_state *crtc_state) 1856 { 1857 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1858 1859 if (!crtc_state->gamma_enable) 1860 return; 1861 1862 crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc); 1863 } 1864 1865 static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc) 1866 { 1867 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1868 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; 1869 enum pipe pipe = crtc->pipe; 1870 struct drm_property_blob *blob; 1871 struct drm_color_lut *lut; 1872 1873 blob = drm_property_create_blob(&dev_priv->drm, 1874 sizeof(struct drm_color_lut) * lut_size, 1875 NULL); 1876 if (IS_ERR(blob)) 1877 return NULL; 1878 1879 lut = blob->data; 1880 1881 for (i = 0; i < lut_size - 1; i++) { 1882 u32 ldw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 0)); 1883 u32 udw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 1)); 1884 1885 i965_lut_10p6_pack(&lut[i], ldw, udw); 1886 } 1887 1888 lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(pipe, 0))); 1889 lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(pipe, 1))); 1890 lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(pipe, 2))); 1891 1892 return blob; 1893 } 1894 1895 static void i965_read_luts(struct intel_crtc_state *crtc_state) 1896 { 1897 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1898 1899 if (!crtc_state->gamma_enable) 1900 return; 1901 1902 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) 1903 crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc); 1904 else 1905 crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc); 1906 } 1907 1908 static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc) 1909 { 1910 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1911 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; 1912 enum pipe pipe = crtc->pipe; 1913 struct drm_property_blob *blob; 1914 struct drm_color_lut *lut; 1915 1916 blob = drm_property_create_blob(&dev_priv->drm, 1917 sizeof(struct drm_color_lut) * lut_size, 1918 NULL); 1919 if (IS_ERR(blob)) 1920 return NULL; 1921 1922 lut = blob->data; 1923 1924 for (i = 0; i < lut_size; i++) { 1925 u32 ldw = intel_de_read_fw(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0)); 1926 u32 udw = intel_de_read_fw(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1)); 1927 1928 chv_cgm_gamma_pack(&lut[i], ldw, udw); 1929 } 1930 1931 return blob; 1932 } 1933 1934 static void chv_read_luts(struct intel_crtc_state *crtc_state) 1935 { 1936 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1937 1938 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) 1939 crtc_state->hw.gamma_lut = chv_read_cgm_gamma(crtc); 1940 else 1941 i965_read_luts(crtc_state); 1942 } 1943 1944 static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc) 1945 { 1946 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1947 enum pipe pipe = crtc->pipe; 1948 struct drm_property_blob *blob; 1949 struct drm_color_lut *lut; 1950 int i; 1951 1952 blob = drm_property_create_blob(&dev_priv->drm, 1953 sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH, 1954 NULL); 1955 if (IS_ERR(blob)) 1956 return NULL; 1957 1958 lut = blob->data; 1959 1960 for (i = 0; i < LEGACY_LUT_LENGTH; i++) { 1961 u32 val = intel_de_read_fw(dev_priv, LGC_PALETTE(pipe, i)); 1962 1963 i9xx_lut_8_pack(&lut[i], val); 1964 } 1965 1966 return blob; 1967 } 1968 1969 static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc) 1970 { 1971 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1972 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; 1973 enum pipe pipe = crtc->pipe; 1974 struct drm_property_blob *blob; 1975 struct drm_color_lut *lut; 1976 1977 blob = drm_property_create_blob(&dev_priv->drm, 1978 sizeof(struct drm_color_lut) * lut_size, 1979 NULL); 1980 if (IS_ERR(blob)) 1981 return NULL; 1982 1983 lut = blob->data; 1984 1985 for (i = 0; i < lut_size; i++) { 1986 u32 val = intel_de_read_fw(dev_priv, PREC_PALETTE(pipe, i)); 1987 1988 ilk_lut_10_pack(&lut[i], val); 1989 } 1990 1991 return blob; 1992 } 1993 1994 static void ilk_read_luts(struct intel_crtc_state *crtc_state) 1995 { 1996 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1997 1998 if (!crtc_state->gamma_enable) 1999 return; 2000 2001 if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0) 2002 return; 2003 2004 switch (crtc_state->gamma_mode) { 2005 case GAMMA_MODE_MODE_8BIT: 2006 crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc); 2007 break; 2008 case GAMMA_MODE_MODE_10BIT: 2009 crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc); 2010 break; 2011 default: 2012 MISSING_CASE(crtc_state->gamma_mode); 2013 break; 2014 } 2015 } 2016 2017 /* On BDW+ the index auto increment mode actually works */ 2018 static struct drm_property_blob *bdw_read_lut_10(struct intel_crtc *crtc, 2019 u32 prec_index) 2020 { 2021 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2022 int i, hw_lut_size = ivb_lut_10_size(prec_index); 2023 int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; 2024 enum pipe pipe = crtc->pipe; 2025 struct drm_property_blob *blob; 2026 struct drm_color_lut *lut; 2027 2028 drm_WARN_ON(&dev_priv->drm, lut_size != hw_lut_size); 2029 2030 blob = drm_property_create_blob(&dev_priv->drm, 2031 sizeof(struct drm_color_lut) * lut_size, 2032 NULL); 2033 if (IS_ERR(blob)) 2034 return NULL; 2035 2036 lut = blob->data; 2037 2038 intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe), 2039 prec_index | PAL_PREC_AUTO_INCREMENT); 2040 2041 for (i = 0; i < lut_size; i++) { 2042 u32 val = intel_de_read_fw(dev_priv, PREC_PAL_DATA(pipe)); 2043 2044 ilk_lut_10_pack(&lut[i], val); 2045 } 2046 2047 intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe), 0); 2048 2049 return blob; 2050 } 2051 2052 static void glk_read_luts(struct intel_crtc_state *crtc_state) 2053 { 2054 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2055 2056 if (!crtc_state->gamma_enable) 2057 return; 2058 2059 switch (crtc_state->gamma_mode) { 2060 case GAMMA_MODE_MODE_8BIT: 2061 crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc); 2062 break; 2063 case GAMMA_MODE_MODE_10BIT: 2064 crtc_state->hw.gamma_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0)); 2065 break; 2066 default: 2067 MISSING_CASE(crtc_state->gamma_mode); 2068 break; 2069 } 2070 } 2071 2072 static struct drm_property_blob * 2073 icl_read_lut_multi_segment(struct intel_crtc *crtc) 2074 { 2075 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2076 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; 2077 enum pipe pipe = crtc->pipe; 2078 struct drm_property_blob *blob; 2079 struct drm_color_lut *lut; 2080 2081 blob = drm_property_create_blob(&dev_priv->drm, 2082 sizeof(struct drm_color_lut) * lut_size, 2083 NULL); 2084 if (IS_ERR(blob)) 2085 return NULL; 2086 2087 lut = blob->data; 2088 2089 intel_de_write_fw(dev_priv, PREC_PAL_MULTI_SEG_INDEX(pipe), 2090 PAL_PREC_AUTO_INCREMENT); 2091 2092 for (i = 0; i < 9; i++) { 2093 u32 ldw = intel_de_read_fw(dev_priv, PREC_PAL_MULTI_SEG_DATA(pipe)); 2094 u32 udw = intel_de_read_fw(dev_priv, PREC_PAL_MULTI_SEG_DATA(pipe)); 2095 2096 icl_lut_multi_seg_pack(&lut[i], ldw, udw); 2097 } 2098 2099 intel_de_write_fw(dev_priv, PREC_PAL_MULTI_SEG_INDEX(pipe), 0); 2100 2101 /* 2102 * FIXME readouts from PAL_PREC_DATA register aren't giving 2103 * correct values in the case of fine and coarse segments. 2104 * Restricting readouts only for super fine segment as of now. 2105 */ 2106 2107 return blob; 2108 } 2109 2110 static void icl_read_luts(struct intel_crtc_state *crtc_state) 2111 { 2112 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2113 2114 if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0) 2115 return; 2116 2117 switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { 2118 case GAMMA_MODE_MODE_8BIT: 2119 crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc); 2120 break; 2121 case GAMMA_MODE_MODE_10BIT: 2122 crtc_state->hw.gamma_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0)); 2123 break; 2124 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: 2125 crtc_state->hw.gamma_lut = icl_read_lut_multi_segment(crtc); 2126 break; 2127 default: 2128 MISSING_CASE(crtc_state->gamma_mode); 2129 break; 2130 } 2131 } 2132 2133 static const struct intel_color_funcs chv_color_funcs = { 2134 .color_check = chv_color_check, 2135 .color_commit = i9xx_color_commit, 2136 .load_luts = chv_load_luts, 2137 .read_luts = chv_read_luts, 2138 }; 2139 2140 static const struct intel_color_funcs i965_color_funcs = { 2141 .color_check = i9xx_color_check, 2142 .color_commit = i9xx_color_commit, 2143 .load_luts = i965_load_luts, 2144 .read_luts = i965_read_luts, 2145 }; 2146 2147 static const struct intel_color_funcs i9xx_color_funcs = { 2148 .color_check = i9xx_color_check, 2149 .color_commit = i9xx_color_commit, 2150 .load_luts = i9xx_load_luts, 2151 .read_luts = i9xx_read_luts, 2152 }; 2153 2154 static const struct intel_color_funcs icl_color_funcs = { 2155 .color_check = icl_color_check, 2156 .color_commit = skl_color_commit, 2157 .load_luts = icl_load_luts, 2158 .read_luts = icl_read_luts, 2159 }; 2160 2161 static const struct intel_color_funcs glk_color_funcs = { 2162 .color_check = glk_color_check, 2163 .color_commit = skl_color_commit, 2164 .load_luts = glk_load_luts, 2165 .read_luts = glk_read_luts, 2166 }; 2167 2168 static const struct intel_color_funcs skl_color_funcs = { 2169 .color_check = ivb_color_check, 2170 .color_commit = skl_color_commit, 2171 .load_luts = bdw_load_luts, 2172 .read_luts = NULL, 2173 }; 2174 2175 static const struct intel_color_funcs bdw_color_funcs = { 2176 .color_check = ivb_color_check, 2177 .color_commit = hsw_color_commit, 2178 .load_luts = bdw_load_luts, 2179 .read_luts = NULL, 2180 }; 2181 2182 static const struct intel_color_funcs hsw_color_funcs = { 2183 .color_check = ivb_color_check, 2184 .color_commit = hsw_color_commit, 2185 .load_luts = ivb_load_luts, 2186 .read_luts = NULL, 2187 }; 2188 2189 static const struct intel_color_funcs ivb_color_funcs = { 2190 .color_check = ivb_color_check, 2191 .color_commit = ilk_color_commit, 2192 .load_luts = ivb_load_luts, 2193 .read_luts = NULL, 2194 }; 2195 2196 static const struct intel_color_funcs ilk_color_funcs = { 2197 .color_check = ilk_color_check, 2198 .color_commit = ilk_color_commit, 2199 .load_luts = ilk_load_luts, 2200 .read_luts = ilk_read_luts, 2201 }; 2202 2203 void intel_color_init(struct intel_crtc *crtc) 2204 { 2205 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2206 bool has_ctm = INTEL_INFO(dev_priv)->color.degamma_lut_size != 0; 2207 2208 drm_mode_crtc_set_gamma_size(&crtc->base, 256); 2209 2210 if (HAS_GMCH(dev_priv)) { 2211 if (IS_CHERRYVIEW(dev_priv)) { 2212 dev_priv->color_funcs = &chv_color_funcs; 2213 } else if (DISPLAY_VER(dev_priv) >= 4) { 2214 dev_priv->color_funcs = &i965_color_funcs; 2215 } else { 2216 dev_priv->color_funcs = &i9xx_color_funcs; 2217 } 2218 } else { 2219 if (DISPLAY_VER(dev_priv) >= 11) 2220 dev_priv->color_funcs = &icl_color_funcs; 2221 else if (DISPLAY_VER(dev_priv) == 10) 2222 dev_priv->color_funcs = &glk_color_funcs; 2223 else if (DISPLAY_VER(dev_priv) == 9) 2224 dev_priv->color_funcs = &skl_color_funcs; 2225 else if (DISPLAY_VER(dev_priv) == 8) 2226 dev_priv->color_funcs = &bdw_color_funcs; 2227 else if (DISPLAY_VER(dev_priv) == 7) { 2228 if (IS_HASWELL(dev_priv)) 2229 dev_priv->color_funcs = &hsw_color_funcs; 2230 else 2231 dev_priv->color_funcs = &ivb_color_funcs; 2232 } else 2233 dev_priv->color_funcs = &ilk_color_funcs; 2234 } 2235 2236 drm_crtc_enable_color_mgmt(&crtc->base, 2237 INTEL_INFO(dev_priv)->color.degamma_lut_size, 2238 has_ctm, 2239 INTEL_INFO(dev_priv)->color.gamma_lut_size); 2240 } 2241