1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include "intel_color.h" 26 #include "intel_display_types.h" 27 28 #define CTM_COEFF_SIGN (1ULL << 63) 29 30 #define CTM_COEFF_1_0 (1ULL << 32) 31 #define CTM_COEFF_2_0 (CTM_COEFF_1_0 << 1) 32 #define CTM_COEFF_4_0 (CTM_COEFF_2_0 << 1) 33 #define CTM_COEFF_8_0 (CTM_COEFF_4_0 << 1) 34 #define CTM_COEFF_0_5 (CTM_COEFF_1_0 >> 1) 35 #define CTM_COEFF_0_25 (CTM_COEFF_0_5 >> 1) 36 #define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1) 37 38 #define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255) 39 40 #define CTM_COEFF_NEGATIVE(coeff) (((coeff) & CTM_COEFF_SIGN) != 0) 41 #define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1)) 42 43 #define LEGACY_LUT_LENGTH 256 44 45 /* 46 * ILK+ csc matrix: 47 * 48 * |R/Cr| | c0 c1 c2 | ( |R/Cr| |preoff0| ) |postoff0| 49 * |G/Y | = | c3 c4 c5 | x ( |G/Y | + |preoff1| ) + |postoff1| 50 * |B/Cb| | c6 c7 c8 | ( |B/Cb| |preoff2| ) |postoff2| 51 * 52 * ILK/SNB don't have explicit post offsets, and instead 53 * CSC_MODE_YUV_TO_RGB and CSC_BLACK_SCREEN_OFFSET are used: 54 * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=0 -> 1/2, 0, 1/2 55 * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/2, 1/16, 1/2 56 * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=0 -> 0, 0, 0 57 * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/16, 1/16, 1/16 58 */ 59 60 /* 61 * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point 62 * format). This macro takes the coefficient we want transformed and the 63 * number of fractional bits. 64 * 65 * We only have a 9 bits precision window which slides depending on the value 66 * of the CTM coefficient and we write the value from bit 3. We also round the 67 * value. 68 */ 69 #define ILK_CSC_COEFF_FP(coeff, fbits) \ 70 (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8) 71 72 #define ILK_CSC_COEFF_LIMITED_RANGE 0x0dc0 73 #define ILK_CSC_COEFF_1_0 0x7800 74 75 #define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255) 76 77 /* Nop pre/post offsets */ 78 static const u16 ilk_csc_off_zero[3] = {}; 79 80 /* Identity matrix */ 81 static const u16 ilk_csc_coeff_identity[9] = { 82 ILK_CSC_COEFF_1_0, 0, 0, 83 0, ILK_CSC_COEFF_1_0, 0, 84 0, 0, ILK_CSC_COEFF_1_0, 85 }; 86 87 /* Limited range RGB post offsets */ 88 static const u16 ilk_csc_postoff_limited_range[3] = { 89 ILK_CSC_POSTOFF_LIMITED_RANGE, 90 ILK_CSC_POSTOFF_LIMITED_RANGE, 91 ILK_CSC_POSTOFF_LIMITED_RANGE, 92 }; 93 94 /* Full range RGB -> limited range RGB matrix */ 95 static const u16 ilk_csc_coeff_limited_range[9] = { 96 ILK_CSC_COEFF_LIMITED_RANGE, 0, 0, 97 0, ILK_CSC_COEFF_LIMITED_RANGE, 0, 98 0, 0, ILK_CSC_COEFF_LIMITED_RANGE, 99 }; 100 101 /* BT.709 full range RGB -> limited range YCbCr matrix */ 102 static const u16 ilk_csc_coeff_rgb_to_ycbcr[9] = { 103 0x1e08, 0x9cc0, 0xb528, 104 0x2ba8, 0x09d8, 0x37e8, 105 0xbce8, 0x9ad8, 0x1e08, 106 }; 107 108 /* Limited range YCbCr post offsets */ 109 static const u16 ilk_csc_postoff_rgb_to_ycbcr[3] = { 110 0x0800, 0x0100, 0x0800, 111 }; 112 113 static bool lut_is_legacy(const struct drm_property_blob *lut) 114 { 115 return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH; 116 } 117 118 static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state) 119 { 120 return !crtc_state->hw.degamma_lut && 121 !crtc_state->hw.ctm && 122 crtc_state->hw.gamma_lut && 123 lut_is_legacy(crtc_state->hw.gamma_lut); 124 } 125 126 /* 127 * When using limited range, multiply the matrix given by userspace by 128 * the matrix that we would use for the limited range. 129 */ 130 static u64 *ctm_mult_by_limited(u64 *result, const u64 *input) 131 { 132 int i; 133 134 for (i = 0; i < 9; i++) { 135 u64 user_coeff = input[i]; 136 u32 limited_coeff = CTM_COEFF_LIMITED_RANGE; 137 u32 abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff), 0, 138 CTM_COEFF_4_0 - 1) >> 2; 139 140 /* 141 * By scaling every co-efficient with limited range (16-235) 142 * vs full range (0-255) the final o/p will be scaled down to 143 * fit in the limited range supported by the panel. 144 */ 145 result[i] = mul_u32_u32(limited_coeff, abs_coeff) >> 30; 146 result[i] |= user_coeff & CTM_COEFF_SIGN; 147 } 148 149 return result; 150 } 151 152 static void ilk_update_pipe_csc(struct intel_crtc *crtc, 153 const u16 preoff[3], 154 const u16 coeff[9], 155 const u16 postoff[3]) 156 { 157 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 158 enum pipe pipe = crtc->pipe; 159 160 intel_de_write(dev_priv, PIPE_CSC_PREOFF_HI(pipe), preoff[0]); 161 intel_de_write(dev_priv, PIPE_CSC_PREOFF_ME(pipe), preoff[1]); 162 intel_de_write(dev_priv, PIPE_CSC_PREOFF_LO(pipe), preoff[2]); 163 164 intel_de_write(dev_priv, PIPE_CSC_COEFF_RY_GY(pipe), 165 coeff[0] << 16 | coeff[1]); 166 intel_de_write(dev_priv, PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16); 167 168 intel_de_write(dev_priv, PIPE_CSC_COEFF_RU_GU(pipe), 169 coeff[3] << 16 | coeff[4]); 170 intel_de_write(dev_priv, PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16); 171 172 intel_de_write(dev_priv, PIPE_CSC_COEFF_RV_GV(pipe), 173 coeff[6] << 16 | coeff[7]); 174 intel_de_write(dev_priv, PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16); 175 176 if (INTEL_GEN(dev_priv) >= 7) { 177 intel_de_write(dev_priv, PIPE_CSC_POSTOFF_HI(pipe), 178 postoff[0]); 179 intel_de_write(dev_priv, PIPE_CSC_POSTOFF_ME(pipe), 180 postoff[1]); 181 intel_de_write(dev_priv, PIPE_CSC_POSTOFF_LO(pipe), 182 postoff[2]); 183 } 184 } 185 186 static void icl_update_output_csc(struct intel_crtc *crtc, 187 const u16 preoff[3], 188 const u16 coeff[9], 189 const u16 postoff[3]) 190 { 191 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 192 enum pipe pipe = crtc->pipe; 193 194 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_HI(pipe), preoff[0]); 195 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_ME(pipe), preoff[1]); 196 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]); 197 198 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe), 199 coeff[0] << 16 | coeff[1]); 200 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BY(pipe), 201 coeff[2] << 16); 202 203 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe), 204 coeff[3] << 16 | coeff[4]); 205 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BU(pipe), 206 coeff[5] << 16); 207 208 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe), 209 coeff[6] << 16 | coeff[7]); 210 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BV(pipe), 211 coeff[8] << 16); 212 213 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]); 214 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]); 215 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), postoff[2]); 216 } 217 218 static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state) 219 { 220 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 221 222 /* 223 * FIXME if there's a gamma LUT after the CSC, we should 224 * do the range compression using the gamma LUT instead. 225 */ 226 return crtc_state->limited_color_range && 227 (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) || 228 IS_GEN_RANGE(dev_priv, 9, 10)); 229 } 230 231 static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state, 232 u16 coeffs[9]) 233 { 234 const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data; 235 const u64 *input; 236 u64 temp[9]; 237 int i; 238 239 if (ilk_csc_limited_range(crtc_state)) 240 input = ctm_mult_by_limited(temp, ctm->matrix); 241 else 242 input = ctm->matrix; 243 244 /* 245 * Convert fixed point S31.32 input to format supported by the 246 * hardware. 247 */ 248 for (i = 0; i < 9; i++) { 249 u64 abs_coeff = ((1ULL << 63) - 1) & input[i]; 250 251 /* 252 * Clamp input value to min/max supported by 253 * hardware. 254 */ 255 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1); 256 257 coeffs[i] = 0; 258 259 /* sign bit */ 260 if (CTM_COEFF_NEGATIVE(input[i])) 261 coeffs[i] |= 1 << 15; 262 263 if (abs_coeff < CTM_COEFF_0_125) 264 coeffs[i] |= (3 << 12) | 265 ILK_CSC_COEFF_FP(abs_coeff, 12); 266 else if (abs_coeff < CTM_COEFF_0_25) 267 coeffs[i] |= (2 << 12) | 268 ILK_CSC_COEFF_FP(abs_coeff, 11); 269 else if (abs_coeff < CTM_COEFF_0_5) 270 coeffs[i] |= (1 << 12) | 271 ILK_CSC_COEFF_FP(abs_coeff, 10); 272 else if (abs_coeff < CTM_COEFF_1_0) 273 coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9); 274 else if (abs_coeff < CTM_COEFF_2_0) 275 coeffs[i] |= (7 << 12) | 276 ILK_CSC_COEFF_FP(abs_coeff, 8); 277 else 278 coeffs[i] |= (6 << 12) | 279 ILK_CSC_COEFF_FP(abs_coeff, 7); 280 } 281 } 282 283 static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state) 284 { 285 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 286 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 287 bool limited_color_range = ilk_csc_limited_range(crtc_state); 288 289 if (crtc_state->hw.ctm) { 290 u16 coeff[9]; 291 292 ilk_csc_convert_ctm(crtc_state, coeff); 293 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeff, 294 limited_color_range ? 295 ilk_csc_postoff_limited_range : 296 ilk_csc_off_zero); 297 } else if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) { 298 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, 299 ilk_csc_coeff_rgb_to_ycbcr, 300 ilk_csc_postoff_rgb_to_ycbcr); 301 } else if (limited_color_range) { 302 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, 303 ilk_csc_coeff_limited_range, 304 ilk_csc_postoff_limited_range); 305 } else if (crtc_state->csc_enable) { 306 /* 307 * On GLK+ both pipe CSC and degamma LUT are controlled 308 * by csc_enable. Hence for the cases where the degama 309 * LUT is needed but CSC is not we need to load an 310 * identity matrix. 311 */ 312 drm_WARN_ON(&dev_priv->drm, !IS_CANNONLAKE(dev_priv) && 313 !IS_GEMINILAKE(dev_priv)); 314 315 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, 316 ilk_csc_coeff_identity, 317 ilk_csc_off_zero); 318 } 319 320 intel_de_write(dev_priv, PIPE_CSC_MODE(crtc->pipe), 321 crtc_state->csc_mode); 322 } 323 324 static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state) 325 { 326 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 327 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 328 329 if (crtc_state->hw.ctm) { 330 u16 coeff[9]; 331 332 ilk_csc_convert_ctm(crtc_state, coeff); 333 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, 334 coeff, ilk_csc_off_zero); 335 } 336 337 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) { 338 icl_update_output_csc(crtc, ilk_csc_off_zero, 339 ilk_csc_coeff_rgb_to_ycbcr, 340 ilk_csc_postoff_rgb_to_ycbcr); 341 } else if (crtc_state->limited_color_range) { 342 icl_update_output_csc(crtc, ilk_csc_off_zero, 343 ilk_csc_coeff_limited_range, 344 ilk_csc_postoff_limited_range); 345 } 346 347 intel_de_write(dev_priv, PIPE_CSC_MODE(crtc->pipe), 348 crtc_state->csc_mode); 349 } 350 351 static void chv_load_cgm_csc(struct intel_crtc *crtc, 352 const struct drm_property_blob *blob) 353 { 354 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 355 const struct drm_color_ctm *ctm = blob->data; 356 enum pipe pipe = crtc->pipe; 357 u16 coeffs[9]; 358 int i; 359 360 for (i = 0; i < ARRAY_SIZE(coeffs); i++) { 361 u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i]; 362 363 /* Round coefficient. */ 364 abs_coeff += 1 << (32 - 13); 365 /* Clamp to hardware limits. */ 366 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1); 367 368 coeffs[i] = 0; 369 370 /* Write coefficients in S3.12 format. */ 371 if (ctm->matrix[i] & (1ULL << 63)) 372 coeffs[i] |= 1 << 15; 373 374 coeffs[i] |= ((abs_coeff >> 32) & 7) << 12; 375 coeffs[i] |= (abs_coeff >> 20) & 0xfff; 376 } 377 378 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF01(pipe), 379 coeffs[1] << 16 | coeffs[0]); 380 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF23(pipe), 381 coeffs[3] << 16 | coeffs[2]); 382 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF45(pipe), 383 coeffs[5] << 16 | coeffs[4]); 384 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF67(pipe), 385 coeffs[7] << 16 | coeffs[6]); 386 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF8(pipe), 387 coeffs[8]); 388 } 389 390 /* convert hw value with given bit_precision to lut property val */ 391 static u32 intel_color_lut_pack(u32 val, int bit_precision) 392 { 393 u32 max = 0xffff >> (16 - bit_precision); 394 395 val = clamp_val(val, 0, max); 396 397 if (bit_precision < 16) 398 val <<= 16 - bit_precision; 399 400 return val; 401 } 402 403 static u32 i9xx_lut_8(const struct drm_color_lut *color) 404 { 405 return drm_color_lut_extract(color->red, 8) << 16 | 406 drm_color_lut_extract(color->green, 8) << 8 | 407 drm_color_lut_extract(color->blue, 8); 408 } 409 410 static void i9xx_lut_8_pack(struct drm_color_lut *entry, u32 val) 411 { 412 entry->red = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_RED_MASK, val), 8); 413 entry->green = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_GREEN_MASK, val), 8); 414 entry->blue = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_BLUE_MASK, val), 8); 415 } 416 417 /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */ 418 static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color) 419 { 420 return (color->red & 0xff) << 16 | 421 (color->green & 0xff) << 8 | 422 (color->blue & 0xff); 423 } 424 425 /* i965+ "10.6" interpolated format "odd DW" (high 8 bits) */ 426 static u32 i965_lut_10p6_udw(const struct drm_color_lut *color) 427 { 428 return (color->red >> 8) << 16 | 429 (color->green >> 8) << 8 | 430 (color->blue >> 8); 431 } 432 433 static void i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) 434 { 435 entry->red = REG_FIELD_GET(PALETTE_RED_MASK, udw) << 8 | 436 REG_FIELD_GET(PALETTE_RED_MASK, ldw); 437 entry->green = REG_FIELD_GET(PALETTE_GREEN_MASK, udw) << 8 | 438 REG_FIELD_GET(PALETTE_GREEN_MASK, ldw); 439 entry->blue = REG_FIELD_GET(PALETTE_BLUE_MASK, udw) << 8 | 440 REG_FIELD_GET(PALETTE_BLUE_MASK, ldw); 441 } 442 443 static u16 i965_lut_11p6_max_pack(u32 val) 444 { 445 /* PIPEGCMAX is 11.6, clamp to 10.6 */ 446 return clamp_val(val, 0, 0xffff); 447 } 448 449 static u32 ilk_lut_10(const struct drm_color_lut *color) 450 { 451 return drm_color_lut_extract(color->red, 10) << 20 | 452 drm_color_lut_extract(color->green, 10) << 10 | 453 drm_color_lut_extract(color->blue, 10); 454 } 455 456 static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val) 457 { 458 entry->red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_RED_MASK, val), 10); 459 entry->green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_GREEN_MASK, val), 10); 460 entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10); 461 } 462 463 static void icl_lut_multi_seg_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) 464 { 465 entry->red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, udw) << 6 | 466 REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, ldw); 467 entry->green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, udw) << 6 | 468 REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, ldw); 469 entry->blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, udw) << 6 | 470 REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw); 471 } 472 473 static void i9xx_color_commit(const struct intel_crtc_state *crtc_state) 474 { 475 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 476 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 477 enum pipe pipe = crtc->pipe; 478 u32 val; 479 480 val = intel_de_read(dev_priv, PIPECONF(pipe)); 481 val &= ~PIPECONF_GAMMA_MODE_MASK_I9XX; 482 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 483 intel_de_write(dev_priv, PIPECONF(pipe), val); 484 } 485 486 static void ilk_color_commit(const struct intel_crtc_state *crtc_state) 487 { 488 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 489 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 490 enum pipe pipe = crtc->pipe; 491 u32 val; 492 493 val = intel_de_read(dev_priv, PIPECONF(pipe)); 494 val &= ~PIPECONF_GAMMA_MODE_MASK_ILK; 495 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 496 intel_de_write(dev_priv, PIPECONF(pipe), val); 497 498 ilk_load_csc_matrix(crtc_state); 499 } 500 501 static void hsw_color_commit(const struct intel_crtc_state *crtc_state) 502 { 503 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 504 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 505 506 intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe), 507 crtc_state->gamma_mode); 508 509 ilk_load_csc_matrix(crtc_state); 510 } 511 512 static void skl_color_commit(const struct intel_crtc_state *crtc_state) 513 { 514 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 515 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 516 enum pipe pipe = crtc->pipe; 517 u32 val = 0; 518 519 /* 520 * We don't (yet) allow userspace to control the pipe background color, 521 * so force it to black, but apply pipe gamma and CSC appropriately 522 * so that its handling will match how we program our planes. 523 */ 524 if (crtc_state->gamma_enable) 525 val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE; 526 if (crtc_state->csc_enable) 527 val |= SKL_BOTTOM_COLOR_CSC_ENABLE; 528 intel_de_write(dev_priv, SKL_BOTTOM_COLOR(pipe), val); 529 530 intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe), 531 crtc_state->gamma_mode); 532 533 if (INTEL_GEN(dev_priv) >= 11) 534 icl_load_csc_matrix(crtc_state); 535 else 536 ilk_load_csc_matrix(crtc_state); 537 } 538 539 static void i9xx_load_lut_8(struct intel_crtc *crtc, 540 const struct drm_property_blob *blob) 541 { 542 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 543 const struct drm_color_lut *lut; 544 enum pipe pipe = crtc->pipe; 545 int i; 546 547 if (!blob) 548 return; 549 550 lut = blob->data; 551 552 for (i = 0; i < 256; i++) 553 intel_de_write(dev_priv, PALETTE(pipe, i), 554 i9xx_lut_8(&lut[i])); 555 } 556 557 static void i9xx_load_luts(const struct intel_crtc_state *crtc_state) 558 { 559 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 560 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 561 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 562 563 assert_pll_enabled(dev_priv, crtc->pipe); 564 565 i9xx_load_lut_8(crtc, gamma_lut); 566 } 567 568 static void i965_load_lut_10p6(struct intel_crtc *crtc, 569 const struct drm_property_blob *blob) 570 { 571 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 572 const struct drm_color_lut *lut = blob->data; 573 int i, lut_size = drm_color_lut_size(blob); 574 enum pipe pipe = crtc->pipe; 575 576 for (i = 0; i < lut_size - 1; i++) { 577 intel_de_write(dev_priv, PALETTE(pipe, 2 * i + 0), 578 i965_lut_10p6_ldw(&lut[i])); 579 intel_de_write(dev_priv, PALETTE(pipe, 2 * i + 1), 580 i965_lut_10p6_udw(&lut[i])); 581 } 582 583 intel_de_write(dev_priv, PIPEGCMAX(pipe, 0), lut[i].red); 584 intel_de_write(dev_priv, PIPEGCMAX(pipe, 1), lut[i].green); 585 intel_de_write(dev_priv, PIPEGCMAX(pipe, 2), lut[i].blue); 586 } 587 588 static void i965_load_luts(const struct intel_crtc_state *crtc_state) 589 { 590 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 591 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 592 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 593 594 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 595 assert_dsi_pll_enabled(dev_priv); 596 else 597 assert_pll_enabled(dev_priv, crtc->pipe); 598 599 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) 600 i9xx_load_lut_8(crtc, gamma_lut); 601 else 602 i965_load_lut_10p6(crtc, gamma_lut); 603 } 604 605 static void ilk_load_lut_8(struct intel_crtc *crtc, 606 const struct drm_property_blob *blob) 607 { 608 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 609 const struct drm_color_lut *lut; 610 enum pipe pipe = crtc->pipe; 611 int i; 612 613 if (!blob) 614 return; 615 616 lut = blob->data; 617 618 for (i = 0; i < 256; i++) 619 intel_de_write(dev_priv, LGC_PALETTE(pipe, i), 620 i9xx_lut_8(&lut[i])); 621 } 622 623 static void ilk_load_lut_10(struct intel_crtc *crtc, 624 const struct drm_property_blob *blob) 625 { 626 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 627 const struct drm_color_lut *lut = blob->data; 628 int i, lut_size = drm_color_lut_size(blob); 629 enum pipe pipe = crtc->pipe; 630 631 for (i = 0; i < lut_size; i++) 632 intel_de_write(dev_priv, PREC_PALETTE(pipe, i), 633 ilk_lut_10(&lut[i])); 634 } 635 636 static void ilk_load_luts(const struct intel_crtc_state *crtc_state) 637 { 638 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 639 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 640 641 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) 642 ilk_load_lut_8(crtc, gamma_lut); 643 else 644 ilk_load_lut_10(crtc, gamma_lut); 645 } 646 647 static int ivb_lut_10_size(u32 prec_index) 648 { 649 if (prec_index & PAL_PREC_SPLIT_MODE) 650 return 512; 651 else 652 return 1024; 653 } 654 655 /* 656 * IVB/HSW Bspec / PAL_PREC_INDEX: 657 * "Restriction : Index auto increment mode is not 658 * supported and must not be enabled." 659 */ 660 static void ivb_load_lut_10(struct intel_crtc *crtc, 661 const struct drm_property_blob *blob, 662 u32 prec_index) 663 { 664 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 665 int hw_lut_size = ivb_lut_10_size(prec_index); 666 const struct drm_color_lut *lut = blob->data; 667 int i, lut_size = drm_color_lut_size(blob); 668 enum pipe pipe = crtc->pipe; 669 670 for (i = 0; i < hw_lut_size; i++) { 671 /* We discard half the user entries in split gamma mode */ 672 const struct drm_color_lut *entry = 673 &lut[i * (lut_size - 1) / (hw_lut_size - 1)]; 674 675 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), prec_index++); 676 intel_de_write(dev_priv, PREC_PAL_DATA(pipe), 677 ilk_lut_10(entry)); 678 } 679 680 /* 681 * Reset the index, otherwise it prevents the legacy palette to be 682 * written properly. 683 */ 684 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0); 685 } 686 687 /* On BDW+ the index auto increment mode actually works */ 688 static void bdw_load_lut_10(struct intel_crtc *crtc, 689 const struct drm_property_blob *blob, 690 u32 prec_index) 691 { 692 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 693 int hw_lut_size = ivb_lut_10_size(prec_index); 694 const struct drm_color_lut *lut = blob->data; 695 int i, lut_size = drm_color_lut_size(blob); 696 enum pipe pipe = crtc->pipe; 697 698 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 699 prec_index | PAL_PREC_AUTO_INCREMENT); 700 701 for (i = 0; i < hw_lut_size; i++) { 702 /* We discard half the user entries in split gamma mode */ 703 const struct drm_color_lut *entry = 704 &lut[i * (lut_size - 1) / (hw_lut_size - 1)]; 705 706 intel_de_write(dev_priv, PREC_PAL_DATA(pipe), 707 ilk_lut_10(entry)); 708 } 709 710 /* 711 * Reset the index, otherwise it prevents the legacy palette to be 712 * written properly. 713 */ 714 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0); 715 } 716 717 static void ivb_load_lut_ext_max(struct intel_crtc *crtc) 718 { 719 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 720 struct intel_dsb *dsb = intel_dsb_get(crtc); 721 enum pipe pipe = crtc->pipe; 722 723 /* Program the max register to clamp values > 1.0. */ 724 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16); 725 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16); 726 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16); 727 728 /* 729 * Program the gc max 2 register to clamp values > 1.0. 730 * ToDo: Extend the ABI to be able to program values 731 * from 3.0 to 7.0 732 */ 733 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { 734 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 0), 735 1 << 16); 736 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 1), 737 1 << 16); 738 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 2), 739 1 << 16); 740 } 741 742 intel_dsb_put(dsb); 743 } 744 745 static void ivb_load_luts(const struct intel_crtc_state *crtc_state) 746 { 747 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 748 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 749 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut; 750 751 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) { 752 ilk_load_lut_8(crtc, gamma_lut); 753 } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) { 754 ivb_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE | 755 PAL_PREC_INDEX_VALUE(0)); 756 ivb_load_lut_ext_max(crtc); 757 ivb_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE | 758 PAL_PREC_INDEX_VALUE(512)); 759 } else { 760 const struct drm_property_blob *blob = gamma_lut ?: degamma_lut; 761 762 ivb_load_lut_10(crtc, blob, 763 PAL_PREC_INDEX_VALUE(0)); 764 ivb_load_lut_ext_max(crtc); 765 } 766 } 767 768 static void bdw_load_luts(const struct intel_crtc_state *crtc_state) 769 { 770 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 771 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 772 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut; 773 774 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) { 775 ilk_load_lut_8(crtc, gamma_lut); 776 } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) { 777 bdw_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE | 778 PAL_PREC_INDEX_VALUE(0)); 779 ivb_load_lut_ext_max(crtc); 780 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE | 781 PAL_PREC_INDEX_VALUE(512)); 782 } else { 783 const struct drm_property_blob *blob = gamma_lut ?: degamma_lut; 784 785 bdw_load_lut_10(crtc, blob, 786 PAL_PREC_INDEX_VALUE(0)); 787 ivb_load_lut_ext_max(crtc); 788 } 789 } 790 791 static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state) 792 { 793 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 794 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 795 enum pipe pipe = crtc->pipe; 796 int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; 797 const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data; 798 799 /* 800 * When setting the auto-increment bit, the hardware seems to 801 * ignore the index bits, so we need to reset it to index 0 802 * separately. 803 */ 804 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0); 805 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 806 PRE_CSC_GAMC_AUTO_INCREMENT); 807 808 for (i = 0; i < lut_size; i++) { 809 /* 810 * First 33 entries represent range from 0 to 1.0 811 * 34th and 35th entry will represent extended range 812 * inputs 3.0 and 7.0 respectively, currently clamped 813 * at 1.0. Since the precision is 16bit, the user 814 * value can be directly filled to register. 815 * The pipe degamma table in GLK+ onwards doesn't 816 * support different values per channel, so this just 817 * programs green value which will be equal to Red and 818 * Blue into the lut registers. 819 * ToDo: Extend to max 7.0. Enable 32 bit input value 820 * as compared to just 16 to achieve this. 821 */ 822 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 823 lut[i].green); 824 } 825 826 /* Clamp values > 1.0. */ 827 while (i++ < 35) 828 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16); 829 } 830 831 static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_state) 832 { 833 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 834 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 835 enum pipe pipe = crtc->pipe; 836 int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; 837 838 /* 839 * When setting the auto-increment bit, the hardware seems to 840 * ignore the index bits, so we need to reset it to index 0 841 * separately. 842 */ 843 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0); 844 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 845 PRE_CSC_GAMC_AUTO_INCREMENT); 846 847 for (i = 0; i < lut_size; i++) { 848 u32 v = (i << 16) / (lut_size - 1); 849 850 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), v); 851 } 852 853 /* Clamp values > 1.0. */ 854 while (i++ < 35) 855 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16); 856 } 857 858 static void glk_load_luts(const struct intel_crtc_state *crtc_state) 859 { 860 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 861 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 862 863 /* 864 * On GLK+ both pipe CSC and degamma LUT are controlled 865 * by csc_enable. Hence for the cases where the CSC is 866 * needed but degamma LUT is not we need to load a 867 * linear degamma LUT. In fact we'll just always load 868 * the degama LUT so that we don't have to reload 869 * it every time the pipe CSC is being enabled. 870 */ 871 if (crtc_state->hw.degamma_lut) 872 glk_load_degamma_lut(crtc_state); 873 else 874 glk_load_degamma_lut_linear(crtc_state); 875 876 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) { 877 ilk_load_lut_8(crtc, gamma_lut); 878 } else { 879 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0)); 880 ivb_load_lut_ext_max(crtc); 881 } 882 } 883 884 /* ilk+ "12.4" interpolated format (high 10 bits) */ 885 static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color) 886 { 887 return (color->red >> 6) << 20 | (color->green >> 6) << 10 | 888 (color->blue >> 6); 889 } 890 891 /* ilk+ "12.4" interpolated format (low 6 bits) */ 892 static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color) 893 { 894 return (color->red & 0x3f) << 24 | (color->green & 0x3f) << 14 | 895 (color->blue & 0x3f) << 4; 896 } 897 898 static void 899 icl_load_gcmax(const struct intel_crtc_state *crtc_state, 900 const struct drm_color_lut *color) 901 { 902 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 903 struct intel_dsb *dsb = intel_dsb_get(crtc); 904 enum pipe pipe = crtc->pipe; 905 906 /* FIXME LUT entries are 16 bit only, so we can prog 0xFFFF max */ 907 intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 0), color->red); 908 intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 1), color->green); 909 intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 2), color->blue); 910 intel_dsb_put(dsb); 911 } 912 913 static void 914 icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state) 915 { 916 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 917 const struct drm_property_blob *blob = crtc_state->hw.gamma_lut; 918 const struct drm_color_lut *lut = blob->data; 919 struct intel_dsb *dsb = intel_dsb_get(crtc); 920 enum pipe pipe = crtc->pipe; 921 int i; 922 923 /* 924 * Program Super Fine segment (let's call it seg1)... 925 * 926 * Super Fine segment's step is 1/(8 * 128 * 256) and it has 927 * 9 entries, corresponding to values 0, 1/(8 * 128 * 256), 928 * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256). 929 */ 930 intel_dsb_reg_write(dsb, PREC_PAL_MULTI_SEG_INDEX(pipe), 931 PAL_PREC_AUTO_INCREMENT); 932 933 for (i = 0; i < 9; i++) { 934 const struct drm_color_lut *entry = &lut[i]; 935 936 intel_dsb_indexed_reg_write(dsb, PREC_PAL_MULTI_SEG_DATA(pipe), 937 ilk_lut_12p4_ldw(entry)); 938 intel_dsb_indexed_reg_write(dsb, PREC_PAL_MULTI_SEG_DATA(pipe), 939 ilk_lut_12p4_udw(entry)); 940 } 941 942 intel_dsb_put(dsb); 943 } 944 945 static void 946 icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state) 947 { 948 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 949 const struct drm_property_blob *blob = crtc_state->hw.gamma_lut; 950 const struct drm_color_lut *lut = blob->data; 951 const struct drm_color_lut *entry; 952 struct intel_dsb *dsb = intel_dsb_get(crtc); 953 enum pipe pipe = crtc->pipe; 954 int i; 955 956 /* 957 * Program Fine segment (let's call it seg2)... 958 * 959 * Fine segment's step is 1/(128 * 256) i.e. 1/(128 * 256), 2/(128 * 256) 960 * ... 256/(128 * 256). So in order to program fine segment of LUT we 961 * need to pick every 8th entry in the LUT, and program 256 indexes. 962 * 963 * PAL_PREC_INDEX[0] and PAL_PREC_INDEX[1] map to seg2[1], 964 * seg2[0] being unused by the hardware. 965 */ 966 intel_dsb_reg_write(dsb, PREC_PAL_INDEX(pipe), PAL_PREC_AUTO_INCREMENT); 967 for (i = 1; i < 257; i++) { 968 entry = &lut[i * 8]; 969 intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe), 970 ilk_lut_12p4_ldw(entry)); 971 intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe), 972 ilk_lut_12p4_udw(entry)); 973 } 974 975 /* 976 * Program Coarse segment (let's call it seg3)... 977 * 978 * Coarse segment starts from index 0 and it's step is 1/256 ie 0, 979 * 1/256, 2/256 ... 256/256. As per the description of each entry in LUT 980 * above, we need to pick every (8 * 128)th entry in LUT, and 981 * program 256 of those. 982 * 983 * Spec is not very clear about if entries seg3[0] and seg3[1] are 984 * being used or not, but we still need to program these to advance 985 * the index. 986 */ 987 for (i = 0; i < 256; i++) { 988 entry = &lut[i * 8 * 128]; 989 intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe), 990 ilk_lut_12p4_ldw(entry)); 991 intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe), 992 ilk_lut_12p4_udw(entry)); 993 } 994 995 /* The last entry in the LUT is to be programmed in GCMAX */ 996 entry = &lut[256 * 8 * 128]; 997 icl_load_gcmax(crtc_state, entry); 998 ivb_load_lut_ext_max(crtc); 999 intel_dsb_put(dsb); 1000 } 1001 1002 static void icl_load_luts(const struct intel_crtc_state *crtc_state) 1003 { 1004 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 1005 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1006 struct intel_dsb *dsb = intel_dsb_get(crtc); 1007 1008 if (crtc_state->hw.degamma_lut) 1009 glk_load_degamma_lut(crtc_state); 1010 1011 switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { 1012 case GAMMA_MODE_MODE_8BIT: 1013 ilk_load_lut_8(crtc, gamma_lut); 1014 break; 1015 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: 1016 icl_program_gamma_superfine_segment(crtc_state); 1017 icl_program_gamma_multi_segment(crtc_state); 1018 break; 1019 default: 1020 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0)); 1021 ivb_load_lut_ext_max(crtc); 1022 } 1023 1024 intel_dsb_commit(dsb); 1025 intel_dsb_put(dsb); 1026 } 1027 1028 static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color) 1029 { 1030 return drm_color_lut_extract(color->green, 14) << 16 | 1031 drm_color_lut_extract(color->blue, 14); 1032 } 1033 1034 static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color) 1035 { 1036 return drm_color_lut_extract(color->red, 14); 1037 } 1038 1039 static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) 1040 { 1041 entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK, ldw), 10); 1042 entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK, ldw), 10); 1043 entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, udw), 10); 1044 } 1045 1046 static void chv_load_cgm_degamma(struct intel_crtc *crtc, 1047 const struct drm_property_blob *blob) 1048 { 1049 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1050 const struct drm_color_lut *lut = blob->data; 1051 int i, lut_size = drm_color_lut_size(blob); 1052 enum pipe pipe = crtc->pipe; 1053 1054 for (i = 0; i < lut_size; i++) { 1055 intel_de_write(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 0), 1056 chv_cgm_degamma_ldw(&lut[i])); 1057 intel_de_write(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 1), 1058 chv_cgm_degamma_udw(&lut[i])); 1059 } 1060 } 1061 1062 static u32 chv_cgm_gamma_ldw(const struct drm_color_lut *color) 1063 { 1064 return drm_color_lut_extract(color->green, 10) << 16 | 1065 drm_color_lut_extract(color->blue, 10); 1066 } 1067 1068 static u32 chv_cgm_gamma_udw(const struct drm_color_lut *color) 1069 { 1070 return drm_color_lut_extract(color->red, 10); 1071 } 1072 1073 static void chv_load_cgm_gamma(struct intel_crtc *crtc, 1074 const struct drm_property_blob *blob) 1075 { 1076 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1077 const struct drm_color_lut *lut = blob->data; 1078 int i, lut_size = drm_color_lut_size(blob); 1079 enum pipe pipe = crtc->pipe; 1080 1081 for (i = 0; i < lut_size; i++) { 1082 intel_de_write(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0), 1083 chv_cgm_gamma_ldw(&lut[i])); 1084 intel_de_write(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1), 1085 chv_cgm_gamma_udw(&lut[i])); 1086 } 1087 } 1088 1089 static void chv_load_luts(const struct intel_crtc_state *crtc_state) 1090 { 1091 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1092 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1093 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut; 1094 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 1095 const struct drm_property_blob *ctm = crtc_state->hw.ctm; 1096 1097 if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) 1098 chv_load_cgm_csc(crtc, ctm); 1099 1100 if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA) 1101 chv_load_cgm_degamma(crtc, degamma_lut); 1102 1103 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) 1104 chv_load_cgm_gamma(crtc, gamma_lut); 1105 else 1106 i965_load_luts(crtc_state); 1107 1108 intel_de_write(dev_priv, CGM_PIPE_MODE(crtc->pipe), 1109 crtc_state->cgm_mode); 1110 } 1111 1112 void intel_color_load_luts(const struct intel_crtc_state *crtc_state) 1113 { 1114 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1115 1116 dev_priv->display.load_luts(crtc_state); 1117 } 1118 1119 void intel_color_commit(const struct intel_crtc_state *crtc_state) 1120 { 1121 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1122 1123 dev_priv->display.color_commit(crtc_state); 1124 } 1125 1126 static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state) 1127 { 1128 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 1129 struct intel_atomic_state *state = 1130 to_intel_atomic_state(new_crtc_state->uapi.state); 1131 const struct intel_crtc_state *old_crtc_state = 1132 intel_atomic_get_old_crtc_state(state, crtc); 1133 1134 return !old_crtc_state->hw.gamma_lut && 1135 !old_crtc_state->hw.degamma_lut; 1136 } 1137 1138 static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state) 1139 { 1140 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 1141 struct intel_atomic_state *state = 1142 to_intel_atomic_state(new_crtc_state->uapi.state); 1143 const struct intel_crtc_state *old_crtc_state = 1144 intel_atomic_get_old_crtc_state(state, crtc); 1145 1146 /* 1147 * CGM_PIPE_MODE is itself single buffered. We'd have to 1148 * somehow split it out from chv_load_luts() if we wanted 1149 * the ability to preload the CGM LUTs/CSC without tearing. 1150 */ 1151 if (old_crtc_state->cgm_mode || new_crtc_state->cgm_mode) 1152 return false; 1153 1154 return !old_crtc_state->hw.gamma_lut; 1155 } 1156 1157 static bool glk_can_preload_luts(const struct intel_crtc_state *new_crtc_state) 1158 { 1159 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 1160 struct intel_atomic_state *state = 1161 to_intel_atomic_state(new_crtc_state->uapi.state); 1162 const struct intel_crtc_state *old_crtc_state = 1163 intel_atomic_get_old_crtc_state(state, crtc); 1164 1165 /* 1166 * The hardware degamma is active whenever the pipe 1167 * CSC is active. Thus even if the old state has no 1168 * software degamma we need to avoid clobbering the 1169 * linear hardware degamma mid scanout. 1170 */ 1171 return !old_crtc_state->csc_enable && 1172 !old_crtc_state->hw.gamma_lut; 1173 } 1174 1175 int intel_color_check(struct intel_crtc_state *crtc_state) 1176 { 1177 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1178 1179 return dev_priv->display.color_check(crtc_state); 1180 } 1181 1182 void intel_color_get_config(struct intel_crtc_state *crtc_state) 1183 { 1184 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1185 1186 if (dev_priv->display.read_luts) 1187 dev_priv->display.read_luts(crtc_state); 1188 } 1189 1190 static bool need_plane_update(struct intel_plane *plane, 1191 const struct intel_crtc_state *crtc_state) 1192 { 1193 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1194 1195 /* 1196 * On pre-SKL the pipe gamma enable and pipe csc enable for 1197 * the pipe bottom color are configured via the primary plane. 1198 * We have to reconfigure that even if the plane is inactive. 1199 */ 1200 return crtc_state->active_planes & BIT(plane->id) || 1201 (INTEL_GEN(dev_priv) < 9 && 1202 plane->id == PLANE_PRIMARY); 1203 } 1204 1205 static int 1206 intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state) 1207 { 1208 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 1209 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1210 struct intel_atomic_state *state = 1211 to_intel_atomic_state(new_crtc_state->uapi.state); 1212 const struct intel_crtc_state *old_crtc_state = 1213 intel_atomic_get_old_crtc_state(state, crtc); 1214 struct intel_plane *plane; 1215 1216 if (!new_crtc_state->hw.active || 1217 drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) 1218 return 0; 1219 1220 if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable && 1221 new_crtc_state->csc_enable == old_crtc_state->csc_enable) 1222 return 0; 1223 1224 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 1225 struct intel_plane_state *plane_state; 1226 1227 if (!need_plane_update(plane, new_crtc_state)) 1228 continue; 1229 1230 plane_state = intel_atomic_get_plane_state(state, plane); 1231 if (IS_ERR(plane_state)) 1232 return PTR_ERR(plane_state); 1233 1234 new_crtc_state->update_planes |= BIT(plane->id); 1235 } 1236 1237 return 0; 1238 } 1239 1240 static int check_lut_size(const struct drm_property_blob *lut, int expected) 1241 { 1242 int len; 1243 1244 if (!lut) 1245 return 0; 1246 1247 len = drm_color_lut_size(lut); 1248 if (len != expected) { 1249 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n", 1250 len, expected); 1251 return -EINVAL; 1252 } 1253 1254 return 0; 1255 } 1256 1257 static int check_luts(const struct intel_crtc_state *crtc_state) 1258 { 1259 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1260 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 1261 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut; 1262 int gamma_length, degamma_length; 1263 u32 gamma_tests, degamma_tests; 1264 1265 /* Always allow legacy gamma LUT with no further checking. */ 1266 if (crtc_state_is_legacy_gamma(crtc_state)) 1267 return 0; 1268 1269 /* C8 relies on its palette being stored in the legacy LUT */ 1270 if (crtc_state->c8_planes) { 1271 drm_dbg_kms(&dev_priv->drm, 1272 "C8 pixelformat requires the legacy LUT\n"); 1273 return -EINVAL; 1274 } 1275 1276 degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size; 1277 gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size; 1278 degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests; 1279 gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests; 1280 1281 if (check_lut_size(degamma_lut, degamma_length) || 1282 check_lut_size(gamma_lut, gamma_length)) 1283 return -EINVAL; 1284 1285 if (drm_color_lut_check(degamma_lut, degamma_tests) || 1286 drm_color_lut_check(gamma_lut, gamma_tests)) 1287 return -EINVAL; 1288 1289 return 0; 1290 } 1291 1292 static u32 i9xx_gamma_mode(struct intel_crtc_state *crtc_state) 1293 { 1294 if (!crtc_state->gamma_enable || 1295 crtc_state_is_legacy_gamma(crtc_state)) 1296 return GAMMA_MODE_MODE_8BIT; 1297 else 1298 return GAMMA_MODE_MODE_10BIT; /* i965+ only */ 1299 } 1300 1301 static int i9xx_color_check(struct intel_crtc_state *crtc_state) 1302 { 1303 int ret; 1304 1305 ret = check_luts(crtc_state); 1306 if (ret) 1307 return ret; 1308 1309 crtc_state->gamma_enable = 1310 crtc_state->hw.gamma_lut && 1311 !crtc_state->c8_planes; 1312 1313 crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state); 1314 1315 ret = intel_color_add_affected_planes(crtc_state); 1316 if (ret) 1317 return ret; 1318 1319 crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 1320 1321 return 0; 1322 } 1323 1324 static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state) 1325 { 1326 u32 cgm_mode = 0; 1327 1328 if (crtc_state_is_legacy_gamma(crtc_state)) 1329 return 0; 1330 1331 if (crtc_state->hw.degamma_lut) 1332 cgm_mode |= CGM_PIPE_MODE_DEGAMMA; 1333 if (crtc_state->hw.ctm) 1334 cgm_mode |= CGM_PIPE_MODE_CSC; 1335 if (crtc_state->hw.gamma_lut) 1336 cgm_mode |= CGM_PIPE_MODE_GAMMA; 1337 1338 return cgm_mode; 1339 } 1340 1341 /* 1342 * CHV color pipeline: 1343 * u0.10 -> CGM degamma -> u0.14 -> CGM csc -> u0.14 -> CGM gamma -> 1344 * u0.10 -> WGC csc -> u0.10 -> pipe gamma -> u0.10 1345 * 1346 * We always bypass the WGC csc and use the CGM csc 1347 * instead since it has degamma and better precision. 1348 */ 1349 static int chv_color_check(struct intel_crtc_state *crtc_state) 1350 { 1351 int ret; 1352 1353 ret = check_luts(crtc_state); 1354 if (ret) 1355 return ret; 1356 1357 /* 1358 * Pipe gamma will be used only for the legacy LUT. 1359 * Otherwise we bypass it and use the CGM gamma instead. 1360 */ 1361 crtc_state->gamma_enable = 1362 crtc_state_is_legacy_gamma(crtc_state) && 1363 !crtc_state->c8_planes; 1364 1365 crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT; 1366 1367 crtc_state->cgm_mode = chv_cgm_mode(crtc_state); 1368 1369 ret = intel_color_add_affected_planes(crtc_state); 1370 if (ret) 1371 return ret; 1372 1373 crtc_state->preload_luts = chv_can_preload_luts(crtc_state); 1374 1375 return 0; 1376 } 1377 1378 static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state) 1379 { 1380 if (!crtc_state->gamma_enable || 1381 crtc_state_is_legacy_gamma(crtc_state)) 1382 return GAMMA_MODE_MODE_8BIT; 1383 else 1384 return GAMMA_MODE_MODE_10BIT; 1385 } 1386 1387 static u32 ilk_csc_mode(const struct intel_crtc_state *crtc_state) 1388 { 1389 /* 1390 * CSC comes after the LUT in RGB->YCbCr mode. 1391 * RGB->YCbCr needs the limited range offsets added to 1392 * the output. RGB limited range output is handled by 1393 * the hw automagically elsewhere. 1394 */ 1395 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 1396 return CSC_BLACK_SCREEN_OFFSET; 1397 1398 return CSC_MODE_YUV_TO_RGB | 1399 CSC_POSITION_BEFORE_GAMMA; 1400 } 1401 1402 static int ilk_color_check(struct intel_crtc_state *crtc_state) 1403 { 1404 int ret; 1405 1406 ret = check_luts(crtc_state); 1407 if (ret) 1408 return ret; 1409 1410 crtc_state->gamma_enable = 1411 crtc_state->hw.gamma_lut && 1412 !crtc_state->c8_planes; 1413 1414 /* 1415 * We don't expose the ctm on ilk/snb currently, also RGB 1416 * limited range output is handled by the hw automagically. 1417 */ 1418 crtc_state->csc_enable = 1419 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB; 1420 1421 crtc_state->gamma_mode = ilk_gamma_mode(crtc_state); 1422 1423 crtc_state->csc_mode = ilk_csc_mode(crtc_state); 1424 1425 ret = intel_color_add_affected_planes(crtc_state); 1426 if (ret) 1427 return ret; 1428 1429 crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 1430 1431 return 0; 1432 } 1433 1434 static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state) 1435 { 1436 if (!crtc_state->gamma_enable || 1437 crtc_state_is_legacy_gamma(crtc_state)) 1438 return GAMMA_MODE_MODE_8BIT; 1439 else if (crtc_state->hw.gamma_lut && 1440 crtc_state->hw.degamma_lut) 1441 return GAMMA_MODE_MODE_SPLIT; 1442 else 1443 return GAMMA_MODE_MODE_10BIT; 1444 } 1445 1446 static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state) 1447 { 1448 bool limited_color_range = ilk_csc_limited_range(crtc_state); 1449 1450 /* 1451 * CSC comes after the LUT in degamma, RGB->YCbCr, 1452 * and RGB full->limited range mode. 1453 */ 1454 if (crtc_state->hw.degamma_lut || 1455 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || 1456 limited_color_range) 1457 return 0; 1458 1459 return CSC_POSITION_BEFORE_GAMMA; 1460 } 1461 1462 static int ivb_color_check(struct intel_crtc_state *crtc_state) 1463 { 1464 bool limited_color_range = ilk_csc_limited_range(crtc_state); 1465 int ret; 1466 1467 ret = check_luts(crtc_state); 1468 if (ret) 1469 return ret; 1470 1471 crtc_state->gamma_enable = 1472 (crtc_state->hw.gamma_lut || 1473 crtc_state->hw.degamma_lut) && 1474 !crtc_state->c8_planes; 1475 1476 crtc_state->csc_enable = 1477 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || 1478 crtc_state->hw.ctm || limited_color_range; 1479 1480 crtc_state->gamma_mode = ivb_gamma_mode(crtc_state); 1481 1482 crtc_state->csc_mode = ivb_csc_mode(crtc_state); 1483 1484 ret = intel_color_add_affected_planes(crtc_state); 1485 if (ret) 1486 return ret; 1487 1488 crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 1489 1490 return 0; 1491 } 1492 1493 static u32 glk_gamma_mode(const struct intel_crtc_state *crtc_state) 1494 { 1495 if (!crtc_state->gamma_enable || 1496 crtc_state_is_legacy_gamma(crtc_state)) 1497 return GAMMA_MODE_MODE_8BIT; 1498 else 1499 return GAMMA_MODE_MODE_10BIT; 1500 } 1501 1502 static int glk_color_check(struct intel_crtc_state *crtc_state) 1503 { 1504 int ret; 1505 1506 ret = check_luts(crtc_state); 1507 if (ret) 1508 return ret; 1509 1510 crtc_state->gamma_enable = 1511 crtc_state->hw.gamma_lut && 1512 !crtc_state->c8_planes; 1513 1514 /* On GLK+ degamma LUT is controlled by csc_enable */ 1515 crtc_state->csc_enable = 1516 crtc_state->hw.degamma_lut || 1517 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || 1518 crtc_state->hw.ctm || crtc_state->limited_color_range; 1519 1520 crtc_state->gamma_mode = glk_gamma_mode(crtc_state); 1521 1522 crtc_state->csc_mode = 0; 1523 1524 ret = intel_color_add_affected_planes(crtc_state); 1525 if (ret) 1526 return ret; 1527 1528 crtc_state->preload_luts = glk_can_preload_luts(crtc_state); 1529 1530 return 0; 1531 } 1532 1533 static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state) 1534 { 1535 u32 gamma_mode = 0; 1536 1537 if (crtc_state->hw.degamma_lut) 1538 gamma_mode |= PRE_CSC_GAMMA_ENABLE; 1539 1540 if (crtc_state->hw.gamma_lut && 1541 !crtc_state->c8_planes) 1542 gamma_mode |= POST_CSC_GAMMA_ENABLE; 1543 1544 if (!crtc_state->hw.gamma_lut || 1545 crtc_state_is_legacy_gamma(crtc_state)) 1546 gamma_mode |= GAMMA_MODE_MODE_8BIT; 1547 else 1548 gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED; 1549 1550 return gamma_mode; 1551 } 1552 1553 static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state) 1554 { 1555 u32 csc_mode = 0; 1556 1557 if (crtc_state->hw.ctm) 1558 csc_mode |= ICL_CSC_ENABLE; 1559 1560 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || 1561 crtc_state->limited_color_range) 1562 csc_mode |= ICL_OUTPUT_CSC_ENABLE; 1563 1564 return csc_mode; 1565 } 1566 1567 static int icl_color_check(struct intel_crtc_state *crtc_state) 1568 { 1569 int ret; 1570 1571 ret = check_luts(crtc_state); 1572 if (ret) 1573 return ret; 1574 1575 crtc_state->gamma_mode = icl_gamma_mode(crtc_state); 1576 1577 crtc_state->csc_mode = icl_csc_mode(crtc_state); 1578 1579 crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 1580 1581 return 0; 1582 } 1583 1584 static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state) 1585 { 1586 if (!crtc_state->gamma_enable) 1587 return 0; 1588 1589 switch (crtc_state->gamma_mode) { 1590 case GAMMA_MODE_MODE_8BIT: 1591 return 8; 1592 case GAMMA_MODE_MODE_10BIT: 1593 return 16; 1594 default: 1595 MISSING_CASE(crtc_state->gamma_mode); 1596 return 0; 1597 } 1598 } 1599 1600 static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state) 1601 { 1602 if (!crtc_state->gamma_enable) 1603 return 0; 1604 1605 if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0) 1606 return 0; 1607 1608 switch (crtc_state->gamma_mode) { 1609 case GAMMA_MODE_MODE_8BIT: 1610 return 8; 1611 case GAMMA_MODE_MODE_10BIT: 1612 return 10; 1613 default: 1614 MISSING_CASE(crtc_state->gamma_mode); 1615 return 0; 1616 } 1617 } 1618 1619 static int chv_gamma_precision(const struct intel_crtc_state *crtc_state) 1620 { 1621 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) 1622 return 10; 1623 else 1624 return i9xx_gamma_precision(crtc_state); 1625 } 1626 1627 static int glk_gamma_precision(const struct intel_crtc_state *crtc_state) 1628 { 1629 if (!crtc_state->gamma_enable) 1630 return 0; 1631 1632 switch (crtc_state->gamma_mode) { 1633 case GAMMA_MODE_MODE_8BIT: 1634 return 8; 1635 case GAMMA_MODE_MODE_10BIT: 1636 return 10; 1637 default: 1638 MISSING_CASE(crtc_state->gamma_mode); 1639 return 0; 1640 } 1641 } 1642 1643 static int icl_gamma_precision(const struct intel_crtc_state *crtc_state) 1644 { 1645 if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0) 1646 return 0; 1647 1648 switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { 1649 case GAMMA_MODE_MODE_8BIT: 1650 return 8; 1651 case GAMMA_MODE_MODE_10BIT: 1652 return 10; 1653 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: 1654 return 16; 1655 default: 1656 MISSING_CASE(crtc_state->gamma_mode); 1657 return 0; 1658 } 1659 } 1660 1661 int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state) 1662 { 1663 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1664 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1665 1666 if (HAS_GMCH(dev_priv)) { 1667 if (IS_CHERRYVIEW(dev_priv)) 1668 return chv_gamma_precision(crtc_state); 1669 else 1670 return i9xx_gamma_precision(crtc_state); 1671 } else { 1672 if (INTEL_GEN(dev_priv) >= 11) 1673 return icl_gamma_precision(crtc_state); 1674 else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) 1675 return glk_gamma_precision(crtc_state); 1676 else if (IS_IRONLAKE(dev_priv)) 1677 return ilk_gamma_precision(crtc_state); 1678 } 1679 1680 return 0; 1681 } 1682 1683 static bool err_check(struct drm_color_lut *lut1, 1684 struct drm_color_lut *lut2, u32 err) 1685 { 1686 return ((abs((long)lut2->red - lut1->red)) <= err) && 1687 ((abs((long)lut2->blue - lut1->blue)) <= err) && 1688 ((abs((long)lut2->green - lut1->green)) <= err); 1689 } 1690 1691 static bool intel_color_lut_entries_equal(struct drm_color_lut *lut1, 1692 struct drm_color_lut *lut2, 1693 int lut_size, u32 err) 1694 { 1695 int i; 1696 1697 for (i = 0; i < lut_size; i++) { 1698 if (!err_check(&lut1[i], &lut2[i], err)) 1699 return false; 1700 } 1701 1702 return true; 1703 } 1704 1705 bool intel_color_lut_equal(struct drm_property_blob *blob1, 1706 struct drm_property_blob *blob2, 1707 u32 gamma_mode, u32 bit_precision) 1708 { 1709 struct drm_color_lut *lut1, *lut2; 1710 int lut_size1, lut_size2; 1711 u32 err; 1712 1713 if (!blob1 != !blob2) 1714 return false; 1715 1716 if (!blob1) 1717 return true; 1718 1719 lut_size1 = drm_color_lut_size(blob1); 1720 lut_size2 = drm_color_lut_size(blob2); 1721 1722 /* check sw and hw lut size */ 1723 if (lut_size1 != lut_size2) 1724 return false; 1725 1726 lut1 = blob1->data; 1727 lut2 = blob2->data; 1728 1729 err = 0xffff >> bit_precision; 1730 1731 /* check sw and hw lut entry to be equal */ 1732 switch (gamma_mode & GAMMA_MODE_MODE_MASK) { 1733 case GAMMA_MODE_MODE_8BIT: 1734 case GAMMA_MODE_MODE_10BIT: 1735 if (!intel_color_lut_entries_equal(lut1, lut2, 1736 lut_size2, err)) 1737 return false; 1738 break; 1739 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: 1740 if (!intel_color_lut_entries_equal(lut1, lut2, 1741 9, err)) 1742 return false; 1743 break; 1744 default: 1745 MISSING_CASE(gamma_mode); 1746 return false; 1747 } 1748 1749 return true; 1750 } 1751 1752 static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc) 1753 { 1754 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1755 enum pipe pipe = crtc->pipe; 1756 struct drm_property_blob *blob; 1757 struct drm_color_lut *lut; 1758 int i; 1759 1760 blob = drm_property_create_blob(&dev_priv->drm, 1761 sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH, 1762 NULL); 1763 if (IS_ERR(blob)) 1764 return NULL; 1765 1766 lut = blob->data; 1767 1768 for (i = 0; i < LEGACY_LUT_LENGTH; i++) { 1769 u32 val = intel_de_read(dev_priv, PALETTE(pipe, i)); 1770 1771 i9xx_lut_8_pack(&lut[i], val); 1772 } 1773 1774 return blob; 1775 } 1776 1777 static void i9xx_read_luts(struct intel_crtc_state *crtc_state) 1778 { 1779 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1780 1781 if (!crtc_state->gamma_enable) 1782 return; 1783 1784 crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc); 1785 } 1786 1787 static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc) 1788 { 1789 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1790 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; 1791 enum pipe pipe = crtc->pipe; 1792 struct drm_property_blob *blob; 1793 struct drm_color_lut *lut; 1794 1795 blob = drm_property_create_blob(&dev_priv->drm, 1796 sizeof(struct drm_color_lut) * lut_size, 1797 NULL); 1798 if (IS_ERR(blob)) 1799 return NULL; 1800 1801 lut = blob->data; 1802 1803 for (i = 0; i < lut_size - 1; i++) { 1804 u32 ldw = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 0)); 1805 u32 udw = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 1)); 1806 1807 i965_lut_10p6_pack(&lut[i], ldw, udw); 1808 } 1809 1810 lut[i].red = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 0))); 1811 lut[i].green = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 1))); 1812 lut[i].blue = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 2))); 1813 1814 return blob; 1815 } 1816 1817 static void i965_read_luts(struct intel_crtc_state *crtc_state) 1818 { 1819 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1820 1821 if (!crtc_state->gamma_enable) 1822 return; 1823 1824 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) 1825 crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc); 1826 else 1827 crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc); 1828 } 1829 1830 static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc) 1831 { 1832 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1833 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; 1834 enum pipe pipe = crtc->pipe; 1835 struct drm_property_blob *blob; 1836 struct drm_color_lut *lut; 1837 1838 blob = drm_property_create_blob(&dev_priv->drm, 1839 sizeof(struct drm_color_lut) * lut_size, 1840 NULL); 1841 if (IS_ERR(blob)) 1842 return NULL; 1843 1844 lut = blob->data; 1845 1846 for (i = 0; i < lut_size; i++) { 1847 u32 ldw = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0)); 1848 u32 udw = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1)); 1849 1850 chv_cgm_gamma_pack(&lut[i], ldw, udw); 1851 } 1852 1853 return blob; 1854 } 1855 1856 static void chv_read_luts(struct intel_crtc_state *crtc_state) 1857 { 1858 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1859 1860 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) 1861 crtc_state->hw.gamma_lut = chv_read_cgm_gamma(crtc); 1862 else 1863 i965_read_luts(crtc_state); 1864 } 1865 1866 static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc) 1867 { 1868 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1869 enum pipe pipe = crtc->pipe; 1870 struct drm_property_blob *blob; 1871 struct drm_color_lut *lut; 1872 int i; 1873 1874 blob = drm_property_create_blob(&dev_priv->drm, 1875 sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH, 1876 NULL); 1877 if (IS_ERR(blob)) 1878 return NULL; 1879 1880 lut = blob->data; 1881 1882 for (i = 0; i < LEGACY_LUT_LENGTH; i++) { 1883 u32 val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i)); 1884 1885 i9xx_lut_8_pack(&lut[i], val); 1886 } 1887 1888 return blob; 1889 } 1890 1891 static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc) 1892 { 1893 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1894 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; 1895 enum pipe pipe = crtc->pipe; 1896 struct drm_property_blob *blob; 1897 struct drm_color_lut *lut; 1898 1899 blob = drm_property_create_blob(&dev_priv->drm, 1900 sizeof(struct drm_color_lut) * lut_size, 1901 NULL); 1902 if (IS_ERR(blob)) 1903 return NULL; 1904 1905 lut = blob->data; 1906 1907 for (i = 0; i < lut_size; i++) { 1908 u32 val = intel_de_read(dev_priv, PREC_PALETTE(pipe, i)); 1909 1910 ilk_lut_10_pack(&lut[i], val); 1911 } 1912 1913 return blob; 1914 } 1915 1916 static void ilk_read_luts(struct intel_crtc_state *crtc_state) 1917 { 1918 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1919 1920 if (!crtc_state->gamma_enable) 1921 return; 1922 1923 if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0) 1924 return; 1925 1926 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) 1927 crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc); 1928 else 1929 crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc); 1930 } 1931 1932 static struct drm_property_blob *glk_read_lut_10(struct intel_crtc *crtc, 1933 u32 prec_index) 1934 { 1935 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1936 int i, hw_lut_size = ivb_lut_10_size(prec_index); 1937 enum pipe pipe = crtc->pipe; 1938 struct drm_property_blob *blob; 1939 struct drm_color_lut *lut; 1940 1941 blob = drm_property_create_blob(&dev_priv->drm, 1942 sizeof(struct drm_color_lut) * hw_lut_size, 1943 NULL); 1944 if (IS_ERR(blob)) 1945 return NULL; 1946 1947 lut = blob->data; 1948 1949 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 1950 prec_index | PAL_PREC_AUTO_INCREMENT); 1951 1952 for (i = 0; i < hw_lut_size; i++) { 1953 u32 val = intel_de_read(dev_priv, PREC_PAL_DATA(pipe)); 1954 1955 ilk_lut_10_pack(&lut[i], val); 1956 } 1957 1958 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0); 1959 1960 return blob; 1961 } 1962 1963 static void glk_read_luts(struct intel_crtc_state *crtc_state) 1964 { 1965 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1966 1967 if (!crtc_state->gamma_enable) 1968 return; 1969 1970 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) 1971 crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc); 1972 else 1973 crtc_state->hw.gamma_lut = glk_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0)); 1974 } 1975 1976 static struct drm_property_blob * 1977 icl_read_lut_multi_segment(struct intel_crtc *crtc) 1978 { 1979 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1980 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; 1981 enum pipe pipe = crtc->pipe; 1982 struct drm_property_blob *blob; 1983 struct drm_color_lut *lut; 1984 1985 blob = drm_property_create_blob(&dev_priv->drm, 1986 sizeof(struct drm_color_lut) * lut_size, 1987 NULL); 1988 if (IS_ERR(blob)) 1989 return NULL; 1990 1991 lut = blob->data; 1992 1993 intel_de_write(dev_priv, PREC_PAL_MULTI_SEG_INDEX(pipe), 1994 PAL_PREC_AUTO_INCREMENT); 1995 1996 for (i = 0; i < 9; i++) { 1997 u32 ldw = intel_de_read(dev_priv, PREC_PAL_MULTI_SEG_DATA(pipe)); 1998 u32 udw = intel_de_read(dev_priv, PREC_PAL_MULTI_SEG_DATA(pipe)); 1999 2000 icl_lut_multi_seg_pack(&lut[i], ldw, udw); 2001 } 2002 2003 intel_de_write(dev_priv, PREC_PAL_MULTI_SEG_INDEX(pipe), 0); 2004 2005 /* 2006 * FIXME readouts from PAL_PREC_DATA register aren't giving 2007 * correct values in the case of fine and coarse segments. 2008 * Restricting readouts only for super fine segment as of now. 2009 */ 2010 2011 return blob; 2012 } 2013 2014 static void icl_read_luts(struct intel_crtc_state *crtc_state) 2015 { 2016 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2017 2018 if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0) 2019 return; 2020 2021 switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { 2022 case GAMMA_MODE_MODE_8BIT: 2023 crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc); 2024 break; 2025 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: 2026 crtc_state->hw.gamma_lut = icl_read_lut_multi_segment(crtc); 2027 break; 2028 default: 2029 crtc_state->hw.gamma_lut = glk_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0)); 2030 } 2031 } 2032 2033 void intel_color_init(struct intel_crtc *crtc) 2034 { 2035 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2036 bool has_ctm = INTEL_INFO(dev_priv)->color.degamma_lut_size != 0; 2037 2038 drm_mode_crtc_set_gamma_size(&crtc->base, 256); 2039 2040 if (HAS_GMCH(dev_priv)) { 2041 if (IS_CHERRYVIEW(dev_priv)) { 2042 dev_priv->display.color_check = chv_color_check; 2043 dev_priv->display.color_commit = i9xx_color_commit; 2044 dev_priv->display.load_luts = chv_load_luts; 2045 dev_priv->display.read_luts = chv_read_luts; 2046 } else if (INTEL_GEN(dev_priv) >= 4) { 2047 dev_priv->display.color_check = i9xx_color_check; 2048 dev_priv->display.color_commit = i9xx_color_commit; 2049 dev_priv->display.load_luts = i965_load_luts; 2050 dev_priv->display.read_luts = i965_read_luts; 2051 } else { 2052 dev_priv->display.color_check = i9xx_color_check; 2053 dev_priv->display.color_commit = i9xx_color_commit; 2054 dev_priv->display.load_luts = i9xx_load_luts; 2055 dev_priv->display.read_luts = i9xx_read_luts; 2056 } 2057 } else { 2058 if (INTEL_GEN(dev_priv) >= 11) 2059 dev_priv->display.color_check = icl_color_check; 2060 else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 2061 dev_priv->display.color_check = glk_color_check; 2062 else if (INTEL_GEN(dev_priv) >= 7) 2063 dev_priv->display.color_check = ivb_color_check; 2064 else 2065 dev_priv->display.color_check = ilk_color_check; 2066 2067 if (INTEL_GEN(dev_priv) >= 9) 2068 dev_priv->display.color_commit = skl_color_commit; 2069 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2070 dev_priv->display.color_commit = hsw_color_commit; 2071 else 2072 dev_priv->display.color_commit = ilk_color_commit; 2073 2074 if (INTEL_GEN(dev_priv) >= 11) { 2075 dev_priv->display.load_luts = icl_load_luts; 2076 dev_priv->display.read_luts = icl_read_luts; 2077 } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { 2078 dev_priv->display.load_luts = glk_load_luts; 2079 dev_priv->display.read_luts = glk_read_luts; 2080 } else if (INTEL_GEN(dev_priv) >= 8) { 2081 dev_priv->display.load_luts = bdw_load_luts; 2082 } else if (INTEL_GEN(dev_priv) >= 7) { 2083 dev_priv->display.load_luts = ivb_load_luts; 2084 } else { 2085 dev_priv->display.load_luts = ilk_load_luts; 2086 dev_priv->display.read_luts = ilk_read_luts; 2087 } 2088 } 2089 2090 drm_crtc_enable_color_mgmt(&crtc->base, 2091 INTEL_INFO(dev_priv)->color.degamma_lut_size, 2092 has_ctm, 2093 INTEL_INFO(dev_priv)->color.gamma_lut_size); 2094 } 2095