1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_CDCLK_H__ 7 #define __INTEL_CDCLK_H__ 8 9 #include <linux/types.h> 10 11 #include "i915_drv.h" 12 #include "intel_display.h" 13 #include "intel_global_state.h" 14 15 struct drm_i915_private; 16 struct intel_atomic_state; 17 struct intel_crtc_state; 18 19 struct intel_cdclk_vals { 20 u32 cdclk; 21 u16 refclk; 22 u8 divider; /* CD2X divider * 2 */ 23 u8 ratio; 24 }; 25 26 struct intel_cdclk_state { 27 struct intel_global_state base; 28 29 /* 30 * Logical configuration of cdclk (used for all scaling, 31 * watermark, etc. calculations and checks). This is 32 * computed as if all enabled crtcs were active. 33 */ 34 struct intel_cdclk_config logical; 35 36 /* 37 * Actual configuration of cdclk, can be different from the 38 * logical configuration only when all crtc's are DPMS off. 39 */ 40 struct intel_cdclk_config actual; 41 42 /* minimum acceptable cdclk for each pipe */ 43 int min_cdclk[I915_MAX_PIPES]; 44 /* minimum acceptable voltage level for each pipe */ 45 u8 min_voltage_level[I915_MAX_PIPES]; 46 47 /* pipe to which cd2x update is synchronized */ 48 enum pipe pipe; 49 50 /* forced minimum cdclk for glk+ audio w/a */ 51 int force_min_cdclk; 52 53 /* bitmask of active pipes */ 54 u8 active_pipes; 55 }; 56 57 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state); 58 void intel_cdclk_init_hw(struct drm_i915_private *i915); 59 void intel_cdclk_uninit_hw(struct drm_i915_private *i915); 60 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv); 61 void intel_update_max_cdclk(struct drm_i915_private *dev_priv); 62 void intel_update_cdclk(struct drm_i915_private *dev_priv); 63 u32 intel_read_rawclk(struct drm_i915_private *dev_priv); 64 bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a, 65 const struct intel_cdclk_config *b); 66 void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state); 67 void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state); 68 void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config, 69 const char *context); 70 int intel_modeset_calc_cdclk(struct intel_atomic_state *state); 71 void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv, 72 struct intel_cdclk_config *cdclk_config); 73 int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state); 74 struct intel_cdclk_state * 75 intel_atomic_get_cdclk_state(struct intel_atomic_state *state); 76 77 #define to_intel_cdclk_state(x) container_of((x), struct intel_cdclk_state, base) 78 #define intel_atomic_get_old_cdclk_state(state) \ 79 to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj)) 80 #define intel_atomic_get_new_cdclk_state(state) \ 81 to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj)) 82 83 int intel_cdclk_init(struct drm_i915_private *dev_priv); 84 85 #endif /* __INTEL_CDCLK_H__ */ 86