1 /* 2 * Copyright © 2006-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/time.h> 25 26 #include "hsw_ips.h" 27 #include "i915_reg.h" 28 #include "intel_atomic.h" 29 #include "intel_atomic_plane.h" 30 #include "intel_audio.h" 31 #include "intel_bw.h" 32 #include "intel_cdclk.h" 33 #include "intel_crtc.h" 34 #include "intel_de.h" 35 #include "intel_display_types.h" 36 #include "intel_mchbar_regs.h" 37 #include "intel_pci_config.h" 38 #include "intel_pcode.h" 39 #include "intel_psr.h" 40 #include "vlv_sideband.h" 41 42 /** 43 * DOC: CDCLK / RAWCLK 44 * 45 * The display engine uses several different clocks to do its work. There 46 * are two main clocks involved that aren't directly related to the actual 47 * pixel clock or any symbol/bit clock of the actual output port. These 48 * are the core display clock (CDCLK) and RAWCLK. 49 * 50 * CDCLK clocks most of the display pipe logic, and thus its frequency 51 * must be high enough to support the rate at which pixels are flowing 52 * through the pipes. Downscaling must also be accounted as that increases 53 * the effective pixel rate. 54 * 55 * On several platforms the CDCLK frequency can be changed dynamically 56 * to minimize power consumption for a given display configuration. 57 * Typically changes to the CDCLK frequency require all the display pipes 58 * to be shut down while the frequency is being changed. 59 * 60 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. 61 * DMC will not change the active CDCLK frequency however, so that part 62 * will still be performed by the driver directly. 63 * 64 * RAWCLK is a fixed frequency clock, often used by various auxiliary 65 * blocks such as AUX CH or backlight PWM. Hence the only thing we 66 * really need to know about RAWCLK is its frequency so that various 67 * dividers can be programmed correctly. 68 */ 69 70 struct intel_cdclk_funcs { 71 void (*get_cdclk)(struct drm_i915_private *i915, 72 struct intel_cdclk_config *cdclk_config); 73 void (*set_cdclk)(struct drm_i915_private *i915, 74 const struct intel_cdclk_config *cdclk_config, 75 enum pipe pipe); 76 int (*modeset_calc_cdclk)(struct intel_cdclk_state *state); 77 u8 (*calc_voltage_level)(int cdclk); 78 }; 79 80 void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv, 81 struct intel_cdclk_config *cdclk_config) 82 { 83 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); 84 } 85 86 static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv, 87 const struct intel_cdclk_config *cdclk_config, 88 enum pipe pipe) 89 { 90 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); 91 } 92 93 static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv, 94 struct intel_cdclk_state *cdclk_config) 95 { 96 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config); 97 } 98 99 static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv, 100 int cdclk) 101 { 102 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); 103 } 104 105 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, 106 struct intel_cdclk_config *cdclk_config) 107 { 108 cdclk_config->cdclk = 133333; 109 } 110 111 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, 112 struct intel_cdclk_config *cdclk_config) 113 { 114 cdclk_config->cdclk = 200000; 115 } 116 117 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, 118 struct intel_cdclk_config *cdclk_config) 119 { 120 cdclk_config->cdclk = 266667; 121 } 122 123 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, 124 struct intel_cdclk_config *cdclk_config) 125 { 126 cdclk_config->cdclk = 333333; 127 } 128 129 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, 130 struct intel_cdclk_config *cdclk_config) 131 { 132 cdclk_config->cdclk = 400000; 133 } 134 135 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, 136 struct intel_cdclk_config *cdclk_config) 137 { 138 cdclk_config->cdclk = 450000; 139 } 140 141 static void i85x_get_cdclk(struct drm_i915_private *dev_priv, 142 struct intel_cdclk_config *cdclk_config) 143 { 144 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 145 u16 hpllcc = 0; 146 147 /* 148 * 852GM/852GMV only supports 133 MHz and the HPLLCC 149 * encoding is different :( 150 * FIXME is this the right way to detect 852GM/852GMV? 151 */ 152 if (pdev->revision == 0x1) { 153 cdclk_config->cdclk = 133333; 154 return; 155 } 156 157 pci_bus_read_config_word(pdev->bus, 158 PCI_DEVFN(0, 3), HPLLCC, &hpllcc); 159 160 /* Assume that the hardware is in the high speed state. This 161 * should be the default. 162 */ 163 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 164 case GC_CLOCK_133_200: 165 case GC_CLOCK_133_200_2: 166 case GC_CLOCK_100_200: 167 cdclk_config->cdclk = 200000; 168 break; 169 case GC_CLOCK_166_250: 170 cdclk_config->cdclk = 250000; 171 break; 172 case GC_CLOCK_100_133: 173 cdclk_config->cdclk = 133333; 174 break; 175 case GC_CLOCK_133_266: 176 case GC_CLOCK_133_266_2: 177 case GC_CLOCK_166_266: 178 cdclk_config->cdclk = 266667; 179 break; 180 } 181 } 182 183 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, 184 struct intel_cdclk_config *cdclk_config) 185 { 186 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 187 u16 gcfgc = 0; 188 189 pci_read_config_word(pdev, GCFGC, &gcfgc); 190 191 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 192 cdclk_config->cdclk = 133333; 193 return; 194 } 195 196 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 197 case GC_DISPLAY_CLOCK_333_320_MHZ: 198 cdclk_config->cdclk = 333333; 199 break; 200 default: 201 case GC_DISPLAY_CLOCK_190_200_MHZ: 202 cdclk_config->cdclk = 190000; 203 break; 204 } 205 } 206 207 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, 208 struct intel_cdclk_config *cdclk_config) 209 { 210 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 211 u16 gcfgc = 0; 212 213 pci_read_config_word(pdev, GCFGC, &gcfgc); 214 215 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 216 cdclk_config->cdclk = 133333; 217 return; 218 } 219 220 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 221 case GC_DISPLAY_CLOCK_333_320_MHZ: 222 cdclk_config->cdclk = 320000; 223 break; 224 default: 225 case GC_DISPLAY_CLOCK_190_200_MHZ: 226 cdclk_config->cdclk = 200000; 227 break; 228 } 229 } 230 231 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) 232 { 233 static const unsigned int blb_vco[8] = { 234 [0] = 3200000, 235 [1] = 4000000, 236 [2] = 5333333, 237 [3] = 4800000, 238 [4] = 6400000, 239 }; 240 static const unsigned int pnv_vco[8] = { 241 [0] = 3200000, 242 [1] = 4000000, 243 [2] = 5333333, 244 [3] = 4800000, 245 [4] = 2666667, 246 }; 247 static const unsigned int cl_vco[8] = { 248 [0] = 3200000, 249 [1] = 4000000, 250 [2] = 5333333, 251 [3] = 6400000, 252 [4] = 3333333, 253 [5] = 3566667, 254 [6] = 4266667, 255 }; 256 static const unsigned int elk_vco[8] = { 257 [0] = 3200000, 258 [1] = 4000000, 259 [2] = 5333333, 260 [3] = 4800000, 261 }; 262 static const unsigned int ctg_vco[8] = { 263 [0] = 3200000, 264 [1] = 4000000, 265 [2] = 5333333, 266 [3] = 6400000, 267 [4] = 2666667, 268 [5] = 4266667, 269 }; 270 const unsigned int *vco_table; 271 unsigned int vco; 272 u8 tmp = 0; 273 274 /* FIXME other chipsets? */ 275 if (IS_GM45(dev_priv)) 276 vco_table = ctg_vco; 277 else if (IS_G45(dev_priv)) 278 vco_table = elk_vco; 279 else if (IS_I965GM(dev_priv)) 280 vco_table = cl_vco; 281 else if (IS_PINEVIEW(dev_priv)) 282 vco_table = pnv_vco; 283 else if (IS_G33(dev_priv)) 284 vco_table = blb_vco; 285 else 286 return 0; 287 288 tmp = intel_de_read(dev_priv, 289 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); 290 291 vco = vco_table[tmp & 0x7]; 292 if (vco == 0) 293 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", 294 tmp); 295 else 296 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); 297 298 return vco; 299 } 300 301 static void g33_get_cdclk(struct drm_i915_private *dev_priv, 302 struct intel_cdclk_config *cdclk_config) 303 { 304 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 305 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 }; 306 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 }; 307 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 }; 308 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 }; 309 const u8 *div_table; 310 unsigned int cdclk_sel; 311 u16 tmp = 0; 312 313 cdclk_config->vco = intel_hpll_vco(dev_priv); 314 315 pci_read_config_word(pdev, GCFGC, &tmp); 316 317 cdclk_sel = (tmp >> 4) & 0x7; 318 319 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 320 goto fail; 321 322 switch (cdclk_config->vco) { 323 case 3200000: 324 div_table = div_3200; 325 break; 326 case 4000000: 327 div_table = div_4000; 328 break; 329 case 4800000: 330 div_table = div_4800; 331 break; 332 case 5333333: 333 div_table = div_5333; 334 break; 335 default: 336 goto fail; 337 } 338 339 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 340 div_table[cdclk_sel]); 341 return; 342 343 fail: 344 drm_err(&dev_priv->drm, 345 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", 346 cdclk_config->vco, tmp); 347 cdclk_config->cdclk = 190476; 348 } 349 350 static void pnv_get_cdclk(struct drm_i915_private *dev_priv, 351 struct intel_cdclk_config *cdclk_config) 352 { 353 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 354 u16 gcfgc = 0; 355 356 pci_read_config_word(pdev, GCFGC, &gcfgc); 357 358 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 359 case GC_DISPLAY_CLOCK_267_MHZ_PNV: 360 cdclk_config->cdclk = 266667; 361 break; 362 case GC_DISPLAY_CLOCK_333_MHZ_PNV: 363 cdclk_config->cdclk = 333333; 364 break; 365 case GC_DISPLAY_CLOCK_444_MHZ_PNV: 366 cdclk_config->cdclk = 444444; 367 break; 368 case GC_DISPLAY_CLOCK_200_MHZ_PNV: 369 cdclk_config->cdclk = 200000; 370 break; 371 default: 372 drm_err(&dev_priv->drm, 373 "Unknown pnv display core clock 0x%04x\n", gcfgc); 374 fallthrough; 375 case GC_DISPLAY_CLOCK_133_MHZ_PNV: 376 cdclk_config->cdclk = 133333; 377 break; 378 case GC_DISPLAY_CLOCK_167_MHZ_PNV: 379 cdclk_config->cdclk = 166667; 380 break; 381 } 382 } 383 384 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, 385 struct intel_cdclk_config *cdclk_config) 386 { 387 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 388 static const u8 div_3200[] = { 16, 10, 8 }; 389 static const u8 div_4000[] = { 20, 12, 10 }; 390 static const u8 div_5333[] = { 24, 16, 14 }; 391 const u8 *div_table; 392 unsigned int cdclk_sel; 393 u16 tmp = 0; 394 395 cdclk_config->vco = intel_hpll_vco(dev_priv); 396 397 pci_read_config_word(pdev, GCFGC, &tmp); 398 399 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; 400 401 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 402 goto fail; 403 404 switch (cdclk_config->vco) { 405 case 3200000: 406 div_table = div_3200; 407 break; 408 case 4000000: 409 div_table = div_4000; 410 break; 411 case 5333333: 412 div_table = div_5333; 413 break; 414 default: 415 goto fail; 416 } 417 418 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 419 div_table[cdclk_sel]); 420 return; 421 422 fail: 423 drm_err(&dev_priv->drm, 424 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", 425 cdclk_config->vco, tmp); 426 cdclk_config->cdclk = 200000; 427 } 428 429 static void gm45_get_cdclk(struct drm_i915_private *dev_priv, 430 struct intel_cdclk_config *cdclk_config) 431 { 432 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 433 unsigned int cdclk_sel; 434 u16 tmp = 0; 435 436 cdclk_config->vco = intel_hpll_vco(dev_priv); 437 438 pci_read_config_word(pdev, GCFGC, &tmp); 439 440 cdclk_sel = (tmp >> 12) & 0x1; 441 442 switch (cdclk_config->vco) { 443 case 2666667: 444 case 4000000: 445 case 5333333: 446 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; 447 break; 448 case 3200000: 449 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; 450 break; 451 default: 452 drm_err(&dev_priv->drm, 453 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", 454 cdclk_config->vco, tmp); 455 cdclk_config->cdclk = 222222; 456 break; 457 } 458 } 459 460 static void hsw_get_cdclk(struct drm_i915_private *dev_priv, 461 struct intel_cdclk_config *cdclk_config) 462 { 463 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); 464 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 465 466 if (lcpll & LCPLL_CD_SOURCE_FCLK) 467 cdclk_config->cdclk = 800000; 468 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 469 cdclk_config->cdclk = 450000; 470 else if (freq == LCPLL_CLK_FREQ_450) 471 cdclk_config->cdclk = 450000; 472 else if (IS_HSW_ULT(dev_priv)) 473 cdclk_config->cdclk = 337500; 474 else 475 cdclk_config->cdclk = 540000; 476 } 477 478 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) 479 { 480 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 481 333333 : 320000; 482 483 /* 484 * We seem to get an unstable or solid color picture at 200MHz. 485 * Not sure what's wrong. For now use 200MHz only when all pipes 486 * are off. 487 */ 488 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) 489 return 400000; 490 else if (min_cdclk > 266667) 491 return freq_320; 492 else if (min_cdclk > 0) 493 return 266667; 494 else 495 return 200000; 496 } 497 498 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) 499 { 500 if (IS_VALLEYVIEW(dev_priv)) { 501 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ 502 return 2; 503 else if (cdclk >= 266667) 504 return 1; 505 else 506 return 0; 507 } else { 508 /* 509 * Specs are full of misinformation, but testing on actual 510 * hardware has shown that we just need to write the desired 511 * CCK divider into the Punit register. 512 */ 513 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; 514 } 515 } 516 517 static void vlv_get_cdclk(struct drm_i915_private *dev_priv, 518 struct intel_cdclk_config *cdclk_config) 519 { 520 u32 val; 521 522 vlv_iosf_sb_get(dev_priv, 523 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 524 525 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); 526 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", 527 CCK_DISPLAY_CLOCK_CONTROL, 528 cdclk_config->vco); 529 530 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 531 532 vlv_iosf_sb_put(dev_priv, 533 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 534 535 if (IS_VALLEYVIEW(dev_priv)) 536 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> 537 DSPFREQGUAR_SHIFT; 538 else 539 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> 540 DSPFREQGUAR_SHIFT_CHV; 541 } 542 543 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) 544 { 545 unsigned int credits, default_credits; 546 547 if (IS_CHERRYVIEW(dev_priv)) 548 default_credits = PFI_CREDIT(12); 549 else 550 default_credits = PFI_CREDIT(8); 551 552 if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) { 553 /* CHV suggested value is 31 or 63 */ 554 if (IS_CHERRYVIEW(dev_priv)) 555 credits = PFI_CREDIT_63; 556 else 557 credits = PFI_CREDIT(15); 558 } else { 559 credits = default_credits; 560 } 561 562 /* 563 * WA - write default credits before re-programming 564 * FIXME: should we also set the resend bit here? 565 */ 566 intel_de_write(dev_priv, GCI_CONTROL, 567 VGA_FAST_MODE_DISABLE | default_credits); 568 569 intel_de_write(dev_priv, GCI_CONTROL, 570 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND); 571 572 /* 573 * FIXME is this guaranteed to clear 574 * immediately or should we poll for it? 575 */ 576 drm_WARN_ON(&dev_priv->drm, 577 intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND); 578 } 579 580 static void vlv_set_cdclk(struct drm_i915_private *dev_priv, 581 const struct intel_cdclk_config *cdclk_config, 582 enum pipe pipe) 583 { 584 int cdclk = cdclk_config->cdclk; 585 u32 val, cmd = cdclk_config->voltage_level; 586 intel_wakeref_t wakeref; 587 588 switch (cdclk) { 589 case 400000: 590 case 333333: 591 case 320000: 592 case 266667: 593 case 200000: 594 break; 595 default: 596 MISSING_CASE(cdclk); 597 return; 598 } 599 600 /* There are cases where we can end up here with power domains 601 * off and a CDCLK frequency other than the minimum, like when 602 * issuing a modeset without actually changing any display after 603 * a system suspend. So grab the display core domain, which covers 604 * the HW blocks needed for the following programming. 605 */ 606 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); 607 608 vlv_iosf_sb_get(dev_priv, 609 BIT(VLV_IOSF_SB_CCK) | 610 BIT(VLV_IOSF_SB_BUNIT) | 611 BIT(VLV_IOSF_SB_PUNIT)); 612 613 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 614 val &= ~DSPFREQGUAR_MASK; 615 val |= (cmd << DSPFREQGUAR_SHIFT); 616 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); 617 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & 618 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 619 50)) { 620 drm_err(&dev_priv->drm, 621 "timed out waiting for CDclk change\n"); 622 } 623 624 if (cdclk == 400000) { 625 u32 divider; 626 627 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, 628 cdclk) - 1; 629 630 /* adjust cdclk divider */ 631 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); 632 val &= ~CCK_FREQUENCY_VALUES; 633 val |= divider; 634 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); 635 636 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & 637 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 638 50)) 639 drm_err(&dev_priv->drm, 640 "timed out waiting for CDclk change\n"); 641 } 642 643 /* adjust self-refresh exit latency value */ 644 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); 645 val &= ~0x7f; 646 647 /* 648 * For high bandwidth configs, we set a higher latency in the bunit 649 * so that the core display fetch happens in time to avoid underruns. 650 */ 651 if (cdclk == 400000) 652 val |= 4500 / 250; /* 4.5 usec */ 653 else 654 val |= 3000 / 250; /* 3.0 usec */ 655 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); 656 657 vlv_iosf_sb_put(dev_priv, 658 BIT(VLV_IOSF_SB_CCK) | 659 BIT(VLV_IOSF_SB_BUNIT) | 660 BIT(VLV_IOSF_SB_PUNIT)); 661 662 intel_update_cdclk(dev_priv); 663 664 vlv_program_pfi_credits(dev_priv); 665 666 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); 667 } 668 669 static void chv_set_cdclk(struct drm_i915_private *dev_priv, 670 const struct intel_cdclk_config *cdclk_config, 671 enum pipe pipe) 672 { 673 int cdclk = cdclk_config->cdclk; 674 u32 val, cmd = cdclk_config->voltage_level; 675 intel_wakeref_t wakeref; 676 677 switch (cdclk) { 678 case 333333: 679 case 320000: 680 case 266667: 681 case 200000: 682 break; 683 default: 684 MISSING_CASE(cdclk); 685 return; 686 } 687 688 /* There are cases where we can end up here with power domains 689 * off and a CDCLK frequency other than the minimum, like when 690 * issuing a modeset without actually changing any display after 691 * a system suspend. So grab the display core domain, which covers 692 * the HW blocks needed for the following programming. 693 */ 694 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); 695 696 vlv_punit_get(dev_priv); 697 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 698 val &= ~DSPFREQGUAR_MASK_CHV; 699 val |= (cmd << DSPFREQGUAR_SHIFT_CHV); 700 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); 701 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & 702 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 703 50)) { 704 drm_err(&dev_priv->drm, 705 "timed out waiting for CDclk change\n"); 706 } 707 708 vlv_punit_put(dev_priv); 709 710 intel_update_cdclk(dev_priv); 711 712 vlv_program_pfi_credits(dev_priv); 713 714 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); 715 } 716 717 static int bdw_calc_cdclk(int min_cdclk) 718 { 719 if (min_cdclk > 540000) 720 return 675000; 721 else if (min_cdclk > 450000) 722 return 540000; 723 else if (min_cdclk > 337500) 724 return 450000; 725 else 726 return 337500; 727 } 728 729 static u8 bdw_calc_voltage_level(int cdclk) 730 { 731 switch (cdclk) { 732 default: 733 case 337500: 734 return 2; 735 case 450000: 736 return 0; 737 case 540000: 738 return 1; 739 case 675000: 740 return 3; 741 } 742 } 743 744 static void bdw_get_cdclk(struct drm_i915_private *dev_priv, 745 struct intel_cdclk_config *cdclk_config) 746 { 747 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); 748 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 749 750 if (lcpll & LCPLL_CD_SOURCE_FCLK) 751 cdclk_config->cdclk = 800000; 752 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 753 cdclk_config->cdclk = 450000; 754 else if (freq == LCPLL_CLK_FREQ_450) 755 cdclk_config->cdclk = 450000; 756 else if (freq == LCPLL_CLK_FREQ_54O_BDW) 757 cdclk_config->cdclk = 540000; 758 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 759 cdclk_config->cdclk = 337500; 760 else 761 cdclk_config->cdclk = 675000; 762 763 /* 764 * Can't read this out :( Let's assume it's 765 * at least what the CDCLK frequency requires. 766 */ 767 cdclk_config->voltage_level = 768 bdw_calc_voltage_level(cdclk_config->cdclk); 769 } 770 771 static u32 bdw_cdclk_freq_sel(int cdclk) 772 { 773 switch (cdclk) { 774 default: 775 MISSING_CASE(cdclk); 776 fallthrough; 777 case 337500: 778 return LCPLL_CLK_FREQ_337_5_BDW; 779 case 450000: 780 return LCPLL_CLK_FREQ_450; 781 case 540000: 782 return LCPLL_CLK_FREQ_54O_BDW; 783 case 675000: 784 return LCPLL_CLK_FREQ_675_BDW; 785 } 786 } 787 788 static void bdw_set_cdclk(struct drm_i915_private *dev_priv, 789 const struct intel_cdclk_config *cdclk_config, 790 enum pipe pipe) 791 { 792 int cdclk = cdclk_config->cdclk; 793 int ret; 794 795 if (drm_WARN(&dev_priv->drm, 796 (intel_de_read(dev_priv, LCPLL_CTL) & 797 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | 798 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | 799 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | 800 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, 801 "trying to change cdclk frequency with cdclk not enabled\n")) 802 return; 803 804 ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); 805 if (ret) { 806 drm_err(&dev_priv->drm, 807 "failed to inform pcode about cdclk change\n"); 808 return; 809 } 810 811 intel_de_rmw(dev_priv, LCPLL_CTL, 812 0, LCPLL_CD_SOURCE_FCLK); 813 814 /* 815 * According to the spec, it should be enough to poll for this 1 us. 816 * However, extensive testing shows that this can take longer. 817 */ 818 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) & 819 LCPLL_CD_SOURCE_FCLK_DONE, 100)) 820 drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); 821 822 intel_de_rmw(dev_priv, LCPLL_CTL, 823 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk)); 824 825 intel_de_rmw(dev_priv, LCPLL_CTL, 826 LCPLL_CD_SOURCE_FCLK, 0); 827 828 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) & 829 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 830 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n"); 831 832 snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ, 833 cdclk_config->voltage_level); 834 835 intel_de_write(dev_priv, CDCLK_FREQ, 836 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); 837 838 intel_update_cdclk(dev_priv); 839 } 840 841 static int skl_calc_cdclk(int min_cdclk, int vco) 842 { 843 if (vco == 8640000) { 844 if (min_cdclk > 540000) 845 return 617143; 846 else if (min_cdclk > 432000) 847 return 540000; 848 else if (min_cdclk > 308571) 849 return 432000; 850 else 851 return 308571; 852 } else { 853 if (min_cdclk > 540000) 854 return 675000; 855 else if (min_cdclk > 450000) 856 return 540000; 857 else if (min_cdclk > 337500) 858 return 450000; 859 else 860 return 337500; 861 } 862 } 863 864 static u8 skl_calc_voltage_level(int cdclk) 865 { 866 if (cdclk > 540000) 867 return 3; 868 else if (cdclk > 450000) 869 return 2; 870 else if (cdclk > 337500) 871 return 1; 872 else 873 return 0; 874 } 875 876 static void skl_dpll0_update(struct drm_i915_private *dev_priv, 877 struct intel_cdclk_config *cdclk_config) 878 { 879 u32 val; 880 881 cdclk_config->ref = 24000; 882 cdclk_config->vco = 0; 883 884 val = intel_de_read(dev_priv, LCPLL1_CTL); 885 if ((val & LCPLL_PLL_ENABLE) == 0) 886 return; 887 888 if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0)) 889 return; 890 891 val = intel_de_read(dev_priv, DPLL_CTRL1); 892 893 if (drm_WARN_ON(&dev_priv->drm, 894 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 895 DPLL_CTRL1_SSC(SKL_DPLL0) | 896 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != 897 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) 898 return; 899 900 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { 901 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): 902 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): 903 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): 904 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): 905 cdclk_config->vco = 8100000; 906 break; 907 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): 908 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): 909 cdclk_config->vco = 8640000; 910 break; 911 default: 912 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 913 break; 914 } 915 } 916 917 static void skl_get_cdclk(struct drm_i915_private *dev_priv, 918 struct intel_cdclk_config *cdclk_config) 919 { 920 u32 cdctl; 921 922 skl_dpll0_update(dev_priv, cdclk_config); 923 924 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; 925 926 if (cdclk_config->vco == 0) 927 goto out; 928 929 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 930 931 if (cdclk_config->vco == 8640000) { 932 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 933 case CDCLK_FREQ_450_432: 934 cdclk_config->cdclk = 432000; 935 break; 936 case CDCLK_FREQ_337_308: 937 cdclk_config->cdclk = 308571; 938 break; 939 case CDCLK_FREQ_540: 940 cdclk_config->cdclk = 540000; 941 break; 942 case CDCLK_FREQ_675_617: 943 cdclk_config->cdclk = 617143; 944 break; 945 default: 946 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 947 break; 948 } 949 } else { 950 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 951 case CDCLK_FREQ_450_432: 952 cdclk_config->cdclk = 450000; 953 break; 954 case CDCLK_FREQ_337_308: 955 cdclk_config->cdclk = 337500; 956 break; 957 case CDCLK_FREQ_540: 958 cdclk_config->cdclk = 540000; 959 break; 960 case CDCLK_FREQ_675_617: 961 cdclk_config->cdclk = 675000; 962 break; 963 default: 964 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 965 break; 966 } 967 } 968 969 out: 970 /* 971 * Can't read this out :( Let's assume it's 972 * at least what the CDCLK frequency requires. 973 */ 974 cdclk_config->voltage_level = 975 skl_calc_voltage_level(cdclk_config->cdclk); 976 } 977 978 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ 979 static int skl_cdclk_decimal(int cdclk) 980 { 981 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); 982 } 983 984 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, 985 int vco) 986 { 987 bool changed = dev_priv->skl_preferred_vco_freq != vco; 988 989 dev_priv->skl_preferred_vco_freq = vco; 990 991 if (changed) 992 intel_update_max_cdclk(dev_priv); 993 } 994 995 static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco) 996 { 997 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); 998 999 /* 1000 * We always enable DPLL0 with the lowest link rate possible, but still 1001 * taking into account the VCO required to operate the eDP panel at the 1002 * desired frequency. The usual DP link rates operate with a VCO of 1003 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. 1004 * The modeset code is responsible for the selection of the exact link 1005 * rate later on, with the constraint of choosing a frequency that 1006 * works with vco. 1007 */ 1008 if (vco == 8640000) 1009 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0); 1010 else 1011 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0); 1012 } 1013 1014 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) 1015 { 1016 intel_de_rmw(dev_priv, DPLL_CTRL1, 1017 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 1018 DPLL_CTRL1_SSC(SKL_DPLL0) | 1019 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0), 1020 DPLL_CTRL1_OVERRIDE(SKL_DPLL0) | 1021 skl_dpll0_link_rate(dev_priv, vco)); 1022 intel_de_posting_read(dev_priv, DPLL_CTRL1); 1023 1024 intel_de_rmw(dev_priv, LCPLL1_CTL, 1025 0, LCPLL_PLL_ENABLE); 1026 1027 if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) 1028 drm_err(&dev_priv->drm, "DPLL0 not locked\n"); 1029 1030 dev_priv->display.cdclk.hw.vco = vco; 1031 1032 /* We'll want to keep using the current vco from now on. */ 1033 skl_set_preferred_cdclk_vco(dev_priv, vco); 1034 } 1035 1036 static void skl_dpll0_disable(struct drm_i915_private *dev_priv) 1037 { 1038 intel_de_rmw(dev_priv, LCPLL1_CTL, 1039 LCPLL_PLL_ENABLE, 0); 1040 1041 if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) 1042 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n"); 1043 1044 dev_priv->display.cdclk.hw.vco = 0; 1045 } 1046 1047 static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv, 1048 int cdclk, int vco) 1049 { 1050 switch (cdclk) { 1051 default: 1052 drm_WARN_ON(&dev_priv->drm, 1053 cdclk != dev_priv->display.cdclk.hw.bypass); 1054 drm_WARN_ON(&dev_priv->drm, vco != 0); 1055 fallthrough; 1056 case 308571: 1057 case 337500: 1058 return CDCLK_FREQ_337_308; 1059 case 450000: 1060 case 432000: 1061 return CDCLK_FREQ_450_432; 1062 case 540000: 1063 return CDCLK_FREQ_540; 1064 case 617143: 1065 case 675000: 1066 return CDCLK_FREQ_675_617; 1067 } 1068 } 1069 1070 static void skl_set_cdclk(struct drm_i915_private *dev_priv, 1071 const struct intel_cdclk_config *cdclk_config, 1072 enum pipe pipe) 1073 { 1074 int cdclk = cdclk_config->cdclk; 1075 int vco = cdclk_config->vco; 1076 u32 freq_select, cdclk_ctl; 1077 int ret; 1078 1079 /* 1080 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are 1081 * unsupported on SKL. In theory this should never happen since only 1082 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not 1083 * supported on SKL either, see the above WA. WARN whenever trying to 1084 * use the corresponding VCO freq as that always leads to using the 1085 * minimum 308MHz CDCLK. 1086 */ 1087 drm_WARN_ON_ONCE(&dev_priv->drm, 1088 IS_SKYLAKE(dev_priv) && vco == 8640000); 1089 1090 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 1091 SKL_CDCLK_PREPARE_FOR_CHANGE, 1092 SKL_CDCLK_READY_FOR_CHANGE, 1093 SKL_CDCLK_READY_FOR_CHANGE, 3); 1094 if (ret) { 1095 drm_err(&dev_priv->drm, 1096 "Failed to inform PCU about cdclk change (%d)\n", ret); 1097 return; 1098 } 1099 1100 freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco); 1101 1102 if (dev_priv->display.cdclk.hw.vco != 0 && 1103 dev_priv->display.cdclk.hw.vco != vco) 1104 skl_dpll0_disable(dev_priv); 1105 1106 cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL); 1107 1108 if (dev_priv->display.cdclk.hw.vco != vco) { 1109 /* Wa Display #1183: skl,kbl,cfl */ 1110 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1111 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1112 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1113 } 1114 1115 /* Wa Display #1183: skl,kbl,cfl */ 1116 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; 1117 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1118 intel_de_posting_read(dev_priv, CDCLK_CTL); 1119 1120 if (dev_priv->display.cdclk.hw.vco != vco) 1121 skl_dpll0_enable(dev_priv, vco); 1122 1123 /* Wa Display #1183: skl,kbl,cfl */ 1124 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1125 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1126 1127 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1128 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1129 1130 /* Wa Display #1183: skl,kbl,cfl */ 1131 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; 1132 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1133 intel_de_posting_read(dev_priv, CDCLK_CTL); 1134 1135 /* inform PCU of the change */ 1136 snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 1137 cdclk_config->voltage_level); 1138 1139 intel_update_cdclk(dev_priv); 1140 } 1141 1142 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) 1143 { 1144 u32 cdctl, expected; 1145 1146 /* 1147 * check if the pre-os initialized the display 1148 * There is SWF18 scratchpad register defined which is set by the 1149 * pre-os which can be used by the OS drivers to check the status 1150 */ 1151 if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) 1152 goto sanitize; 1153 1154 intel_update_cdclk(dev_priv); 1155 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); 1156 1157 /* Is PLL enabled and locked ? */ 1158 if (dev_priv->display.cdclk.hw.vco == 0 || 1159 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) 1160 goto sanitize; 1161 1162 /* DPLL okay; verify the cdclock 1163 * 1164 * Noticed in some instances that the freq selection is correct but 1165 * decimal part is programmed wrong from BIOS where pre-os does not 1166 * enable display. Verify the same as well. 1167 */ 1168 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 1169 expected = (cdctl & CDCLK_FREQ_SEL_MASK) | 1170 skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk); 1171 if (cdctl == expected) 1172 /* All well; nothing to sanitize */ 1173 return; 1174 1175 sanitize: 1176 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); 1177 1178 /* force cdclk programming */ 1179 dev_priv->display.cdclk.hw.cdclk = 0; 1180 /* force full PLL disable + enable */ 1181 dev_priv->display.cdclk.hw.vco = -1; 1182 } 1183 1184 static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv) 1185 { 1186 struct intel_cdclk_config cdclk_config; 1187 1188 skl_sanitize_cdclk(dev_priv); 1189 1190 if (dev_priv->display.cdclk.hw.cdclk != 0 && 1191 dev_priv->display.cdclk.hw.vco != 0) { 1192 /* 1193 * Use the current vco as our initial 1194 * guess as to what the preferred vco is. 1195 */ 1196 if (dev_priv->skl_preferred_vco_freq == 0) 1197 skl_set_preferred_cdclk_vco(dev_priv, 1198 dev_priv->display.cdclk.hw.vco); 1199 return; 1200 } 1201 1202 cdclk_config = dev_priv->display.cdclk.hw; 1203 1204 cdclk_config.vco = dev_priv->skl_preferred_vco_freq; 1205 if (cdclk_config.vco == 0) 1206 cdclk_config.vco = 8100000; 1207 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); 1208 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1209 1210 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1211 } 1212 1213 static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv) 1214 { 1215 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; 1216 1217 cdclk_config.cdclk = cdclk_config.bypass; 1218 cdclk_config.vco = 0; 1219 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1220 1221 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1222 } 1223 1224 struct intel_cdclk_vals { 1225 u32 cdclk; 1226 u16 refclk; 1227 u16 waveform; 1228 u8 divider; /* CD2X divider * 2 */ 1229 u8 ratio; 1230 }; 1231 1232 static const struct intel_cdclk_vals bxt_cdclk_table[] = { 1233 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 }, 1234 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 }, 1235 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 }, 1236 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 }, 1237 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 }, 1238 {} 1239 }; 1240 1241 static const struct intel_cdclk_vals glk_cdclk_table[] = { 1242 { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 }, 1243 { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 }, 1244 { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 }, 1245 {} 1246 }; 1247 1248 static const struct intel_cdclk_vals icl_cdclk_table[] = { 1249 { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 }, 1250 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 }, 1251 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 }, 1252 { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 }, 1253 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 }, 1254 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 }, 1255 1256 { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 }, 1257 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 }, 1258 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 }, 1259 { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 }, 1260 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 }, 1261 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 }, 1262 1263 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 }, 1264 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 }, 1265 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 }, 1266 { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 }, 1267 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 }, 1268 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 }, 1269 {} 1270 }; 1271 1272 static const struct intel_cdclk_vals rkl_cdclk_table[] = { 1273 { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 }, 1274 { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 }, 1275 { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 }, 1276 { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 }, 1277 { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 }, 1278 { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 }, 1279 1280 { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 }, 1281 { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 }, 1282 { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 }, 1283 { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 }, 1284 { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 }, 1285 { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 }, 1286 1287 { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 }, 1288 { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 }, 1289 { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 }, 1290 { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 }, 1291 { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 }, 1292 { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 }, 1293 {} 1294 }; 1295 1296 static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = { 1297 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 }, 1298 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 }, 1299 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 }, 1300 1301 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 }, 1302 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 }, 1303 { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 }, 1304 1305 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 }, 1306 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 }, 1307 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 }, 1308 {} 1309 }; 1310 1311 static const struct intel_cdclk_vals adlp_cdclk_table[] = { 1312 { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 }, 1313 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 }, 1314 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 }, 1315 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 }, 1316 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 }, 1317 1318 { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 }, 1319 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 }, 1320 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 }, 1321 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 }, 1322 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 }, 1323 1324 { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 }, 1325 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 }, 1326 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 }, 1327 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 }, 1328 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 }, 1329 {} 1330 }; 1331 1332 static const struct intel_cdclk_vals rplu_cdclk_table[] = { 1333 { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 }, 1334 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 }, 1335 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 }, 1336 { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 }, 1337 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 }, 1338 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 }, 1339 1340 { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 }, 1341 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 }, 1342 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 }, 1343 { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 }, 1344 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 }, 1345 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 }, 1346 1347 { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 }, 1348 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 }, 1349 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 }, 1350 { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 }, 1351 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 }, 1352 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 }, 1353 {} 1354 }; 1355 1356 static const struct intel_cdclk_vals dg2_cdclk_table[] = { 1357 { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 }, 1358 { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 }, 1359 { .refclk = 38400, .cdclk = 244800, .divider = 2, .ratio = 34, .waveform = 0xa4a4 }, 1360 { .refclk = 38400, .cdclk = 285600, .divider = 2, .ratio = 34, .waveform = 0xa54a }, 1361 { .refclk = 38400, .cdclk = 326400, .divider = 2, .ratio = 34, .waveform = 0xaaaa }, 1362 { .refclk = 38400, .cdclk = 367200, .divider = 2, .ratio = 34, .waveform = 0xad5a }, 1363 { .refclk = 38400, .cdclk = 408000, .divider = 2, .ratio = 34, .waveform = 0xb6b6 }, 1364 { .refclk = 38400, .cdclk = 448800, .divider = 2, .ratio = 34, .waveform = 0xdbb6 }, 1365 { .refclk = 38400, .cdclk = 489600, .divider = 2, .ratio = 34, .waveform = 0xeeee }, 1366 { .refclk = 38400, .cdclk = 530400, .divider = 2, .ratio = 34, .waveform = 0xf7de }, 1367 { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe }, 1368 { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe }, 1369 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff }, 1370 {} 1371 }; 1372 1373 static const struct intel_cdclk_vals mtl_cdclk_table[] = { 1374 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a }, 1375 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 }, 1376 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 }, 1377 { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 }, 1378 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 }, 1379 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 }, 1380 {} 1381 }; 1382 1383 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) 1384 { 1385 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; 1386 int i; 1387 1388 for (i = 0; table[i].refclk; i++) 1389 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && 1390 table[i].cdclk >= min_cdclk) 1391 return table[i].cdclk; 1392 1393 drm_WARN(&dev_priv->drm, 1, 1394 "Cannot satisfy minimum cdclk %d with refclk %u\n", 1395 min_cdclk, dev_priv->display.cdclk.hw.ref); 1396 return 0; 1397 } 1398 1399 static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) 1400 { 1401 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; 1402 int i; 1403 1404 if (cdclk == dev_priv->display.cdclk.hw.bypass) 1405 return 0; 1406 1407 for (i = 0; table[i].refclk; i++) 1408 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && 1409 table[i].cdclk == cdclk) 1410 return dev_priv->display.cdclk.hw.ref * table[i].ratio; 1411 1412 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", 1413 cdclk, dev_priv->display.cdclk.hw.ref); 1414 return 0; 1415 } 1416 1417 static u8 bxt_calc_voltage_level(int cdclk) 1418 { 1419 return DIV_ROUND_UP(cdclk, 25000); 1420 } 1421 1422 static u8 icl_calc_voltage_level(int cdclk) 1423 { 1424 if (cdclk > 556800) 1425 return 2; 1426 else if (cdclk > 312000) 1427 return 1; 1428 else 1429 return 0; 1430 } 1431 1432 static u8 ehl_calc_voltage_level(int cdclk) 1433 { 1434 if (cdclk > 326400) 1435 return 3; 1436 else if (cdclk > 312000) 1437 return 2; 1438 else if (cdclk > 180000) 1439 return 1; 1440 else 1441 return 0; 1442 } 1443 1444 static u8 tgl_calc_voltage_level(int cdclk) 1445 { 1446 if (cdclk > 556800) 1447 return 3; 1448 else if (cdclk > 326400) 1449 return 2; 1450 else if (cdclk > 312000) 1451 return 1; 1452 else 1453 return 0; 1454 } 1455 1456 static void icl_readout_refclk(struct drm_i915_private *dev_priv, 1457 struct intel_cdclk_config *cdclk_config) 1458 { 1459 u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; 1460 1461 switch (dssm) { 1462 default: 1463 MISSING_CASE(dssm); 1464 fallthrough; 1465 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz: 1466 cdclk_config->ref = 24000; 1467 break; 1468 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz: 1469 cdclk_config->ref = 19200; 1470 break; 1471 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz: 1472 cdclk_config->ref = 38400; 1473 break; 1474 } 1475 } 1476 1477 static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, 1478 struct intel_cdclk_config *cdclk_config) 1479 { 1480 u32 val, ratio; 1481 1482 if (IS_DG2(dev_priv)) 1483 cdclk_config->ref = 38400; 1484 else if (DISPLAY_VER(dev_priv) >= 11) 1485 icl_readout_refclk(dev_priv, cdclk_config); 1486 else 1487 cdclk_config->ref = 19200; 1488 1489 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE); 1490 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || 1491 (val & BXT_DE_PLL_LOCK) == 0) { 1492 /* 1493 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but 1494 * setting it to zero is a way to signal that. 1495 */ 1496 cdclk_config->vco = 0; 1497 return; 1498 } 1499 1500 /* 1501 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register, 1502 * gen9lp had it in a separate PLL control register. 1503 */ 1504 if (DISPLAY_VER(dev_priv) >= 11) 1505 ratio = val & ICL_CDCLK_PLL_RATIO_MASK; 1506 else 1507 ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; 1508 1509 cdclk_config->vco = ratio * cdclk_config->ref; 1510 } 1511 1512 static void bxt_get_cdclk(struct drm_i915_private *dev_priv, 1513 struct intel_cdclk_config *cdclk_config) 1514 { 1515 u32 squash_ctl = 0; 1516 u32 divider; 1517 int div; 1518 1519 bxt_de_pll_readout(dev_priv, cdclk_config); 1520 1521 if (DISPLAY_VER(dev_priv) >= 12) 1522 cdclk_config->bypass = cdclk_config->ref / 2; 1523 else if (DISPLAY_VER(dev_priv) >= 11) 1524 cdclk_config->bypass = 50000; 1525 else 1526 cdclk_config->bypass = cdclk_config->ref; 1527 1528 if (cdclk_config->vco == 0) { 1529 cdclk_config->cdclk = cdclk_config->bypass; 1530 goto out; 1531 } 1532 1533 divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; 1534 1535 switch (divider) { 1536 case BXT_CDCLK_CD2X_DIV_SEL_1: 1537 div = 2; 1538 break; 1539 case BXT_CDCLK_CD2X_DIV_SEL_1_5: 1540 div = 3; 1541 break; 1542 case BXT_CDCLK_CD2X_DIV_SEL_2: 1543 div = 4; 1544 break; 1545 case BXT_CDCLK_CD2X_DIV_SEL_4: 1546 div = 8; 1547 break; 1548 default: 1549 MISSING_CASE(divider); 1550 return; 1551 } 1552 1553 if (HAS_CDCLK_SQUASH(dev_priv)) 1554 squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL); 1555 1556 if (squash_ctl & CDCLK_SQUASH_ENABLE) { 1557 u16 waveform; 1558 int size; 1559 1560 size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1; 1561 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size); 1562 1563 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * 1564 cdclk_config->vco, size * div); 1565 } else { 1566 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); 1567 } 1568 1569 out: 1570 /* 1571 * Can't read this out :( Let's assume it's 1572 * at least what the CDCLK frequency requires. 1573 */ 1574 cdclk_config->voltage_level = 1575 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk); 1576 } 1577 1578 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) 1579 { 1580 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0); 1581 1582 /* Timeout 200us */ 1583 if (intel_de_wait_for_clear(dev_priv, 1584 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1585 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n"); 1586 1587 dev_priv->display.cdclk.hw.vco = 0; 1588 } 1589 1590 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) 1591 { 1592 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); 1593 1594 intel_de_rmw(dev_priv, BXT_DE_PLL_CTL, 1595 BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio)); 1596 1597 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); 1598 1599 /* Timeout 200us */ 1600 if (intel_de_wait_for_set(dev_priv, 1601 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1602 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n"); 1603 1604 dev_priv->display.cdclk.hw.vco = vco; 1605 } 1606 1607 static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv) 1608 { 1609 intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE, 1610 BXT_DE_PLL_PLL_ENABLE, 0); 1611 1612 /* Timeout 200us */ 1613 if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1614 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n"); 1615 1616 dev_priv->display.cdclk.hw.vco = 0; 1617 } 1618 1619 static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) 1620 { 1621 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); 1622 u32 val; 1623 1624 val = ICL_CDCLK_PLL_RATIO(ratio); 1625 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1626 1627 val |= BXT_DE_PLL_PLL_ENABLE; 1628 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1629 1630 /* Timeout 200us */ 1631 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1632 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n"); 1633 1634 dev_priv->display.cdclk.hw.vco = vco; 1635 } 1636 1637 static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco) 1638 { 1639 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); 1640 u32 val; 1641 1642 /* Write PLL ratio without disabling */ 1643 val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE; 1644 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1645 1646 /* Submit freq change request */ 1647 val |= BXT_DE_PLL_FREQ_REQ; 1648 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1649 1650 /* Timeout 200us */ 1651 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, 1652 BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1)) 1653 drm_err(&dev_priv->drm, "timeout waiting for FREQ change request ack\n"); 1654 1655 val &= ~BXT_DE_PLL_FREQ_REQ; 1656 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1657 1658 dev_priv->display.cdclk.hw.vco = vco; 1659 } 1660 1661 static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 1662 { 1663 if (DISPLAY_VER(dev_priv) >= 12) { 1664 if (pipe == INVALID_PIPE) 1665 return TGL_CDCLK_CD2X_PIPE_NONE; 1666 else 1667 return TGL_CDCLK_CD2X_PIPE(pipe); 1668 } else if (DISPLAY_VER(dev_priv) >= 11) { 1669 if (pipe == INVALID_PIPE) 1670 return ICL_CDCLK_CD2X_PIPE_NONE; 1671 else 1672 return ICL_CDCLK_CD2X_PIPE(pipe); 1673 } else { 1674 if (pipe == INVALID_PIPE) 1675 return BXT_CDCLK_CD2X_PIPE_NONE; 1676 else 1677 return BXT_CDCLK_CD2X_PIPE(pipe); 1678 } 1679 } 1680 1681 static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv, 1682 int cdclk, int vco) 1683 { 1684 /* cdclk = vco / 2 / div{1,1.5,2,4} */ 1685 switch (DIV_ROUND_CLOSEST(vco, cdclk)) { 1686 default: 1687 drm_WARN_ON(&dev_priv->drm, 1688 cdclk != dev_priv->display.cdclk.hw.bypass); 1689 drm_WARN_ON(&dev_priv->drm, vco != 0); 1690 fallthrough; 1691 case 2: 1692 return BXT_CDCLK_CD2X_DIV_SEL_1; 1693 case 3: 1694 return BXT_CDCLK_CD2X_DIV_SEL_1_5; 1695 case 4: 1696 return BXT_CDCLK_CD2X_DIV_SEL_2; 1697 case 8: 1698 return BXT_CDCLK_CD2X_DIV_SEL_4; 1699 } 1700 } 1701 1702 static u32 cdclk_squash_waveform(struct drm_i915_private *dev_priv, 1703 int cdclk) 1704 { 1705 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; 1706 int i; 1707 1708 if (cdclk == dev_priv->display.cdclk.hw.bypass) 1709 return 0; 1710 1711 for (i = 0; table[i].refclk; i++) 1712 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && 1713 table[i].cdclk == cdclk) 1714 return table[i].waveform; 1715 1716 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", 1717 cdclk, dev_priv->display.cdclk.hw.ref); 1718 1719 return 0xffff; 1720 } 1721 1722 static void icl_cdclk_pll_update(struct drm_i915_private *i915, int vco) 1723 { 1724 if (i915->display.cdclk.hw.vco != 0 && 1725 i915->display.cdclk.hw.vco != vco) 1726 icl_cdclk_pll_disable(i915); 1727 1728 if (i915->display.cdclk.hw.vco != vco) 1729 icl_cdclk_pll_enable(i915, vco); 1730 } 1731 1732 static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco) 1733 { 1734 if (i915->display.cdclk.hw.vco != 0 && 1735 i915->display.cdclk.hw.vco != vco) 1736 bxt_de_pll_disable(i915); 1737 1738 if (i915->display.cdclk.hw.vco != vco) 1739 bxt_de_pll_enable(i915, vco); 1740 } 1741 1742 static void dg2_cdclk_squash_program(struct drm_i915_private *i915, 1743 u16 waveform) 1744 { 1745 u32 squash_ctl = 0; 1746 1747 if (waveform) 1748 squash_ctl = CDCLK_SQUASH_ENABLE | 1749 CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; 1750 1751 intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl); 1752 } 1753 1754 static bool cdclk_pll_is_unknown(unsigned int vco) 1755 { 1756 /* 1757 * Ensure driver does not take the crawl path for the 1758 * case when the vco is set to ~0 in the 1759 * sanitize path. 1760 */ 1761 return vco == ~0; 1762 } 1763 1764 static int cdclk_squash_divider(u16 waveform) 1765 { 1766 return hweight16(waveform ?: 0xffff); 1767 } 1768 1769 static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i915, 1770 const struct intel_cdclk_config *old_cdclk_config, 1771 const struct intel_cdclk_config *new_cdclk_config, 1772 struct intel_cdclk_config *mid_cdclk_config) 1773 { 1774 u16 old_waveform, new_waveform, mid_waveform; 1775 int size = 16; 1776 int div = 2; 1777 1778 /* Return if PLL is in an unknown state, force a complete disable and re-enable. */ 1779 if (cdclk_pll_is_unknown(old_cdclk_config->vco)) 1780 return false; 1781 1782 /* Return if both Squash and Crawl are not present */ 1783 if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915)) 1784 return false; 1785 1786 old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk); 1787 new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk); 1788 1789 /* Return if Squash only or Crawl only is the desired action */ 1790 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 || 1791 old_cdclk_config->vco == new_cdclk_config->vco || 1792 old_waveform == new_waveform) 1793 return false; 1794 1795 *mid_cdclk_config = *new_cdclk_config; 1796 1797 /* 1798 * Populate the mid_cdclk_config accordingly. 1799 * - If moving to a higher cdclk, the desired action is squashing. 1800 * The mid cdclk config should have the new (squash) waveform. 1801 * - If moving to a lower cdclk, the desired action is crawling. 1802 * The mid cdclk config should have the new vco. 1803 */ 1804 1805 if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) { 1806 mid_cdclk_config->vco = old_cdclk_config->vco; 1807 mid_waveform = new_waveform; 1808 } else { 1809 mid_cdclk_config->vco = new_cdclk_config->vco; 1810 mid_waveform = old_waveform; 1811 } 1812 1813 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) * 1814 mid_cdclk_config->vco, size * div); 1815 1816 /* make sure the mid clock came out sane */ 1817 1818 drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk < 1819 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); 1820 drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk > 1821 i915->display.cdclk.max_cdclk_freq); 1822 drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915, mid_cdclk_config->cdclk) != 1823 mid_waveform); 1824 1825 return true; 1826 } 1827 1828 static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv) 1829 { 1830 return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv)) && 1831 dev_priv->display.cdclk.hw.vco > 0 && 1832 HAS_CDCLK_SQUASH(dev_priv)); 1833 } 1834 1835 static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, 1836 const struct intel_cdclk_config *cdclk_config, 1837 enum pipe pipe) 1838 { 1839 int cdclk = cdclk_config->cdclk; 1840 int vco = cdclk_config->vco; 1841 u32 val; 1842 u16 waveform; 1843 int clock; 1844 1845 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 && 1846 !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) { 1847 if (dev_priv->display.cdclk.hw.vco != vco) 1848 adlp_cdclk_pll_crawl(dev_priv, vco); 1849 } else if (DISPLAY_VER(dev_priv) >= 11) { 1850 /* wa_15010685871: dg2, mtl */ 1851 if (pll_enable_wa_needed(dev_priv)) 1852 dg2_cdclk_squash_program(dev_priv, 0); 1853 1854 icl_cdclk_pll_update(dev_priv, vco); 1855 } else 1856 bxt_cdclk_pll_update(dev_priv, vco); 1857 1858 waveform = cdclk_squash_waveform(dev_priv, cdclk); 1859 1860 if (waveform) 1861 clock = vco / 2; 1862 else 1863 clock = cdclk; 1864 1865 if (HAS_CDCLK_SQUASH(dev_priv)) 1866 dg2_cdclk_squash_program(dev_priv, waveform); 1867 1868 val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) | 1869 bxt_cdclk_cd2x_pipe(dev_priv, pipe) | 1870 skl_cdclk_decimal(cdclk); 1871 1872 /* 1873 * Disable SSA Precharge when CD clock frequency < 500 MHz, 1874 * enable otherwise. 1875 */ 1876 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1877 cdclk >= 500000) 1878 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 1879 intel_de_write(dev_priv, CDCLK_CTL, val); 1880 1881 if (pipe != INVALID_PIPE) 1882 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe)); 1883 } 1884 1885 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 1886 const struct intel_cdclk_config *cdclk_config, 1887 enum pipe pipe) 1888 { 1889 struct intel_cdclk_config mid_cdclk_config; 1890 int cdclk = cdclk_config->cdclk; 1891 int ret = 0; 1892 1893 /* 1894 * Inform power controller of upcoming frequency change. 1895 * Display versions 14 and beyond do not follow the PUnit 1896 * mailbox communication, skip 1897 * this step. 1898 */ 1899 if (DISPLAY_VER(dev_priv) >= 14) 1900 /* NOOP */; 1901 else if (DISPLAY_VER(dev_priv) >= 11) 1902 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 1903 SKL_CDCLK_PREPARE_FOR_CHANGE, 1904 SKL_CDCLK_READY_FOR_CHANGE, 1905 SKL_CDCLK_READY_FOR_CHANGE, 3); 1906 else 1907 /* 1908 * BSpec requires us to wait up to 150usec, but that leads to 1909 * timeouts; the 2ms used here is based on experiment. 1910 */ 1911 ret = snb_pcode_write_timeout(&dev_priv->uncore, 1912 HSW_PCODE_DE_WRITE_FREQ_REQ, 1913 0x80000000, 150, 2); 1914 1915 if (ret) { 1916 drm_err(&dev_priv->drm, 1917 "Failed to inform PCU about cdclk change (err %d, freq %d)\n", 1918 ret, cdclk); 1919 return; 1920 } 1921 1922 if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw, 1923 cdclk_config, &mid_cdclk_config)) { 1924 _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe); 1925 _bxt_set_cdclk(dev_priv, cdclk_config, pipe); 1926 } else { 1927 _bxt_set_cdclk(dev_priv, cdclk_config, pipe); 1928 } 1929 1930 if (DISPLAY_VER(dev_priv) >= 14) 1931 /* 1932 * NOOP - No Pcode communication needed for 1933 * Display versions 14 and beyond 1934 */; 1935 else if (DISPLAY_VER(dev_priv) >= 11) 1936 ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 1937 cdclk_config->voltage_level); 1938 else 1939 /* 1940 * The timeout isn't specified, the 2ms used here is based on 1941 * experiment. 1942 * FIXME: Waiting for the request completion could be delayed 1943 * until the next PCODE request based on BSpec. 1944 */ 1945 ret = snb_pcode_write_timeout(&dev_priv->uncore, 1946 HSW_PCODE_DE_WRITE_FREQ_REQ, 1947 cdclk_config->voltage_level, 1948 150, 2); 1949 1950 if (ret) { 1951 drm_err(&dev_priv->drm, 1952 "PCode CDCLK freq set failed, (err %d, freq %d)\n", 1953 ret, cdclk); 1954 return; 1955 } 1956 1957 intel_update_cdclk(dev_priv); 1958 1959 if (DISPLAY_VER(dev_priv) >= 11) 1960 /* 1961 * Can't read out the voltage level :( 1962 * Let's just assume everything is as expected. 1963 */ 1964 dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level; 1965 } 1966 1967 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) 1968 { 1969 u32 cdctl, expected; 1970 int cdclk, clock, vco; 1971 1972 intel_update_cdclk(dev_priv); 1973 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); 1974 1975 if (dev_priv->display.cdclk.hw.vco == 0 || 1976 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) 1977 goto sanitize; 1978 1979 /* DPLL okay; verify the cdclock 1980 * 1981 * Some BIOS versions leave an incorrect decimal frequency value and 1982 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, 1983 * so sanitize this register. 1984 */ 1985 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 1986 /* 1987 * Let's ignore the pipe field, since BIOS could have configured the 1988 * dividers both synching to an active pipe, or asynchronously 1989 * (PIPE_NONE). 1990 */ 1991 cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); 1992 1993 /* Make sure this is a legal cdclk value for the platform */ 1994 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk); 1995 if (cdclk != dev_priv->display.cdclk.hw.cdclk) 1996 goto sanitize; 1997 1998 /* Make sure the VCO is correct for the cdclk */ 1999 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 2000 if (vco != dev_priv->display.cdclk.hw.vco) 2001 goto sanitize; 2002 2003 expected = skl_cdclk_decimal(cdclk); 2004 2005 /* Figure out what CD2X divider we should be using for this cdclk */ 2006 if (HAS_CDCLK_SQUASH(dev_priv)) 2007 clock = dev_priv->display.cdclk.hw.vco / 2; 2008 else 2009 clock = dev_priv->display.cdclk.hw.cdclk; 2010 2011 expected |= bxt_cdclk_cd2x_div_sel(dev_priv, clock, 2012 dev_priv->display.cdclk.hw.vco); 2013 2014 /* 2015 * Disable SSA Precharge when CD clock frequency < 500 MHz, 2016 * enable otherwise. 2017 */ 2018 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 2019 dev_priv->display.cdclk.hw.cdclk >= 500000) 2020 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 2021 2022 if (cdctl == expected) 2023 /* All well; nothing to sanitize */ 2024 return; 2025 2026 sanitize: 2027 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); 2028 2029 /* force cdclk programming */ 2030 dev_priv->display.cdclk.hw.cdclk = 0; 2031 2032 /* force full PLL disable + enable */ 2033 dev_priv->display.cdclk.hw.vco = -1; 2034 } 2035 2036 static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv) 2037 { 2038 struct intel_cdclk_config cdclk_config; 2039 2040 bxt_sanitize_cdclk(dev_priv); 2041 2042 if (dev_priv->display.cdclk.hw.cdclk != 0 && 2043 dev_priv->display.cdclk.hw.vco != 0) 2044 return; 2045 2046 cdclk_config = dev_priv->display.cdclk.hw; 2047 2048 /* 2049 * FIXME: 2050 * - The initial CDCLK needs to be read from VBT. 2051 * Need to make this change after VBT has changes for BXT. 2052 */ 2053 cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0); 2054 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); 2055 cdclk_config.voltage_level = 2056 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); 2057 2058 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 2059 } 2060 2061 static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv) 2062 { 2063 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; 2064 2065 cdclk_config.cdclk = cdclk_config.bypass; 2066 cdclk_config.vco = 0; 2067 cdclk_config.voltage_level = 2068 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); 2069 2070 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 2071 } 2072 2073 /** 2074 * intel_cdclk_init_hw - Initialize CDCLK hardware 2075 * @i915: i915 device 2076 * 2077 * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and 2078 * sanitizing the state of the hardware if needed. This is generally done only 2079 * during the display core initialization sequence, after which the DMC will 2080 * take care of turning CDCLK off/on as needed. 2081 */ 2082 void intel_cdclk_init_hw(struct drm_i915_private *i915) 2083 { 2084 if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915)) 2085 bxt_cdclk_init_hw(i915); 2086 else if (DISPLAY_VER(i915) == 9) 2087 skl_cdclk_init_hw(i915); 2088 } 2089 2090 /** 2091 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware 2092 * @i915: i915 device 2093 * 2094 * Uninitialize CDCLK. This is done only during the display core 2095 * uninitialization sequence. 2096 */ 2097 void intel_cdclk_uninit_hw(struct drm_i915_private *i915) 2098 { 2099 if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915)) 2100 bxt_cdclk_uninit_hw(i915); 2101 else if (DISPLAY_VER(i915) == 9) 2102 skl_cdclk_uninit_hw(i915); 2103 } 2104 2105 static bool intel_cdclk_can_crawl_and_squash(struct drm_i915_private *i915, 2106 const struct intel_cdclk_config *a, 2107 const struct intel_cdclk_config *b) 2108 { 2109 u16 old_waveform; 2110 u16 new_waveform; 2111 2112 drm_WARN_ON(&i915->drm, cdclk_pll_is_unknown(a->vco)); 2113 2114 if (a->vco == 0 || b->vco == 0) 2115 return false; 2116 2117 if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915)) 2118 return false; 2119 2120 old_waveform = cdclk_squash_waveform(i915, a->cdclk); 2121 new_waveform = cdclk_squash_waveform(i915, b->cdclk); 2122 2123 return a->vco != b->vco && 2124 old_waveform != new_waveform; 2125 } 2126 2127 static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, 2128 const struct intel_cdclk_config *a, 2129 const struct intel_cdclk_config *b) 2130 { 2131 int a_div, b_div; 2132 2133 if (!HAS_CDCLK_CRAWL(dev_priv)) 2134 return false; 2135 2136 /* 2137 * The vco and cd2x divider will change independently 2138 * from each, so we disallow cd2x change when crawling. 2139 */ 2140 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); 2141 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); 2142 2143 return a->vco != 0 && b->vco != 0 && 2144 a->vco != b->vco && 2145 a_div == b_div && 2146 a->ref == b->ref; 2147 } 2148 2149 static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, 2150 const struct intel_cdclk_config *a, 2151 const struct intel_cdclk_config *b) 2152 { 2153 /* 2154 * FIXME should store a bit more state in intel_cdclk_config 2155 * to differentiate squasher vs. cd2x divider properly. For 2156 * the moment all platforms with squasher use a fixed cd2x 2157 * divider. 2158 */ 2159 if (!HAS_CDCLK_SQUASH(dev_priv)) 2160 return false; 2161 2162 return a->cdclk != b->cdclk && 2163 a->vco != 0 && 2164 a->vco == b->vco && 2165 a->ref == b->ref; 2166 } 2167 2168 /** 2169 * intel_cdclk_needs_modeset - Determine if changong between the CDCLK 2170 * configurations requires a modeset on all pipes 2171 * @a: first CDCLK configuration 2172 * @b: second CDCLK configuration 2173 * 2174 * Returns: 2175 * True if changing between the two CDCLK configurations 2176 * requires all pipes to be off, false if not. 2177 */ 2178 bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a, 2179 const struct intel_cdclk_config *b) 2180 { 2181 return a->cdclk != b->cdclk || 2182 a->vco != b->vco || 2183 a->ref != b->ref; 2184 } 2185 2186 /** 2187 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK 2188 * configurations requires only a cd2x divider update 2189 * @dev_priv: i915 device 2190 * @a: first CDCLK configuration 2191 * @b: second CDCLK configuration 2192 * 2193 * Returns: 2194 * True if changing between the two CDCLK configurations 2195 * can be done with just a cd2x divider update, false if not. 2196 */ 2197 static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, 2198 const struct intel_cdclk_config *a, 2199 const struct intel_cdclk_config *b) 2200 { 2201 /* Older hw doesn't have the capability */ 2202 if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv)) 2203 return false; 2204 2205 /* 2206 * FIXME should store a bit more state in intel_cdclk_config 2207 * to differentiate squasher vs. cd2x divider properly. For 2208 * the moment all platforms with squasher use a fixed cd2x 2209 * divider. 2210 */ 2211 if (HAS_CDCLK_SQUASH(dev_priv)) 2212 return false; 2213 2214 return a->cdclk != b->cdclk && 2215 a->vco != 0 && 2216 a->vco == b->vco && 2217 a->ref == b->ref; 2218 } 2219 2220 /** 2221 * intel_cdclk_changed - Determine if two CDCLK configurations are different 2222 * @a: first CDCLK configuration 2223 * @b: second CDCLK configuration 2224 * 2225 * Returns: 2226 * True if the CDCLK configurations don't match, false if they do. 2227 */ 2228 static bool intel_cdclk_changed(const struct intel_cdclk_config *a, 2229 const struct intel_cdclk_config *b) 2230 { 2231 return intel_cdclk_needs_modeset(a, b) || 2232 a->voltage_level != b->voltage_level; 2233 } 2234 2235 void intel_cdclk_dump_config(struct drm_i915_private *i915, 2236 const struct intel_cdclk_config *cdclk_config, 2237 const char *context) 2238 { 2239 drm_dbg_kms(&i915->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", 2240 context, cdclk_config->cdclk, cdclk_config->vco, 2241 cdclk_config->ref, cdclk_config->bypass, 2242 cdclk_config->voltage_level); 2243 } 2244 2245 /** 2246 * intel_set_cdclk - Push the CDCLK configuration to the hardware 2247 * @dev_priv: i915 device 2248 * @cdclk_config: new CDCLK configuration 2249 * @pipe: pipe with which to synchronize the update 2250 * 2251 * Program the hardware based on the passed in CDCLK state, 2252 * if necessary. 2253 */ 2254 static void intel_set_cdclk(struct drm_i915_private *dev_priv, 2255 const struct intel_cdclk_config *cdclk_config, 2256 enum pipe pipe) 2257 { 2258 struct intel_encoder *encoder; 2259 2260 if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config)) 2261 return; 2262 2263 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk)) 2264 return; 2265 2266 intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to"); 2267 2268 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2269 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2270 2271 intel_psr_pause(intel_dp); 2272 } 2273 2274 intel_audio_cdclk_change_pre(dev_priv); 2275 2276 /* 2277 * Lock aux/gmbus while we change cdclk in case those 2278 * functions use cdclk. Not all platforms/ports do, 2279 * but we'll lock them all for simplicity. 2280 */ 2281 mutex_lock(&dev_priv->display.gmbus.mutex); 2282 for_each_intel_dp(&dev_priv->drm, encoder) { 2283 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2284 2285 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, 2286 &dev_priv->display.gmbus.mutex); 2287 } 2288 2289 intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe); 2290 2291 for_each_intel_dp(&dev_priv->drm, encoder) { 2292 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2293 2294 mutex_unlock(&intel_dp->aux.hw_mutex); 2295 } 2296 mutex_unlock(&dev_priv->display.gmbus.mutex); 2297 2298 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2299 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2300 2301 intel_psr_resume(intel_dp); 2302 } 2303 2304 intel_audio_cdclk_change_post(dev_priv); 2305 2306 if (drm_WARN(&dev_priv->drm, 2307 intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config), 2308 "cdclk state doesn't match!\n")) { 2309 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]"); 2310 intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]"); 2311 } 2312 } 2313 2314 /** 2315 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware 2316 * @state: intel atomic state 2317 * 2318 * Program the hardware before updating the HW plane state based on the 2319 * new CDCLK state, if necessary. 2320 */ 2321 void 2322 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) 2323 { 2324 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2325 const struct intel_cdclk_state *old_cdclk_state = 2326 intel_atomic_get_old_cdclk_state(state); 2327 const struct intel_cdclk_state *new_cdclk_state = 2328 intel_atomic_get_new_cdclk_state(state); 2329 enum pipe pipe = new_cdclk_state->pipe; 2330 2331 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2332 &new_cdclk_state->actual)) 2333 return; 2334 2335 if (pipe == INVALID_PIPE || 2336 old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) { 2337 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); 2338 2339 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); 2340 } 2341 } 2342 2343 /** 2344 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware 2345 * @state: intel atomic state 2346 * 2347 * Program the hardware after updating the HW plane state based on the 2348 * new CDCLK state, if necessary. 2349 */ 2350 void 2351 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) 2352 { 2353 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2354 const struct intel_cdclk_state *old_cdclk_state = 2355 intel_atomic_get_old_cdclk_state(state); 2356 const struct intel_cdclk_state *new_cdclk_state = 2357 intel_atomic_get_new_cdclk_state(state); 2358 enum pipe pipe = new_cdclk_state->pipe; 2359 2360 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2361 &new_cdclk_state->actual)) 2362 return; 2363 2364 if (pipe != INVALID_PIPE && 2365 old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) { 2366 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); 2367 2368 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); 2369 } 2370 } 2371 2372 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) 2373 { 2374 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2375 int pixel_rate = crtc_state->pixel_rate; 2376 2377 if (DISPLAY_VER(dev_priv) >= 10) 2378 return DIV_ROUND_UP(pixel_rate, 2); 2379 else if (DISPLAY_VER(dev_priv) == 9 || 2380 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2381 return pixel_rate; 2382 else if (IS_CHERRYVIEW(dev_priv)) 2383 return DIV_ROUND_UP(pixel_rate * 100, 95); 2384 else if (crtc_state->double_wide) 2385 return DIV_ROUND_UP(pixel_rate * 100, 90 * 2); 2386 else 2387 return DIV_ROUND_UP(pixel_rate * 100, 90); 2388 } 2389 2390 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) 2391 { 2392 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2393 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2394 struct intel_plane *plane; 2395 int min_cdclk = 0; 2396 2397 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 2398 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk); 2399 2400 return min_cdclk; 2401 } 2402 2403 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) 2404 { 2405 struct drm_i915_private *dev_priv = 2406 to_i915(crtc_state->uapi.crtc->dev); 2407 int min_cdclk; 2408 2409 if (!crtc_state->hw.enable) 2410 return 0; 2411 2412 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state); 2413 2414 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ 2415 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state)) 2416 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95); 2417 2418 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, 2419 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else 2420 * there may be audio corruption or screen corruption." This cdclk 2421 * restriction for GLK is 316.8 MHz. 2422 */ 2423 if (intel_crtc_has_dp_encoder(crtc_state) && 2424 crtc_state->has_audio && 2425 crtc_state->port_clock >= 540000 && 2426 crtc_state->lane_count == 4) { 2427 if (DISPLAY_VER(dev_priv) == 10) { 2428 /* Display WA #1145: glk */ 2429 min_cdclk = max(316800, min_cdclk); 2430 } else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) { 2431 /* Display WA #1144: skl,bxt */ 2432 min_cdclk = max(432000, min_cdclk); 2433 } 2434 } 2435 2436 /* 2437 * According to BSpec, "The CD clock frequency must be at least twice 2438 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. 2439 */ 2440 if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9) 2441 min_cdclk = max(2 * 96000, min_cdclk); 2442 2443 /* 2444 * "For DP audio configuration, cdclk frequency shall be set to 2445 * meet the following requirements: 2446 * DP Link Frequency(MHz) | Cdclk frequency(MHz) 2447 * 270 | 320 or higher 2448 * 162 | 200 or higher" 2449 */ 2450 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2451 intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio) 2452 min_cdclk = max(crtc_state->port_clock, min_cdclk); 2453 2454 /* 2455 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower 2456 * than 320000KHz. 2457 */ 2458 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 2459 IS_VALLEYVIEW(dev_priv)) 2460 min_cdclk = max(320000, min_cdclk); 2461 2462 /* 2463 * On Geminilake once the CDCLK gets as low as 79200 2464 * picture gets unstable, despite that values are 2465 * correct for DSI PLL and DE PLL. 2466 */ 2467 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 2468 IS_GEMINILAKE(dev_priv)) 2469 min_cdclk = max(158400, min_cdclk); 2470 2471 /* Account for additional needs from the planes */ 2472 min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); 2473 2474 /* 2475 * When we decide to use only one VDSC engine, since 2476 * each VDSC operates with 1 ppc throughput, pixel clock 2477 * cannot be higher than the VDSC clock (cdclk) 2478 */ 2479 if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split) 2480 min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); 2481 2482 /* 2483 * HACK. Currently for TGL/DG2 platforms we calculate 2484 * min_cdclk initially based on pixel_rate divided 2485 * by 2, accounting for also plane requirements, 2486 * however in some cases the lowest possible CDCLK 2487 * doesn't work and causing the underruns. 2488 * Explicitly stating here that this seems to be currently 2489 * rather a Hack, than final solution. 2490 */ 2491 if (IS_TIGERLAKE(dev_priv) || IS_DG2(dev_priv)) { 2492 /* 2493 * Clamp to max_cdclk_freq in case pixel rate is higher, 2494 * in order not to break an 8K, but still leave W/A at place. 2495 */ 2496 min_cdclk = max_t(int, min_cdclk, 2497 min_t(int, crtc_state->pixel_rate, 2498 dev_priv->display.cdclk.max_cdclk_freq)); 2499 } 2500 2501 return min_cdclk; 2502 } 2503 2504 static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) 2505 { 2506 struct intel_atomic_state *state = cdclk_state->base.state; 2507 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2508 const struct intel_bw_state *bw_state; 2509 struct intel_crtc *crtc; 2510 struct intel_crtc_state *crtc_state; 2511 int min_cdclk, i; 2512 enum pipe pipe; 2513 2514 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2515 int ret; 2516 2517 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 2518 if (min_cdclk < 0) 2519 return min_cdclk; 2520 2521 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk) 2522 continue; 2523 2524 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 2525 2526 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2527 if (ret) 2528 return ret; 2529 } 2530 2531 bw_state = intel_atomic_get_new_bw_state(state); 2532 if (bw_state) { 2533 min_cdclk = intel_bw_min_cdclk(dev_priv, bw_state); 2534 2535 if (cdclk_state->bw_min_cdclk != min_cdclk) { 2536 int ret; 2537 2538 cdclk_state->bw_min_cdclk = min_cdclk; 2539 2540 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2541 if (ret) 2542 return ret; 2543 } 2544 } 2545 2546 min_cdclk = max(cdclk_state->force_min_cdclk, 2547 cdclk_state->bw_min_cdclk); 2548 for_each_pipe(dev_priv, pipe) 2549 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); 2550 2551 if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) { 2552 drm_dbg_kms(&dev_priv->drm, 2553 "required cdclk (%d kHz) exceeds max (%d kHz)\n", 2554 min_cdclk, dev_priv->display.cdclk.max_cdclk_freq); 2555 return -EINVAL; 2556 } 2557 2558 return min_cdclk; 2559 } 2560 2561 /* 2562 * Account for port clock min voltage level requirements. 2563 * This only really does something on DISPLA_VER >= 11 but can be 2564 * called on earlier platforms as well. 2565 * 2566 * Note that this functions assumes that 0 is 2567 * the lowest voltage value, and higher values 2568 * correspond to increasingly higher voltages. 2569 * 2570 * Should that relationship no longer hold on 2571 * future platforms this code will need to be 2572 * adjusted. 2573 */ 2574 static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state) 2575 { 2576 struct intel_atomic_state *state = cdclk_state->base.state; 2577 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2578 struct intel_crtc *crtc; 2579 struct intel_crtc_state *crtc_state; 2580 u8 min_voltage_level; 2581 int i; 2582 enum pipe pipe; 2583 2584 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2585 int ret; 2586 2587 if (crtc_state->hw.enable) 2588 min_voltage_level = crtc_state->min_voltage_level; 2589 else 2590 min_voltage_level = 0; 2591 2592 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level) 2593 continue; 2594 2595 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level; 2596 2597 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2598 if (ret) 2599 return ret; 2600 } 2601 2602 min_voltage_level = 0; 2603 for_each_pipe(dev_priv, pipe) 2604 min_voltage_level = max(cdclk_state->min_voltage_level[pipe], 2605 min_voltage_level); 2606 2607 return min_voltage_level; 2608 } 2609 2610 static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2611 { 2612 struct intel_atomic_state *state = cdclk_state->base.state; 2613 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2614 int min_cdclk, cdclk; 2615 2616 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2617 if (min_cdclk < 0) 2618 return min_cdclk; 2619 2620 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); 2621 2622 cdclk_state->logical.cdclk = cdclk; 2623 cdclk_state->logical.voltage_level = 2624 vlv_calc_voltage_level(dev_priv, cdclk); 2625 2626 if (!cdclk_state->active_pipes) { 2627 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); 2628 2629 cdclk_state->actual.cdclk = cdclk; 2630 cdclk_state->actual.voltage_level = 2631 vlv_calc_voltage_level(dev_priv, cdclk); 2632 } else { 2633 cdclk_state->actual = cdclk_state->logical; 2634 } 2635 2636 return 0; 2637 } 2638 2639 static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2640 { 2641 int min_cdclk, cdclk; 2642 2643 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2644 if (min_cdclk < 0) 2645 return min_cdclk; 2646 2647 cdclk = bdw_calc_cdclk(min_cdclk); 2648 2649 cdclk_state->logical.cdclk = cdclk; 2650 cdclk_state->logical.voltage_level = 2651 bdw_calc_voltage_level(cdclk); 2652 2653 if (!cdclk_state->active_pipes) { 2654 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); 2655 2656 cdclk_state->actual.cdclk = cdclk; 2657 cdclk_state->actual.voltage_level = 2658 bdw_calc_voltage_level(cdclk); 2659 } else { 2660 cdclk_state->actual = cdclk_state->logical; 2661 } 2662 2663 return 0; 2664 } 2665 2666 static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state) 2667 { 2668 struct intel_atomic_state *state = cdclk_state->base.state; 2669 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2670 struct intel_crtc *crtc; 2671 struct intel_crtc_state *crtc_state; 2672 int vco, i; 2673 2674 vco = cdclk_state->logical.vco; 2675 if (!vco) 2676 vco = dev_priv->skl_preferred_vco_freq; 2677 2678 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2679 if (!crtc_state->hw.enable) 2680 continue; 2681 2682 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 2683 continue; 2684 2685 /* 2686 * DPLL0 VCO may need to be adjusted to get the correct 2687 * clock for eDP. This will affect cdclk as well. 2688 */ 2689 switch (crtc_state->port_clock / 2) { 2690 case 108000: 2691 case 216000: 2692 vco = 8640000; 2693 break; 2694 default: 2695 vco = 8100000; 2696 break; 2697 } 2698 } 2699 2700 return vco; 2701 } 2702 2703 static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2704 { 2705 int min_cdclk, cdclk, vco; 2706 2707 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2708 if (min_cdclk < 0) 2709 return min_cdclk; 2710 2711 vco = skl_dpll0_vco(cdclk_state); 2712 2713 cdclk = skl_calc_cdclk(min_cdclk, vco); 2714 2715 cdclk_state->logical.vco = vco; 2716 cdclk_state->logical.cdclk = cdclk; 2717 cdclk_state->logical.voltage_level = 2718 skl_calc_voltage_level(cdclk); 2719 2720 if (!cdclk_state->active_pipes) { 2721 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); 2722 2723 cdclk_state->actual.vco = vco; 2724 cdclk_state->actual.cdclk = cdclk; 2725 cdclk_state->actual.voltage_level = 2726 skl_calc_voltage_level(cdclk); 2727 } else { 2728 cdclk_state->actual = cdclk_state->logical; 2729 } 2730 2731 return 0; 2732 } 2733 2734 static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2735 { 2736 struct intel_atomic_state *state = cdclk_state->base.state; 2737 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2738 int min_cdclk, min_voltage_level, cdclk, vco; 2739 2740 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2741 if (min_cdclk < 0) 2742 return min_cdclk; 2743 2744 min_voltage_level = bxt_compute_min_voltage_level(cdclk_state); 2745 if (min_voltage_level < 0) 2746 return min_voltage_level; 2747 2748 cdclk = bxt_calc_cdclk(dev_priv, min_cdclk); 2749 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 2750 2751 cdclk_state->logical.vco = vco; 2752 cdclk_state->logical.cdclk = cdclk; 2753 cdclk_state->logical.voltage_level = 2754 max_t(int, min_voltage_level, 2755 intel_cdclk_calc_voltage_level(dev_priv, cdclk)); 2756 2757 if (!cdclk_state->active_pipes) { 2758 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); 2759 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 2760 2761 cdclk_state->actual.vco = vco; 2762 cdclk_state->actual.cdclk = cdclk; 2763 cdclk_state->actual.voltage_level = 2764 intel_cdclk_calc_voltage_level(dev_priv, cdclk); 2765 } else { 2766 cdclk_state->actual = cdclk_state->logical; 2767 } 2768 2769 return 0; 2770 } 2771 2772 static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2773 { 2774 int min_cdclk; 2775 2776 /* 2777 * We can't change the cdclk frequency, but we still want to 2778 * check that the required minimum frequency doesn't exceed 2779 * the actual cdclk frequency. 2780 */ 2781 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2782 if (min_cdclk < 0) 2783 return min_cdclk; 2784 2785 return 0; 2786 } 2787 2788 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj) 2789 { 2790 struct intel_cdclk_state *cdclk_state; 2791 2792 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); 2793 if (!cdclk_state) 2794 return NULL; 2795 2796 cdclk_state->pipe = INVALID_PIPE; 2797 2798 return &cdclk_state->base; 2799 } 2800 2801 static void intel_cdclk_destroy_state(struct intel_global_obj *obj, 2802 struct intel_global_state *state) 2803 { 2804 kfree(state); 2805 } 2806 2807 static const struct intel_global_state_funcs intel_cdclk_funcs = { 2808 .atomic_duplicate_state = intel_cdclk_duplicate_state, 2809 .atomic_destroy_state = intel_cdclk_destroy_state, 2810 }; 2811 2812 struct intel_cdclk_state * 2813 intel_atomic_get_cdclk_state(struct intel_atomic_state *state) 2814 { 2815 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2816 struct intel_global_state *cdclk_state; 2817 2818 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj); 2819 if (IS_ERR(cdclk_state)) 2820 return ERR_CAST(cdclk_state); 2821 2822 return to_intel_cdclk_state(cdclk_state); 2823 } 2824 2825 int intel_cdclk_atomic_check(struct intel_atomic_state *state, 2826 bool *need_cdclk_calc) 2827 { 2828 const struct intel_cdclk_state *old_cdclk_state; 2829 const struct intel_cdclk_state *new_cdclk_state; 2830 struct intel_plane_state *plane_state; 2831 struct intel_plane *plane; 2832 int ret; 2833 int i; 2834 2835 /* 2836 * active_planes bitmask has been updated, and potentially affected 2837 * planes are part of the state. We can now compute the minimum cdclk 2838 * for each plane. 2839 */ 2840 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 2841 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc); 2842 if (ret) 2843 return ret; 2844 } 2845 2846 ret = intel_bw_calc_min_cdclk(state, need_cdclk_calc); 2847 if (ret) 2848 return ret; 2849 2850 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 2851 new_cdclk_state = intel_atomic_get_new_cdclk_state(state); 2852 2853 if (new_cdclk_state && 2854 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) 2855 *need_cdclk_calc = true; 2856 2857 return 0; 2858 } 2859 2860 int intel_cdclk_init(struct drm_i915_private *dev_priv) 2861 { 2862 struct intel_cdclk_state *cdclk_state; 2863 2864 cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL); 2865 if (!cdclk_state) 2866 return -ENOMEM; 2867 2868 intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj, 2869 &cdclk_state->base, &intel_cdclk_funcs); 2870 2871 return 0; 2872 } 2873 2874 int intel_modeset_calc_cdclk(struct intel_atomic_state *state) 2875 { 2876 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2877 const struct intel_cdclk_state *old_cdclk_state; 2878 struct intel_cdclk_state *new_cdclk_state; 2879 enum pipe pipe = INVALID_PIPE; 2880 int ret; 2881 2882 new_cdclk_state = intel_atomic_get_cdclk_state(state); 2883 if (IS_ERR(new_cdclk_state)) 2884 return PTR_ERR(new_cdclk_state); 2885 2886 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 2887 2888 new_cdclk_state->active_pipes = 2889 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); 2890 2891 ret = intel_cdclk_modeset_calc_cdclk(dev_priv, new_cdclk_state); 2892 if (ret) 2893 return ret; 2894 2895 if (intel_cdclk_changed(&old_cdclk_state->actual, 2896 &new_cdclk_state->actual)) { 2897 /* 2898 * Also serialize commits across all crtcs 2899 * if the actual hw needs to be poked. 2900 */ 2901 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); 2902 if (ret) 2903 return ret; 2904 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes || 2905 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk || 2906 intel_cdclk_changed(&old_cdclk_state->logical, 2907 &new_cdclk_state->logical)) { 2908 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 2909 if (ret) 2910 return ret; 2911 } else { 2912 return 0; 2913 } 2914 2915 if (is_power_of_2(new_cdclk_state->active_pipes) && 2916 intel_cdclk_can_cd2x_update(dev_priv, 2917 &old_cdclk_state->actual, 2918 &new_cdclk_state->actual)) { 2919 struct intel_crtc *crtc; 2920 struct intel_crtc_state *crtc_state; 2921 2922 pipe = ilog2(new_cdclk_state->active_pipes); 2923 crtc = intel_crtc_for_pipe(dev_priv, pipe); 2924 2925 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 2926 if (IS_ERR(crtc_state)) 2927 return PTR_ERR(crtc_state); 2928 2929 if (intel_crtc_needs_modeset(crtc_state)) 2930 pipe = INVALID_PIPE; 2931 } 2932 2933 if (intel_cdclk_can_crawl_and_squash(dev_priv, 2934 &old_cdclk_state->actual, 2935 &new_cdclk_state->actual)) { 2936 drm_dbg_kms(&dev_priv->drm, 2937 "Can change cdclk via crawling and squashing\n"); 2938 } else if (intel_cdclk_can_squash(dev_priv, 2939 &old_cdclk_state->actual, 2940 &new_cdclk_state->actual)) { 2941 drm_dbg_kms(&dev_priv->drm, 2942 "Can change cdclk via squashing\n"); 2943 } else if (intel_cdclk_can_crawl(dev_priv, 2944 &old_cdclk_state->actual, 2945 &new_cdclk_state->actual)) { 2946 drm_dbg_kms(&dev_priv->drm, 2947 "Can change cdclk via crawling\n"); 2948 } else if (pipe != INVALID_PIPE) { 2949 new_cdclk_state->pipe = pipe; 2950 2951 drm_dbg_kms(&dev_priv->drm, 2952 "Can change cdclk cd2x divider with pipe %c active\n", 2953 pipe_name(pipe)); 2954 } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual, 2955 &new_cdclk_state->actual)) { 2956 /* All pipes must be switched off while we change the cdclk. */ 2957 ret = intel_modeset_all_pipes(state, "CDCLK change"); 2958 if (ret) 2959 return ret; 2960 2961 drm_dbg_kms(&dev_priv->drm, 2962 "Modeset required for cdclk change\n"); 2963 } 2964 2965 drm_dbg_kms(&dev_priv->drm, 2966 "New cdclk calculated to be logical %u kHz, actual %u kHz\n", 2967 new_cdclk_state->logical.cdclk, 2968 new_cdclk_state->actual.cdclk); 2969 drm_dbg_kms(&dev_priv->drm, 2970 "New voltage level calculated to be logical %u, actual %u\n", 2971 new_cdclk_state->logical.voltage_level, 2972 new_cdclk_state->actual.voltage_level); 2973 2974 return 0; 2975 } 2976 2977 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) 2978 { 2979 int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq; 2980 2981 if (DISPLAY_VER(dev_priv) >= 10) 2982 return 2 * max_cdclk_freq; 2983 else if (DISPLAY_VER(dev_priv) == 9 || 2984 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2985 return max_cdclk_freq; 2986 else if (IS_CHERRYVIEW(dev_priv)) 2987 return max_cdclk_freq*95/100; 2988 else if (DISPLAY_VER(dev_priv) < 4) 2989 return 2*max_cdclk_freq*90/100; 2990 else 2991 return max_cdclk_freq*90/100; 2992 } 2993 2994 /** 2995 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency 2996 * @dev_priv: i915 device 2997 * 2998 * Determine the maximum CDCLK frequency the platform supports, and also 2999 * derive the maximum dot clock frequency the maximum CDCLK frequency 3000 * allows. 3001 */ 3002 void intel_update_max_cdclk(struct drm_i915_private *dev_priv) 3003 { 3004 if (IS_JSL_EHL(dev_priv)) { 3005 if (dev_priv->display.cdclk.hw.ref == 24000) 3006 dev_priv->display.cdclk.max_cdclk_freq = 552000; 3007 else 3008 dev_priv->display.cdclk.max_cdclk_freq = 556800; 3009 } else if (DISPLAY_VER(dev_priv) >= 11) { 3010 if (dev_priv->display.cdclk.hw.ref == 24000) 3011 dev_priv->display.cdclk.max_cdclk_freq = 648000; 3012 else 3013 dev_priv->display.cdclk.max_cdclk_freq = 652800; 3014 } else if (IS_GEMINILAKE(dev_priv)) { 3015 dev_priv->display.cdclk.max_cdclk_freq = 316800; 3016 } else if (IS_BROXTON(dev_priv)) { 3017 dev_priv->display.cdclk.max_cdclk_freq = 624000; 3018 } else if (DISPLAY_VER(dev_priv) == 9) { 3019 u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; 3020 int max_cdclk, vco; 3021 3022 vco = dev_priv->skl_preferred_vco_freq; 3023 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); 3024 3025 /* 3026 * Use the lower (vco 8640) cdclk values as a 3027 * first guess. skl_calc_cdclk() will correct it 3028 * if the preferred vco is 8100 instead. 3029 */ 3030 if (limit == SKL_DFSM_CDCLK_LIMIT_675) 3031 max_cdclk = 617143; 3032 else if (limit == SKL_DFSM_CDCLK_LIMIT_540) 3033 max_cdclk = 540000; 3034 else if (limit == SKL_DFSM_CDCLK_LIMIT_450) 3035 max_cdclk = 432000; 3036 else 3037 max_cdclk = 308571; 3038 3039 dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); 3040 } else if (IS_BROADWELL(dev_priv)) { 3041 /* 3042 * FIXME with extra cooling we can allow 3043 * 540 MHz for ULX and 675 Mhz for ULT. 3044 * How can we know if extra cooling is 3045 * available? PCI ID, VTB, something else? 3046 */ 3047 if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 3048 dev_priv->display.cdclk.max_cdclk_freq = 450000; 3049 else if (IS_BDW_ULX(dev_priv)) 3050 dev_priv->display.cdclk.max_cdclk_freq = 450000; 3051 else if (IS_BDW_ULT(dev_priv)) 3052 dev_priv->display.cdclk.max_cdclk_freq = 540000; 3053 else 3054 dev_priv->display.cdclk.max_cdclk_freq = 675000; 3055 } else if (IS_CHERRYVIEW(dev_priv)) { 3056 dev_priv->display.cdclk.max_cdclk_freq = 320000; 3057 } else if (IS_VALLEYVIEW(dev_priv)) { 3058 dev_priv->display.cdclk.max_cdclk_freq = 400000; 3059 } else { 3060 /* otherwise assume cdclk is fixed */ 3061 dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk; 3062 } 3063 3064 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); 3065 3066 drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n", 3067 dev_priv->display.cdclk.max_cdclk_freq); 3068 3069 drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n", 3070 dev_priv->max_dotclk_freq); 3071 } 3072 3073 /** 3074 * intel_update_cdclk - Determine the current CDCLK frequency 3075 * @dev_priv: i915 device 3076 * 3077 * Determine the current CDCLK frequency. 3078 */ 3079 void intel_update_cdclk(struct drm_i915_private *dev_priv) 3080 { 3081 intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw); 3082 3083 /* 3084 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): 3085 * Programmng [sic] note: bit[9:2] should be programmed to the number 3086 * of cdclk that generates 4MHz reference clock freq which is used to 3087 * generate GMBus clock. This will vary with the cdclk freq. 3088 */ 3089 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 3090 intel_de_write(dev_priv, GMBUSFREQ_VLV, 3091 DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000)); 3092 } 3093 3094 static int dg1_rawclk(struct drm_i915_private *dev_priv) 3095 { 3096 /* 3097 * DG1 always uses a 38.4 MHz rawclk. The bspec tells us 3098 * "Program Numerator=2, Denominator=4, Divider=37 decimal." 3099 */ 3100 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, 3101 CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2)); 3102 3103 return 38400; 3104 } 3105 3106 static int cnp_rawclk(struct drm_i915_private *dev_priv) 3107 { 3108 u32 rawclk; 3109 int divider, fraction; 3110 3111 if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { 3112 /* 24 MHz */ 3113 divider = 24000; 3114 fraction = 0; 3115 } else { 3116 /* 19.2 MHz */ 3117 divider = 19000; 3118 fraction = 200; 3119 } 3120 3121 rawclk = CNP_RAWCLK_DIV(divider / 1000); 3122 if (fraction) { 3123 int numerator = 1; 3124 3125 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000, 3126 fraction) - 1); 3127 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 3128 rawclk |= ICP_RAWCLK_NUM(numerator); 3129 } 3130 3131 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk); 3132 return divider + fraction; 3133 } 3134 3135 static int pch_rawclk(struct drm_i915_private *dev_priv) 3136 { 3137 return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; 3138 } 3139 3140 static int vlv_hrawclk(struct drm_i915_private *dev_priv) 3141 { 3142 /* RAWCLK_FREQ_VLV register updated from power well code */ 3143 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", 3144 CCK_DISPLAY_REF_CLOCK_CONTROL); 3145 } 3146 3147 static int i9xx_hrawclk(struct drm_i915_private *dev_priv) 3148 { 3149 u32 clkcfg; 3150 3151 /* 3152 * hrawclock is 1/4 the FSB frequency 3153 * 3154 * Note that this only reads the state of the FSB 3155 * straps, not the actual FSB frequency. Some BIOSen 3156 * let you configure each independently. Ideally we'd 3157 * read out the actual FSB frequency but sadly we 3158 * don't know which registers have that information, 3159 * and all the relevant docs have gone to bit heaven :( 3160 */ 3161 clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK; 3162 3163 if (IS_MOBILE(dev_priv)) { 3164 switch (clkcfg) { 3165 case CLKCFG_FSB_400: 3166 return 100000; 3167 case CLKCFG_FSB_533: 3168 return 133333; 3169 case CLKCFG_FSB_667: 3170 return 166667; 3171 case CLKCFG_FSB_800: 3172 return 200000; 3173 case CLKCFG_FSB_1067: 3174 return 266667; 3175 case CLKCFG_FSB_1333: 3176 return 333333; 3177 default: 3178 MISSING_CASE(clkcfg); 3179 return 133333; 3180 } 3181 } else { 3182 switch (clkcfg) { 3183 case CLKCFG_FSB_400_ALT: 3184 return 100000; 3185 case CLKCFG_FSB_533: 3186 return 133333; 3187 case CLKCFG_FSB_667: 3188 return 166667; 3189 case CLKCFG_FSB_800: 3190 return 200000; 3191 case CLKCFG_FSB_1067_ALT: 3192 return 266667; 3193 case CLKCFG_FSB_1333_ALT: 3194 return 333333; 3195 case CLKCFG_FSB_1600_ALT: 3196 return 400000; 3197 default: 3198 return 133333; 3199 } 3200 } 3201 } 3202 3203 /** 3204 * intel_read_rawclk - Determine the current RAWCLK frequency 3205 * @dev_priv: i915 device 3206 * 3207 * Determine the current RAWCLK frequency. RAWCLK is a fixed 3208 * frequency clock so this needs to done only once. 3209 */ 3210 u32 intel_read_rawclk(struct drm_i915_private *dev_priv) 3211 { 3212 u32 freq; 3213 3214 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 3215 freq = dg1_rawclk(dev_priv); 3216 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP) 3217 /* 3218 * MTL always uses a 38.4 MHz rawclk. The bspec tells us 3219 * "RAWCLK_FREQ defaults to the values for 38.4 and does 3220 * not need to be programmed." 3221 */ 3222 freq = 38400; 3223 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) 3224 freq = cnp_rawclk(dev_priv); 3225 else if (HAS_PCH_SPLIT(dev_priv)) 3226 freq = pch_rawclk(dev_priv); 3227 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 3228 freq = vlv_hrawclk(dev_priv); 3229 else if (DISPLAY_VER(dev_priv) >= 3) 3230 freq = i9xx_hrawclk(dev_priv); 3231 else 3232 /* no rawclk on other platforms, or no need to know it */ 3233 return 0; 3234 3235 return freq; 3236 } 3237 3238 static const struct intel_cdclk_funcs mtl_cdclk_funcs = { 3239 .get_cdclk = bxt_get_cdclk, 3240 .set_cdclk = bxt_set_cdclk, 3241 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3242 .calc_voltage_level = tgl_calc_voltage_level, 3243 }; 3244 3245 static const struct intel_cdclk_funcs tgl_cdclk_funcs = { 3246 .get_cdclk = bxt_get_cdclk, 3247 .set_cdclk = bxt_set_cdclk, 3248 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3249 .calc_voltage_level = tgl_calc_voltage_level, 3250 }; 3251 3252 static const struct intel_cdclk_funcs ehl_cdclk_funcs = { 3253 .get_cdclk = bxt_get_cdclk, 3254 .set_cdclk = bxt_set_cdclk, 3255 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3256 .calc_voltage_level = ehl_calc_voltage_level, 3257 }; 3258 3259 static const struct intel_cdclk_funcs icl_cdclk_funcs = { 3260 .get_cdclk = bxt_get_cdclk, 3261 .set_cdclk = bxt_set_cdclk, 3262 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3263 .calc_voltage_level = icl_calc_voltage_level, 3264 }; 3265 3266 static const struct intel_cdclk_funcs bxt_cdclk_funcs = { 3267 .get_cdclk = bxt_get_cdclk, 3268 .set_cdclk = bxt_set_cdclk, 3269 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3270 .calc_voltage_level = bxt_calc_voltage_level, 3271 }; 3272 3273 static const struct intel_cdclk_funcs skl_cdclk_funcs = { 3274 .get_cdclk = skl_get_cdclk, 3275 .set_cdclk = skl_set_cdclk, 3276 .modeset_calc_cdclk = skl_modeset_calc_cdclk, 3277 }; 3278 3279 static const struct intel_cdclk_funcs bdw_cdclk_funcs = { 3280 .get_cdclk = bdw_get_cdclk, 3281 .set_cdclk = bdw_set_cdclk, 3282 .modeset_calc_cdclk = bdw_modeset_calc_cdclk, 3283 }; 3284 3285 static const struct intel_cdclk_funcs chv_cdclk_funcs = { 3286 .get_cdclk = vlv_get_cdclk, 3287 .set_cdclk = chv_set_cdclk, 3288 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3289 }; 3290 3291 static const struct intel_cdclk_funcs vlv_cdclk_funcs = { 3292 .get_cdclk = vlv_get_cdclk, 3293 .set_cdclk = vlv_set_cdclk, 3294 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3295 }; 3296 3297 static const struct intel_cdclk_funcs hsw_cdclk_funcs = { 3298 .get_cdclk = hsw_get_cdclk, 3299 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3300 }; 3301 3302 /* SNB, IVB, 965G, 945G */ 3303 static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = { 3304 .get_cdclk = fixed_400mhz_get_cdclk, 3305 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3306 }; 3307 3308 static const struct intel_cdclk_funcs ilk_cdclk_funcs = { 3309 .get_cdclk = fixed_450mhz_get_cdclk, 3310 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3311 }; 3312 3313 static const struct intel_cdclk_funcs gm45_cdclk_funcs = { 3314 .get_cdclk = gm45_get_cdclk, 3315 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3316 }; 3317 3318 /* G45 uses G33 */ 3319 3320 static const struct intel_cdclk_funcs i965gm_cdclk_funcs = { 3321 .get_cdclk = i965gm_get_cdclk, 3322 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3323 }; 3324 3325 /* i965G uses fixed 400 */ 3326 3327 static const struct intel_cdclk_funcs pnv_cdclk_funcs = { 3328 .get_cdclk = pnv_get_cdclk, 3329 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3330 }; 3331 3332 static const struct intel_cdclk_funcs g33_cdclk_funcs = { 3333 .get_cdclk = g33_get_cdclk, 3334 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3335 }; 3336 3337 static const struct intel_cdclk_funcs i945gm_cdclk_funcs = { 3338 .get_cdclk = i945gm_get_cdclk, 3339 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3340 }; 3341 3342 /* i945G uses fixed 400 */ 3343 3344 static const struct intel_cdclk_funcs i915gm_cdclk_funcs = { 3345 .get_cdclk = i915gm_get_cdclk, 3346 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3347 }; 3348 3349 static const struct intel_cdclk_funcs i915g_cdclk_funcs = { 3350 .get_cdclk = fixed_333mhz_get_cdclk, 3351 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3352 }; 3353 3354 static const struct intel_cdclk_funcs i865g_cdclk_funcs = { 3355 .get_cdclk = fixed_266mhz_get_cdclk, 3356 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3357 }; 3358 3359 static const struct intel_cdclk_funcs i85x_cdclk_funcs = { 3360 .get_cdclk = i85x_get_cdclk, 3361 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3362 }; 3363 3364 static const struct intel_cdclk_funcs i845g_cdclk_funcs = { 3365 .get_cdclk = fixed_200mhz_get_cdclk, 3366 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3367 }; 3368 3369 static const struct intel_cdclk_funcs i830_cdclk_funcs = { 3370 .get_cdclk = fixed_133mhz_get_cdclk, 3371 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3372 }; 3373 3374 /** 3375 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks 3376 * @dev_priv: i915 device 3377 */ 3378 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) 3379 { 3380 if (IS_METEORLAKE(dev_priv)) { 3381 dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs; 3382 dev_priv->display.cdclk.table = mtl_cdclk_table; 3383 } else if (IS_DG2(dev_priv)) { 3384 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3385 dev_priv->display.cdclk.table = dg2_cdclk_table; 3386 } else if (IS_ALDERLAKE_P(dev_priv)) { 3387 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3388 /* Wa_22011320316:adl-p[a0] */ 3389 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 3390 dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; 3391 else if (IS_ADLP_RPLU(dev_priv)) 3392 dev_priv->display.cdclk.table = rplu_cdclk_table; 3393 else 3394 dev_priv->display.cdclk.table = adlp_cdclk_table; 3395 } else if (IS_ROCKETLAKE(dev_priv)) { 3396 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3397 dev_priv->display.cdclk.table = rkl_cdclk_table; 3398 } else if (DISPLAY_VER(dev_priv) >= 12) { 3399 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3400 dev_priv->display.cdclk.table = icl_cdclk_table; 3401 } else if (IS_JSL_EHL(dev_priv)) { 3402 dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs; 3403 dev_priv->display.cdclk.table = icl_cdclk_table; 3404 } else if (DISPLAY_VER(dev_priv) >= 11) { 3405 dev_priv->display.funcs.cdclk = &icl_cdclk_funcs; 3406 dev_priv->display.cdclk.table = icl_cdclk_table; 3407 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 3408 dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs; 3409 if (IS_GEMINILAKE(dev_priv)) 3410 dev_priv->display.cdclk.table = glk_cdclk_table; 3411 else 3412 dev_priv->display.cdclk.table = bxt_cdclk_table; 3413 } else if (DISPLAY_VER(dev_priv) == 9) { 3414 dev_priv->display.funcs.cdclk = &skl_cdclk_funcs; 3415 } else if (IS_BROADWELL(dev_priv)) { 3416 dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs; 3417 } else if (IS_HASWELL(dev_priv)) { 3418 dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs; 3419 } else if (IS_CHERRYVIEW(dev_priv)) { 3420 dev_priv->display.funcs.cdclk = &chv_cdclk_funcs; 3421 } else if (IS_VALLEYVIEW(dev_priv)) { 3422 dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs; 3423 } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) { 3424 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3425 } else if (IS_IRONLAKE(dev_priv)) { 3426 dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs; 3427 } else if (IS_GM45(dev_priv)) { 3428 dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs; 3429 } else if (IS_G45(dev_priv)) { 3430 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; 3431 } else if (IS_I965GM(dev_priv)) { 3432 dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs; 3433 } else if (IS_I965G(dev_priv)) { 3434 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3435 } else if (IS_PINEVIEW(dev_priv)) { 3436 dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs; 3437 } else if (IS_G33(dev_priv)) { 3438 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; 3439 } else if (IS_I945GM(dev_priv)) { 3440 dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs; 3441 } else if (IS_I945G(dev_priv)) { 3442 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3443 } else if (IS_I915GM(dev_priv)) { 3444 dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs; 3445 } else if (IS_I915G(dev_priv)) { 3446 dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs; 3447 } else if (IS_I865G(dev_priv)) { 3448 dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs; 3449 } else if (IS_I85X(dev_priv)) { 3450 dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs; 3451 } else if (IS_I845G(dev_priv)) { 3452 dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs; 3453 } else if (IS_I830(dev_priv)) { 3454 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; 3455 } 3456 3457 if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk, 3458 "Unknown platform. Assuming i830\n")) 3459 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; 3460 } 3461