1 /* 2 * Copyright © 2006-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/time.h> 25 26 #include "hsw_ips.h" 27 #include "intel_atomic.h" 28 #include "intel_atomic_plane.h" 29 #include "intel_audio.h" 30 #include "intel_bw.h" 31 #include "intel_cdclk.h" 32 #include "intel_crtc.h" 33 #include "intel_de.h" 34 #include "intel_display_types.h" 35 #include "intel_mchbar_regs.h" 36 #include "intel_pci_config.h" 37 #include "intel_pcode.h" 38 #include "intel_psr.h" 39 #include "vlv_sideband.h" 40 41 /** 42 * DOC: CDCLK / RAWCLK 43 * 44 * The display engine uses several different clocks to do its work. There 45 * are two main clocks involved that aren't directly related to the actual 46 * pixel clock or any symbol/bit clock of the actual output port. These 47 * are the core display clock (CDCLK) and RAWCLK. 48 * 49 * CDCLK clocks most of the display pipe logic, and thus its frequency 50 * must be high enough to support the rate at which pixels are flowing 51 * through the pipes. Downscaling must also be accounted as that increases 52 * the effective pixel rate. 53 * 54 * On several platforms the CDCLK frequency can be changed dynamically 55 * to minimize power consumption for a given display configuration. 56 * Typically changes to the CDCLK frequency require all the display pipes 57 * to be shut down while the frequency is being changed. 58 * 59 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. 60 * DMC will not change the active CDCLK frequency however, so that part 61 * will still be performed by the driver directly. 62 * 63 * RAWCLK is a fixed frequency clock, often used by various auxiliary 64 * blocks such as AUX CH or backlight PWM. Hence the only thing we 65 * really need to know about RAWCLK is its frequency so that various 66 * dividers can be programmed correctly. 67 */ 68 69 struct intel_cdclk_funcs { 70 void (*get_cdclk)(struct drm_i915_private *i915, 71 struct intel_cdclk_config *cdclk_config); 72 void (*set_cdclk)(struct drm_i915_private *i915, 73 const struct intel_cdclk_config *cdclk_config, 74 enum pipe pipe); 75 int (*modeset_calc_cdclk)(struct intel_cdclk_state *state); 76 u8 (*calc_voltage_level)(int cdclk); 77 }; 78 79 void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv, 80 struct intel_cdclk_config *cdclk_config) 81 { 82 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); 83 } 84 85 static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv, 86 const struct intel_cdclk_config *cdclk_config, 87 enum pipe pipe) 88 { 89 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); 90 } 91 92 static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv, 93 struct intel_cdclk_state *cdclk_config) 94 { 95 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config); 96 } 97 98 static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv, 99 int cdclk) 100 { 101 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); 102 } 103 104 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, 105 struct intel_cdclk_config *cdclk_config) 106 { 107 cdclk_config->cdclk = 133333; 108 } 109 110 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, 111 struct intel_cdclk_config *cdclk_config) 112 { 113 cdclk_config->cdclk = 200000; 114 } 115 116 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, 117 struct intel_cdclk_config *cdclk_config) 118 { 119 cdclk_config->cdclk = 266667; 120 } 121 122 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, 123 struct intel_cdclk_config *cdclk_config) 124 { 125 cdclk_config->cdclk = 333333; 126 } 127 128 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, 129 struct intel_cdclk_config *cdclk_config) 130 { 131 cdclk_config->cdclk = 400000; 132 } 133 134 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, 135 struct intel_cdclk_config *cdclk_config) 136 { 137 cdclk_config->cdclk = 450000; 138 } 139 140 static void i85x_get_cdclk(struct drm_i915_private *dev_priv, 141 struct intel_cdclk_config *cdclk_config) 142 { 143 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 144 u16 hpllcc = 0; 145 146 /* 147 * 852GM/852GMV only supports 133 MHz and the HPLLCC 148 * encoding is different :( 149 * FIXME is this the right way to detect 852GM/852GMV? 150 */ 151 if (pdev->revision == 0x1) { 152 cdclk_config->cdclk = 133333; 153 return; 154 } 155 156 pci_bus_read_config_word(pdev->bus, 157 PCI_DEVFN(0, 3), HPLLCC, &hpllcc); 158 159 /* Assume that the hardware is in the high speed state. This 160 * should be the default. 161 */ 162 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 163 case GC_CLOCK_133_200: 164 case GC_CLOCK_133_200_2: 165 case GC_CLOCK_100_200: 166 cdclk_config->cdclk = 200000; 167 break; 168 case GC_CLOCK_166_250: 169 cdclk_config->cdclk = 250000; 170 break; 171 case GC_CLOCK_100_133: 172 cdclk_config->cdclk = 133333; 173 break; 174 case GC_CLOCK_133_266: 175 case GC_CLOCK_133_266_2: 176 case GC_CLOCK_166_266: 177 cdclk_config->cdclk = 266667; 178 break; 179 } 180 } 181 182 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, 183 struct intel_cdclk_config *cdclk_config) 184 { 185 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 186 u16 gcfgc = 0; 187 188 pci_read_config_word(pdev, GCFGC, &gcfgc); 189 190 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 191 cdclk_config->cdclk = 133333; 192 return; 193 } 194 195 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 196 case GC_DISPLAY_CLOCK_333_320_MHZ: 197 cdclk_config->cdclk = 333333; 198 break; 199 default: 200 case GC_DISPLAY_CLOCK_190_200_MHZ: 201 cdclk_config->cdclk = 190000; 202 break; 203 } 204 } 205 206 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, 207 struct intel_cdclk_config *cdclk_config) 208 { 209 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 210 u16 gcfgc = 0; 211 212 pci_read_config_word(pdev, GCFGC, &gcfgc); 213 214 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 215 cdclk_config->cdclk = 133333; 216 return; 217 } 218 219 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 220 case GC_DISPLAY_CLOCK_333_320_MHZ: 221 cdclk_config->cdclk = 320000; 222 break; 223 default: 224 case GC_DISPLAY_CLOCK_190_200_MHZ: 225 cdclk_config->cdclk = 200000; 226 break; 227 } 228 } 229 230 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) 231 { 232 static const unsigned int blb_vco[8] = { 233 [0] = 3200000, 234 [1] = 4000000, 235 [2] = 5333333, 236 [3] = 4800000, 237 [4] = 6400000, 238 }; 239 static const unsigned int pnv_vco[8] = { 240 [0] = 3200000, 241 [1] = 4000000, 242 [2] = 5333333, 243 [3] = 4800000, 244 [4] = 2666667, 245 }; 246 static const unsigned int cl_vco[8] = { 247 [0] = 3200000, 248 [1] = 4000000, 249 [2] = 5333333, 250 [3] = 6400000, 251 [4] = 3333333, 252 [5] = 3566667, 253 [6] = 4266667, 254 }; 255 static const unsigned int elk_vco[8] = { 256 [0] = 3200000, 257 [1] = 4000000, 258 [2] = 5333333, 259 [3] = 4800000, 260 }; 261 static const unsigned int ctg_vco[8] = { 262 [0] = 3200000, 263 [1] = 4000000, 264 [2] = 5333333, 265 [3] = 6400000, 266 [4] = 2666667, 267 [5] = 4266667, 268 }; 269 const unsigned int *vco_table; 270 unsigned int vco; 271 u8 tmp = 0; 272 273 /* FIXME other chipsets? */ 274 if (IS_GM45(dev_priv)) 275 vco_table = ctg_vco; 276 else if (IS_G45(dev_priv)) 277 vco_table = elk_vco; 278 else if (IS_I965GM(dev_priv)) 279 vco_table = cl_vco; 280 else if (IS_PINEVIEW(dev_priv)) 281 vco_table = pnv_vco; 282 else if (IS_G33(dev_priv)) 283 vco_table = blb_vco; 284 else 285 return 0; 286 287 tmp = intel_de_read(dev_priv, 288 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); 289 290 vco = vco_table[tmp & 0x7]; 291 if (vco == 0) 292 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", 293 tmp); 294 else 295 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); 296 297 return vco; 298 } 299 300 static void g33_get_cdclk(struct drm_i915_private *dev_priv, 301 struct intel_cdclk_config *cdclk_config) 302 { 303 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 304 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 }; 305 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 }; 306 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 }; 307 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 }; 308 const u8 *div_table; 309 unsigned int cdclk_sel; 310 u16 tmp = 0; 311 312 cdclk_config->vco = intel_hpll_vco(dev_priv); 313 314 pci_read_config_word(pdev, GCFGC, &tmp); 315 316 cdclk_sel = (tmp >> 4) & 0x7; 317 318 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 319 goto fail; 320 321 switch (cdclk_config->vco) { 322 case 3200000: 323 div_table = div_3200; 324 break; 325 case 4000000: 326 div_table = div_4000; 327 break; 328 case 4800000: 329 div_table = div_4800; 330 break; 331 case 5333333: 332 div_table = div_5333; 333 break; 334 default: 335 goto fail; 336 } 337 338 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 339 div_table[cdclk_sel]); 340 return; 341 342 fail: 343 drm_err(&dev_priv->drm, 344 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", 345 cdclk_config->vco, tmp); 346 cdclk_config->cdclk = 190476; 347 } 348 349 static void pnv_get_cdclk(struct drm_i915_private *dev_priv, 350 struct intel_cdclk_config *cdclk_config) 351 { 352 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 353 u16 gcfgc = 0; 354 355 pci_read_config_word(pdev, GCFGC, &gcfgc); 356 357 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 358 case GC_DISPLAY_CLOCK_267_MHZ_PNV: 359 cdclk_config->cdclk = 266667; 360 break; 361 case GC_DISPLAY_CLOCK_333_MHZ_PNV: 362 cdclk_config->cdclk = 333333; 363 break; 364 case GC_DISPLAY_CLOCK_444_MHZ_PNV: 365 cdclk_config->cdclk = 444444; 366 break; 367 case GC_DISPLAY_CLOCK_200_MHZ_PNV: 368 cdclk_config->cdclk = 200000; 369 break; 370 default: 371 drm_err(&dev_priv->drm, 372 "Unknown pnv display core clock 0x%04x\n", gcfgc); 373 fallthrough; 374 case GC_DISPLAY_CLOCK_133_MHZ_PNV: 375 cdclk_config->cdclk = 133333; 376 break; 377 case GC_DISPLAY_CLOCK_167_MHZ_PNV: 378 cdclk_config->cdclk = 166667; 379 break; 380 } 381 } 382 383 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, 384 struct intel_cdclk_config *cdclk_config) 385 { 386 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 387 static const u8 div_3200[] = { 16, 10, 8 }; 388 static const u8 div_4000[] = { 20, 12, 10 }; 389 static const u8 div_5333[] = { 24, 16, 14 }; 390 const u8 *div_table; 391 unsigned int cdclk_sel; 392 u16 tmp = 0; 393 394 cdclk_config->vco = intel_hpll_vco(dev_priv); 395 396 pci_read_config_word(pdev, GCFGC, &tmp); 397 398 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; 399 400 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 401 goto fail; 402 403 switch (cdclk_config->vco) { 404 case 3200000: 405 div_table = div_3200; 406 break; 407 case 4000000: 408 div_table = div_4000; 409 break; 410 case 5333333: 411 div_table = div_5333; 412 break; 413 default: 414 goto fail; 415 } 416 417 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 418 div_table[cdclk_sel]); 419 return; 420 421 fail: 422 drm_err(&dev_priv->drm, 423 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", 424 cdclk_config->vco, tmp); 425 cdclk_config->cdclk = 200000; 426 } 427 428 static void gm45_get_cdclk(struct drm_i915_private *dev_priv, 429 struct intel_cdclk_config *cdclk_config) 430 { 431 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 432 unsigned int cdclk_sel; 433 u16 tmp = 0; 434 435 cdclk_config->vco = intel_hpll_vco(dev_priv); 436 437 pci_read_config_word(pdev, GCFGC, &tmp); 438 439 cdclk_sel = (tmp >> 12) & 0x1; 440 441 switch (cdclk_config->vco) { 442 case 2666667: 443 case 4000000: 444 case 5333333: 445 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; 446 break; 447 case 3200000: 448 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; 449 break; 450 default: 451 drm_err(&dev_priv->drm, 452 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", 453 cdclk_config->vco, tmp); 454 cdclk_config->cdclk = 222222; 455 break; 456 } 457 } 458 459 static void hsw_get_cdclk(struct drm_i915_private *dev_priv, 460 struct intel_cdclk_config *cdclk_config) 461 { 462 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); 463 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 464 465 if (lcpll & LCPLL_CD_SOURCE_FCLK) 466 cdclk_config->cdclk = 800000; 467 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 468 cdclk_config->cdclk = 450000; 469 else if (freq == LCPLL_CLK_FREQ_450) 470 cdclk_config->cdclk = 450000; 471 else if (IS_HSW_ULT(dev_priv)) 472 cdclk_config->cdclk = 337500; 473 else 474 cdclk_config->cdclk = 540000; 475 } 476 477 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) 478 { 479 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 480 333333 : 320000; 481 482 /* 483 * We seem to get an unstable or solid color picture at 200MHz. 484 * Not sure what's wrong. For now use 200MHz only when all pipes 485 * are off. 486 */ 487 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) 488 return 400000; 489 else if (min_cdclk > 266667) 490 return freq_320; 491 else if (min_cdclk > 0) 492 return 266667; 493 else 494 return 200000; 495 } 496 497 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) 498 { 499 if (IS_VALLEYVIEW(dev_priv)) { 500 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ 501 return 2; 502 else if (cdclk >= 266667) 503 return 1; 504 else 505 return 0; 506 } else { 507 /* 508 * Specs are full of misinformation, but testing on actual 509 * hardware has shown that we just need to write the desired 510 * CCK divider into the Punit register. 511 */ 512 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; 513 } 514 } 515 516 static void vlv_get_cdclk(struct drm_i915_private *dev_priv, 517 struct intel_cdclk_config *cdclk_config) 518 { 519 u32 val; 520 521 vlv_iosf_sb_get(dev_priv, 522 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 523 524 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); 525 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", 526 CCK_DISPLAY_CLOCK_CONTROL, 527 cdclk_config->vco); 528 529 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 530 531 vlv_iosf_sb_put(dev_priv, 532 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 533 534 if (IS_VALLEYVIEW(dev_priv)) 535 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> 536 DSPFREQGUAR_SHIFT; 537 else 538 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> 539 DSPFREQGUAR_SHIFT_CHV; 540 } 541 542 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) 543 { 544 unsigned int credits, default_credits; 545 546 if (IS_CHERRYVIEW(dev_priv)) 547 default_credits = PFI_CREDIT(12); 548 else 549 default_credits = PFI_CREDIT(8); 550 551 if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) { 552 /* CHV suggested value is 31 or 63 */ 553 if (IS_CHERRYVIEW(dev_priv)) 554 credits = PFI_CREDIT_63; 555 else 556 credits = PFI_CREDIT(15); 557 } else { 558 credits = default_credits; 559 } 560 561 /* 562 * WA - write default credits before re-programming 563 * FIXME: should we also set the resend bit here? 564 */ 565 intel_de_write(dev_priv, GCI_CONTROL, 566 VGA_FAST_MODE_DISABLE | default_credits); 567 568 intel_de_write(dev_priv, GCI_CONTROL, 569 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND); 570 571 /* 572 * FIXME is this guaranteed to clear 573 * immediately or should we poll for it? 574 */ 575 drm_WARN_ON(&dev_priv->drm, 576 intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND); 577 } 578 579 static void vlv_set_cdclk(struct drm_i915_private *dev_priv, 580 const struct intel_cdclk_config *cdclk_config, 581 enum pipe pipe) 582 { 583 int cdclk = cdclk_config->cdclk; 584 u32 val, cmd = cdclk_config->voltage_level; 585 intel_wakeref_t wakeref; 586 587 switch (cdclk) { 588 case 400000: 589 case 333333: 590 case 320000: 591 case 266667: 592 case 200000: 593 break; 594 default: 595 MISSING_CASE(cdclk); 596 return; 597 } 598 599 /* There are cases where we can end up here with power domains 600 * off and a CDCLK frequency other than the minimum, like when 601 * issuing a modeset without actually changing any display after 602 * a system suspend. So grab the display core domain, which covers 603 * the HW blocks needed for the following programming. 604 */ 605 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); 606 607 vlv_iosf_sb_get(dev_priv, 608 BIT(VLV_IOSF_SB_CCK) | 609 BIT(VLV_IOSF_SB_BUNIT) | 610 BIT(VLV_IOSF_SB_PUNIT)); 611 612 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 613 val &= ~DSPFREQGUAR_MASK; 614 val |= (cmd << DSPFREQGUAR_SHIFT); 615 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); 616 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & 617 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 618 50)) { 619 drm_err(&dev_priv->drm, 620 "timed out waiting for CDclk change\n"); 621 } 622 623 if (cdclk == 400000) { 624 u32 divider; 625 626 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, 627 cdclk) - 1; 628 629 /* adjust cdclk divider */ 630 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); 631 val &= ~CCK_FREQUENCY_VALUES; 632 val |= divider; 633 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); 634 635 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & 636 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 637 50)) 638 drm_err(&dev_priv->drm, 639 "timed out waiting for CDclk change\n"); 640 } 641 642 /* adjust self-refresh exit latency value */ 643 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); 644 val &= ~0x7f; 645 646 /* 647 * For high bandwidth configs, we set a higher latency in the bunit 648 * so that the core display fetch happens in time to avoid underruns. 649 */ 650 if (cdclk == 400000) 651 val |= 4500 / 250; /* 4.5 usec */ 652 else 653 val |= 3000 / 250; /* 3.0 usec */ 654 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); 655 656 vlv_iosf_sb_put(dev_priv, 657 BIT(VLV_IOSF_SB_CCK) | 658 BIT(VLV_IOSF_SB_BUNIT) | 659 BIT(VLV_IOSF_SB_PUNIT)); 660 661 intel_update_cdclk(dev_priv); 662 663 vlv_program_pfi_credits(dev_priv); 664 665 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); 666 } 667 668 static void chv_set_cdclk(struct drm_i915_private *dev_priv, 669 const struct intel_cdclk_config *cdclk_config, 670 enum pipe pipe) 671 { 672 int cdclk = cdclk_config->cdclk; 673 u32 val, cmd = cdclk_config->voltage_level; 674 intel_wakeref_t wakeref; 675 676 switch (cdclk) { 677 case 333333: 678 case 320000: 679 case 266667: 680 case 200000: 681 break; 682 default: 683 MISSING_CASE(cdclk); 684 return; 685 } 686 687 /* There are cases where we can end up here with power domains 688 * off and a CDCLK frequency other than the minimum, like when 689 * issuing a modeset without actually changing any display after 690 * a system suspend. So grab the display core domain, which covers 691 * the HW blocks needed for the following programming. 692 */ 693 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); 694 695 vlv_punit_get(dev_priv); 696 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 697 val &= ~DSPFREQGUAR_MASK_CHV; 698 val |= (cmd << DSPFREQGUAR_SHIFT_CHV); 699 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); 700 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & 701 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 702 50)) { 703 drm_err(&dev_priv->drm, 704 "timed out waiting for CDclk change\n"); 705 } 706 707 vlv_punit_put(dev_priv); 708 709 intel_update_cdclk(dev_priv); 710 711 vlv_program_pfi_credits(dev_priv); 712 713 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); 714 } 715 716 static int bdw_calc_cdclk(int min_cdclk) 717 { 718 if (min_cdclk > 540000) 719 return 675000; 720 else if (min_cdclk > 450000) 721 return 540000; 722 else if (min_cdclk > 337500) 723 return 450000; 724 else 725 return 337500; 726 } 727 728 static u8 bdw_calc_voltage_level(int cdclk) 729 { 730 switch (cdclk) { 731 default: 732 case 337500: 733 return 2; 734 case 450000: 735 return 0; 736 case 540000: 737 return 1; 738 case 675000: 739 return 3; 740 } 741 } 742 743 static void bdw_get_cdclk(struct drm_i915_private *dev_priv, 744 struct intel_cdclk_config *cdclk_config) 745 { 746 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); 747 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 748 749 if (lcpll & LCPLL_CD_SOURCE_FCLK) 750 cdclk_config->cdclk = 800000; 751 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 752 cdclk_config->cdclk = 450000; 753 else if (freq == LCPLL_CLK_FREQ_450) 754 cdclk_config->cdclk = 450000; 755 else if (freq == LCPLL_CLK_FREQ_54O_BDW) 756 cdclk_config->cdclk = 540000; 757 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 758 cdclk_config->cdclk = 337500; 759 else 760 cdclk_config->cdclk = 675000; 761 762 /* 763 * Can't read this out :( Let's assume it's 764 * at least what the CDCLK frequency requires. 765 */ 766 cdclk_config->voltage_level = 767 bdw_calc_voltage_level(cdclk_config->cdclk); 768 } 769 770 static u32 bdw_cdclk_freq_sel(int cdclk) 771 { 772 switch (cdclk) { 773 default: 774 MISSING_CASE(cdclk); 775 fallthrough; 776 case 337500: 777 return LCPLL_CLK_FREQ_337_5_BDW; 778 case 450000: 779 return LCPLL_CLK_FREQ_450; 780 case 540000: 781 return LCPLL_CLK_FREQ_54O_BDW; 782 case 675000: 783 return LCPLL_CLK_FREQ_675_BDW; 784 } 785 } 786 787 static void bdw_set_cdclk(struct drm_i915_private *dev_priv, 788 const struct intel_cdclk_config *cdclk_config, 789 enum pipe pipe) 790 { 791 int cdclk = cdclk_config->cdclk; 792 int ret; 793 794 if (drm_WARN(&dev_priv->drm, 795 (intel_de_read(dev_priv, LCPLL_CTL) & 796 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | 797 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | 798 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | 799 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, 800 "trying to change cdclk frequency with cdclk not enabled\n")) 801 return; 802 803 ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); 804 if (ret) { 805 drm_err(&dev_priv->drm, 806 "failed to inform pcode about cdclk change\n"); 807 return; 808 } 809 810 intel_de_rmw(dev_priv, LCPLL_CTL, 811 0, LCPLL_CD_SOURCE_FCLK); 812 813 /* 814 * According to the spec, it should be enough to poll for this 1 us. 815 * However, extensive testing shows that this can take longer. 816 */ 817 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) & 818 LCPLL_CD_SOURCE_FCLK_DONE, 100)) 819 drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); 820 821 intel_de_rmw(dev_priv, LCPLL_CTL, 822 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk)); 823 824 intel_de_rmw(dev_priv, LCPLL_CTL, 825 LCPLL_CD_SOURCE_FCLK, 0); 826 827 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) & 828 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 829 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n"); 830 831 snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ, 832 cdclk_config->voltage_level); 833 834 intel_de_write(dev_priv, CDCLK_FREQ, 835 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); 836 837 intel_update_cdclk(dev_priv); 838 } 839 840 static int skl_calc_cdclk(int min_cdclk, int vco) 841 { 842 if (vco == 8640000) { 843 if (min_cdclk > 540000) 844 return 617143; 845 else if (min_cdclk > 432000) 846 return 540000; 847 else if (min_cdclk > 308571) 848 return 432000; 849 else 850 return 308571; 851 } else { 852 if (min_cdclk > 540000) 853 return 675000; 854 else if (min_cdclk > 450000) 855 return 540000; 856 else if (min_cdclk > 337500) 857 return 450000; 858 else 859 return 337500; 860 } 861 } 862 863 static u8 skl_calc_voltage_level(int cdclk) 864 { 865 if (cdclk > 540000) 866 return 3; 867 else if (cdclk > 450000) 868 return 2; 869 else if (cdclk > 337500) 870 return 1; 871 else 872 return 0; 873 } 874 875 static void skl_dpll0_update(struct drm_i915_private *dev_priv, 876 struct intel_cdclk_config *cdclk_config) 877 { 878 u32 val; 879 880 cdclk_config->ref = 24000; 881 cdclk_config->vco = 0; 882 883 val = intel_de_read(dev_priv, LCPLL1_CTL); 884 if ((val & LCPLL_PLL_ENABLE) == 0) 885 return; 886 887 if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0)) 888 return; 889 890 val = intel_de_read(dev_priv, DPLL_CTRL1); 891 892 if (drm_WARN_ON(&dev_priv->drm, 893 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 894 DPLL_CTRL1_SSC(SKL_DPLL0) | 895 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != 896 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) 897 return; 898 899 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { 900 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): 901 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): 902 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): 903 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): 904 cdclk_config->vco = 8100000; 905 break; 906 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): 907 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): 908 cdclk_config->vco = 8640000; 909 break; 910 default: 911 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 912 break; 913 } 914 } 915 916 static void skl_get_cdclk(struct drm_i915_private *dev_priv, 917 struct intel_cdclk_config *cdclk_config) 918 { 919 u32 cdctl; 920 921 skl_dpll0_update(dev_priv, cdclk_config); 922 923 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; 924 925 if (cdclk_config->vco == 0) 926 goto out; 927 928 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 929 930 if (cdclk_config->vco == 8640000) { 931 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 932 case CDCLK_FREQ_450_432: 933 cdclk_config->cdclk = 432000; 934 break; 935 case CDCLK_FREQ_337_308: 936 cdclk_config->cdclk = 308571; 937 break; 938 case CDCLK_FREQ_540: 939 cdclk_config->cdclk = 540000; 940 break; 941 case CDCLK_FREQ_675_617: 942 cdclk_config->cdclk = 617143; 943 break; 944 default: 945 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 946 break; 947 } 948 } else { 949 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 950 case CDCLK_FREQ_450_432: 951 cdclk_config->cdclk = 450000; 952 break; 953 case CDCLK_FREQ_337_308: 954 cdclk_config->cdclk = 337500; 955 break; 956 case CDCLK_FREQ_540: 957 cdclk_config->cdclk = 540000; 958 break; 959 case CDCLK_FREQ_675_617: 960 cdclk_config->cdclk = 675000; 961 break; 962 default: 963 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 964 break; 965 } 966 } 967 968 out: 969 /* 970 * Can't read this out :( Let's assume it's 971 * at least what the CDCLK frequency requires. 972 */ 973 cdclk_config->voltage_level = 974 skl_calc_voltage_level(cdclk_config->cdclk); 975 } 976 977 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ 978 static int skl_cdclk_decimal(int cdclk) 979 { 980 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); 981 } 982 983 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, 984 int vco) 985 { 986 bool changed = dev_priv->skl_preferred_vco_freq != vco; 987 988 dev_priv->skl_preferred_vco_freq = vco; 989 990 if (changed) 991 intel_update_max_cdclk(dev_priv); 992 } 993 994 static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco) 995 { 996 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); 997 998 /* 999 * We always enable DPLL0 with the lowest link rate possible, but still 1000 * taking into account the VCO required to operate the eDP panel at the 1001 * desired frequency. The usual DP link rates operate with a VCO of 1002 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. 1003 * The modeset code is responsible for the selection of the exact link 1004 * rate later on, with the constraint of choosing a frequency that 1005 * works with vco. 1006 */ 1007 if (vco == 8640000) 1008 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0); 1009 else 1010 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0); 1011 } 1012 1013 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) 1014 { 1015 intel_de_rmw(dev_priv, DPLL_CTRL1, 1016 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 1017 DPLL_CTRL1_SSC(SKL_DPLL0) | 1018 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0), 1019 DPLL_CTRL1_OVERRIDE(SKL_DPLL0) | 1020 skl_dpll0_link_rate(dev_priv, vco)); 1021 intel_de_posting_read(dev_priv, DPLL_CTRL1); 1022 1023 intel_de_rmw(dev_priv, LCPLL1_CTL, 1024 0, LCPLL_PLL_ENABLE); 1025 1026 if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) 1027 drm_err(&dev_priv->drm, "DPLL0 not locked\n"); 1028 1029 dev_priv->display.cdclk.hw.vco = vco; 1030 1031 /* We'll want to keep using the current vco from now on. */ 1032 skl_set_preferred_cdclk_vco(dev_priv, vco); 1033 } 1034 1035 static void skl_dpll0_disable(struct drm_i915_private *dev_priv) 1036 { 1037 intel_de_rmw(dev_priv, LCPLL1_CTL, 1038 LCPLL_PLL_ENABLE, 0); 1039 1040 if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) 1041 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n"); 1042 1043 dev_priv->display.cdclk.hw.vco = 0; 1044 } 1045 1046 static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv, 1047 int cdclk, int vco) 1048 { 1049 switch (cdclk) { 1050 default: 1051 drm_WARN_ON(&dev_priv->drm, 1052 cdclk != dev_priv->display.cdclk.hw.bypass); 1053 drm_WARN_ON(&dev_priv->drm, vco != 0); 1054 fallthrough; 1055 case 308571: 1056 case 337500: 1057 return CDCLK_FREQ_337_308; 1058 case 450000: 1059 case 432000: 1060 return CDCLK_FREQ_450_432; 1061 case 540000: 1062 return CDCLK_FREQ_540; 1063 case 617143: 1064 case 675000: 1065 return CDCLK_FREQ_675_617; 1066 } 1067 } 1068 1069 static void skl_set_cdclk(struct drm_i915_private *dev_priv, 1070 const struct intel_cdclk_config *cdclk_config, 1071 enum pipe pipe) 1072 { 1073 int cdclk = cdclk_config->cdclk; 1074 int vco = cdclk_config->vco; 1075 u32 freq_select, cdclk_ctl; 1076 int ret; 1077 1078 /* 1079 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are 1080 * unsupported on SKL. In theory this should never happen since only 1081 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not 1082 * supported on SKL either, see the above WA. WARN whenever trying to 1083 * use the corresponding VCO freq as that always leads to using the 1084 * minimum 308MHz CDCLK. 1085 */ 1086 drm_WARN_ON_ONCE(&dev_priv->drm, 1087 IS_SKYLAKE(dev_priv) && vco == 8640000); 1088 1089 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 1090 SKL_CDCLK_PREPARE_FOR_CHANGE, 1091 SKL_CDCLK_READY_FOR_CHANGE, 1092 SKL_CDCLK_READY_FOR_CHANGE, 3); 1093 if (ret) { 1094 drm_err(&dev_priv->drm, 1095 "Failed to inform PCU about cdclk change (%d)\n", ret); 1096 return; 1097 } 1098 1099 freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco); 1100 1101 if (dev_priv->display.cdclk.hw.vco != 0 && 1102 dev_priv->display.cdclk.hw.vco != vco) 1103 skl_dpll0_disable(dev_priv); 1104 1105 cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL); 1106 1107 if (dev_priv->display.cdclk.hw.vco != vco) { 1108 /* Wa Display #1183: skl,kbl,cfl */ 1109 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1110 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1111 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1112 } 1113 1114 /* Wa Display #1183: skl,kbl,cfl */ 1115 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; 1116 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1117 intel_de_posting_read(dev_priv, CDCLK_CTL); 1118 1119 if (dev_priv->display.cdclk.hw.vco != vco) 1120 skl_dpll0_enable(dev_priv, vco); 1121 1122 /* Wa Display #1183: skl,kbl,cfl */ 1123 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1124 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1125 1126 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1127 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1128 1129 /* Wa Display #1183: skl,kbl,cfl */ 1130 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; 1131 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1132 intel_de_posting_read(dev_priv, CDCLK_CTL); 1133 1134 /* inform PCU of the change */ 1135 snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 1136 cdclk_config->voltage_level); 1137 1138 intel_update_cdclk(dev_priv); 1139 } 1140 1141 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) 1142 { 1143 u32 cdctl, expected; 1144 1145 /* 1146 * check if the pre-os initialized the display 1147 * There is SWF18 scratchpad register defined which is set by the 1148 * pre-os which can be used by the OS drivers to check the status 1149 */ 1150 if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) 1151 goto sanitize; 1152 1153 intel_update_cdclk(dev_priv); 1154 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); 1155 1156 /* Is PLL enabled and locked ? */ 1157 if (dev_priv->display.cdclk.hw.vco == 0 || 1158 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) 1159 goto sanitize; 1160 1161 /* DPLL okay; verify the cdclock 1162 * 1163 * Noticed in some instances that the freq selection is correct but 1164 * decimal part is programmed wrong from BIOS where pre-os does not 1165 * enable display. Verify the same as well. 1166 */ 1167 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 1168 expected = (cdctl & CDCLK_FREQ_SEL_MASK) | 1169 skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk); 1170 if (cdctl == expected) 1171 /* All well; nothing to sanitize */ 1172 return; 1173 1174 sanitize: 1175 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); 1176 1177 /* force cdclk programming */ 1178 dev_priv->display.cdclk.hw.cdclk = 0; 1179 /* force full PLL disable + enable */ 1180 dev_priv->display.cdclk.hw.vco = -1; 1181 } 1182 1183 static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv) 1184 { 1185 struct intel_cdclk_config cdclk_config; 1186 1187 skl_sanitize_cdclk(dev_priv); 1188 1189 if (dev_priv->display.cdclk.hw.cdclk != 0 && 1190 dev_priv->display.cdclk.hw.vco != 0) { 1191 /* 1192 * Use the current vco as our initial 1193 * guess as to what the preferred vco is. 1194 */ 1195 if (dev_priv->skl_preferred_vco_freq == 0) 1196 skl_set_preferred_cdclk_vco(dev_priv, 1197 dev_priv->display.cdclk.hw.vco); 1198 return; 1199 } 1200 1201 cdclk_config = dev_priv->display.cdclk.hw; 1202 1203 cdclk_config.vco = dev_priv->skl_preferred_vco_freq; 1204 if (cdclk_config.vco == 0) 1205 cdclk_config.vco = 8100000; 1206 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); 1207 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1208 1209 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1210 } 1211 1212 static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv) 1213 { 1214 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; 1215 1216 cdclk_config.cdclk = cdclk_config.bypass; 1217 cdclk_config.vco = 0; 1218 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1219 1220 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1221 } 1222 1223 struct intel_cdclk_vals { 1224 u32 cdclk; 1225 u16 refclk; 1226 u16 waveform; 1227 u8 divider; /* CD2X divider * 2 */ 1228 u8 ratio; 1229 }; 1230 1231 static const struct intel_cdclk_vals bxt_cdclk_table[] = { 1232 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 }, 1233 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 }, 1234 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 }, 1235 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 }, 1236 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 }, 1237 {} 1238 }; 1239 1240 static const struct intel_cdclk_vals glk_cdclk_table[] = { 1241 { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 }, 1242 { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 }, 1243 { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 }, 1244 {} 1245 }; 1246 1247 static const struct intel_cdclk_vals icl_cdclk_table[] = { 1248 { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 }, 1249 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 }, 1250 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 }, 1251 { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 }, 1252 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 }, 1253 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 }, 1254 1255 { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 }, 1256 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 }, 1257 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 }, 1258 { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 }, 1259 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 }, 1260 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 }, 1261 1262 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 }, 1263 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 }, 1264 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 }, 1265 { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 }, 1266 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 }, 1267 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 }, 1268 {} 1269 }; 1270 1271 static const struct intel_cdclk_vals rkl_cdclk_table[] = { 1272 { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 }, 1273 { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 }, 1274 { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 }, 1275 { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 }, 1276 { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 }, 1277 { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 }, 1278 1279 { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 }, 1280 { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 }, 1281 { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 }, 1282 { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 }, 1283 { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 }, 1284 { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 }, 1285 1286 { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 }, 1287 { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 }, 1288 { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 }, 1289 { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 }, 1290 { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 }, 1291 { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 }, 1292 {} 1293 }; 1294 1295 static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = { 1296 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 }, 1297 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 }, 1298 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 }, 1299 1300 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 }, 1301 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 }, 1302 { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 }, 1303 1304 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 }, 1305 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 }, 1306 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 }, 1307 {} 1308 }; 1309 1310 static const struct intel_cdclk_vals adlp_cdclk_table[] = { 1311 { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 }, 1312 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 }, 1313 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 }, 1314 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 }, 1315 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 }, 1316 1317 { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 }, 1318 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 }, 1319 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 }, 1320 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 }, 1321 { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 }, 1322 1323 { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 }, 1324 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 }, 1325 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 }, 1326 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 }, 1327 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 }, 1328 {} 1329 }; 1330 1331 static const struct intel_cdclk_vals dg2_cdclk_table[] = { 1332 { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 }, 1333 { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 }, 1334 { .refclk = 38400, .cdclk = 244800, .divider = 2, .ratio = 34, .waveform = 0xa4a4 }, 1335 { .refclk = 38400, .cdclk = 285600, .divider = 2, .ratio = 34, .waveform = 0xa54a }, 1336 { .refclk = 38400, .cdclk = 326400, .divider = 2, .ratio = 34, .waveform = 0xaaaa }, 1337 { .refclk = 38400, .cdclk = 367200, .divider = 2, .ratio = 34, .waveform = 0xad5a }, 1338 { .refclk = 38400, .cdclk = 408000, .divider = 2, .ratio = 34, .waveform = 0xb6b6 }, 1339 { .refclk = 38400, .cdclk = 448800, .divider = 2, .ratio = 34, .waveform = 0xdbb6 }, 1340 { .refclk = 38400, .cdclk = 489600, .divider = 2, .ratio = 34, .waveform = 0xeeee }, 1341 { .refclk = 38400, .cdclk = 530400, .divider = 2, .ratio = 34, .waveform = 0xf7de }, 1342 { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe }, 1343 { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe }, 1344 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff }, 1345 {} 1346 }; 1347 1348 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) 1349 { 1350 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; 1351 int i; 1352 1353 for (i = 0; table[i].refclk; i++) 1354 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && 1355 table[i].cdclk >= min_cdclk) 1356 return table[i].cdclk; 1357 1358 drm_WARN(&dev_priv->drm, 1, 1359 "Cannot satisfy minimum cdclk %d with refclk %u\n", 1360 min_cdclk, dev_priv->display.cdclk.hw.ref); 1361 return 0; 1362 } 1363 1364 static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) 1365 { 1366 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; 1367 int i; 1368 1369 if (cdclk == dev_priv->display.cdclk.hw.bypass) 1370 return 0; 1371 1372 for (i = 0; table[i].refclk; i++) 1373 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && 1374 table[i].cdclk == cdclk) 1375 return dev_priv->display.cdclk.hw.ref * table[i].ratio; 1376 1377 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", 1378 cdclk, dev_priv->display.cdclk.hw.ref); 1379 return 0; 1380 } 1381 1382 static u8 bxt_calc_voltage_level(int cdclk) 1383 { 1384 return DIV_ROUND_UP(cdclk, 25000); 1385 } 1386 1387 static u8 icl_calc_voltage_level(int cdclk) 1388 { 1389 if (cdclk > 556800) 1390 return 2; 1391 else if (cdclk > 312000) 1392 return 1; 1393 else 1394 return 0; 1395 } 1396 1397 static u8 ehl_calc_voltage_level(int cdclk) 1398 { 1399 if (cdclk > 326400) 1400 return 3; 1401 else if (cdclk > 312000) 1402 return 2; 1403 else if (cdclk > 180000) 1404 return 1; 1405 else 1406 return 0; 1407 } 1408 1409 static u8 tgl_calc_voltage_level(int cdclk) 1410 { 1411 if (cdclk > 556800) 1412 return 3; 1413 else if (cdclk > 326400) 1414 return 2; 1415 else if (cdclk > 312000) 1416 return 1; 1417 else 1418 return 0; 1419 } 1420 1421 static void icl_readout_refclk(struct drm_i915_private *dev_priv, 1422 struct intel_cdclk_config *cdclk_config) 1423 { 1424 u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; 1425 1426 switch (dssm) { 1427 default: 1428 MISSING_CASE(dssm); 1429 fallthrough; 1430 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz: 1431 cdclk_config->ref = 24000; 1432 break; 1433 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz: 1434 cdclk_config->ref = 19200; 1435 break; 1436 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz: 1437 cdclk_config->ref = 38400; 1438 break; 1439 } 1440 } 1441 1442 static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, 1443 struct intel_cdclk_config *cdclk_config) 1444 { 1445 u32 val, ratio; 1446 1447 if (IS_DG2(dev_priv)) 1448 cdclk_config->ref = 38400; 1449 else if (DISPLAY_VER(dev_priv) >= 11) 1450 icl_readout_refclk(dev_priv, cdclk_config); 1451 else 1452 cdclk_config->ref = 19200; 1453 1454 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE); 1455 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || 1456 (val & BXT_DE_PLL_LOCK) == 0) { 1457 /* 1458 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but 1459 * setting it to zero is a way to signal that. 1460 */ 1461 cdclk_config->vco = 0; 1462 return; 1463 } 1464 1465 /* 1466 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register, 1467 * gen9lp had it in a separate PLL control register. 1468 */ 1469 if (DISPLAY_VER(dev_priv) >= 11) 1470 ratio = val & ICL_CDCLK_PLL_RATIO_MASK; 1471 else 1472 ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; 1473 1474 cdclk_config->vco = ratio * cdclk_config->ref; 1475 } 1476 1477 static void bxt_get_cdclk(struct drm_i915_private *dev_priv, 1478 struct intel_cdclk_config *cdclk_config) 1479 { 1480 u32 squash_ctl = 0; 1481 u32 divider; 1482 int div; 1483 1484 bxt_de_pll_readout(dev_priv, cdclk_config); 1485 1486 if (DISPLAY_VER(dev_priv) >= 12) 1487 cdclk_config->bypass = cdclk_config->ref / 2; 1488 else if (DISPLAY_VER(dev_priv) >= 11) 1489 cdclk_config->bypass = 50000; 1490 else 1491 cdclk_config->bypass = cdclk_config->ref; 1492 1493 if (cdclk_config->vco == 0) { 1494 cdclk_config->cdclk = cdclk_config->bypass; 1495 goto out; 1496 } 1497 1498 divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; 1499 1500 switch (divider) { 1501 case BXT_CDCLK_CD2X_DIV_SEL_1: 1502 div = 2; 1503 break; 1504 case BXT_CDCLK_CD2X_DIV_SEL_1_5: 1505 div = 3; 1506 break; 1507 case BXT_CDCLK_CD2X_DIV_SEL_2: 1508 div = 4; 1509 break; 1510 case BXT_CDCLK_CD2X_DIV_SEL_4: 1511 div = 8; 1512 break; 1513 default: 1514 MISSING_CASE(divider); 1515 return; 1516 } 1517 1518 if (HAS_CDCLK_SQUASH(dev_priv)) 1519 squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL); 1520 1521 if (squash_ctl & CDCLK_SQUASH_ENABLE) { 1522 u16 waveform; 1523 int size; 1524 1525 size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1; 1526 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size); 1527 1528 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * 1529 cdclk_config->vco, size * div); 1530 } else { 1531 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); 1532 } 1533 1534 out: 1535 /* 1536 * Can't read this out :( Let's assume it's 1537 * at least what the CDCLK frequency requires. 1538 */ 1539 cdclk_config->voltage_level = 1540 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk); 1541 } 1542 1543 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) 1544 { 1545 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0); 1546 1547 /* Timeout 200us */ 1548 if (intel_de_wait_for_clear(dev_priv, 1549 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1550 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n"); 1551 1552 dev_priv->display.cdclk.hw.vco = 0; 1553 } 1554 1555 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) 1556 { 1557 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); 1558 1559 intel_de_rmw(dev_priv, BXT_DE_PLL_CTL, 1560 BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio)); 1561 1562 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); 1563 1564 /* Timeout 200us */ 1565 if (intel_de_wait_for_set(dev_priv, 1566 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1567 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n"); 1568 1569 dev_priv->display.cdclk.hw.vco = vco; 1570 } 1571 1572 static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv) 1573 { 1574 intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE, 1575 BXT_DE_PLL_PLL_ENABLE, 0); 1576 1577 /* Timeout 200us */ 1578 if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1579 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n"); 1580 1581 dev_priv->display.cdclk.hw.vco = 0; 1582 } 1583 1584 static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) 1585 { 1586 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); 1587 u32 val; 1588 1589 val = ICL_CDCLK_PLL_RATIO(ratio); 1590 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1591 1592 val |= BXT_DE_PLL_PLL_ENABLE; 1593 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1594 1595 /* Timeout 200us */ 1596 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1597 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n"); 1598 1599 dev_priv->display.cdclk.hw.vco = vco; 1600 } 1601 1602 static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco) 1603 { 1604 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); 1605 u32 val; 1606 1607 /* Write PLL ratio without disabling */ 1608 val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE; 1609 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1610 1611 /* Submit freq change request */ 1612 val |= BXT_DE_PLL_FREQ_REQ; 1613 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1614 1615 /* Timeout 200us */ 1616 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, 1617 BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1)) 1618 drm_err(&dev_priv->drm, "timeout waiting for FREQ change request ack\n"); 1619 1620 val &= ~BXT_DE_PLL_FREQ_REQ; 1621 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1622 1623 dev_priv->display.cdclk.hw.vco = vco; 1624 } 1625 1626 static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 1627 { 1628 if (DISPLAY_VER(dev_priv) >= 12) { 1629 if (pipe == INVALID_PIPE) 1630 return TGL_CDCLK_CD2X_PIPE_NONE; 1631 else 1632 return TGL_CDCLK_CD2X_PIPE(pipe); 1633 } else if (DISPLAY_VER(dev_priv) >= 11) { 1634 if (pipe == INVALID_PIPE) 1635 return ICL_CDCLK_CD2X_PIPE_NONE; 1636 else 1637 return ICL_CDCLK_CD2X_PIPE(pipe); 1638 } else { 1639 if (pipe == INVALID_PIPE) 1640 return BXT_CDCLK_CD2X_PIPE_NONE; 1641 else 1642 return BXT_CDCLK_CD2X_PIPE(pipe); 1643 } 1644 } 1645 1646 static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv, 1647 int cdclk, int vco) 1648 { 1649 /* cdclk = vco / 2 / div{1,1.5,2,4} */ 1650 switch (DIV_ROUND_CLOSEST(vco, cdclk)) { 1651 default: 1652 drm_WARN_ON(&dev_priv->drm, 1653 cdclk != dev_priv->display.cdclk.hw.bypass); 1654 drm_WARN_ON(&dev_priv->drm, vco != 0); 1655 fallthrough; 1656 case 2: 1657 return BXT_CDCLK_CD2X_DIV_SEL_1; 1658 case 3: 1659 return BXT_CDCLK_CD2X_DIV_SEL_1_5; 1660 case 4: 1661 return BXT_CDCLK_CD2X_DIV_SEL_2; 1662 case 8: 1663 return BXT_CDCLK_CD2X_DIV_SEL_4; 1664 } 1665 } 1666 1667 static u32 cdclk_squash_waveform(struct drm_i915_private *dev_priv, 1668 int cdclk) 1669 { 1670 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; 1671 int i; 1672 1673 if (cdclk == dev_priv->display.cdclk.hw.bypass) 1674 return 0; 1675 1676 for (i = 0; table[i].refclk; i++) 1677 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && 1678 table[i].cdclk == cdclk) 1679 return table[i].waveform; 1680 1681 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", 1682 cdclk, dev_priv->display.cdclk.hw.ref); 1683 1684 return 0xffff; 1685 } 1686 1687 static void icl_cdclk_pll_update(struct drm_i915_private *i915, int vco) 1688 { 1689 if (i915->display.cdclk.hw.vco != 0 && 1690 i915->display.cdclk.hw.vco != vco) 1691 icl_cdclk_pll_disable(i915); 1692 1693 if (i915->display.cdclk.hw.vco != vco) 1694 icl_cdclk_pll_enable(i915, vco); 1695 } 1696 1697 static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco) 1698 { 1699 if (i915->display.cdclk.hw.vco != 0 && 1700 i915->display.cdclk.hw.vco != vco) 1701 bxt_de_pll_disable(i915); 1702 1703 if (i915->display.cdclk.hw.vco != vco) 1704 bxt_de_pll_enable(i915, vco); 1705 } 1706 1707 static void dg2_cdclk_squash_program(struct drm_i915_private *i915, 1708 u16 waveform) 1709 { 1710 u32 squash_ctl = 0; 1711 1712 if (waveform) 1713 squash_ctl = CDCLK_SQUASH_ENABLE | 1714 CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; 1715 1716 intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl); 1717 } 1718 1719 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 1720 const struct intel_cdclk_config *cdclk_config, 1721 enum pipe pipe) 1722 { 1723 int cdclk = cdclk_config->cdclk; 1724 int vco = cdclk_config->vco; 1725 u32 val; 1726 u16 waveform; 1727 int clock; 1728 int ret; 1729 1730 /* Inform power controller of upcoming frequency change. */ 1731 if (DISPLAY_VER(dev_priv) >= 11) 1732 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 1733 SKL_CDCLK_PREPARE_FOR_CHANGE, 1734 SKL_CDCLK_READY_FOR_CHANGE, 1735 SKL_CDCLK_READY_FOR_CHANGE, 3); 1736 else 1737 /* 1738 * BSpec requires us to wait up to 150usec, but that leads to 1739 * timeouts; the 2ms used here is based on experiment. 1740 */ 1741 ret = snb_pcode_write_timeout(&dev_priv->uncore, 1742 HSW_PCODE_DE_WRITE_FREQ_REQ, 1743 0x80000000, 150, 2); 1744 if (ret) { 1745 drm_err(&dev_priv->drm, 1746 "Failed to inform PCU about cdclk change (err %d, freq %d)\n", 1747 ret, cdclk); 1748 return; 1749 } 1750 1751 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0) { 1752 if (dev_priv->display.cdclk.hw.vco != vco) 1753 adlp_cdclk_pll_crawl(dev_priv, vco); 1754 } else if (DISPLAY_VER(dev_priv) >= 11) 1755 icl_cdclk_pll_update(dev_priv, vco); 1756 else 1757 bxt_cdclk_pll_update(dev_priv, vco); 1758 1759 waveform = cdclk_squash_waveform(dev_priv, cdclk); 1760 1761 if (waveform) 1762 clock = vco / 2; 1763 else 1764 clock = cdclk; 1765 1766 if (HAS_CDCLK_SQUASH(dev_priv)) 1767 dg2_cdclk_squash_program(dev_priv, waveform); 1768 1769 val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) | 1770 bxt_cdclk_cd2x_pipe(dev_priv, pipe) | 1771 skl_cdclk_decimal(cdclk); 1772 1773 /* 1774 * Disable SSA Precharge when CD clock frequency < 500 MHz, 1775 * enable otherwise. 1776 */ 1777 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1778 cdclk >= 500000) 1779 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 1780 intel_de_write(dev_priv, CDCLK_CTL, val); 1781 1782 if (pipe != INVALID_PIPE) 1783 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe)); 1784 1785 if (DISPLAY_VER(dev_priv) >= 11) { 1786 ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 1787 cdclk_config->voltage_level); 1788 } else { 1789 /* 1790 * The timeout isn't specified, the 2ms used here is based on 1791 * experiment. 1792 * FIXME: Waiting for the request completion could be delayed 1793 * until the next PCODE request based on BSpec. 1794 */ 1795 ret = snb_pcode_write_timeout(&dev_priv->uncore, 1796 HSW_PCODE_DE_WRITE_FREQ_REQ, 1797 cdclk_config->voltage_level, 1798 150, 2); 1799 } 1800 1801 if (ret) { 1802 drm_err(&dev_priv->drm, 1803 "PCode CDCLK freq set failed, (err %d, freq %d)\n", 1804 ret, cdclk); 1805 return; 1806 } 1807 1808 intel_update_cdclk(dev_priv); 1809 1810 if (DISPLAY_VER(dev_priv) >= 11) 1811 /* 1812 * Can't read out the voltage level :( 1813 * Let's just assume everything is as expected. 1814 */ 1815 dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level; 1816 } 1817 1818 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) 1819 { 1820 u32 cdctl, expected; 1821 int cdclk, clock, vco; 1822 1823 intel_update_cdclk(dev_priv); 1824 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); 1825 1826 if (dev_priv->display.cdclk.hw.vco == 0 || 1827 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) 1828 goto sanitize; 1829 1830 /* DPLL okay; verify the cdclock 1831 * 1832 * Some BIOS versions leave an incorrect decimal frequency value and 1833 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, 1834 * so sanitize this register. 1835 */ 1836 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 1837 /* 1838 * Let's ignore the pipe field, since BIOS could have configured the 1839 * dividers both synching to an active pipe, or asynchronously 1840 * (PIPE_NONE). 1841 */ 1842 cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); 1843 1844 /* Make sure this is a legal cdclk value for the platform */ 1845 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk); 1846 if (cdclk != dev_priv->display.cdclk.hw.cdclk) 1847 goto sanitize; 1848 1849 /* Make sure the VCO is correct for the cdclk */ 1850 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 1851 if (vco != dev_priv->display.cdclk.hw.vco) 1852 goto sanitize; 1853 1854 expected = skl_cdclk_decimal(cdclk); 1855 1856 /* Figure out what CD2X divider we should be using for this cdclk */ 1857 if (HAS_CDCLK_SQUASH(dev_priv)) 1858 clock = dev_priv->display.cdclk.hw.vco / 2; 1859 else 1860 clock = dev_priv->display.cdclk.hw.cdclk; 1861 1862 expected |= bxt_cdclk_cd2x_div_sel(dev_priv, clock, 1863 dev_priv->display.cdclk.hw.vco); 1864 1865 /* 1866 * Disable SSA Precharge when CD clock frequency < 500 MHz, 1867 * enable otherwise. 1868 */ 1869 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1870 dev_priv->display.cdclk.hw.cdclk >= 500000) 1871 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 1872 1873 if (cdctl == expected) 1874 /* All well; nothing to sanitize */ 1875 return; 1876 1877 sanitize: 1878 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); 1879 1880 /* force cdclk programming */ 1881 dev_priv->display.cdclk.hw.cdclk = 0; 1882 1883 /* force full PLL disable + enable */ 1884 dev_priv->display.cdclk.hw.vco = -1; 1885 } 1886 1887 static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv) 1888 { 1889 struct intel_cdclk_config cdclk_config; 1890 1891 bxt_sanitize_cdclk(dev_priv); 1892 1893 if (dev_priv->display.cdclk.hw.cdclk != 0 && 1894 dev_priv->display.cdclk.hw.vco != 0) 1895 return; 1896 1897 cdclk_config = dev_priv->display.cdclk.hw; 1898 1899 /* 1900 * FIXME: 1901 * - The initial CDCLK needs to be read from VBT. 1902 * Need to make this change after VBT has changes for BXT. 1903 */ 1904 cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0); 1905 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); 1906 cdclk_config.voltage_level = 1907 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); 1908 1909 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1910 } 1911 1912 static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv) 1913 { 1914 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; 1915 1916 cdclk_config.cdclk = cdclk_config.bypass; 1917 cdclk_config.vco = 0; 1918 cdclk_config.voltage_level = 1919 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); 1920 1921 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1922 } 1923 1924 /** 1925 * intel_cdclk_init_hw - Initialize CDCLK hardware 1926 * @i915: i915 device 1927 * 1928 * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and 1929 * sanitizing the state of the hardware if needed. This is generally done only 1930 * during the display core initialization sequence, after which the DMC will 1931 * take care of turning CDCLK off/on as needed. 1932 */ 1933 void intel_cdclk_init_hw(struct drm_i915_private *i915) 1934 { 1935 if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915)) 1936 bxt_cdclk_init_hw(i915); 1937 else if (DISPLAY_VER(i915) == 9) 1938 skl_cdclk_init_hw(i915); 1939 } 1940 1941 /** 1942 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware 1943 * @i915: i915 device 1944 * 1945 * Uninitialize CDCLK. This is done only during the display core 1946 * uninitialization sequence. 1947 */ 1948 void intel_cdclk_uninit_hw(struct drm_i915_private *i915) 1949 { 1950 if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915)) 1951 bxt_cdclk_uninit_hw(i915); 1952 else if (DISPLAY_VER(i915) == 9) 1953 skl_cdclk_uninit_hw(i915); 1954 } 1955 1956 static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, 1957 const struct intel_cdclk_config *a, 1958 const struct intel_cdclk_config *b) 1959 { 1960 int a_div, b_div; 1961 1962 if (!HAS_CDCLK_CRAWL(dev_priv)) 1963 return false; 1964 1965 /* 1966 * The vco and cd2x divider will change independently 1967 * from each, so we disallow cd2x change when crawling. 1968 */ 1969 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); 1970 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); 1971 1972 return a->vco != 0 && b->vco != 0 && 1973 a->vco != b->vco && 1974 a_div == b_div && 1975 a->ref == b->ref; 1976 } 1977 1978 static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, 1979 const struct intel_cdclk_config *a, 1980 const struct intel_cdclk_config *b) 1981 { 1982 /* 1983 * FIXME should store a bit more state in intel_cdclk_config 1984 * to differentiate squasher vs. cd2x divider properly. For 1985 * the moment all platforms with squasher use a fixed cd2x 1986 * divider. 1987 */ 1988 if (!HAS_CDCLK_SQUASH(dev_priv)) 1989 return false; 1990 1991 return a->cdclk != b->cdclk && 1992 a->vco != 0 && 1993 a->vco == b->vco && 1994 a->ref == b->ref; 1995 } 1996 1997 /** 1998 * intel_cdclk_needs_modeset - Determine if changong between the CDCLK 1999 * configurations requires a modeset on all pipes 2000 * @a: first CDCLK configuration 2001 * @b: second CDCLK configuration 2002 * 2003 * Returns: 2004 * True if changing between the two CDCLK configurations 2005 * requires all pipes to be off, false if not. 2006 */ 2007 bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a, 2008 const struct intel_cdclk_config *b) 2009 { 2010 return a->cdclk != b->cdclk || 2011 a->vco != b->vco || 2012 a->ref != b->ref; 2013 } 2014 2015 /** 2016 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK 2017 * configurations requires only a cd2x divider update 2018 * @dev_priv: i915 device 2019 * @a: first CDCLK configuration 2020 * @b: second CDCLK configuration 2021 * 2022 * Returns: 2023 * True if changing between the two CDCLK configurations 2024 * can be done with just a cd2x divider update, false if not. 2025 */ 2026 static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, 2027 const struct intel_cdclk_config *a, 2028 const struct intel_cdclk_config *b) 2029 { 2030 /* Older hw doesn't have the capability */ 2031 if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv)) 2032 return false; 2033 2034 /* 2035 * FIXME should store a bit more state in intel_cdclk_config 2036 * to differentiate squasher vs. cd2x divider properly. For 2037 * the moment all platforms with squasher use a fixed cd2x 2038 * divider. 2039 */ 2040 if (HAS_CDCLK_SQUASH(dev_priv)) 2041 return false; 2042 2043 return a->cdclk != b->cdclk && 2044 a->vco != 0 && 2045 a->vco == b->vco && 2046 a->ref == b->ref; 2047 } 2048 2049 /** 2050 * intel_cdclk_changed - Determine if two CDCLK configurations are different 2051 * @a: first CDCLK configuration 2052 * @b: second CDCLK configuration 2053 * 2054 * Returns: 2055 * True if the CDCLK configurations don't match, false if they do. 2056 */ 2057 static bool intel_cdclk_changed(const struct intel_cdclk_config *a, 2058 const struct intel_cdclk_config *b) 2059 { 2060 return intel_cdclk_needs_modeset(a, b) || 2061 a->voltage_level != b->voltage_level; 2062 } 2063 2064 void intel_cdclk_dump_config(struct drm_i915_private *i915, 2065 const struct intel_cdclk_config *cdclk_config, 2066 const char *context) 2067 { 2068 drm_dbg_kms(&i915->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", 2069 context, cdclk_config->cdclk, cdclk_config->vco, 2070 cdclk_config->ref, cdclk_config->bypass, 2071 cdclk_config->voltage_level); 2072 } 2073 2074 /** 2075 * intel_set_cdclk - Push the CDCLK configuration to the hardware 2076 * @dev_priv: i915 device 2077 * @cdclk_config: new CDCLK configuration 2078 * @pipe: pipe with which to synchronize the update 2079 * 2080 * Program the hardware based on the passed in CDCLK state, 2081 * if necessary. 2082 */ 2083 static void intel_set_cdclk(struct drm_i915_private *dev_priv, 2084 const struct intel_cdclk_config *cdclk_config, 2085 enum pipe pipe) 2086 { 2087 struct intel_encoder *encoder; 2088 2089 if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config)) 2090 return; 2091 2092 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk)) 2093 return; 2094 2095 intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to"); 2096 2097 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2098 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2099 2100 intel_psr_pause(intel_dp); 2101 } 2102 2103 intel_audio_cdclk_change_pre(dev_priv); 2104 2105 /* 2106 * Lock aux/gmbus while we change cdclk in case those 2107 * functions use cdclk. Not all platforms/ports do, 2108 * but we'll lock them all for simplicity. 2109 */ 2110 mutex_lock(&dev_priv->display.gmbus.mutex); 2111 for_each_intel_dp(&dev_priv->drm, encoder) { 2112 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2113 2114 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, 2115 &dev_priv->display.gmbus.mutex); 2116 } 2117 2118 intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe); 2119 2120 for_each_intel_dp(&dev_priv->drm, encoder) { 2121 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2122 2123 mutex_unlock(&intel_dp->aux.hw_mutex); 2124 } 2125 mutex_unlock(&dev_priv->display.gmbus.mutex); 2126 2127 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2128 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2129 2130 intel_psr_resume(intel_dp); 2131 } 2132 2133 intel_audio_cdclk_change_post(dev_priv); 2134 2135 if (drm_WARN(&dev_priv->drm, 2136 intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config), 2137 "cdclk state doesn't match!\n")) { 2138 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]"); 2139 intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]"); 2140 } 2141 } 2142 2143 /** 2144 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware 2145 * @state: intel atomic state 2146 * 2147 * Program the hardware before updating the HW plane state based on the 2148 * new CDCLK state, if necessary. 2149 */ 2150 void 2151 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) 2152 { 2153 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2154 const struct intel_cdclk_state *old_cdclk_state = 2155 intel_atomic_get_old_cdclk_state(state); 2156 const struct intel_cdclk_state *new_cdclk_state = 2157 intel_atomic_get_new_cdclk_state(state); 2158 enum pipe pipe = new_cdclk_state->pipe; 2159 2160 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2161 &new_cdclk_state->actual)) 2162 return; 2163 2164 if (pipe == INVALID_PIPE || 2165 old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) { 2166 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); 2167 2168 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); 2169 } 2170 } 2171 2172 /** 2173 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware 2174 * @state: intel atomic state 2175 * 2176 * Program the hardware after updating the HW plane state based on the 2177 * new CDCLK state, if necessary. 2178 */ 2179 void 2180 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) 2181 { 2182 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2183 const struct intel_cdclk_state *old_cdclk_state = 2184 intel_atomic_get_old_cdclk_state(state); 2185 const struct intel_cdclk_state *new_cdclk_state = 2186 intel_atomic_get_new_cdclk_state(state); 2187 enum pipe pipe = new_cdclk_state->pipe; 2188 2189 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2190 &new_cdclk_state->actual)) 2191 return; 2192 2193 if (pipe != INVALID_PIPE && 2194 old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) { 2195 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); 2196 2197 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); 2198 } 2199 } 2200 2201 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) 2202 { 2203 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2204 int pixel_rate = crtc_state->pixel_rate; 2205 2206 if (DISPLAY_VER(dev_priv) >= 10) 2207 return DIV_ROUND_UP(pixel_rate, 2); 2208 else if (DISPLAY_VER(dev_priv) == 9 || 2209 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2210 return pixel_rate; 2211 else if (IS_CHERRYVIEW(dev_priv)) 2212 return DIV_ROUND_UP(pixel_rate * 100, 95); 2213 else if (crtc_state->double_wide) 2214 return DIV_ROUND_UP(pixel_rate * 100, 90 * 2); 2215 else 2216 return DIV_ROUND_UP(pixel_rate * 100, 90); 2217 } 2218 2219 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) 2220 { 2221 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2222 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2223 struct intel_plane *plane; 2224 int min_cdclk = 0; 2225 2226 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 2227 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk); 2228 2229 return min_cdclk; 2230 } 2231 2232 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) 2233 { 2234 struct drm_i915_private *dev_priv = 2235 to_i915(crtc_state->uapi.crtc->dev); 2236 int min_cdclk; 2237 2238 if (!crtc_state->hw.enable) 2239 return 0; 2240 2241 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state); 2242 2243 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ 2244 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state)) 2245 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95); 2246 2247 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, 2248 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else 2249 * there may be audio corruption or screen corruption." This cdclk 2250 * restriction for GLK is 316.8 MHz. 2251 */ 2252 if (intel_crtc_has_dp_encoder(crtc_state) && 2253 crtc_state->has_audio && 2254 crtc_state->port_clock >= 540000 && 2255 crtc_state->lane_count == 4) { 2256 if (DISPLAY_VER(dev_priv) == 10) { 2257 /* Display WA #1145: glk */ 2258 min_cdclk = max(316800, min_cdclk); 2259 } else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) { 2260 /* Display WA #1144: skl,bxt */ 2261 min_cdclk = max(432000, min_cdclk); 2262 } 2263 } 2264 2265 /* 2266 * According to BSpec, "The CD clock frequency must be at least twice 2267 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. 2268 */ 2269 if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9) 2270 min_cdclk = max(2 * 96000, min_cdclk); 2271 2272 /* 2273 * "For DP audio configuration, cdclk frequency shall be set to 2274 * meet the following requirements: 2275 * DP Link Frequency(MHz) | Cdclk frequency(MHz) 2276 * 270 | 320 or higher 2277 * 162 | 200 or higher" 2278 */ 2279 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2280 intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio) 2281 min_cdclk = max(crtc_state->port_clock, min_cdclk); 2282 2283 /* 2284 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower 2285 * than 320000KHz. 2286 */ 2287 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 2288 IS_VALLEYVIEW(dev_priv)) 2289 min_cdclk = max(320000, min_cdclk); 2290 2291 /* 2292 * On Geminilake once the CDCLK gets as low as 79200 2293 * picture gets unstable, despite that values are 2294 * correct for DSI PLL and DE PLL. 2295 */ 2296 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 2297 IS_GEMINILAKE(dev_priv)) 2298 min_cdclk = max(158400, min_cdclk); 2299 2300 /* Account for additional needs from the planes */ 2301 min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); 2302 2303 /* 2304 * When we decide to use only one VDSC engine, since 2305 * each VDSC operates with 1 ppc throughput, pixel clock 2306 * cannot be higher than the VDSC clock (cdclk) 2307 */ 2308 if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split) 2309 min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); 2310 2311 /* 2312 * HACK. Currently for TGL/DG2 platforms we calculate 2313 * min_cdclk initially based on pixel_rate divided 2314 * by 2, accounting for also plane requirements, 2315 * however in some cases the lowest possible CDCLK 2316 * doesn't work and causing the underruns. 2317 * Explicitly stating here that this seems to be currently 2318 * rather a Hack, than final solution. 2319 */ 2320 if (IS_TIGERLAKE(dev_priv) || IS_DG2(dev_priv)) { 2321 /* 2322 * Clamp to max_cdclk_freq in case pixel rate is higher, 2323 * in order not to break an 8K, but still leave W/A at place. 2324 */ 2325 min_cdclk = max_t(int, min_cdclk, 2326 min_t(int, crtc_state->pixel_rate, 2327 dev_priv->display.cdclk.max_cdclk_freq)); 2328 } 2329 2330 return min_cdclk; 2331 } 2332 2333 static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) 2334 { 2335 struct intel_atomic_state *state = cdclk_state->base.state; 2336 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2337 const struct intel_bw_state *bw_state; 2338 struct intel_crtc *crtc; 2339 struct intel_crtc_state *crtc_state; 2340 int min_cdclk, i; 2341 enum pipe pipe; 2342 2343 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2344 int ret; 2345 2346 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 2347 if (min_cdclk < 0) 2348 return min_cdclk; 2349 2350 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk) 2351 continue; 2352 2353 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 2354 2355 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2356 if (ret) 2357 return ret; 2358 } 2359 2360 bw_state = intel_atomic_get_new_bw_state(state); 2361 if (bw_state) { 2362 min_cdclk = intel_bw_min_cdclk(dev_priv, bw_state); 2363 2364 if (cdclk_state->bw_min_cdclk != min_cdclk) { 2365 int ret; 2366 2367 cdclk_state->bw_min_cdclk = min_cdclk; 2368 2369 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2370 if (ret) 2371 return ret; 2372 } 2373 } 2374 2375 min_cdclk = max(cdclk_state->force_min_cdclk, 2376 cdclk_state->bw_min_cdclk); 2377 for_each_pipe(dev_priv, pipe) 2378 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); 2379 2380 if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) { 2381 drm_dbg_kms(&dev_priv->drm, 2382 "required cdclk (%d kHz) exceeds max (%d kHz)\n", 2383 min_cdclk, dev_priv->display.cdclk.max_cdclk_freq); 2384 return -EINVAL; 2385 } 2386 2387 return min_cdclk; 2388 } 2389 2390 /* 2391 * Account for port clock min voltage level requirements. 2392 * This only really does something on DISPLA_VER >= 11 but can be 2393 * called on earlier platforms as well. 2394 * 2395 * Note that this functions assumes that 0 is 2396 * the lowest voltage value, and higher values 2397 * correspond to increasingly higher voltages. 2398 * 2399 * Should that relationship no longer hold on 2400 * future platforms this code will need to be 2401 * adjusted. 2402 */ 2403 static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state) 2404 { 2405 struct intel_atomic_state *state = cdclk_state->base.state; 2406 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2407 struct intel_crtc *crtc; 2408 struct intel_crtc_state *crtc_state; 2409 u8 min_voltage_level; 2410 int i; 2411 enum pipe pipe; 2412 2413 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2414 int ret; 2415 2416 if (crtc_state->hw.enable) 2417 min_voltage_level = crtc_state->min_voltage_level; 2418 else 2419 min_voltage_level = 0; 2420 2421 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level) 2422 continue; 2423 2424 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level; 2425 2426 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2427 if (ret) 2428 return ret; 2429 } 2430 2431 min_voltage_level = 0; 2432 for_each_pipe(dev_priv, pipe) 2433 min_voltage_level = max(cdclk_state->min_voltage_level[pipe], 2434 min_voltage_level); 2435 2436 return min_voltage_level; 2437 } 2438 2439 static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2440 { 2441 struct intel_atomic_state *state = cdclk_state->base.state; 2442 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2443 int min_cdclk, cdclk; 2444 2445 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2446 if (min_cdclk < 0) 2447 return min_cdclk; 2448 2449 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); 2450 2451 cdclk_state->logical.cdclk = cdclk; 2452 cdclk_state->logical.voltage_level = 2453 vlv_calc_voltage_level(dev_priv, cdclk); 2454 2455 if (!cdclk_state->active_pipes) { 2456 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); 2457 2458 cdclk_state->actual.cdclk = cdclk; 2459 cdclk_state->actual.voltage_level = 2460 vlv_calc_voltage_level(dev_priv, cdclk); 2461 } else { 2462 cdclk_state->actual = cdclk_state->logical; 2463 } 2464 2465 return 0; 2466 } 2467 2468 static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2469 { 2470 int min_cdclk, cdclk; 2471 2472 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2473 if (min_cdclk < 0) 2474 return min_cdclk; 2475 2476 cdclk = bdw_calc_cdclk(min_cdclk); 2477 2478 cdclk_state->logical.cdclk = cdclk; 2479 cdclk_state->logical.voltage_level = 2480 bdw_calc_voltage_level(cdclk); 2481 2482 if (!cdclk_state->active_pipes) { 2483 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); 2484 2485 cdclk_state->actual.cdclk = cdclk; 2486 cdclk_state->actual.voltage_level = 2487 bdw_calc_voltage_level(cdclk); 2488 } else { 2489 cdclk_state->actual = cdclk_state->logical; 2490 } 2491 2492 return 0; 2493 } 2494 2495 static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state) 2496 { 2497 struct intel_atomic_state *state = cdclk_state->base.state; 2498 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2499 struct intel_crtc *crtc; 2500 struct intel_crtc_state *crtc_state; 2501 int vco, i; 2502 2503 vco = cdclk_state->logical.vco; 2504 if (!vco) 2505 vco = dev_priv->skl_preferred_vco_freq; 2506 2507 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2508 if (!crtc_state->hw.enable) 2509 continue; 2510 2511 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 2512 continue; 2513 2514 /* 2515 * DPLL0 VCO may need to be adjusted to get the correct 2516 * clock for eDP. This will affect cdclk as well. 2517 */ 2518 switch (crtc_state->port_clock / 2) { 2519 case 108000: 2520 case 216000: 2521 vco = 8640000; 2522 break; 2523 default: 2524 vco = 8100000; 2525 break; 2526 } 2527 } 2528 2529 return vco; 2530 } 2531 2532 static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2533 { 2534 int min_cdclk, cdclk, vco; 2535 2536 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2537 if (min_cdclk < 0) 2538 return min_cdclk; 2539 2540 vco = skl_dpll0_vco(cdclk_state); 2541 2542 cdclk = skl_calc_cdclk(min_cdclk, vco); 2543 2544 cdclk_state->logical.vco = vco; 2545 cdclk_state->logical.cdclk = cdclk; 2546 cdclk_state->logical.voltage_level = 2547 skl_calc_voltage_level(cdclk); 2548 2549 if (!cdclk_state->active_pipes) { 2550 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); 2551 2552 cdclk_state->actual.vco = vco; 2553 cdclk_state->actual.cdclk = cdclk; 2554 cdclk_state->actual.voltage_level = 2555 skl_calc_voltage_level(cdclk); 2556 } else { 2557 cdclk_state->actual = cdclk_state->logical; 2558 } 2559 2560 return 0; 2561 } 2562 2563 static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2564 { 2565 struct intel_atomic_state *state = cdclk_state->base.state; 2566 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2567 int min_cdclk, min_voltage_level, cdclk, vco; 2568 2569 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2570 if (min_cdclk < 0) 2571 return min_cdclk; 2572 2573 min_voltage_level = bxt_compute_min_voltage_level(cdclk_state); 2574 if (min_voltage_level < 0) 2575 return min_voltage_level; 2576 2577 cdclk = bxt_calc_cdclk(dev_priv, min_cdclk); 2578 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 2579 2580 cdclk_state->logical.vco = vco; 2581 cdclk_state->logical.cdclk = cdclk; 2582 cdclk_state->logical.voltage_level = 2583 max_t(int, min_voltage_level, 2584 intel_cdclk_calc_voltage_level(dev_priv, cdclk)); 2585 2586 if (!cdclk_state->active_pipes) { 2587 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); 2588 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 2589 2590 cdclk_state->actual.vco = vco; 2591 cdclk_state->actual.cdclk = cdclk; 2592 cdclk_state->actual.voltage_level = 2593 intel_cdclk_calc_voltage_level(dev_priv, cdclk); 2594 } else { 2595 cdclk_state->actual = cdclk_state->logical; 2596 } 2597 2598 return 0; 2599 } 2600 2601 static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2602 { 2603 int min_cdclk; 2604 2605 /* 2606 * We can't change the cdclk frequency, but we still want to 2607 * check that the required minimum frequency doesn't exceed 2608 * the actual cdclk frequency. 2609 */ 2610 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2611 if (min_cdclk < 0) 2612 return min_cdclk; 2613 2614 return 0; 2615 } 2616 2617 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj) 2618 { 2619 struct intel_cdclk_state *cdclk_state; 2620 2621 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); 2622 if (!cdclk_state) 2623 return NULL; 2624 2625 cdclk_state->pipe = INVALID_PIPE; 2626 2627 return &cdclk_state->base; 2628 } 2629 2630 static void intel_cdclk_destroy_state(struct intel_global_obj *obj, 2631 struct intel_global_state *state) 2632 { 2633 kfree(state); 2634 } 2635 2636 static const struct intel_global_state_funcs intel_cdclk_funcs = { 2637 .atomic_duplicate_state = intel_cdclk_duplicate_state, 2638 .atomic_destroy_state = intel_cdclk_destroy_state, 2639 }; 2640 2641 struct intel_cdclk_state * 2642 intel_atomic_get_cdclk_state(struct intel_atomic_state *state) 2643 { 2644 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2645 struct intel_global_state *cdclk_state; 2646 2647 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj); 2648 if (IS_ERR(cdclk_state)) 2649 return ERR_CAST(cdclk_state); 2650 2651 return to_intel_cdclk_state(cdclk_state); 2652 } 2653 2654 int intel_cdclk_atomic_check(struct intel_atomic_state *state, 2655 bool *need_cdclk_calc) 2656 { 2657 const struct intel_cdclk_state *old_cdclk_state; 2658 const struct intel_cdclk_state *new_cdclk_state; 2659 struct intel_plane_state *plane_state; 2660 struct intel_plane *plane; 2661 int ret; 2662 int i; 2663 2664 /* 2665 * active_planes bitmask has been updated, and potentially affected 2666 * planes are part of the state. We can now compute the minimum cdclk 2667 * for each plane. 2668 */ 2669 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 2670 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc); 2671 if (ret) 2672 return ret; 2673 } 2674 2675 ret = intel_bw_calc_min_cdclk(state, need_cdclk_calc); 2676 if (ret) 2677 return ret; 2678 2679 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 2680 new_cdclk_state = intel_atomic_get_new_cdclk_state(state); 2681 2682 if (new_cdclk_state && 2683 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) 2684 *need_cdclk_calc = true; 2685 2686 return 0; 2687 } 2688 2689 int intel_cdclk_init(struct drm_i915_private *dev_priv) 2690 { 2691 struct intel_cdclk_state *cdclk_state; 2692 2693 cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL); 2694 if (!cdclk_state) 2695 return -ENOMEM; 2696 2697 intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj, 2698 &cdclk_state->base, &intel_cdclk_funcs); 2699 2700 return 0; 2701 } 2702 2703 int intel_modeset_calc_cdclk(struct intel_atomic_state *state) 2704 { 2705 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2706 const struct intel_cdclk_state *old_cdclk_state; 2707 struct intel_cdclk_state *new_cdclk_state; 2708 enum pipe pipe = INVALID_PIPE; 2709 int ret; 2710 2711 new_cdclk_state = intel_atomic_get_cdclk_state(state); 2712 if (IS_ERR(new_cdclk_state)) 2713 return PTR_ERR(new_cdclk_state); 2714 2715 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 2716 2717 new_cdclk_state->active_pipes = 2718 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); 2719 2720 ret = intel_cdclk_modeset_calc_cdclk(dev_priv, new_cdclk_state); 2721 if (ret) 2722 return ret; 2723 2724 if (intel_cdclk_changed(&old_cdclk_state->actual, 2725 &new_cdclk_state->actual)) { 2726 /* 2727 * Also serialize commits across all crtcs 2728 * if the actual hw needs to be poked. 2729 */ 2730 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); 2731 if (ret) 2732 return ret; 2733 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes || 2734 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk || 2735 intel_cdclk_changed(&old_cdclk_state->logical, 2736 &new_cdclk_state->logical)) { 2737 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 2738 if (ret) 2739 return ret; 2740 } else { 2741 return 0; 2742 } 2743 2744 if (is_power_of_2(new_cdclk_state->active_pipes) && 2745 intel_cdclk_can_cd2x_update(dev_priv, 2746 &old_cdclk_state->actual, 2747 &new_cdclk_state->actual)) { 2748 struct intel_crtc *crtc; 2749 struct intel_crtc_state *crtc_state; 2750 2751 pipe = ilog2(new_cdclk_state->active_pipes); 2752 crtc = intel_crtc_for_pipe(dev_priv, pipe); 2753 2754 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 2755 if (IS_ERR(crtc_state)) 2756 return PTR_ERR(crtc_state); 2757 2758 if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) 2759 pipe = INVALID_PIPE; 2760 } 2761 2762 if (intel_cdclk_can_squash(dev_priv, 2763 &old_cdclk_state->actual, 2764 &new_cdclk_state->actual)) { 2765 drm_dbg_kms(&dev_priv->drm, 2766 "Can change cdclk via squashing\n"); 2767 } else if (intel_cdclk_can_crawl(dev_priv, 2768 &old_cdclk_state->actual, 2769 &new_cdclk_state->actual)) { 2770 drm_dbg_kms(&dev_priv->drm, 2771 "Can change cdclk via crawling\n"); 2772 } else if (pipe != INVALID_PIPE) { 2773 new_cdclk_state->pipe = pipe; 2774 2775 drm_dbg_kms(&dev_priv->drm, 2776 "Can change cdclk cd2x divider with pipe %c active\n", 2777 pipe_name(pipe)); 2778 } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual, 2779 &new_cdclk_state->actual)) { 2780 /* All pipes must be switched off while we change the cdclk. */ 2781 ret = intel_modeset_all_pipes(state, "CDCLK change"); 2782 if (ret) 2783 return ret; 2784 2785 drm_dbg_kms(&dev_priv->drm, 2786 "Modeset required for cdclk change\n"); 2787 } 2788 2789 drm_dbg_kms(&dev_priv->drm, 2790 "New cdclk calculated to be logical %u kHz, actual %u kHz\n", 2791 new_cdclk_state->logical.cdclk, 2792 new_cdclk_state->actual.cdclk); 2793 drm_dbg_kms(&dev_priv->drm, 2794 "New voltage level calculated to be logical %u, actual %u\n", 2795 new_cdclk_state->logical.voltage_level, 2796 new_cdclk_state->actual.voltage_level); 2797 2798 return 0; 2799 } 2800 2801 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) 2802 { 2803 int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq; 2804 2805 if (DISPLAY_VER(dev_priv) >= 10) 2806 return 2 * max_cdclk_freq; 2807 else if (DISPLAY_VER(dev_priv) == 9 || 2808 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2809 return max_cdclk_freq; 2810 else if (IS_CHERRYVIEW(dev_priv)) 2811 return max_cdclk_freq*95/100; 2812 else if (DISPLAY_VER(dev_priv) < 4) 2813 return 2*max_cdclk_freq*90/100; 2814 else 2815 return max_cdclk_freq*90/100; 2816 } 2817 2818 /** 2819 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency 2820 * @dev_priv: i915 device 2821 * 2822 * Determine the maximum CDCLK frequency the platform supports, and also 2823 * derive the maximum dot clock frequency the maximum CDCLK frequency 2824 * allows. 2825 */ 2826 void intel_update_max_cdclk(struct drm_i915_private *dev_priv) 2827 { 2828 if (IS_JSL_EHL(dev_priv)) { 2829 if (dev_priv->display.cdclk.hw.ref == 24000) 2830 dev_priv->display.cdclk.max_cdclk_freq = 552000; 2831 else 2832 dev_priv->display.cdclk.max_cdclk_freq = 556800; 2833 } else if (DISPLAY_VER(dev_priv) >= 11) { 2834 if (dev_priv->display.cdclk.hw.ref == 24000) 2835 dev_priv->display.cdclk.max_cdclk_freq = 648000; 2836 else 2837 dev_priv->display.cdclk.max_cdclk_freq = 652800; 2838 } else if (IS_GEMINILAKE(dev_priv)) { 2839 dev_priv->display.cdclk.max_cdclk_freq = 316800; 2840 } else if (IS_BROXTON(dev_priv)) { 2841 dev_priv->display.cdclk.max_cdclk_freq = 624000; 2842 } else if (DISPLAY_VER(dev_priv) == 9) { 2843 u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; 2844 int max_cdclk, vco; 2845 2846 vco = dev_priv->skl_preferred_vco_freq; 2847 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); 2848 2849 /* 2850 * Use the lower (vco 8640) cdclk values as a 2851 * first guess. skl_calc_cdclk() will correct it 2852 * if the preferred vco is 8100 instead. 2853 */ 2854 if (limit == SKL_DFSM_CDCLK_LIMIT_675) 2855 max_cdclk = 617143; 2856 else if (limit == SKL_DFSM_CDCLK_LIMIT_540) 2857 max_cdclk = 540000; 2858 else if (limit == SKL_DFSM_CDCLK_LIMIT_450) 2859 max_cdclk = 432000; 2860 else 2861 max_cdclk = 308571; 2862 2863 dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); 2864 } else if (IS_BROADWELL(dev_priv)) { 2865 /* 2866 * FIXME with extra cooling we can allow 2867 * 540 MHz for ULX and 675 Mhz for ULT. 2868 * How can we know if extra cooling is 2869 * available? PCI ID, VTB, something else? 2870 */ 2871 if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 2872 dev_priv->display.cdclk.max_cdclk_freq = 450000; 2873 else if (IS_BDW_ULX(dev_priv)) 2874 dev_priv->display.cdclk.max_cdclk_freq = 450000; 2875 else if (IS_BDW_ULT(dev_priv)) 2876 dev_priv->display.cdclk.max_cdclk_freq = 540000; 2877 else 2878 dev_priv->display.cdclk.max_cdclk_freq = 675000; 2879 } else if (IS_CHERRYVIEW(dev_priv)) { 2880 dev_priv->display.cdclk.max_cdclk_freq = 320000; 2881 } else if (IS_VALLEYVIEW(dev_priv)) { 2882 dev_priv->display.cdclk.max_cdclk_freq = 400000; 2883 } else { 2884 /* otherwise assume cdclk is fixed */ 2885 dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk; 2886 } 2887 2888 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); 2889 2890 drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n", 2891 dev_priv->display.cdclk.max_cdclk_freq); 2892 2893 drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n", 2894 dev_priv->max_dotclk_freq); 2895 } 2896 2897 /** 2898 * intel_update_cdclk - Determine the current CDCLK frequency 2899 * @dev_priv: i915 device 2900 * 2901 * Determine the current CDCLK frequency. 2902 */ 2903 void intel_update_cdclk(struct drm_i915_private *dev_priv) 2904 { 2905 intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw); 2906 2907 /* 2908 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): 2909 * Programmng [sic] note: bit[9:2] should be programmed to the number 2910 * of cdclk that generates 4MHz reference clock freq which is used to 2911 * generate GMBus clock. This will vary with the cdclk freq. 2912 */ 2913 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 2914 intel_de_write(dev_priv, GMBUSFREQ_VLV, 2915 DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000)); 2916 } 2917 2918 static int dg1_rawclk(struct drm_i915_private *dev_priv) 2919 { 2920 /* 2921 * DG1 always uses a 38.4 MHz rawclk. The bspec tells us 2922 * "Program Numerator=2, Denominator=4, Divider=37 decimal." 2923 */ 2924 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, 2925 CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2)); 2926 2927 return 38400; 2928 } 2929 2930 static int cnp_rawclk(struct drm_i915_private *dev_priv) 2931 { 2932 u32 rawclk; 2933 int divider, fraction; 2934 2935 if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { 2936 /* 24 MHz */ 2937 divider = 24000; 2938 fraction = 0; 2939 } else { 2940 /* 19.2 MHz */ 2941 divider = 19000; 2942 fraction = 200; 2943 } 2944 2945 rawclk = CNP_RAWCLK_DIV(divider / 1000); 2946 if (fraction) { 2947 int numerator = 1; 2948 2949 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000, 2950 fraction) - 1); 2951 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 2952 rawclk |= ICP_RAWCLK_NUM(numerator); 2953 } 2954 2955 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk); 2956 return divider + fraction; 2957 } 2958 2959 static int pch_rawclk(struct drm_i915_private *dev_priv) 2960 { 2961 return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; 2962 } 2963 2964 static int vlv_hrawclk(struct drm_i915_private *dev_priv) 2965 { 2966 /* RAWCLK_FREQ_VLV register updated from power well code */ 2967 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", 2968 CCK_DISPLAY_REF_CLOCK_CONTROL); 2969 } 2970 2971 static int i9xx_hrawclk(struct drm_i915_private *dev_priv) 2972 { 2973 u32 clkcfg; 2974 2975 /* 2976 * hrawclock is 1/4 the FSB frequency 2977 * 2978 * Note that this only reads the state of the FSB 2979 * straps, not the actual FSB frequency. Some BIOSen 2980 * let you configure each independently. Ideally we'd 2981 * read out the actual FSB frequency but sadly we 2982 * don't know which registers have that information, 2983 * and all the relevant docs have gone to bit heaven :( 2984 */ 2985 clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK; 2986 2987 if (IS_MOBILE(dev_priv)) { 2988 switch (clkcfg) { 2989 case CLKCFG_FSB_400: 2990 return 100000; 2991 case CLKCFG_FSB_533: 2992 return 133333; 2993 case CLKCFG_FSB_667: 2994 return 166667; 2995 case CLKCFG_FSB_800: 2996 return 200000; 2997 case CLKCFG_FSB_1067: 2998 return 266667; 2999 case CLKCFG_FSB_1333: 3000 return 333333; 3001 default: 3002 MISSING_CASE(clkcfg); 3003 return 133333; 3004 } 3005 } else { 3006 switch (clkcfg) { 3007 case CLKCFG_FSB_400_ALT: 3008 return 100000; 3009 case CLKCFG_FSB_533: 3010 return 133333; 3011 case CLKCFG_FSB_667: 3012 return 166667; 3013 case CLKCFG_FSB_800: 3014 return 200000; 3015 case CLKCFG_FSB_1067_ALT: 3016 return 266667; 3017 case CLKCFG_FSB_1333_ALT: 3018 return 333333; 3019 case CLKCFG_FSB_1600_ALT: 3020 return 400000; 3021 default: 3022 return 133333; 3023 } 3024 } 3025 } 3026 3027 /** 3028 * intel_read_rawclk - Determine the current RAWCLK frequency 3029 * @dev_priv: i915 device 3030 * 3031 * Determine the current RAWCLK frequency. RAWCLK is a fixed 3032 * frequency clock so this needs to done only once. 3033 */ 3034 u32 intel_read_rawclk(struct drm_i915_private *dev_priv) 3035 { 3036 u32 freq; 3037 3038 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 3039 freq = dg1_rawclk(dev_priv); 3040 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP) 3041 /* 3042 * MTL always uses a 38.4 MHz rawclk. The bspec tells us 3043 * "RAWCLK_FREQ defaults to the values for 38.4 and does 3044 * not need to be programmed." 3045 */ 3046 freq = 38400; 3047 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) 3048 freq = cnp_rawclk(dev_priv); 3049 else if (HAS_PCH_SPLIT(dev_priv)) 3050 freq = pch_rawclk(dev_priv); 3051 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 3052 freq = vlv_hrawclk(dev_priv); 3053 else if (DISPLAY_VER(dev_priv) >= 3) 3054 freq = i9xx_hrawclk(dev_priv); 3055 else 3056 /* no rawclk on other platforms, or no need to know it */ 3057 return 0; 3058 3059 return freq; 3060 } 3061 3062 static const struct intel_cdclk_funcs tgl_cdclk_funcs = { 3063 .get_cdclk = bxt_get_cdclk, 3064 .set_cdclk = bxt_set_cdclk, 3065 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3066 .calc_voltage_level = tgl_calc_voltage_level, 3067 }; 3068 3069 static const struct intel_cdclk_funcs ehl_cdclk_funcs = { 3070 .get_cdclk = bxt_get_cdclk, 3071 .set_cdclk = bxt_set_cdclk, 3072 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3073 .calc_voltage_level = ehl_calc_voltage_level, 3074 }; 3075 3076 static const struct intel_cdclk_funcs icl_cdclk_funcs = { 3077 .get_cdclk = bxt_get_cdclk, 3078 .set_cdclk = bxt_set_cdclk, 3079 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3080 .calc_voltage_level = icl_calc_voltage_level, 3081 }; 3082 3083 static const struct intel_cdclk_funcs bxt_cdclk_funcs = { 3084 .get_cdclk = bxt_get_cdclk, 3085 .set_cdclk = bxt_set_cdclk, 3086 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3087 .calc_voltage_level = bxt_calc_voltage_level, 3088 }; 3089 3090 static const struct intel_cdclk_funcs skl_cdclk_funcs = { 3091 .get_cdclk = skl_get_cdclk, 3092 .set_cdclk = skl_set_cdclk, 3093 .modeset_calc_cdclk = skl_modeset_calc_cdclk, 3094 }; 3095 3096 static const struct intel_cdclk_funcs bdw_cdclk_funcs = { 3097 .get_cdclk = bdw_get_cdclk, 3098 .set_cdclk = bdw_set_cdclk, 3099 .modeset_calc_cdclk = bdw_modeset_calc_cdclk, 3100 }; 3101 3102 static const struct intel_cdclk_funcs chv_cdclk_funcs = { 3103 .get_cdclk = vlv_get_cdclk, 3104 .set_cdclk = chv_set_cdclk, 3105 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3106 }; 3107 3108 static const struct intel_cdclk_funcs vlv_cdclk_funcs = { 3109 .get_cdclk = vlv_get_cdclk, 3110 .set_cdclk = vlv_set_cdclk, 3111 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3112 }; 3113 3114 static const struct intel_cdclk_funcs hsw_cdclk_funcs = { 3115 .get_cdclk = hsw_get_cdclk, 3116 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3117 }; 3118 3119 /* SNB, IVB, 965G, 945G */ 3120 static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = { 3121 .get_cdclk = fixed_400mhz_get_cdclk, 3122 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3123 }; 3124 3125 static const struct intel_cdclk_funcs ilk_cdclk_funcs = { 3126 .get_cdclk = fixed_450mhz_get_cdclk, 3127 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3128 }; 3129 3130 static const struct intel_cdclk_funcs gm45_cdclk_funcs = { 3131 .get_cdclk = gm45_get_cdclk, 3132 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3133 }; 3134 3135 /* G45 uses G33 */ 3136 3137 static const struct intel_cdclk_funcs i965gm_cdclk_funcs = { 3138 .get_cdclk = i965gm_get_cdclk, 3139 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3140 }; 3141 3142 /* i965G uses fixed 400 */ 3143 3144 static const struct intel_cdclk_funcs pnv_cdclk_funcs = { 3145 .get_cdclk = pnv_get_cdclk, 3146 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3147 }; 3148 3149 static const struct intel_cdclk_funcs g33_cdclk_funcs = { 3150 .get_cdclk = g33_get_cdclk, 3151 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3152 }; 3153 3154 static const struct intel_cdclk_funcs i945gm_cdclk_funcs = { 3155 .get_cdclk = i945gm_get_cdclk, 3156 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3157 }; 3158 3159 /* i945G uses fixed 400 */ 3160 3161 static const struct intel_cdclk_funcs i915gm_cdclk_funcs = { 3162 .get_cdclk = i915gm_get_cdclk, 3163 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3164 }; 3165 3166 static const struct intel_cdclk_funcs i915g_cdclk_funcs = { 3167 .get_cdclk = fixed_333mhz_get_cdclk, 3168 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3169 }; 3170 3171 static const struct intel_cdclk_funcs i865g_cdclk_funcs = { 3172 .get_cdclk = fixed_266mhz_get_cdclk, 3173 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3174 }; 3175 3176 static const struct intel_cdclk_funcs i85x_cdclk_funcs = { 3177 .get_cdclk = i85x_get_cdclk, 3178 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3179 }; 3180 3181 static const struct intel_cdclk_funcs i845g_cdclk_funcs = { 3182 .get_cdclk = fixed_200mhz_get_cdclk, 3183 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3184 }; 3185 3186 static const struct intel_cdclk_funcs i830_cdclk_funcs = { 3187 .get_cdclk = fixed_133mhz_get_cdclk, 3188 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3189 }; 3190 3191 /** 3192 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks 3193 * @dev_priv: i915 device 3194 */ 3195 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) 3196 { 3197 if (IS_DG2(dev_priv)) { 3198 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3199 dev_priv->display.cdclk.table = dg2_cdclk_table; 3200 } else if (IS_ALDERLAKE_P(dev_priv)) { 3201 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3202 /* Wa_22011320316:adl-p[a0] */ 3203 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 3204 dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; 3205 else 3206 dev_priv->display.cdclk.table = adlp_cdclk_table; 3207 } else if (IS_ROCKETLAKE(dev_priv)) { 3208 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3209 dev_priv->display.cdclk.table = rkl_cdclk_table; 3210 } else if (DISPLAY_VER(dev_priv) >= 12) { 3211 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3212 dev_priv->display.cdclk.table = icl_cdclk_table; 3213 } else if (IS_JSL_EHL(dev_priv)) { 3214 dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs; 3215 dev_priv->display.cdclk.table = icl_cdclk_table; 3216 } else if (DISPLAY_VER(dev_priv) >= 11) { 3217 dev_priv->display.funcs.cdclk = &icl_cdclk_funcs; 3218 dev_priv->display.cdclk.table = icl_cdclk_table; 3219 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 3220 dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs; 3221 if (IS_GEMINILAKE(dev_priv)) 3222 dev_priv->display.cdclk.table = glk_cdclk_table; 3223 else 3224 dev_priv->display.cdclk.table = bxt_cdclk_table; 3225 } else if (DISPLAY_VER(dev_priv) == 9) { 3226 dev_priv->display.funcs.cdclk = &skl_cdclk_funcs; 3227 } else if (IS_BROADWELL(dev_priv)) { 3228 dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs; 3229 } else if (IS_HASWELL(dev_priv)) { 3230 dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs; 3231 } else if (IS_CHERRYVIEW(dev_priv)) { 3232 dev_priv->display.funcs.cdclk = &chv_cdclk_funcs; 3233 } else if (IS_VALLEYVIEW(dev_priv)) { 3234 dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs; 3235 } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) { 3236 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3237 } else if (IS_IRONLAKE(dev_priv)) { 3238 dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs; 3239 } else if (IS_GM45(dev_priv)) { 3240 dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs; 3241 } else if (IS_G45(dev_priv)) { 3242 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; 3243 } else if (IS_I965GM(dev_priv)) { 3244 dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs; 3245 } else if (IS_I965G(dev_priv)) { 3246 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3247 } else if (IS_PINEVIEW(dev_priv)) { 3248 dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs; 3249 } else if (IS_G33(dev_priv)) { 3250 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; 3251 } else if (IS_I945GM(dev_priv)) { 3252 dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs; 3253 } else if (IS_I945G(dev_priv)) { 3254 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3255 } else if (IS_I915GM(dev_priv)) { 3256 dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs; 3257 } else if (IS_I915G(dev_priv)) { 3258 dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs; 3259 } else if (IS_I865G(dev_priv)) { 3260 dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs; 3261 } else if (IS_I85X(dev_priv)) { 3262 dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs; 3263 } else if (IS_I845G(dev_priv)) { 3264 dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs; 3265 } else if (IS_I830(dev_priv)) { 3266 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; 3267 } 3268 3269 if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk, 3270 "Unknown platform. Assuming i830\n")) 3271 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; 3272 } 3273