1 /* 2 * Copyright © 2006-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/time.h> 25 26 #include "intel_atomic.h" 27 #include "intel_bw.h" 28 #include "intel_cdclk.h" 29 #include "intel_display_types.h" 30 #include "intel_sideband.h" 31 32 /** 33 * DOC: CDCLK / RAWCLK 34 * 35 * The display engine uses several different clocks to do its work. There 36 * are two main clocks involved that aren't directly related to the actual 37 * pixel clock or any symbol/bit clock of the actual output port. These 38 * are the core display clock (CDCLK) and RAWCLK. 39 * 40 * CDCLK clocks most of the display pipe logic, and thus its frequency 41 * must be high enough to support the rate at which pixels are flowing 42 * through the pipes. Downscaling must also be accounted as that increases 43 * the effective pixel rate. 44 * 45 * On several platforms the CDCLK frequency can be changed dynamically 46 * to minimize power consumption for a given display configuration. 47 * Typically changes to the CDCLK frequency require all the display pipes 48 * to be shut down while the frequency is being changed. 49 * 50 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. 51 * DMC will not change the active CDCLK frequency however, so that part 52 * will still be performed by the driver directly. 53 * 54 * RAWCLK is a fixed frequency clock, often used by various auxiliary 55 * blocks such as AUX CH or backlight PWM. Hence the only thing we 56 * really need to know about RAWCLK is its frequency so that various 57 * dividers can be programmed correctly. 58 */ 59 60 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, 61 struct intel_cdclk_config *cdclk_config) 62 { 63 cdclk_config->cdclk = 133333; 64 } 65 66 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, 67 struct intel_cdclk_config *cdclk_config) 68 { 69 cdclk_config->cdclk = 200000; 70 } 71 72 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, 73 struct intel_cdclk_config *cdclk_config) 74 { 75 cdclk_config->cdclk = 266667; 76 } 77 78 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, 79 struct intel_cdclk_config *cdclk_config) 80 { 81 cdclk_config->cdclk = 333333; 82 } 83 84 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, 85 struct intel_cdclk_config *cdclk_config) 86 { 87 cdclk_config->cdclk = 400000; 88 } 89 90 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, 91 struct intel_cdclk_config *cdclk_config) 92 { 93 cdclk_config->cdclk = 450000; 94 } 95 96 static void i85x_get_cdclk(struct drm_i915_private *dev_priv, 97 struct intel_cdclk_config *cdclk_config) 98 { 99 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 100 u16 hpllcc = 0; 101 102 /* 103 * 852GM/852GMV only supports 133 MHz and the HPLLCC 104 * encoding is different :( 105 * FIXME is this the right way to detect 852GM/852GMV? 106 */ 107 if (pdev->revision == 0x1) { 108 cdclk_config->cdclk = 133333; 109 return; 110 } 111 112 pci_bus_read_config_word(pdev->bus, 113 PCI_DEVFN(0, 3), HPLLCC, &hpllcc); 114 115 /* Assume that the hardware is in the high speed state. This 116 * should be the default. 117 */ 118 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 119 case GC_CLOCK_133_200: 120 case GC_CLOCK_133_200_2: 121 case GC_CLOCK_100_200: 122 cdclk_config->cdclk = 200000; 123 break; 124 case GC_CLOCK_166_250: 125 cdclk_config->cdclk = 250000; 126 break; 127 case GC_CLOCK_100_133: 128 cdclk_config->cdclk = 133333; 129 break; 130 case GC_CLOCK_133_266: 131 case GC_CLOCK_133_266_2: 132 case GC_CLOCK_166_266: 133 cdclk_config->cdclk = 266667; 134 break; 135 } 136 } 137 138 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, 139 struct intel_cdclk_config *cdclk_config) 140 { 141 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 142 u16 gcfgc = 0; 143 144 pci_read_config_word(pdev, GCFGC, &gcfgc); 145 146 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 147 cdclk_config->cdclk = 133333; 148 return; 149 } 150 151 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 152 case GC_DISPLAY_CLOCK_333_320_MHZ: 153 cdclk_config->cdclk = 333333; 154 break; 155 default: 156 case GC_DISPLAY_CLOCK_190_200_MHZ: 157 cdclk_config->cdclk = 190000; 158 break; 159 } 160 } 161 162 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, 163 struct intel_cdclk_config *cdclk_config) 164 { 165 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 166 u16 gcfgc = 0; 167 168 pci_read_config_word(pdev, GCFGC, &gcfgc); 169 170 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 171 cdclk_config->cdclk = 133333; 172 return; 173 } 174 175 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 176 case GC_DISPLAY_CLOCK_333_320_MHZ: 177 cdclk_config->cdclk = 320000; 178 break; 179 default: 180 case GC_DISPLAY_CLOCK_190_200_MHZ: 181 cdclk_config->cdclk = 200000; 182 break; 183 } 184 } 185 186 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) 187 { 188 static const unsigned int blb_vco[8] = { 189 [0] = 3200000, 190 [1] = 4000000, 191 [2] = 5333333, 192 [3] = 4800000, 193 [4] = 6400000, 194 }; 195 static const unsigned int pnv_vco[8] = { 196 [0] = 3200000, 197 [1] = 4000000, 198 [2] = 5333333, 199 [3] = 4800000, 200 [4] = 2666667, 201 }; 202 static const unsigned int cl_vco[8] = { 203 [0] = 3200000, 204 [1] = 4000000, 205 [2] = 5333333, 206 [3] = 6400000, 207 [4] = 3333333, 208 [5] = 3566667, 209 [6] = 4266667, 210 }; 211 static const unsigned int elk_vco[8] = { 212 [0] = 3200000, 213 [1] = 4000000, 214 [2] = 5333333, 215 [3] = 4800000, 216 }; 217 static const unsigned int ctg_vco[8] = { 218 [0] = 3200000, 219 [1] = 4000000, 220 [2] = 5333333, 221 [3] = 6400000, 222 [4] = 2666667, 223 [5] = 4266667, 224 }; 225 const unsigned int *vco_table; 226 unsigned int vco; 227 u8 tmp = 0; 228 229 /* FIXME other chipsets? */ 230 if (IS_GM45(dev_priv)) 231 vco_table = ctg_vco; 232 else if (IS_G45(dev_priv)) 233 vco_table = elk_vco; 234 else if (IS_I965GM(dev_priv)) 235 vco_table = cl_vco; 236 else if (IS_PINEVIEW(dev_priv)) 237 vco_table = pnv_vco; 238 else if (IS_G33(dev_priv)) 239 vco_table = blb_vco; 240 else 241 return 0; 242 243 tmp = intel_de_read(dev_priv, 244 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); 245 246 vco = vco_table[tmp & 0x7]; 247 if (vco == 0) 248 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", 249 tmp); 250 else 251 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); 252 253 return vco; 254 } 255 256 static void g33_get_cdclk(struct drm_i915_private *dev_priv, 257 struct intel_cdclk_config *cdclk_config) 258 { 259 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 260 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 }; 261 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 }; 262 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 }; 263 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 }; 264 const u8 *div_table; 265 unsigned int cdclk_sel; 266 u16 tmp = 0; 267 268 cdclk_config->vco = intel_hpll_vco(dev_priv); 269 270 pci_read_config_word(pdev, GCFGC, &tmp); 271 272 cdclk_sel = (tmp >> 4) & 0x7; 273 274 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 275 goto fail; 276 277 switch (cdclk_config->vco) { 278 case 3200000: 279 div_table = div_3200; 280 break; 281 case 4000000: 282 div_table = div_4000; 283 break; 284 case 4800000: 285 div_table = div_4800; 286 break; 287 case 5333333: 288 div_table = div_5333; 289 break; 290 default: 291 goto fail; 292 } 293 294 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 295 div_table[cdclk_sel]); 296 return; 297 298 fail: 299 drm_err(&dev_priv->drm, 300 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", 301 cdclk_config->vco, tmp); 302 cdclk_config->cdclk = 190476; 303 } 304 305 static void pnv_get_cdclk(struct drm_i915_private *dev_priv, 306 struct intel_cdclk_config *cdclk_config) 307 { 308 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 309 u16 gcfgc = 0; 310 311 pci_read_config_word(pdev, GCFGC, &gcfgc); 312 313 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 314 case GC_DISPLAY_CLOCK_267_MHZ_PNV: 315 cdclk_config->cdclk = 266667; 316 break; 317 case GC_DISPLAY_CLOCK_333_MHZ_PNV: 318 cdclk_config->cdclk = 333333; 319 break; 320 case GC_DISPLAY_CLOCK_444_MHZ_PNV: 321 cdclk_config->cdclk = 444444; 322 break; 323 case GC_DISPLAY_CLOCK_200_MHZ_PNV: 324 cdclk_config->cdclk = 200000; 325 break; 326 default: 327 drm_err(&dev_priv->drm, 328 "Unknown pnv display core clock 0x%04x\n", gcfgc); 329 fallthrough; 330 case GC_DISPLAY_CLOCK_133_MHZ_PNV: 331 cdclk_config->cdclk = 133333; 332 break; 333 case GC_DISPLAY_CLOCK_167_MHZ_PNV: 334 cdclk_config->cdclk = 166667; 335 break; 336 } 337 } 338 339 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, 340 struct intel_cdclk_config *cdclk_config) 341 { 342 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 343 static const u8 div_3200[] = { 16, 10, 8 }; 344 static const u8 div_4000[] = { 20, 12, 10 }; 345 static const u8 div_5333[] = { 24, 16, 14 }; 346 const u8 *div_table; 347 unsigned int cdclk_sel; 348 u16 tmp = 0; 349 350 cdclk_config->vco = intel_hpll_vco(dev_priv); 351 352 pci_read_config_word(pdev, GCFGC, &tmp); 353 354 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; 355 356 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 357 goto fail; 358 359 switch (cdclk_config->vco) { 360 case 3200000: 361 div_table = div_3200; 362 break; 363 case 4000000: 364 div_table = div_4000; 365 break; 366 case 5333333: 367 div_table = div_5333; 368 break; 369 default: 370 goto fail; 371 } 372 373 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 374 div_table[cdclk_sel]); 375 return; 376 377 fail: 378 drm_err(&dev_priv->drm, 379 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", 380 cdclk_config->vco, tmp); 381 cdclk_config->cdclk = 200000; 382 } 383 384 static void gm45_get_cdclk(struct drm_i915_private *dev_priv, 385 struct intel_cdclk_config *cdclk_config) 386 { 387 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 388 unsigned int cdclk_sel; 389 u16 tmp = 0; 390 391 cdclk_config->vco = intel_hpll_vco(dev_priv); 392 393 pci_read_config_word(pdev, GCFGC, &tmp); 394 395 cdclk_sel = (tmp >> 12) & 0x1; 396 397 switch (cdclk_config->vco) { 398 case 2666667: 399 case 4000000: 400 case 5333333: 401 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; 402 break; 403 case 3200000: 404 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; 405 break; 406 default: 407 drm_err(&dev_priv->drm, 408 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", 409 cdclk_config->vco, tmp); 410 cdclk_config->cdclk = 222222; 411 break; 412 } 413 } 414 415 static void hsw_get_cdclk(struct drm_i915_private *dev_priv, 416 struct intel_cdclk_config *cdclk_config) 417 { 418 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); 419 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 420 421 if (lcpll & LCPLL_CD_SOURCE_FCLK) 422 cdclk_config->cdclk = 800000; 423 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 424 cdclk_config->cdclk = 450000; 425 else if (freq == LCPLL_CLK_FREQ_450) 426 cdclk_config->cdclk = 450000; 427 else if (IS_HSW_ULT(dev_priv)) 428 cdclk_config->cdclk = 337500; 429 else 430 cdclk_config->cdclk = 540000; 431 } 432 433 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) 434 { 435 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 436 333333 : 320000; 437 438 /* 439 * We seem to get an unstable or solid color picture at 200MHz. 440 * Not sure what's wrong. For now use 200MHz only when all pipes 441 * are off. 442 */ 443 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) 444 return 400000; 445 else if (min_cdclk > 266667) 446 return freq_320; 447 else if (min_cdclk > 0) 448 return 266667; 449 else 450 return 200000; 451 } 452 453 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) 454 { 455 if (IS_VALLEYVIEW(dev_priv)) { 456 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ 457 return 2; 458 else if (cdclk >= 266667) 459 return 1; 460 else 461 return 0; 462 } else { 463 /* 464 * Specs are full of misinformation, but testing on actual 465 * hardware has shown that we just need to write the desired 466 * CCK divider into the Punit register. 467 */ 468 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; 469 } 470 } 471 472 static void vlv_get_cdclk(struct drm_i915_private *dev_priv, 473 struct intel_cdclk_config *cdclk_config) 474 { 475 u32 val; 476 477 vlv_iosf_sb_get(dev_priv, 478 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 479 480 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); 481 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", 482 CCK_DISPLAY_CLOCK_CONTROL, 483 cdclk_config->vco); 484 485 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 486 487 vlv_iosf_sb_put(dev_priv, 488 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 489 490 if (IS_VALLEYVIEW(dev_priv)) 491 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> 492 DSPFREQGUAR_SHIFT; 493 else 494 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> 495 DSPFREQGUAR_SHIFT_CHV; 496 } 497 498 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) 499 { 500 unsigned int credits, default_credits; 501 502 if (IS_CHERRYVIEW(dev_priv)) 503 default_credits = PFI_CREDIT(12); 504 else 505 default_credits = PFI_CREDIT(8); 506 507 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) { 508 /* CHV suggested value is 31 or 63 */ 509 if (IS_CHERRYVIEW(dev_priv)) 510 credits = PFI_CREDIT_63; 511 else 512 credits = PFI_CREDIT(15); 513 } else { 514 credits = default_credits; 515 } 516 517 /* 518 * WA - write default credits before re-programming 519 * FIXME: should we also set the resend bit here? 520 */ 521 intel_de_write(dev_priv, GCI_CONTROL, 522 VGA_FAST_MODE_DISABLE | default_credits); 523 524 intel_de_write(dev_priv, GCI_CONTROL, 525 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND); 526 527 /* 528 * FIXME is this guaranteed to clear 529 * immediately or should we poll for it? 530 */ 531 drm_WARN_ON(&dev_priv->drm, 532 intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND); 533 } 534 535 static void vlv_set_cdclk(struct drm_i915_private *dev_priv, 536 const struct intel_cdclk_config *cdclk_config, 537 enum pipe pipe) 538 { 539 int cdclk = cdclk_config->cdclk; 540 u32 val, cmd = cdclk_config->voltage_level; 541 intel_wakeref_t wakeref; 542 543 switch (cdclk) { 544 case 400000: 545 case 333333: 546 case 320000: 547 case 266667: 548 case 200000: 549 break; 550 default: 551 MISSING_CASE(cdclk); 552 return; 553 } 554 555 /* There are cases where we can end up here with power domains 556 * off and a CDCLK frequency other than the minimum, like when 557 * issuing a modeset without actually changing any display after 558 * a system suspend. So grab the display core domain, which covers 559 * the HW blocks needed for the following programming. 560 */ 561 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); 562 563 vlv_iosf_sb_get(dev_priv, 564 BIT(VLV_IOSF_SB_CCK) | 565 BIT(VLV_IOSF_SB_BUNIT) | 566 BIT(VLV_IOSF_SB_PUNIT)); 567 568 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 569 val &= ~DSPFREQGUAR_MASK; 570 val |= (cmd << DSPFREQGUAR_SHIFT); 571 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); 572 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & 573 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 574 50)) { 575 drm_err(&dev_priv->drm, 576 "timed out waiting for CDclk change\n"); 577 } 578 579 if (cdclk == 400000) { 580 u32 divider; 581 582 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, 583 cdclk) - 1; 584 585 /* adjust cdclk divider */ 586 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); 587 val &= ~CCK_FREQUENCY_VALUES; 588 val |= divider; 589 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); 590 591 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & 592 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 593 50)) 594 drm_err(&dev_priv->drm, 595 "timed out waiting for CDclk change\n"); 596 } 597 598 /* adjust self-refresh exit latency value */ 599 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); 600 val &= ~0x7f; 601 602 /* 603 * For high bandwidth configs, we set a higher latency in the bunit 604 * so that the core display fetch happens in time to avoid underruns. 605 */ 606 if (cdclk == 400000) 607 val |= 4500 / 250; /* 4.5 usec */ 608 else 609 val |= 3000 / 250; /* 3.0 usec */ 610 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); 611 612 vlv_iosf_sb_put(dev_priv, 613 BIT(VLV_IOSF_SB_CCK) | 614 BIT(VLV_IOSF_SB_BUNIT) | 615 BIT(VLV_IOSF_SB_PUNIT)); 616 617 intel_update_cdclk(dev_priv); 618 619 vlv_program_pfi_credits(dev_priv); 620 621 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); 622 } 623 624 static void chv_set_cdclk(struct drm_i915_private *dev_priv, 625 const struct intel_cdclk_config *cdclk_config, 626 enum pipe pipe) 627 { 628 int cdclk = cdclk_config->cdclk; 629 u32 val, cmd = cdclk_config->voltage_level; 630 intel_wakeref_t wakeref; 631 632 switch (cdclk) { 633 case 333333: 634 case 320000: 635 case 266667: 636 case 200000: 637 break; 638 default: 639 MISSING_CASE(cdclk); 640 return; 641 } 642 643 /* There are cases where we can end up here with power domains 644 * off and a CDCLK frequency other than the minimum, like when 645 * issuing a modeset without actually changing any display after 646 * a system suspend. So grab the display core domain, which covers 647 * the HW blocks needed for the following programming. 648 */ 649 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); 650 651 vlv_punit_get(dev_priv); 652 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 653 val &= ~DSPFREQGUAR_MASK_CHV; 654 val |= (cmd << DSPFREQGUAR_SHIFT_CHV); 655 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); 656 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & 657 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 658 50)) { 659 drm_err(&dev_priv->drm, 660 "timed out waiting for CDclk change\n"); 661 } 662 663 vlv_punit_put(dev_priv); 664 665 intel_update_cdclk(dev_priv); 666 667 vlv_program_pfi_credits(dev_priv); 668 669 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); 670 } 671 672 static int bdw_calc_cdclk(int min_cdclk) 673 { 674 if (min_cdclk > 540000) 675 return 675000; 676 else if (min_cdclk > 450000) 677 return 540000; 678 else if (min_cdclk > 337500) 679 return 450000; 680 else 681 return 337500; 682 } 683 684 static u8 bdw_calc_voltage_level(int cdclk) 685 { 686 switch (cdclk) { 687 default: 688 case 337500: 689 return 2; 690 case 450000: 691 return 0; 692 case 540000: 693 return 1; 694 case 675000: 695 return 3; 696 } 697 } 698 699 static void bdw_get_cdclk(struct drm_i915_private *dev_priv, 700 struct intel_cdclk_config *cdclk_config) 701 { 702 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); 703 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 704 705 if (lcpll & LCPLL_CD_SOURCE_FCLK) 706 cdclk_config->cdclk = 800000; 707 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 708 cdclk_config->cdclk = 450000; 709 else if (freq == LCPLL_CLK_FREQ_450) 710 cdclk_config->cdclk = 450000; 711 else if (freq == LCPLL_CLK_FREQ_54O_BDW) 712 cdclk_config->cdclk = 540000; 713 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 714 cdclk_config->cdclk = 337500; 715 else 716 cdclk_config->cdclk = 675000; 717 718 /* 719 * Can't read this out :( Let's assume it's 720 * at least what the CDCLK frequency requires. 721 */ 722 cdclk_config->voltage_level = 723 bdw_calc_voltage_level(cdclk_config->cdclk); 724 } 725 726 static void bdw_set_cdclk(struct drm_i915_private *dev_priv, 727 const struct intel_cdclk_config *cdclk_config, 728 enum pipe pipe) 729 { 730 int cdclk = cdclk_config->cdclk; 731 u32 val; 732 int ret; 733 734 if (drm_WARN(&dev_priv->drm, 735 (intel_de_read(dev_priv, LCPLL_CTL) & 736 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | 737 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | 738 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | 739 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, 740 "trying to change cdclk frequency with cdclk not enabled\n")) 741 return; 742 743 ret = sandybridge_pcode_write(dev_priv, 744 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); 745 if (ret) { 746 drm_err(&dev_priv->drm, 747 "failed to inform pcode about cdclk change\n"); 748 return; 749 } 750 751 val = intel_de_read(dev_priv, LCPLL_CTL); 752 val |= LCPLL_CD_SOURCE_FCLK; 753 intel_de_write(dev_priv, LCPLL_CTL, val); 754 755 /* 756 * According to the spec, it should be enough to poll for this 1 us. 757 * However, extensive testing shows that this can take longer. 758 */ 759 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) & 760 LCPLL_CD_SOURCE_FCLK_DONE, 100)) 761 drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); 762 763 val = intel_de_read(dev_priv, LCPLL_CTL); 764 val &= ~LCPLL_CLK_FREQ_MASK; 765 766 switch (cdclk) { 767 default: 768 MISSING_CASE(cdclk); 769 fallthrough; 770 case 337500: 771 val |= LCPLL_CLK_FREQ_337_5_BDW; 772 break; 773 case 450000: 774 val |= LCPLL_CLK_FREQ_450; 775 break; 776 case 540000: 777 val |= LCPLL_CLK_FREQ_54O_BDW; 778 break; 779 case 675000: 780 val |= LCPLL_CLK_FREQ_675_BDW; 781 break; 782 } 783 784 intel_de_write(dev_priv, LCPLL_CTL, val); 785 786 val = intel_de_read(dev_priv, LCPLL_CTL); 787 val &= ~LCPLL_CD_SOURCE_FCLK; 788 intel_de_write(dev_priv, LCPLL_CTL, val); 789 790 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) & 791 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 792 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n"); 793 794 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, 795 cdclk_config->voltage_level); 796 797 intel_de_write(dev_priv, CDCLK_FREQ, 798 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); 799 800 intel_update_cdclk(dev_priv); 801 } 802 803 static int skl_calc_cdclk(int min_cdclk, int vco) 804 { 805 if (vco == 8640000) { 806 if (min_cdclk > 540000) 807 return 617143; 808 else if (min_cdclk > 432000) 809 return 540000; 810 else if (min_cdclk > 308571) 811 return 432000; 812 else 813 return 308571; 814 } else { 815 if (min_cdclk > 540000) 816 return 675000; 817 else if (min_cdclk > 450000) 818 return 540000; 819 else if (min_cdclk > 337500) 820 return 450000; 821 else 822 return 337500; 823 } 824 } 825 826 static u8 skl_calc_voltage_level(int cdclk) 827 { 828 if (cdclk > 540000) 829 return 3; 830 else if (cdclk > 450000) 831 return 2; 832 else if (cdclk > 337500) 833 return 1; 834 else 835 return 0; 836 } 837 838 static void skl_dpll0_update(struct drm_i915_private *dev_priv, 839 struct intel_cdclk_config *cdclk_config) 840 { 841 u32 val; 842 843 cdclk_config->ref = 24000; 844 cdclk_config->vco = 0; 845 846 val = intel_de_read(dev_priv, LCPLL1_CTL); 847 if ((val & LCPLL_PLL_ENABLE) == 0) 848 return; 849 850 if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0)) 851 return; 852 853 val = intel_de_read(dev_priv, DPLL_CTRL1); 854 855 if (drm_WARN_ON(&dev_priv->drm, 856 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 857 DPLL_CTRL1_SSC(SKL_DPLL0) | 858 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != 859 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) 860 return; 861 862 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { 863 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): 864 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): 865 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): 866 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): 867 cdclk_config->vco = 8100000; 868 break; 869 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): 870 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): 871 cdclk_config->vco = 8640000; 872 break; 873 default: 874 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 875 break; 876 } 877 } 878 879 static void skl_get_cdclk(struct drm_i915_private *dev_priv, 880 struct intel_cdclk_config *cdclk_config) 881 { 882 u32 cdctl; 883 884 skl_dpll0_update(dev_priv, cdclk_config); 885 886 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; 887 888 if (cdclk_config->vco == 0) 889 goto out; 890 891 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 892 893 if (cdclk_config->vco == 8640000) { 894 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 895 case CDCLK_FREQ_450_432: 896 cdclk_config->cdclk = 432000; 897 break; 898 case CDCLK_FREQ_337_308: 899 cdclk_config->cdclk = 308571; 900 break; 901 case CDCLK_FREQ_540: 902 cdclk_config->cdclk = 540000; 903 break; 904 case CDCLK_FREQ_675_617: 905 cdclk_config->cdclk = 617143; 906 break; 907 default: 908 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 909 break; 910 } 911 } else { 912 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 913 case CDCLK_FREQ_450_432: 914 cdclk_config->cdclk = 450000; 915 break; 916 case CDCLK_FREQ_337_308: 917 cdclk_config->cdclk = 337500; 918 break; 919 case CDCLK_FREQ_540: 920 cdclk_config->cdclk = 540000; 921 break; 922 case CDCLK_FREQ_675_617: 923 cdclk_config->cdclk = 675000; 924 break; 925 default: 926 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 927 break; 928 } 929 } 930 931 out: 932 /* 933 * Can't read this out :( Let's assume it's 934 * at least what the CDCLK frequency requires. 935 */ 936 cdclk_config->voltage_level = 937 skl_calc_voltage_level(cdclk_config->cdclk); 938 } 939 940 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ 941 static int skl_cdclk_decimal(int cdclk) 942 { 943 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); 944 } 945 946 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, 947 int vco) 948 { 949 bool changed = dev_priv->skl_preferred_vco_freq != vco; 950 951 dev_priv->skl_preferred_vco_freq = vco; 952 953 if (changed) 954 intel_update_max_cdclk(dev_priv); 955 } 956 957 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) 958 { 959 u32 val; 960 961 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); 962 963 /* 964 * We always enable DPLL0 with the lowest link rate possible, but still 965 * taking into account the VCO required to operate the eDP panel at the 966 * desired frequency. The usual DP link rates operate with a VCO of 967 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. 968 * The modeset code is responsible for the selection of the exact link 969 * rate later on, with the constraint of choosing a frequency that 970 * works with vco. 971 */ 972 val = intel_de_read(dev_priv, DPLL_CTRL1); 973 974 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | 975 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 976 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); 977 if (vco == 8640000) 978 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 979 SKL_DPLL0); 980 else 981 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 982 SKL_DPLL0); 983 984 intel_de_write(dev_priv, DPLL_CTRL1, val); 985 intel_de_posting_read(dev_priv, DPLL_CTRL1); 986 987 intel_de_write(dev_priv, LCPLL1_CTL, 988 intel_de_read(dev_priv, LCPLL1_CTL) | LCPLL_PLL_ENABLE); 989 990 if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) 991 drm_err(&dev_priv->drm, "DPLL0 not locked\n"); 992 993 dev_priv->cdclk.hw.vco = vco; 994 995 /* We'll want to keep using the current vco from now on. */ 996 skl_set_preferred_cdclk_vco(dev_priv, vco); 997 } 998 999 static void skl_dpll0_disable(struct drm_i915_private *dev_priv) 1000 { 1001 intel_de_write(dev_priv, LCPLL1_CTL, 1002 intel_de_read(dev_priv, LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); 1003 if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) 1004 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n"); 1005 1006 dev_priv->cdclk.hw.vco = 0; 1007 } 1008 1009 static void skl_set_cdclk(struct drm_i915_private *dev_priv, 1010 const struct intel_cdclk_config *cdclk_config, 1011 enum pipe pipe) 1012 { 1013 int cdclk = cdclk_config->cdclk; 1014 int vco = cdclk_config->vco; 1015 u32 freq_select, cdclk_ctl; 1016 int ret; 1017 1018 /* 1019 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are 1020 * unsupported on SKL. In theory this should never happen since only 1021 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not 1022 * supported on SKL either, see the above WA. WARN whenever trying to 1023 * use the corresponding VCO freq as that always leads to using the 1024 * minimum 308MHz CDCLK. 1025 */ 1026 drm_WARN_ON_ONCE(&dev_priv->drm, 1027 IS_SKYLAKE(dev_priv) && vco == 8640000); 1028 1029 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, 1030 SKL_CDCLK_PREPARE_FOR_CHANGE, 1031 SKL_CDCLK_READY_FOR_CHANGE, 1032 SKL_CDCLK_READY_FOR_CHANGE, 3); 1033 if (ret) { 1034 drm_err(&dev_priv->drm, 1035 "Failed to inform PCU about cdclk change (%d)\n", ret); 1036 return; 1037 } 1038 1039 /* Choose frequency for this cdclk */ 1040 switch (cdclk) { 1041 default: 1042 drm_WARN_ON(&dev_priv->drm, 1043 cdclk != dev_priv->cdclk.hw.bypass); 1044 drm_WARN_ON(&dev_priv->drm, vco != 0); 1045 fallthrough; 1046 case 308571: 1047 case 337500: 1048 freq_select = CDCLK_FREQ_337_308; 1049 break; 1050 case 450000: 1051 case 432000: 1052 freq_select = CDCLK_FREQ_450_432; 1053 break; 1054 case 540000: 1055 freq_select = CDCLK_FREQ_540; 1056 break; 1057 case 617143: 1058 case 675000: 1059 freq_select = CDCLK_FREQ_675_617; 1060 break; 1061 } 1062 1063 if (dev_priv->cdclk.hw.vco != 0 && 1064 dev_priv->cdclk.hw.vco != vco) 1065 skl_dpll0_disable(dev_priv); 1066 1067 cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL); 1068 1069 if (dev_priv->cdclk.hw.vco != vco) { 1070 /* Wa Display #1183: skl,kbl,cfl */ 1071 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1072 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1073 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1074 } 1075 1076 /* Wa Display #1183: skl,kbl,cfl */ 1077 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; 1078 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1079 intel_de_posting_read(dev_priv, CDCLK_CTL); 1080 1081 if (dev_priv->cdclk.hw.vco != vco) 1082 skl_dpll0_enable(dev_priv, vco); 1083 1084 /* Wa Display #1183: skl,kbl,cfl */ 1085 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1086 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1087 1088 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1089 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1090 1091 /* Wa Display #1183: skl,kbl,cfl */ 1092 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; 1093 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1094 intel_de_posting_read(dev_priv, CDCLK_CTL); 1095 1096 /* inform PCU of the change */ 1097 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, 1098 cdclk_config->voltage_level); 1099 1100 intel_update_cdclk(dev_priv); 1101 } 1102 1103 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) 1104 { 1105 u32 cdctl, expected; 1106 1107 /* 1108 * check if the pre-os initialized the display 1109 * There is SWF18 scratchpad register defined which is set by the 1110 * pre-os which can be used by the OS drivers to check the status 1111 */ 1112 if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) 1113 goto sanitize; 1114 1115 intel_update_cdclk(dev_priv); 1116 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK"); 1117 1118 /* Is PLL enabled and locked ? */ 1119 if (dev_priv->cdclk.hw.vco == 0 || 1120 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) 1121 goto sanitize; 1122 1123 /* DPLL okay; verify the cdclock 1124 * 1125 * Noticed in some instances that the freq selection is correct but 1126 * decimal part is programmed wrong from BIOS where pre-os does not 1127 * enable display. Verify the same as well. 1128 */ 1129 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 1130 expected = (cdctl & CDCLK_FREQ_SEL_MASK) | 1131 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); 1132 if (cdctl == expected) 1133 /* All well; nothing to sanitize */ 1134 return; 1135 1136 sanitize: 1137 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); 1138 1139 /* force cdclk programming */ 1140 dev_priv->cdclk.hw.cdclk = 0; 1141 /* force full PLL disable + enable */ 1142 dev_priv->cdclk.hw.vco = -1; 1143 } 1144 1145 static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv) 1146 { 1147 struct intel_cdclk_config cdclk_config; 1148 1149 skl_sanitize_cdclk(dev_priv); 1150 1151 if (dev_priv->cdclk.hw.cdclk != 0 && 1152 dev_priv->cdclk.hw.vco != 0) { 1153 /* 1154 * Use the current vco as our initial 1155 * guess as to what the preferred vco is. 1156 */ 1157 if (dev_priv->skl_preferred_vco_freq == 0) 1158 skl_set_preferred_cdclk_vco(dev_priv, 1159 dev_priv->cdclk.hw.vco); 1160 return; 1161 } 1162 1163 cdclk_config = dev_priv->cdclk.hw; 1164 1165 cdclk_config.vco = dev_priv->skl_preferred_vco_freq; 1166 if (cdclk_config.vco == 0) 1167 cdclk_config.vco = 8100000; 1168 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); 1169 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1170 1171 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1172 } 1173 1174 static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv) 1175 { 1176 struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw; 1177 1178 cdclk_config.cdclk = cdclk_config.bypass; 1179 cdclk_config.vco = 0; 1180 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1181 1182 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1183 } 1184 1185 static const struct intel_cdclk_vals bxt_cdclk_table[] = { 1186 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 }, 1187 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 }, 1188 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 }, 1189 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 }, 1190 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 }, 1191 {} 1192 }; 1193 1194 static const struct intel_cdclk_vals glk_cdclk_table[] = { 1195 { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 }, 1196 { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 }, 1197 { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 }, 1198 {} 1199 }; 1200 1201 static const struct intel_cdclk_vals cnl_cdclk_table[] = { 1202 { .refclk = 19200, .cdclk = 168000, .divider = 4, .ratio = 35 }, 1203 { .refclk = 19200, .cdclk = 336000, .divider = 2, .ratio = 35 }, 1204 { .refclk = 19200, .cdclk = 528000, .divider = 2, .ratio = 55 }, 1205 1206 { .refclk = 24000, .cdclk = 168000, .divider = 4, .ratio = 28 }, 1207 { .refclk = 24000, .cdclk = 336000, .divider = 2, .ratio = 28 }, 1208 { .refclk = 24000, .cdclk = 528000, .divider = 2, .ratio = 44 }, 1209 {} 1210 }; 1211 1212 static const struct intel_cdclk_vals icl_cdclk_table[] = { 1213 { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 }, 1214 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 }, 1215 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 }, 1216 { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 }, 1217 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 }, 1218 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 }, 1219 1220 { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 }, 1221 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 }, 1222 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 }, 1223 { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 }, 1224 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 }, 1225 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 }, 1226 1227 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 }, 1228 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 }, 1229 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 }, 1230 { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 }, 1231 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 }, 1232 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 }, 1233 {} 1234 }; 1235 1236 static const struct intel_cdclk_vals rkl_cdclk_table[] = { 1237 { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 }, 1238 { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 }, 1239 { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 }, 1240 { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 }, 1241 { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 }, 1242 { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 }, 1243 1244 { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 }, 1245 { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 }, 1246 { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 }, 1247 { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 }, 1248 { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 }, 1249 { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 }, 1250 1251 { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 }, 1252 { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 }, 1253 { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 }, 1254 { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 }, 1255 { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 }, 1256 { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 }, 1257 {} 1258 }; 1259 1260 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) 1261 { 1262 const struct intel_cdclk_vals *table = dev_priv->cdclk.table; 1263 int i; 1264 1265 for (i = 0; table[i].refclk; i++) 1266 if (table[i].refclk == dev_priv->cdclk.hw.ref && 1267 table[i].cdclk >= min_cdclk) 1268 return table[i].cdclk; 1269 1270 drm_WARN(&dev_priv->drm, 1, 1271 "Cannot satisfy minimum cdclk %d with refclk %u\n", 1272 min_cdclk, dev_priv->cdclk.hw.ref); 1273 return 0; 1274 } 1275 1276 static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) 1277 { 1278 const struct intel_cdclk_vals *table = dev_priv->cdclk.table; 1279 int i; 1280 1281 if (cdclk == dev_priv->cdclk.hw.bypass) 1282 return 0; 1283 1284 for (i = 0; table[i].refclk; i++) 1285 if (table[i].refclk == dev_priv->cdclk.hw.ref && 1286 table[i].cdclk == cdclk) 1287 return dev_priv->cdclk.hw.ref * table[i].ratio; 1288 1289 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", 1290 cdclk, dev_priv->cdclk.hw.ref); 1291 return 0; 1292 } 1293 1294 static u8 bxt_calc_voltage_level(int cdclk) 1295 { 1296 return DIV_ROUND_UP(cdclk, 25000); 1297 } 1298 1299 static u8 cnl_calc_voltage_level(int cdclk) 1300 { 1301 if (cdclk > 336000) 1302 return 2; 1303 else if (cdclk > 168000) 1304 return 1; 1305 else 1306 return 0; 1307 } 1308 1309 static u8 icl_calc_voltage_level(int cdclk) 1310 { 1311 if (cdclk > 556800) 1312 return 2; 1313 else if (cdclk > 312000) 1314 return 1; 1315 else 1316 return 0; 1317 } 1318 1319 static u8 ehl_calc_voltage_level(int cdclk) 1320 { 1321 if (cdclk > 326400) 1322 return 3; 1323 else if (cdclk > 312000) 1324 return 2; 1325 else if (cdclk > 180000) 1326 return 1; 1327 else 1328 return 0; 1329 } 1330 1331 static u8 tgl_calc_voltage_level(int cdclk) 1332 { 1333 if (cdclk > 556800) 1334 return 3; 1335 else if (cdclk > 326400) 1336 return 2; 1337 else if (cdclk > 312000) 1338 return 1; 1339 else 1340 return 0; 1341 } 1342 1343 static void cnl_readout_refclk(struct drm_i915_private *dev_priv, 1344 struct intel_cdclk_config *cdclk_config) 1345 { 1346 if (intel_de_read(dev_priv, SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz) 1347 cdclk_config->ref = 24000; 1348 else 1349 cdclk_config->ref = 19200; 1350 } 1351 1352 static void icl_readout_refclk(struct drm_i915_private *dev_priv, 1353 struct intel_cdclk_config *cdclk_config) 1354 { 1355 u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; 1356 1357 switch (dssm) { 1358 default: 1359 MISSING_CASE(dssm); 1360 fallthrough; 1361 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz: 1362 cdclk_config->ref = 24000; 1363 break; 1364 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz: 1365 cdclk_config->ref = 19200; 1366 break; 1367 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz: 1368 cdclk_config->ref = 38400; 1369 break; 1370 } 1371 } 1372 1373 static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, 1374 struct intel_cdclk_config *cdclk_config) 1375 { 1376 u32 val, ratio; 1377 1378 if (DISPLAY_VER(dev_priv) >= 11) 1379 icl_readout_refclk(dev_priv, cdclk_config); 1380 else if (IS_CANNONLAKE(dev_priv)) 1381 cnl_readout_refclk(dev_priv, cdclk_config); 1382 else 1383 cdclk_config->ref = 19200; 1384 1385 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE); 1386 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || 1387 (val & BXT_DE_PLL_LOCK) == 0) { 1388 /* 1389 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but 1390 * setting it to zero is a way to signal that. 1391 */ 1392 cdclk_config->vco = 0; 1393 return; 1394 } 1395 1396 /* 1397 * CNL+ have the ratio directly in the PLL enable register, gen9lp had 1398 * it in a separate PLL control register. 1399 */ 1400 if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) 1401 ratio = val & CNL_CDCLK_PLL_RATIO_MASK; 1402 else 1403 ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; 1404 1405 cdclk_config->vco = ratio * cdclk_config->ref; 1406 } 1407 1408 static void bxt_get_cdclk(struct drm_i915_private *dev_priv, 1409 struct intel_cdclk_config *cdclk_config) 1410 { 1411 u32 divider; 1412 int div; 1413 1414 bxt_de_pll_readout(dev_priv, cdclk_config); 1415 1416 if (DISPLAY_VER(dev_priv) >= 12) 1417 cdclk_config->bypass = cdclk_config->ref / 2; 1418 else if (DISPLAY_VER(dev_priv) >= 11) 1419 cdclk_config->bypass = 50000; 1420 else 1421 cdclk_config->bypass = cdclk_config->ref; 1422 1423 if (cdclk_config->vco == 0) { 1424 cdclk_config->cdclk = cdclk_config->bypass; 1425 goto out; 1426 } 1427 1428 divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; 1429 1430 switch (divider) { 1431 case BXT_CDCLK_CD2X_DIV_SEL_1: 1432 div = 2; 1433 break; 1434 case BXT_CDCLK_CD2X_DIV_SEL_1_5: 1435 drm_WARN(&dev_priv->drm, 1436 DISPLAY_VER(dev_priv) >= 10, 1437 "Unsupported divider\n"); 1438 div = 3; 1439 break; 1440 case BXT_CDCLK_CD2X_DIV_SEL_2: 1441 div = 4; 1442 break; 1443 case BXT_CDCLK_CD2X_DIV_SEL_4: 1444 drm_WARN(&dev_priv->drm, 1445 DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv), 1446 "Unsupported divider\n"); 1447 div = 8; 1448 break; 1449 default: 1450 MISSING_CASE(divider); 1451 return; 1452 } 1453 1454 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); 1455 1456 out: 1457 /* 1458 * Can't read this out :( Let's assume it's 1459 * at least what the CDCLK frequency requires. 1460 */ 1461 cdclk_config->voltage_level = 1462 dev_priv->display.calc_voltage_level(cdclk_config->cdclk); 1463 } 1464 1465 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) 1466 { 1467 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0); 1468 1469 /* Timeout 200us */ 1470 if (intel_de_wait_for_clear(dev_priv, 1471 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1472 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n"); 1473 1474 dev_priv->cdclk.hw.vco = 0; 1475 } 1476 1477 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) 1478 { 1479 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); 1480 u32 val; 1481 1482 val = intel_de_read(dev_priv, BXT_DE_PLL_CTL); 1483 val &= ~BXT_DE_PLL_RATIO_MASK; 1484 val |= BXT_DE_PLL_RATIO(ratio); 1485 intel_de_write(dev_priv, BXT_DE_PLL_CTL, val); 1486 1487 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); 1488 1489 /* Timeout 200us */ 1490 if (intel_de_wait_for_set(dev_priv, 1491 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1492 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n"); 1493 1494 dev_priv->cdclk.hw.vco = vco; 1495 } 1496 1497 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv) 1498 { 1499 u32 val; 1500 1501 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE); 1502 val &= ~BXT_DE_PLL_PLL_ENABLE; 1503 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1504 1505 /* Timeout 200us */ 1506 if (wait_for((intel_de_read(dev_priv, BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1)) 1507 drm_err(&dev_priv->drm, 1508 "timeout waiting for CDCLK PLL unlock\n"); 1509 1510 dev_priv->cdclk.hw.vco = 0; 1511 } 1512 1513 static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) 1514 { 1515 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); 1516 u32 val; 1517 1518 val = CNL_CDCLK_PLL_RATIO(ratio); 1519 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1520 1521 val |= BXT_DE_PLL_PLL_ENABLE; 1522 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1523 1524 /* Timeout 200us */ 1525 if (wait_for((intel_de_read(dev_priv, BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1)) 1526 drm_err(&dev_priv->drm, 1527 "timeout waiting for CDCLK PLL lock\n"); 1528 1529 dev_priv->cdclk.hw.vco = vco; 1530 } 1531 1532 static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 1533 { 1534 if (DISPLAY_VER(dev_priv) >= 12) { 1535 if (pipe == INVALID_PIPE) 1536 return TGL_CDCLK_CD2X_PIPE_NONE; 1537 else 1538 return TGL_CDCLK_CD2X_PIPE(pipe); 1539 } else if (DISPLAY_VER(dev_priv) >= 11) { 1540 if (pipe == INVALID_PIPE) 1541 return ICL_CDCLK_CD2X_PIPE_NONE; 1542 else 1543 return ICL_CDCLK_CD2X_PIPE(pipe); 1544 } else { 1545 if (pipe == INVALID_PIPE) 1546 return BXT_CDCLK_CD2X_PIPE_NONE; 1547 else 1548 return BXT_CDCLK_CD2X_PIPE(pipe); 1549 } 1550 } 1551 1552 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 1553 const struct intel_cdclk_config *cdclk_config, 1554 enum pipe pipe) 1555 { 1556 int cdclk = cdclk_config->cdclk; 1557 int vco = cdclk_config->vco; 1558 u32 val, divider; 1559 int ret; 1560 1561 /* Inform power controller of upcoming frequency change. */ 1562 if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) 1563 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, 1564 SKL_CDCLK_PREPARE_FOR_CHANGE, 1565 SKL_CDCLK_READY_FOR_CHANGE, 1566 SKL_CDCLK_READY_FOR_CHANGE, 3); 1567 else 1568 /* 1569 * BSpec requires us to wait up to 150usec, but that leads to 1570 * timeouts; the 2ms used here is based on experiment. 1571 */ 1572 ret = sandybridge_pcode_write_timeout(dev_priv, 1573 HSW_PCODE_DE_WRITE_FREQ_REQ, 1574 0x80000000, 150, 2); 1575 1576 if (ret) { 1577 drm_err(&dev_priv->drm, 1578 "Failed to inform PCU about cdclk change (err %d, freq %d)\n", 1579 ret, cdclk); 1580 return; 1581 } 1582 1583 /* cdclk = vco / 2 / div{1,1.5,2,4} */ 1584 switch (DIV_ROUND_CLOSEST(vco, cdclk)) { 1585 default: 1586 drm_WARN_ON(&dev_priv->drm, 1587 cdclk != dev_priv->cdclk.hw.bypass); 1588 drm_WARN_ON(&dev_priv->drm, vco != 0); 1589 fallthrough; 1590 case 2: 1591 divider = BXT_CDCLK_CD2X_DIV_SEL_1; 1592 break; 1593 case 3: 1594 drm_WARN(&dev_priv->drm, 1595 DISPLAY_VER(dev_priv) >= 10, 1596 "Unsupported divider\n"); 1597 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; 1598 break; 1599 case 4: 1600 divider = BXT_CDCLK_CD2X_DIV_SEL_2; 1601 break; 1602 case 8: 1603 drm_WARN(&dev_priv->drm, 1604 DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv), 1605 "Unsupported divider\n"); 1606 divider = BXT_CDCLK_CD2X_DIV_SEL_4; 1607 break; 1608 } 1609 1610 if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) { 1611 if (dev_priv->cdclk.hw.vco != 0 && 1612 dev_priv->cdclk.hw.vco != vco) 1613 cnl_cdclk_pll_disable(dev_priv); 1614 1615 if (dev_priv->cdclk.hw.vco != vco) 1616 cnl_cdclk_pll_enable(dev_priv, vco); 1617 1618 } else { 1619 if (dev_priv->cdclk.hw.vco != 0 && 1620 dev_priv->cdclk.hw.vco != vco) 1621 bxt_de_pll_disable(dev_priv); 1622 1623 if (dev_priv->cdclk.hw.vco != vco) 1624 bxt_de_pll_enable(dev_priv, vco); 1625 } 1626 1627 val = divider | skl_cdclk_decimal(cdclk) | 1628 bxt_cdclk_cd2x_pipe(dev_priv, pipe); 1629 1630 /* 1631 * Disable SSA Precharge when CD clock frequency < 500 MHz, 1632 * enable otherwise. 1633 */ 1634 if (IS_GEN9_LP(dev_priv) && cdclk >= 500000) 1635 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 1636 intel_de_write(dev_priv, CDCLK_CTL, val); 1637 1638 if (pipe != INVALID_PIPE) 1639 intel_wait_for_vblank(dev_priv, pipe); 1640 1641 if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) { 1642 ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, 1643 cdclk_config->voltage_level); 1644 } else { 1645 /* 1646 * The timeout isn't specified, the 2ms used here is based on 1647 * experiment. 1648 * FIXME: Waiting for the request completion could be delayed 1649 * until the next PCODE request based on BSpec. 1650 */ 1651 ret = sandybridge_pcode_write_timeout(dev_priv, 1652 HSW_PCODE_DE_WRITE_FREQ_REQ, 1653 cdclk_config->voltage_level, 1654 150, 2); 1655 } 1656 1657 if (ret) { 1658 drm_err(&dev_priv->drm, 1659 "PCode CDCLK freq set failed, (err %d, freq %d)\n", 1660 ret, cdclk); 1661 return; 1662 } 1663 1664 intel_update_cdclk(dev_priv); 1665 1666 if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) 1667 /* 1668 * Can't read out the voltage level :( 1669 * Let's just assume everything is as expected. 1670 */ 1671 dev_priv->cdclk.hw.voltage_level = cdclk_config->voltage_level; 1672 } 1673 1674 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) 1675 { 1676 u32 cdctl, expected; 1677 int cdclk, vco; 1678 1679 intel_update_cdclk(dev_priv); 1680 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK"); 1681 1682 if (dev_priv->cdclk.hw.vco == 0 || 1683 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) 1684 goto sanitize; 1685 1686 /* DPLL okay; verify the cdclock 1687 * 1688 * Some BIOS versions leave an incorrect decimal frequency value and 1689 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, 1690 * so sanitize this register. 1691 */ 1692 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 1693 /* 1694 * Let's ignore the pipe field, since BIOS could have configured the 1695 * dividers both synching to an active pipe, or asynchronously 1696 * (PIPE_NONE). 1697 */ 1698 cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); 1699 1700 /* Make sure this is a legal cdclk value for the platform */ 1701 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk); 1702 if (cdclk != dev_priv->cdclk.hw.cdclk) 1703 goto sanitize; 1704 1705 /* Make sure the VCO is correct for the cdclk */ 1706 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 1707 if (vco != dev_priv->cdclk.hw.vco) 1708 goto sanitize; 1709 1710 expected = skl_cdclk_decimal(cdclk); 1711 1712 /* Figure out what CD2X divider we should be using for this cdclk */ 1713 switch (DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.vco, 1714 dev_priv->cdclk.hw.cdclk)) { 1715 case 2: 1716 expected |= BXT_CDCLK_CD2X_DIV_SEL_1; 1717 break; 1718 case 3: 1719 expected |= BXT_CDCLK_CD2X_DIV_SEL_1_5; 1720 break; 1721 case 4: 1722 expected |= BXT_CDCLK_CD2X_DIV_SEL_2; 1723 break; 1724 case 8: 1725 expected |= BXT_CDCLK_CD2X_DIV_SEL_4; 1726 break; 1727 default: 1728 goto sanitize; 1729 } 1730 1731 /* 1732 * Disable SSA Precharge when CD clock frequency < 500 MHz, 1733 * enable otherwise. 1734 */ 1735 if (IS_GEN9_LP(dev_priv) && dev_priv->cdclk.hw.cdclk >= 500000) 1736 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 1737 1738 if (cdctl == expected) 1739 /* All well; nothing to sanitize */ 1740 return; 1741 1742 sanitize: 1743 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); 1744 1745 /* force cdclk programming */ 1746 dev_priv->cdclk.hw.cdclk = 0; 1747 1748 /* force full PLL disable + enable */ 1749 dev_priv->cdclk.hw.vco = -1; 1750 } 1751 1752 static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv) 1753 { 1754 struct intel_cdclk_config cdclk_config; 1755 1756 bxt_sanitize_cdclk(dev_priv); 1757 1758 if (dev_priv->cdclk.hw.cdclk != 0 && 1759 dev_priv->cdclk.hw.vco != 0) 1760 return; 1761 1762 cdclk_config = dev_priv->cdclk.hw; 1763 1764 /* 1765 * FIXME: 1766 * - The initial CDCLK needs to be read from VBT. 1767 * Need to make this change after VBT has changes for BXT. 1768 */ 1769 cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0); 1770 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); 1771 cdclk_config.voltage_level = 1772 dev_priv->display.calc_voltage_level(cdclk_config.cdclk); 1773 1774 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1775 } 1776 1777 static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv) 1778 { 1779 struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw; 1780 1781 cdclk_config.cdclk = cdclk_config.bypass; 1782 cdclk_config.vco = 0; 1783 cdclk_config.voltage_level = 1784 dev_priv->display.calc_voltage_level(cdclk_config.cdclk); 1785 1786 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1787 } 1788 1789 /** 1790 * intel_cdclk_init_hw - Initialize CDCLK hardware 1791 * @i915: i915 device 1792 * 1793 * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and 1794 * sanitizing the state of the hardware if needed. This is generally done only 1795 * during the display core initialization sequence, after which the DMC will 1796 * take care of turning CDCLK off/on as needed. 1797 */ 1798 void intel_cdclk_init_hw(struct drm_i915_private *i915) 1799 { 1800 if (IS_GEN9_LP(i915) || DISPLAY_VER(i915) >= 10) 1801 bxt_cdclk_init_hw(i915); 1802 else if (IS_GEN9_BC(i915)) 1803 skl_cdclk_init_hw(i915); 1804 } 1805 1806 /** 1807 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware 1808 * @i915: i915 device 1809 * 1810 * Uninitialize CDCLK. This is done only during the display core 1811 * uninitialization sequence. 1812 */ 1813 void intel_cdclk_uninit_hw(struct drm_i915_private *i915) 1814 { 1815 if (DISPLAY_VER(i915) >= 10 || IS_GEN9_LP(i915)) 1816 bxt_cdclk_uninit_hw(i915); 1817 else if (IS_GEN9_BC(i915)) 1818 skl_cdclk_uninit_hw(i915); 1819 } 1820 1821 /** 1822 * intel_cdclk_needs_modeset - Determine if changong between the CDCLK 1823 * configurations requires a modeset on all pipes 1824 * @a: first CDCLK configuration 1825 * @b: second CDCLK configuration 1826 * 1827 * Returns: 1828 * True if changing between the two CDCLK configurations 1829 * requires all pipes to be off, false if not. 1830 */ 1831 bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a, 1832 const struct intel_cdclk_config *b) 1833 { 1834 return a->cdclk != b->cdclk || 1835 a->vco != b->vco || 1836 a->ref != b->ref; 1837 } 1838 1839 /** 1840 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK 1841 * configurations requires only a cd2x divider update 1842 * @dev_priv: i915 device 1843 * @a: first CDCLK configuration 1844 * @b: second CDCLK configuration 1845 * 1846 * Returns: 1847 * True if changing between the two CDCLK configurations 1848 * can be done with just a cd2x divider update, false if not. 1849 */ 1850 static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, 1851 const struct intel_cdclk_config *a, 1852 const struct intel_cdclk_config *b) 1853 { 1854 /* Older hw doesn't have the capability */ 1855 if (DISPLAY_VER(dev_priv) < 10 && !IS_GEN9_LP(dev_priv)) 1856 return false; 1857 1858 return a->cdclk != b->cdclk && 1859 a->vco == b->vco && 1860 a->ref == b->ref; 1861 } 1862 1863 /** 1864 * intel_cdclk_changed - Determine if two CDCLK configurations are different 1865 * @a: first CDCLK configuration 1866 * @b: second CDCLK configuration 1867 * 1868 * Returns: 1869 * True if the CDCLK configurations don't match, false if they do. 1870 */ 1871 static bool intel_cdclk_changed(const struct intel_cdclk_config *a, 1872 const struct intel_cdclk_config *b) 1873 { 1874 return intel_cdclk_needs_modeset(a, b) || 1875 a->voltage_level != b->voltage_level; 1876 } 1877 1878 void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config, 1879 const char *context) 1880 { 1881 DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", 1882 context, cdclk_config->cdclk, cdclk_config->vco, 1883 cdclk_config->ref, cdclk_config->bypass, 1884 cdclk_config->voltage_level); 1885 } 1886 1887 /** 1888 * intel_set_cdclk - Push the CDCLK configuration to the hardware 1889 * @dev_priv: i915 device 1890 * @cdclk_config: new CDCLK configuration 1891 * @pipe: pipe with which to synchronize the update 1892 * 1893 * Program the hardware based on the passed in CDCLK state, 1894 * if necessary. 1895 */ 1896 static void intel_set_cdclk(struct drm_i915_private *dev_priv, 1897 const struct intel_cdclk_config *cdclk_config, 1898 enum pipe pipe) 1899 { 1900 struct intel_encoder *encoder; 1901 1902 if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config)) 1903 return; 1904 1905 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.set_cdclk)) 1906 return; 1907 1908 intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to"); 1909 1910 /* 1911 * Lock aux/gmbus while we change cdclk in case those 1912 * functions use cdclk. Not all platforms/ports do, 1913 * but we'll lock them all for simplicity. 1914 */ 1915 mutex_lock(&dev_priv->gmbus_mutex); 1916 for_each_intel_dp(&dev_priv->drm, encoder) { 1917 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1918 1919 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, 1920 &dev_priv->gmbus_mutex); 1921 } 1922 1923 dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe); 1924 1925 for_each_intel_dp(&dev_priv->drm, encoder) { 1926 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1927 1928 mutex_unlock(&intel_dp->aux.hw_mutex); 1929 } 1930 mutex_unlock(&dev_priv->gmbus_mutex); 1931 1932 if (drm_WARN(&dev_priv->drm, 1933 intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config), 1934 "cdclk state doesn't match!\n")) { 1935 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "[hw state]"); 1936 intel_dump_cdclk_config(cdclk_config, "[sw state]"); 1937 } 1938 } 1939 1940 /** 1941 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware 1942 * @state: intel atomic state 1943 * 1944 * Program the hardware before updating the HW plane state based on the 1945 * new CDCLK state, if necessary. 1946 */ 1947 void 1948 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) 1949 { 1950 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1951 const struct intel_cdclk_state *old_cdclk_state = 1952 intel_atomic_get_old_cdclk_state(state); 1953 const struct intel_cdclk_state *new_cdclk_state = 1954 intel_atomic_get_new_cdclk_state(state); 1955 enum pipe pipe = new_cdclk_state->pipe; 1956 1957 if (!intel_cdclk_changed(&old_cdclk_state->actual, 1958 &new_cdclk_state->actual)) 1959 return; 1960 1961 if (pipe == INVALID_PIPE || 1962 old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) { 1963 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); 1964 1965 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); 1966 } 1967 } 1968 1969 /** 1970 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware 1971 * @state: intel atomic state 1972 * 1973 * Program the hardware after updating the HW plane state based on the 1974 * new CDCLK state, if necessary. 1975 */ 1976 void 1977 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) 1978 { 1979 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1980 const struct intel_cdclk_state *old_cdclk_state = 1981 intel_atomic_get_old_cdclk_state(state); 1982 const struct intel_cdclk_state *new_cdclk_state = 1983 intel_atomic_get_new_cdclk_state(state); 1984 enum pipe pipe = new_cdclk_state->pipe; 1985 1986 if (!intel_cdclk_changed(&old_cdclk_state->actual, 1987 &new_cdclk_state->actual)) 1988 return; 1989 1990 if (pipe != INVALID_PIPE && 1991 old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) { 1992 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); 1993 1994 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); 1995 } 1996 } 1997 1998 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) 1999 { 2000 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2001 int pixel_rate = crtc_state->pixel_rate; 2002 2003 if (DISPLAY_VER(dev_priv) >= 10) 2004 return DIV_ROUND_UP(pixel_rate, 2); 2005 else if (IS_DISPLAY_VER(dev_priv, 9) || 2006 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2007 return pixel_rate; 2008 else if (IS_CHERRYVIEW(dev_priv)) 2009 return DIV_ROUND_UP(pixel_rate * 100, 95); 2010 else if (crtc_state->double_wide) 2011 return DIV_ROUND_UP(pixel_rate * 100, 90 * 2); 2012 else 2013 return DIV_ROUND_UP(pixel_rate * 100, 90); 2014 } 2015 2016 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) 2017 { 2018 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2019 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2020 struct intel_plane *plane; 2021 int min_cdclk = 0; 2022 2023 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 2024 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk); 2025 2026 return min_cdclk; 2027 } 2028 2029 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) 2030 { 2031 struct drm_i915_private *dev_priv = 2032 to_i915(crtc_state->uapi.crtc->dev); 2033 int min_cdclk; 2034 2035 if (!crtc_state->hw.enable) 2036 return 0; 2037 2038 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state); 2039 2040 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ 2041 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state)) 2042 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95); 2043 2044 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, 2045 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else 2046 * there may be audio corruption or screen corruption." This cdclk 2047 * restriction for GLK is 316.8 MHz. 2048 */ 2049 if (intel_crtc_has_dp_encoder(crtc_state) && 2050 crtc_state->has_audio && 2051 crtc_state->port_clock >= 540000 && 2052 crtc_state->lane_count == 4) { 2053 if (IS_DISPLAY_VER(dev_priv, 10)) { 2054 /* Display WA #1145: glk,cnl */ 2055 min_cdclk = max(316800, min_cdclk); 2056 } else if (IS_DISPLAY_VER(dev_priv, 9) || IS_BROADWELL(dev_priv)) { 2057 /* Display WA #1144: skl,bxt */ 2058 min_cdclk = max(432000, min_cdclk); 2059 } 2060 } 2061 2062 /* 2063 * According to BSpec, "The CD clock frequency must be at least twice 2064 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. 2065 */ 2066 if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9) 2067 min_cdclk = max(2 * 96000, min_cdclk); 2068 2069 /* 2070 * "For DP audio configuration, cdclk frequency shall be set to 2071 * meet the following requirements: 2072 * DP Link Frequency(MHz) | Cdclk frequency(MHz) 2073 * 270 | 320 or higher 2074 * 162 | 200 or higher" 2075 */ 2076 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2077 intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio) 2078 min_cdclk = max(crtc_state->port_clock, min_cdclk); 2079 2080 /* 2081 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower 2082 * than 320000KHz. 2083 */ 2084 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 2085 IS_VALLEYVIEW(dev_priv)) 2086 min_cdclk = max(320000, min_cdclk); 2087 2088 /* 2089 * On Geminilake once the CDCLK gets as low as 79200 2090 * picture gets unstable, despite that values are 2091 * correct for DSI PLL and DE PLL. 2092 */ 2093 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 2094 IS_GEMINILAKE(dev_priv)) 2095 min_cdclk = max(158400, min_cdclk); 2096 2097 /* Account for additional needs from the planes */ 2098 min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); 2099 2100 /* 2101 * HACK. Currently for TGL platforms we calculate 2102 * min_cdclk initially based on pixel_rate divided 2103 * by 2, accounting for also plane requirements, 2104 * however in some cases the lowest possible CDCLK 2105 * doesn't work and causing the underruns. 2106 * Explicitly stating here that this seems to be currently 2107 * rather a Hack, than final solution. 2108 */ 2109 if (IS_TIGERLAKE(dev_priv)) { 2110 /* 2111 * Clamp to max_cdclk_freq in case pixel rate is higher, 2112 * in order not to break an 8K, but still leave W/A at place. 2113 */ 2114 min_cdclk = max_t(int, min_cdclk, 2115 min_t(int, crtc_state->pixel_rate, 2116 dev_priv->max_cdclk_freq)); 2117 } 2118 2119 if (min_cdclk > dev_priv->max_cdclk_freq) { 2120 drm_dbg_kms(&dev_priv->drm, 2121 "required cdclk (%d kHz) exceeds max (%d kHz)\n", 2122 min_cdclk, dev_priv->max_cdclk_freq); 2123 return -EINVAL; 2124 } 2125 2126 return min_cdclk; 2127 } 2128 2129 static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) 2130 { 2131 struct intel_atomic_state *state = cdclk_state->base.state; 2132 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2133 struct intel_bw_state *bw_state = NULL; 2134 struct intel_crtc *crtc; 2135 struct intel_crtc_state *crtc_state; 2136 int min_cdclk, i; 2137 enum pipe pipe; 2138 2139 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2140 int ret; 2141 2142 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 2143 if (min_cdclk < 0) 2144 return min_cdclk; 2145 2146 bw_state = intel_atomic_get_bw_state(state); 2147 if (IS_ERR(bw_state)) 2148 return PTR_ERR(bw_state); 2149 2150 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk) 2151 continue; 2152 2153 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 2154 2155 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2156 if (ret) 2157 return ret; 2158 } 2159 2160 min_cdclk = cdclk_state->force_min_cdclk; 2161 for_each_pipe(dev_priv, pipe) { 2162 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); 2163 2164 if (!bw_state) 2165 continue; 2166 2167 min_cdclk = max(bw_state->min_cdclk, min_cdclk); 2168 } 2169 2170 return min_cdclk; 2171 } 2172 2173 /* 2174 * Account for port clock min voltage level requirements. 2175 * This only really does something on CNL+ but can be 2176 * called on earlier platforms as well. 2177 * 2178 * Note that this functions assumes that 0 is 2179 * the lowest voltage value, and higher values 2180 * correspond to increasingly higher voltages. 2181 * 2182 * Should that relationship no longer hold on 2183 * future platforms this code will need to be 2184 * adjusted. 2185 */ 2186 static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state) 2187 { 2188 struct intel_atomic_state *state = cdclk_state->base.state; 2189 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2190 struct intel_crtc *crtc; 2191 struct intel_crtc_state *crtc_state; 2192 u8 min_voltage_level; 2193 int i; 2194 enum pipe pipe; 2195 2196 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2197 int ret; 2198 2199 if (crtc_state->hw.enable) 2200 min_voltage_level = crtc_state->min_voltage_level; 2201 else 2202 min_voltage_level = 0; 2203 2204 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level) 2205 continue; 2206 2207 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level; 2208 2209 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2210 if (ret) 2211 return ret; 2212 } 2213 2214 min_voltage_level = 0; 2215 for_each_pipe(dev_priv, pipe) 2216 min_voltage_level = max(cdclk_state->min_voltage_level[pipe], 2217 min_voltage_level); 2218 2219 return min_voltage_level; 2220 } 2221 2222 static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2223 { 2224 struct intel_atomic_state *state = cdclk_state->base.state; 2225 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2226 int min_cdclk, cdclk; 2227 2228 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2229 if (min_cdclk < 0) 2230 return min_cdclk; 2231 2232 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); 2233 2234 cdclk_state->logical.cdclk = cdclk; 2235 cdclk_state->logical.voltage_level = 2236 vlv_calc_voltage_level(dev_priv, cdclk); 2237 2238 if (!cdclk_state->active_pipes) { 2239 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); 2240 2241 cdclk_state->actual.cdclk = cdclk; 2242 cdclk_state->actual.voltage_level = 2243 vlv_calc_voltage_level(dev_priv, cdclk); 2244 } else { 2245 cdclk_state->actual = cdclk_state->logical; 2246 } 2247 2248 return 0; 2249 } 2250 2251 static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2252 { 2253 int min_cdclk, cdclk; 2254 2255 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2256 if (min_cdclk < 0) 2257 return min_cdclk; 2258 2259 /* 2260 * FIXME should also account for plane ratio 2261 * once 64bpp pixel formats are supported. 2262 */ 2263 cdclk = bdw_calc_cdclk(min_cdclk); 2264 2265 cdclk_state->logical.cdclk = cdclk; 2266 cdclk_state->logical.voltage_level = 2267 bdw_calc_voltage_level(cdclk); 2268 2269 if (!cdclk_state->active_pipes) { 2270 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); 2271 2272 cdclk_state->actual.cdclk = cdclk; 2273 cdclk_state->actual.voltage_level = 2274 bdw_calc_voltage_level(cdclk); 2275 } else { 2276 cdclk_state->actual = cdclk_state->logical; 2277 } 2278 2279 return 0; 2280 } 2281 2282 static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state) 2283 { 2284 struct intel_atomic_state *state = cdclk_state->base.state; 2285 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2286 struct intel_crtc *crtc; 2287 struct intel_crtc_state *crtc_state; 2288 int vco, i; 2289 2290 vco = cdclk_state->logical.vco; 2291 if (!vco) 2292 vco = dev_priv->skl_preferred_vco_freq; 2293 2294 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2295 if (!crtc_state->hw.enable) 2296 continue; 2297 2298 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 2299 continue; 2300 2301 /* 2302 * DPLL0 VCO may need to be adjusted to get the correct 2303 * clock for eDP. This will affect cdclk as well. 2304 */ 2305 switch (crtc_state->port_clock / 2) { 2306 case 108000: 2307 case 216000: 2308 vco = 8640000; 2309 break; 2310 default: 2311 vco = 8100000; 2312 break; 2313 } 2314 } 2315 2316 return vco; 2317 } 2318 2319 static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2320 { 2321 int min_cdclk, cdclk, vco; 2322 2323 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2324 if (min_cdclk < 0) 2325 return min_cdclk; 2326 2327 vco = skl_dpll0_vco(cdclk_state); 2328 2329 /* 2330 * FIXME should also account for plane ratio 2331 * once 64bpp pixel formats are supported. 2332 */ 2333 cdclk = skl_calc_cdclk(min_cdclk, vco); 2334 2335 cdclk_state->logical.vco = vco; 2336 cdclk_state->logical.cdclk = cdclk; 2337 cdclk_state->logical.voltage_level = 2338 skl_calc_voltage_level(cdclk); 2339 2340 if (!cdclk_state->active_pipes) { 2341 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); 2342 2343 cdclk_state->actual.vco = vco; 2344 cdclk_state->actual.cdclk = cdclk; 2345 cdclk_state->actual.voltage_level = 2346 skl_calc_voltage_level(cdclk); 2347 } else { 2348 cdclk_state->actual = cdclk_state->logical; 2349 } 2350 2351 return 0; 2352 } 2353 2354 static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2355 { 2356 struct intel_atomic_state *state = cdclk_state->base.state; 2357 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2358 int min_cdclk, min_voltage_level, cdclk, vco; 2359 2360 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2361 if (min_cdclk < 0) 2362 return min_cdclk; 2363 2364 min_voltage_level = bxt_compute_min_voltage_level(cdclk_state); 2365 if (min_voltage_level < 0) 2366 return min_voltage_level; 2367 2368 cdclk = bxt_calc_cdclk(dev_priv, min_cdclk); 2369 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 2370 2371 cdclk_state->logical.vco = vco; 2372 cdclk_state->logical.cdclk = cdclk; 2373 cdclk_state->logical.voltage_level = 2374 max_t(int, min_voltage_level, 2375 dev_priv->display.calc_voltage_level(cdclk)); 2376 2377 if (!cdclk_state->active_pipes) { 2378 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); 2379 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 2380 2381 cdclk_state->actual.vco = vco; 2382 cdclk_state->actual.cdclk = cdclk; 2383 cdclk_state->actual.voltage_level = 2384 dev_priv->display.calc_voltage_level(cdclk); 2385 } else { 2386 cdclk_state->actual = cdclk_state->logical; 2387 } 2388 2389 return 0; 2390 } 2391 2392 static int intel_modeset_all_pipes(struct intel_atomic_state *state) 2393 { 2394 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2395 struct intel_crtc *crtc; 2396 2397 /* 2398 * Add all pipes to the state, and force 2399 * a modeset on all the active ones. 2400 */ 2401 for_each_intel_crtc(&dev_priv->drm, crtc) { 2402 struct intel_crtc_state *crtc_state; 2403 int ret; 2404 2405 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 2406 if (IS_ERR(crtc_state)) 2407 return PTR_ERR(crtc_state); 2408 2409 if (!crtc_state->hw.active || 2410 drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) 2411 continue; 2412 2413 crtc_state->uapi.mode_changed = true; 2414 2415 ret = drm_atomic_add_affected_connectors(&state->base, 2416 &crtc->base); 2417 if (ret) 2418 return ret; 2419 2420 ret = intel_atomic_add_affected_planes(state, crtc); 2421 if (ret) 2422 return ret; 2423 2424 crtc_state->update_planes |= crtc_state->active_planes; 2425 } 2426 2427 return 0; 2428 } 2429 2430 static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2431 { 2432 int min_cdclk; 2433 2434 /* 2435 * We can't change the cdclk frequency, but we still want to 2436 * check that the required minimum frequency doesn't exceed 2437 * the actual cdclk frequency. 2438 */ 2439 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2440 if (min_cdclk < 0) 2441 return min_cdclk; 2442 2443 return 0; 2444 } 2445 2446 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj) 2447 { 2448 struct intel_cdclk_state *cdclk_state; 2449 2450 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); 2451 if (!cdclk_state) 2452 return NULL; 2453 2454 cdclk_state->pipe = INVALID_PIPE; 2455 2456 return &cdclk_state->base; 2457 } 2458 2459 static void intel_cdclk_destroy_state(struct intel_global_obj *obj, 2460 struct intel_global_state *state) 2461 { 2462 kfree(state); 2463 } 2464 2465 static const struct intel_global_state_funcs intel_cdclk_funcs = { 2466 .atomic_duplicate_state = intel_cdclk_duplicate_state, 2467 .atomic_destroy_state = intel_cdclk_destroy_state, 2468 }; 2469 2470 struct intel_cdclk_state * 2471 intel_atomic_get_cdclk_state(struct intel_atomic_state *state) 2472 { 2473 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2474 struct intel_global_state *cdclk_state; 2475 2476 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->cdclk.obj); 2477 if (IS_ERR(cdclk_state)) 2478 return ERR_CAST(cdclk_state); 2479 2480 return to_intel_cdclk_state(cdclk_state); 2481 } 2482 2483 int intel_cdclk_init(struct drm_i915_private *dev_priv) 2484 { 2485 struct intel_cdclk_state *cdclk_state; 2486 2487 cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL); 2488 if (!cdclk_state) 2489 return -ENOMEM; 2490 2491 intel_atomic_global_obj_init(dev_priv, &dev_priv->cdclk.obj, 2492 &cdclk_state->base, &intel_cdclk_funcs); 2493 2494 return 0; 2495 } 2496 2497 int intel_modeset_calc_cdclk(struct intel_atomic_state *state) 2498 { 2499 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2500 const struct intel_cdclk_state *old_cdclk_state; 2501 struct intel_cdclk_state *new_cdclk_state; 2502 enum pipe pipe; 2503 int ret; 2504 2505 new_cdclk_state = intel_atomic_get_cdclk_state(state); 2506 if (IS_ERR(new_cdclk_state)) 2507 return PTR_ERR(new_cdclk_state); 2508 2509 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 2510 2511 new_cdclk_state->active_pipes = 2512 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); 2513 2514 ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state); 2515 if (ret) 2516 return ret; 2517 2518 if (intel_cdclk_changed(&old_cdclk_state->actual, 2519 &new_cdclk_state->actual)) { 2520 /* 2521 * Also serialize commits across all crtcs 2522 * if the actual hw needs to be poked. 2523 */ 2524 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); 2525 if (ret) 2526 return ret; 2527 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes || 2528 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk || 2529 intel_cdclk_changed(&old_cdclk_state->logical, 2530 &new_cdclk_state->logical)) { 2531 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 2532 if (ret) 2533 return ret; 2534 } else { 2535 return 0; 2536 } 2537 2538 if (is_power_of_2(new_cdclk_state->active_pipes) && 2539 intel_cdclk_can_cd2x_update(dev_priv, 2540 &old_cdclk_state->actual, 2541 &new_cdclk_state->actual)) { 2542 struct intel_crtc *crtc; 2543 struct intel_crtc_state *crtc_state; 2544 2545 pipe = ilog2(new_cdclk_state->active_pipes); 2546 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 2547 2548 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 2549 if (IS_ERR(crtc_state)) 2550 return PTR_ERR(crtc_state); 2551 2552 if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) 2553 pipe = INVALID_PIPE; 2554 } else { 2555 pipe = INVALID_PIPE; 2556 } 2557 2558 if (pipe != INVALID_PIPE) { 2559 new_cdclk_state->pipe = pipe; 2560 2561 drm_dbg_kms(&dev_priv->drm, 2562 "Can change cdclk with pipe %c active\n", 2563 pipe_name(pipe)); 2564 } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual, 2565 &new_cdclk_state->actual)) { 2566 /* All pipes must be switched off while we change the cdclk. */ 2567 ret = intel_modeset_all_pipes(state); 2568 if (ret) 2569 return ret; 2570 2571 new_cdclk_state->pipe = INVALID_PIPE; 2572 2573 drm_dbg_kms(&dev_priv->drm, 2574 "Modeset required for cdclk change\n"); 2575 } 2576 2577 drm_dbg_kms(&dev_priv->drm, 2578 "New cdclk calculated to be logical %u kHz, actual %u kHz\n", 2579 new_cdclk_state->logical.cdclk, 2580 new_cdclk_state->actual.cdclk); 2581 drm_dbg_kms(&dev_priv->drm, 2582 "New voltage level calculated to be logical %u, actual %u\n", 2583 new_cdclk_state->logical.voltage_level, 2584 new_cdclk_state->actual.voltage_level); 2585 2586 return 0; 2587 } 2588 2589 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) 2590 { 2591 int max_cdclk_freq = dev_priv->max_cdclk_freq; 2592 2593 if (DISPLAY_VER(dev_priv) >= 10) 2594 return 2 * max_cdclk_freq; 2595 else if (IS_DISPLAY_VER(dev_priv, 9) || 2596 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2597 return max_cdclk_freq; 2598 else if (IS_CHERRYVIEW(dev_priv)) 2599 return max_cdclk_freq*95/100; 2600 else if (DISPLAY_VER(dev_priv) < 4) 2601 return 2*max_cdclk_freq*90/100; 2602 else 2603 return max_cdclk_freq*90/100; 2604 } 2605 2606 /** 2607 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency 2608 * @dev_priv: i915 device 2609 * 2610 * Determine the maximum CDCLK frequency the platform supports, and also 2611 * derive the maximum dot clock frequency the maximum CDCLK frequency 2612 * allows. 2613 */ 2614 void intel_update_max_cdclk(struct drm_i915_private *dev_priv) 2615 { 2616 if (IS_JSL_EHL(dev_priv)) { 2617 if (dev_priv->cdclk.hw.ref == 24000) 2618 dev_priv->max_cdclk_freq = 552000; 2619 else 2620 dev_priv->max_cdclk_freq = 556800; 2621 } else if (DISPLAY_VER(dev_priv) >= 11) { 2622 if (dev_priv->cdclk.hw.ref == 24000) 2623 dev_priv->max_cdclk_freq = 648000; 2624 else 2625 dev_priv->max_cdclk_freq = 652800; 2626 } else if (IS_CANNONLAKE(dev_priv)) { 2627 dev_priv->max_cdclk_freq = 528000; 2628 } else if (IS_GEN9_BC(dev_priv)) { 2629 u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; 2630 int max_cdclk, vco; 2631 2632 vco = dev_priv->skl_preferred_vco_freq; 2633 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); 2634 2635 /* 2636 * Use the lower (vco 8640) cdclk values as a 2637 * first guess. skl_calc_cdclk() will correct it 2638 * if the preferred vco is 8100 instead. 2639 */ 2640 if (limit == SKL_DFSM_CDCLK_LIMIT_675) 2641 max_cdclk = 617143; 2642 else if (limit == SKL_DFSM_CDCLK_LIMIT_540) 2643 max_cdclk = 540000; 2644 else if (limit == SKL_DFSM_CDCLK_LIMIT_450) 2645 max_cdclk = 432000; 2646 else 2647 max_cdclk = 308571; 2648 2649 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); 2650 } else if (IS_GEMINILAKE(dev_priv)) { 2651 dev_priv->max_cdclk_freq = 316800; 2652 } else if (IS_BROXTON(dev_priv)) { 2653 dev_priv->max_cdclk_freq = 624000; 2654 } else if (IS_BROADWELL(dev_priv)) { 2655 /* 2656 * FIXME with extra cooling we can allow 2657 * 540 MHz for ULX and 675 Mhz for ULT. 2658 * How can we know if extra cooling is 2659 * available? PCI ID, VTB, something else? 2660 */ 2661 if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 2662 dev_priv->max_cdclk_freq = 450000; 2663 else if (IS_BDW_ULX(dev_priv)) 2664 dev_priv->max_cdclk_freq = 450000; 2665 else if (IS_BDW_ULT(dev_priv)) 2666 dev_priv->max_cdclk_freq = 540000; 2667 else 2668 dev_priv->max_cdclk_freq = 675000; 2669 } else if (IS_CHERRYVIEW(dev_priv)) { 2670 dev_priv->max_cdclk_freq = 320000; 2671 } else if (IS_VALLEYVIEW(dev_priv)) { 2672 dev_priv->max_cdclk_freq = 400000; 2673 } else { 2674 /* otherwise assume cdclk is fixed */ 2675 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk; 2676 } 2677 2678 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); 2679 2680 drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n", 2681 dev_priv->max_cdclk_freq); 2682 2683 drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n", 2684 dev_priv->max_dotclk_freq); 2685 } 2686 2687 /** 2688 * intel_update_cdclk - Determine the current CDCLK frequency 2689 * @dev_priv: i915 device 2690 * 2691 * Determine the current CDCLK frequency. 2692 */ 2693 void intel_update_cdclk(struct drm_i915_private *dev_priv) 2694 { 2695 dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw); 2696 2697 /* 2698 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): 2699 * Programmng [sic] note: bit[9:2] should be programmed to the number 2700 * of cdclk that generates 4MHz reference clock freq which is used to 2701 * generate GMBus clock. This will vary with the cdclk freq. 2702 */ 2703 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 2704 intel_de_write(dev_priv, GMBUSFREQ_VLV, 2705 DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000)); 2706 } 2707 2708 static int dg1_rawclk(struct drm_i915_private *dev_priv) 2709 { 2710 /* 2711 * DG1 always uses a 38.4 MHz rawclk. The bspec tells us 2712 * "Program Numerator=2, Denominator=4, Divider=37 decimal." 2713 */ 2714 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, 2715 CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2)); 2716 2717 return 38400; 2718 } 2719 2720 static int cnp_rawclk(struct drm_i915_private *dev_priv) 2721 { 2722 u32 rawclk; 2723 int divider, fraction; 2724 2725 if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { 2726 /* 24 MHz */ 2727 divider = 24000; 2728 fraction = 0; 2729 } else { 2730 /* 19.2 MHz */ 2731 divider = 19000; 2732 fraction = 200; 2733 } 2734 2735 rawclk = CNP_RAWCLK_DIV(divider / 1000); 2736 if (fraction) { 2737 int numerator = 1; 2738 2739 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000, 2740 fraction) - 1); 2741 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 2742 rawclk |= ICP_RAWCLK_NUM(numerator); 2743 } 2744 2745 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk); 2746 return divider + fraction; 2747 } 2748 2749 static int pch_rawclk(struct drm_i915_private *dev_priv) 2750 { 2751 return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; 2752 } 2753 2754 static int vlv_hrawclk(struct drm_i915_private *dev_priv) 2755 { 2756 /* RAWCLK_FREQ_VLV register updated from power well code */ 2757 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", 2758 CCK_DISPLAY_REF_CLOCK_CONTROL); 2759 } 2760 2761 static int i9xx_hrawclk(struct drm_i915_private *dev_priv) 2762 { 2763 u32 clkcfg; 2764 2765 /* 2766 * hrawclock is 1/4 the FSB frequency 2767 * 2768 * Note that this only reads the state of the FSB 2769 * straps, not the actual FSB frequency. Some BIOSen 2770 * let you configure each independently. Ideally we'd 2771 * read out the actual FSB frequency but sadly we 2772 * don't know which registers have that information, 2773 * and all the relevant docs have gone to bit heaven :( 2774 */ 2775 clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK; 2776 2777 if (IS_MOBILE(dev_priv)) { 2778 switch (clkcfg) { 2779 case CLKCFG_FSB_400: 2780 return 100000; 2781 case CLKCFG_FSB_533: 2782 return 133333; 2783 case CLKCFG_FSB_667: 2784 return 166667; 2785 case CLKCFG_FSB_800: 2786 return 200000; 2787 case CLKCFG_FSB_1067: 2788 return 266667; 2789 case CLKCFG_FSB_1333: 2790 return 333333; 2791 default: 2792 MISSING_CASE(clkcfg); 2793 return 133333; 2794 } 2795 } else { 2796 switch (clkcfg) { 2797 case CLKCFG_FSB_400_ALT: 2798 return 100000; 2799 case CLKCFG_FSB_533: 2800 return 133333; 2801 case CLKCFG_FSB_667: 2802 return 166667; 2803 case CLKCFG_FSB_800: 2804 return 200000; 2805 case CLKCFG_FSB_1067_ALT: 2806 return 266667; 2807 case CLKCFG_FSB_1333_ALT: 2808 return 333333; 2809 case CLKCFG_FSB_1600_ALT: 2810 return 400000; 2811 default: 2812 return 133333; 2813 } 2814 } 2815 } 2816 2817 /** 2818 * intel_read_rawclk - Determine the current RAWCLK frequency 2819 * @dev_priv: i915 device 2820 * 2821 * Determine the current RAWCLK frequency. RAWCLK is a fixed 2822 * frequency clock so this needs to done only once. 2823 */ 2824 u32 intel_read_rawclk(struct drm_i915_private *dev_priv) 2825 { 2826 u32 freq; 2827 2828 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 2829 freq = dg1_rawclk(dev_priv); 2830 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) 2831 freq = cnp_rawclk(dev_priv); 2832 else if (HAS_PCH_SPLIT(dev_priv)) 2833 freq = pch_rawclk(dev_priv); 2834 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 2835 freq = vlv_hrawclk(dev_priv); 2836 else if (DISPLAY_VER(dev_priv) >= 3) 2837 freq = i9xx_hrawclk(dev_priv); 2838 else 2839 /* no rawclk on other platforms, or no need to know it */ 2840 return 0; 2841 2842 return freq; 2843 } 2844 2845 /** 2846 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks 2847 * @dev_priv: i915 device 2848 */ 2849 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) 2850 { 2851 if (IS_ROCKETLAKE(dev_priv)) { 2852 dev_priv->display.set_cdclk = bxt_set_cdclk; 2853 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; 2854 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; 2855 dev_priv->display.calc_voltage_level = tgl_calc_voltage_level; 2856 dev_priv->cdclk.table = rkl_cdclk_table; 2857 } else if (DISPLAY_VER(dev_priv) >= 12) { 2858 dev_priv->display.set_cdclk = bxt_set_cdclk; 2859 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; 2860 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; 2861 dev_priv->display.calc_voltage_level = tgl_calc_voltage_level; 2862 dev_priv->cdclk.table = icl_cdclk_table; 2863 } else if (IS_JSL_EHL(dev_priv)) { 2864 dev_priv->display.set_cdclk = bxt_set_cdclk; 2865 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; 2866 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; 2867 dev_priv->display.calc_voltage_level = ehl_calc_voltage_level; 2868 dev_priv->cdclk.table = icl_cdclk_table; 2869 } else if (DISPLAY_VER(dev_priv) >= 11) { 2870 dev_priv->display.set_cdclk = bxt_set_cdclk; 2871 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; 2872 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; 2873 dev_priv->display.calc_voltage_level = icl_calc_voltage_level; 2874 dev_priv->cdclk.table = icl_cdclk_table; 2875 } else if (IS_CANNONLAKE(dev_priv)) { 2876 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; 2877 dev_priv->display.set_cdclk = bxt_set_cdclk; 2878 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; 2879 dev_priv->display.calc_voltage_level = cnl_calc_voltage_level; 2880 dev_priv->cdclk.table = cnl_cdclk_table; 2881 } else if (IS_GEN9_LP(dev_priv)) { 2882 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; 2883 dev_priv->display.set_cdclk = bxt_set_cdclk; 2884 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; 2885 dev_priv->display.calc_voltage_level = bxt_calc_voltage_level; 2886 if (IS_GEMINILAKE(dev_priv)) 2887 dev_priv->cdclk.table = glk_cdclk_table; 2888 else 2889 dev_priv->cdclk.table = bxt_cdclk_table; 2890 } else if (IS_GEN9_BC(dev_priv)) { 2891 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; 2892 dev_priv->display.set_cdclk = skl_set_cdclk; 2893 dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk; 2894 } else if (IS_BROADWELL(dev_priv)) { 2895 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk; 2896 dev_priv->display.set_cdclk = bdw_set_cdclk; 2897 dev_priv->display.modeset_calc_cdclk = bdw_modeset_calc_cdclk; 2898 } else if (IS_CHERRYVIEW(dev_priv)) { 2899 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk; 2900 dev_priv->display.set_cdclk = chv_set_cdclk; 2901 dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk; 2902 } else if (IS_VALLEYVIEW(dev_priv)) { 2903 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk; 2904 dev_priv->display.set_cdclk = vlv_set_cdclk; 2905 dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk; 2906 } else { 2907 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk; 2908 dev_priv->display.modeset_calc_cdclk = fixed_modeset_calc_cdclk; 2909 } 2910 2911 if (DISPLAY_VER(dev_priv) >= 10 || IS_GEN9_LP(dev_priv)) 2912 dev_priv->display.get_cdclk = bxt_get_cdclk; 2913 else if (IS_GEN9_BC(dev_priv)) 2914 dev_priv->display.get_cdclk = skl_get_cdclk; 2915 else if (IS_BROADWELL(dev_priv)) 2916 dev_priv->display.get_cdclk = bdw_get_cdclk; 2917 else if (IS_HASWELL(dev_priv)) 2918 dev_priv->display.get_cdclk = hsw_get_cdclk; 2919 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 2920 dev_priv->display.get_cdclk = vlv_get_cdclk; 2921 else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) 2922 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; 2923 else if (IS_IRONLAKE(dev_priv)) 2924 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk; 2925 else if (IS_GM45(dev_priv)) 2926 dev_priv->display.get_cdclk = gm45_get_cdclk; 2927 else if (IS_G45(dev_priv)) 2928 dev_priv->display.get_cdclk = g33_get_cdclk; 2929 else if (IS_I965GM(dev_priv)) 2930 dev_priv->display.get_cdclk = i965gm_get_cdclk; 2931 else if (IS_I965G(dev_priv)) 2932 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; 2933 else if (IS_PINEVIEW(dev_priv)) 2934 dev_priv->display.get_cdclk = pnv_get_cdclk; 2935 else if (IS_G33(dev_priv)) 2936 dev_priv->display.get_cdclk = g33_get_cdclk; 2937 else if (IS_I945GM(dev_priv)) 2938 dev_priv->display.get_cdclk = i945gm_get_cdclk; 2939 else if (IS_I945G(dev_priv)) 2940 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; 2941 else if (IS_I915GM(dev_priv)) 2942 dev_priv->display.get_cdclk = i915gm_get_cdclk; 2943 else if (IS_I915G(dev_priv)) 2944 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk; 2945 else if (IS_I865G(dev_priv)) 2946 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk; 2947 else if (IS_I85X(dev_priv)) 2948 dev_priv->display.get_cdclk = i85x_get_cdclk; 2949 else if (IS_I845G(dev_priv)) 2950 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk; 2951 else if (IS_I830(dev_priv)) 2952 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk; 2953 2954 if (drm_WARN(&dev_priv->drm, !dev_priv->display.get_cdclk, 2955 "Unknown platform. Assuming 133 MHz CDCLK\n")) 2956 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk; 2957 } 2958