1 /* 2 * Copyright © 2006-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "intel_cdclk.h" 25 #include "intel_drv.h" 26 #include "intel_sideband.h" 27 28 /** 29 * DOC: CDCLK / RAWCLK 30 * 31 * The display engine uses several different clocks to do its work. There 32 * are two main clocks involved that aren't directly related to the actual 33 * pixel clock or any symbol/bit clock of the actual output port. These 34 * are the core display clock (CDCLK) and RAWCLK. 35 * 36 * CDCLK clocks most of the display pipe logic, and thus its frequency 37 * must be high enough to support the rate at which pixels are flowing 38 * through the pipes. Downscaling must also be accounted as that increases 39 * the effective pixel rate. 40 * 41 * On several platforms the CDCLK frequency can be changed dynamically 42 * to minimize power consumption for a given display configuration. 43 * Typically changes to the CDCLK frequency require all the display pipes 44 * to be shut down while the frequency is being changed. 45 * 46 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. 47 * DMC will not change the active CDCLK frequency however, so that part 48 * will still be performed by the driver directly. 49 * 50 * RAWCLK is a fixed frequency clock, often used by various auxiliary 51 * blocks such as AUX CH or backlight PWM. Hence the only thing we 52 * really need to know about RAWCLK is its frequency so that various 53 * dividers can be programmed correctly. 54 */ 55 56 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, 57 struct intel_cdclk_state *cdclk_state) 58 { 59 cdclk_state->cdclk = 133333; 60 } 61 62 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, 63 struct intel_cdclk_state *cdclk_state) 64 { 65 cdclk_state->cdclk = 200000; 66 } 67 68 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, 69 struct intel_cdclk_state *cdclk_state) 70 { 71 cdclk_state->cdclk = 266667; 72 } 73 74 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, 75 struct intel_cdclk_state *cdclk_state) 76 { 77 cdclk_state->cdclk = 333333; 78 } 79 80 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, 81 struct intel_cdclk_state *cdclk_state) 82 { 83 cdclk_state->cdclk = 400000; 84 } 85 86 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, 87 struct intel_cdclk_state *cdclk_state) 88 { 89 cdclk_state->cdclk = 450000; 90 } 91 92 static void i85x_get_cdclk(struct drm_i915_private *dev_priv, 93 struct intel_cdclk_state *cdclk_state) 94 { 95 struct pci_dev *pdev = dev_priv->drm.pdev; 96 u16 hpllcc = 0; 97 98 /* 99 * 852GM/852GMV only supports 133 MHz and the HPLLCC 100 * encoding is different :( 101 * FIXME is this the right way to detect 852GM/852GMV? 102 */ 103 if (pdev->revision == 0x1) { 104 cdclk_state->cdclk = 133333; 105 return; 106 } 107 108 pci_bus_read_config_word(pdev->bus, 109 PCI_DEVFN(0, 3), HPLLCC, &hpllcc); 110 111 /* Assume that the hardware is in the high speed state. This 112 * should be the default. 113 */ 114 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 115 case GC_CLOCK_133_200: 116 case GC_CLOCK_133_200_2: 117 case GC_CLOCK_100_200: 118 cdclk_state->cdclk = 200000; 119 break; 120 case GC_CLOCK_166_250: 121 cdclk_state->cdclk = 250000; 122 break; 123 case GC_CLOCK_100_133: 124 cdclk_state->cdclk = 133333; 125 break; 126 case GC_CLOCK_133_266: 127 case GC_CLOCK_133_266_2: 128 case GC_CLOCK_166_266: 129 cdclk_state->cdclk = 266667; 130 break; 131 } 132 } 133 134 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, 135 struct intel_cdclk_state *cdclk_state) 136 { 137 struct pci_dev *pdev = dev_priv->drm.pdev; 138 u16 gcfgc = 0; 139 140 pci_read_config_word(pdev, GCFGC, &gcfgc); 141 142 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 143 cdclk_state->cdclk = 133333; 144 return; 145 } 146 147 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 148 case GC_DISPLAY_CLOCK_333_320_MHZ: 149 cdclk_state->cdclk = 333333; 150 break; 151 default: 152 case GC_DISPLAY_CLOCK_190_200_MHZ: 153 cdclk_state->cdclk = 190000; 154 break; 155 } 156 } 157 158 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, 159 struct intel_cdclk_state *cdclk_state) 160 { 161 struct pci_dev *pdev = dev_priv->drm.pdev; 162 u16 gcfgc = 0; 163 164 pci_read_config_word(pdev, GCFGC, &gcfgc); 165 166 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 167 cdclk_state->cdclk = 133333; 168 return; 169 } 170 171 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 172 case GC_DISPLAY_CLOCK_333_320_MHZ: 173 cdclk_state->cdclk = 320000; 174 break; 175 default: 176 case GC_DISPLAY_CLOCK_190_200_MHZ: 177 cdclk_state->cdclk = 200000; 178 break; 179 } 180 } 181 182 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) 183 { 184 static const unsigned int blb_vco[8] = { 185 [0] = 3200000, 186 [1] = 4000000, 187 [2] = 5333333, 188 [3] = 4800000, 189 [4] = 6400000, 190 }; 191 static const unsigned int pnv_vco[8] = { 192 [0] = 3200000, 193 [1] = 4000000, 194 [2] = 5333333, 195 [3] = 4800000, 196 [4] = 2666667, 197 }; 198 static const unsigned int cl_vco[8] = { 199 [0] = 3200000, 200 [1] = 4000000, 201 [2] = 5333333, 202 [3] = 6400000, 203 [4] = 3333333, 204 [5] = 3566667, 205 [6] = 4266667, 206 }; 207 static const unsigned int elk_vco[8] = { 208 [0] = 3200000, 209 [1] = 4000000, 210 [2] = 5333333, 211 [3] = 4800000, 212 }; 213 static const unsigned int ctg_vco[8] = { 214 [0] = 3200000, 215 [1] = 4000000, 216 [2] = 5333333, 217 [3] = 6400000, 218 [4] = 2666667, 219 [5] = 4266667, 220 }; 221 const unsigned int *vco_table; 222 unsigned int vco; 223 u8 tmp = 0; 224 225 /* FIXME other chipsets? */ 226 if (IS_GM45(dev_priv)) 227 vco_table = ctg_vco; 228 else if (IS_G45(dev_priv)) 229 vco_table = elk_vco; 230 else if (IS_I965GM(dev_priv)) 231 vco_table = cl_vco; 232 else if (IS_PINEVIEW(dev_priv)) 233 vco_table = pnv_vco; 234 else if (IS_G33(dev_priv)) 235 vco_table = blb_vco; 236 else 237 return 0; 238 239 tmp = I915_READ(IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? 240 HPLLVCO_MOBILE : HPLLVCO); 241 242 vco = vco_table[tmp & 0x7]; 243 if (vco == 0) 244 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); 245 else 246 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); 247 248 return vco; 249 } 250 251 static void g33_get_cdclk(struct drm_i915_private *dev_priv, 252 struct intel_cdclk_state *cdclk_state) 253 { 254 struct pci_dev *pdev = dev_priv->drm.pdev; 255 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 }; 256 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 }; 257 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 }; 258 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 }; 259 const u8 *div_table; 260 unsigned int cdclk_sel; 261 u16 tmp = 0; 262 263 cdclk_state->vco = intel_hpll_vco(dev_priv); 264 265 pci_read_config_word(pdev, GCFGC, &tmp); 266 267 cdclk_sel = (tmp >> 4) & 0x7; 268 269 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 270 goto fail; 271 272 switch (cdclk_state->vco) { 273 case 3200000: 274 div_table = div_3200; 275 break; 276 case 4000000: 277 div_table = div_4000; 278 break; 279 case 4800000: 280 div_table = div_4800; 281 break; 282 case 5333333: 283 div_table = div_5333; 284 break; 285 default: 286 goto fail; 287 } 288 289 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, 290 div_table[cdclk_sel]); 291 return; 292 293 fail: 294 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", 295 cdclk_state->vco, tmp); 296 cdclk_state->cdclk = 190476; 297 } 298 299 static void pnv_get_cdclk(struct drm_i915_private *dev_priv, 300 struct intel_cdclk_state *cdclk_state) 301 { 302 struct pci_dev *pdev = dev_priv->drm.pdev; 303 u16 gcfgc = 0; 304 305 pci_read_config_word(pdev, GCFGC, &gcfgc); 306 307 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 308 case GC_DISPLAY_CLOCK_267_MHZ_PNV: 309 cdclk_state->cdclk = 266667; 310 break; 311 case GC_DISPLAY_CLOCK_333_MHZ_PNV: 312 cdclk_state->cdclk = 333333; 313 break; 314 case GC_DISPLAY_CLOCK_444_MHZ_PNV: 315 cdclk_state->cdclk = 444444; 316 break; 317 case GC_DISPLAY_CLOCK_200_MHZ_PNV: 318 cdclk_state->cdclk = 200000; 319 break; 320 default: 321 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); 322 /* fall through */ 323 case GC_DISPLAY_CLOCK_133_MHZ_PNV: 324 cdclk_state->cdclk = 133333; 325 break; 326 case GC_DISPLAY_CLOCK_167_MHZ_PNV: 327 cdclk_state->cdclk = 166667; 328 break; 329 } 330 } 331 332 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, 333 struct intel_cdclk_state *cdclk_state) 334 { 335 struct pci_dev *pdev = dev_priv->drm.pdev; 336 static const u8 div_3200[] = { 16, 10, 8 }; 337 static const u8 div_4000[] = { 20, 12, 10 }; 338 static const u8 div_5333[] = { 24, 16, 14 }; 339 const u8 *div_table; 340 unsigned int cdclk_sel; 341 u16 tmp = 0; 342 343 cdclk_state->vco = intel_hpll_vco(dev_priv); 344 345 pci_read_config_word(pdev, GCFGC, &tmp); 346 347 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; 348 349 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 350 goto fail; 351 352 switch (cdclk_state->vco) { 353 case 3200000: 354 div_table = div_3200; 355 break; 356 case 4000000: 357 div_table = div_4000; 358 break; 359 case 5333333: 360 div_table = div_5333; 361 break; 362 default: 363 goto fail; 364 } 365 366 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, 367 div_table[cdclk_sel]); 368 return; 369 370 fail: 371 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", 372 cdclk_state->vco, tmp); 373 cdclk_state->cdclk = 200000; 374 } 375 376 static void gm45_get_cdclk(struct drm_i915_private *dev_priv, 377 struct intel_cdclk_state *cdclk_state) 378 { 379 struct pci_dev *pdev = dev_priv->drm.pdev; 380 unsigned int cdclk_sel; 381 u16 tmp = 0; 382 383 cdclk_state->vco = intel_hpll_vco(dev_priv); 384 385 pci_read_config_word(pdev, GCFGC, &tmp); 386 387 cdclk_sel = (tmp >> 12) & 0x1; 388 389 switch (cdclk_state->vco) { 390 case 2666667: 391 case 4000000: 392 case 5333333: 393 cdclk_state->cdclk = cdclk_sel ? 333333 : 222222; 394 break; 395 case 3200000: 396 cdclk_state->cdclk = cdclk_sel ? 320000 : 228571; 397 break; 398 default: 399 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", 400 cdclk_state->vco, tmp); 401 cdclk_state->cdclk = 222222; 402 break; 403 } 404 } 405 406 static void hsw_get_cdclk(struct drm_i915_private *dev_priv, 407 struct intel_cdclk_state *cdclk_state) 408 { 409 u32 lcpll = I915_READ(LCPLL_CTL); 410 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 411 412 if (lcpll & LCPLL_CD_SOURCE_FCLK) 413 cdclk_state->cdclk = 800000; 414 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) 415 cdclk_state->cdclk = 450000; 416 else if (freq == LCPLL_CLK_FREQ_450) 417 cdclk_state->cdclk = 450000; 418 else if (IS_HSW_ULT(dev_priv)) 419 cdclk_state->cdclk = 337500; 420 else 421 cdclk_state->cdclk = 540000; 422 } 423 424 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) 425 { 426 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 427 333333 : 320000; 428 429 /* 430 * We seem to get an unstable or solid color picture at 200MHz. 431 * Not sure what's wrong. For now use 200MHz only when all pipes 432 * are off. 433 */ 434 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) 435 return 400000; 436 else if (min_cdclk > 266667) 437 return freq_320; 438 else if (min_cdclk > 0) 439 return 266667; 440 else 441 return 200000; 442 } 443 444 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) 445 { 446 if (IS_VALLEYVIEW(dev_priv)) { 447 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ 448 return 2; 449 else if (cdclk >= 266667) 450 return 1; 451 else 452 return 0; 453 } else { 454 /* 455 * Specs are full of misinformation, but testing on actual 456 * hardware has shown that we just need to write the desired 457 * CCK divider into the Punit register. 458 */ 459 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; 460 } 461 } 462 463 static void vlv_get_cdclk(struct drm_i915_private *dev_priv, 464 struct intel_cdclk_state *cdclk_state) 465 { 466 u32 val; 467 468 vlv_iosf_sb_get(dev_priv, 469 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 470 471 cdclk_state->vco = vlv_get_hpll_vco(dev_priv); 472 cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", 473 CCK_DISPLAY_CLOCK_CONTROL, 474 cdclk_state->vco); 475 476 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 477 478 vlv_iosf_sb_put(dev_priv, 479 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 480 481 if (IS_VALLEYVIEW(dev_priv)) 482 cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK) >> 483 DSPFREQGUAR_SHIFT; 484 else 485 cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> 486 DSPFREQGUAR_SHIFT_CHV; 487 } 488 489 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) 490 { 491 unsigned int credits, default_credits; 492 493 if (IS_CHERRYVIEW(dev_priv)) 494 default_credits = PFI_CREDIT(12); 495 else 496 default_credits = PFI_CREDIT(8); 497 498 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) { 499 /* CHV suggested value is 31 or 63 */ 500 if (IS_CHERRYVIEW(dev_priv)) 501 credits = PFI_CREDIT_63; 502 else 503 credits = PFI_CREDIT(15); 504 } else { 505 credits = default_credits; 506 } 507 508 /* 509 * WA - write default credits before re-programming 510 * FIXME: should we also set the resend bit here? 511 */ 512 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | 513 default_credits); 514 515 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | 516 credits | PFI_CREDIT_RESEND); 517 518 /* 519 * FIXME is this guaranteed to clear 520 * immediately or should we poll for it? 521 */ 522 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); 523 } 524 525 static void vlv_set_cdclk(struct drm_i915_private *dev_priv, 526 const struct intel_cdclk_state *cdclk_state, 527 enum pipe pipe) 528 { 529 int cdclk = cdclk_state->cdclk; 530 u32 val, cmd = cdclk_state->voltage_level; 531 intel_wakeref_t wakeref; 532 533 switch (cdclk) { 534 case 400000: 535 case 333333: 536 case 320000: 537 case 266667: 538 case 200000: 539 break; 540 default: 541 MISSING_CASE(cdclk); 542 return; 543 } 544 545 /* There are cases where we can end up here with power domains 546 * off and a CDCLK frequency other than the minimum, like when 547 * issuing a modeset without actually changing any display after 548 * a system suspend. So grab the display core domain, which covers 549 * the HW blocks needed for the following programming. 550 */ 551 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); 552 553 vlv_iosf_sb_get(dev_priv, 554 BIT(VLV_IOSF_SB_CCK) | 555 BIT(VLV_IOSF_SB_BUNIT) | 556 BIT(VLV_IOSF_SB_PUNIT)); 557 558 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 559 val &= ~DSPFREQGUAR_MASK; 560 val |= (cmd << DSPFREQGUAR_SHIFT); 561 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); 562 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & 563 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 564 50)) { 565 DRM_ERROR("timed out waiting for CDclk change\n"); 566 } 567 568 if (cdclk == 400000) { 569 u32 divider; 570 571 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, 572 cdclk) - 1; 573 574 /* adjust cdclk divider */ 575 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); 576 val &= ~CCK_FREQUENCY_VALUES; 577 val |= divider; 578 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); 579 580 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & 581 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 582 50)) 583 DRM_ERROR("timed out waiting for CDclk change\n"); 584 } 585 586 /* adjust self-refresh exit latency value */ 587 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); 588 val &= ~0x7f; 589 590 /* 591 * For high bandwidth configs, we set a higher latency in the bunit 592 * so that the core display fetch happens in time to avoid underruns. 593 */ 594 if (cdclk == 400000) 595 val |= 4500 / 250; /* 4.5 usec */ 596 else 597 val |= 3000 / 250; /* 3.0 usec */ 598 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); 599 600 vlv_iosf_sb_put(dev_priv, 601 BIT(VLV_IOSF_SB_CCK) | 602 BIT(VLV_IOSF_SB_BUNIT) | 603 BIT(VLV_IOSF_SB_PUNIT)); 604 605 intel_update_cdclk(dev_priv); 606 607 vlv_program_pfi_credits(dev_priv); 608 609 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); 610 } 611 612 static void chv_set_cdclk(struct drm_i915_private *dev_priv, 613 const struct intel_cdclk_state *cdclk_state, 614 enum pipe pipe) 615 { 616 int cdclk = cdclk_state->cdclk; 617 u32 val, cmd = cdclk_state->voltage_level; 618 intel_wakeref_t wakeref; 619 620 switch (cdclk) { 621 case 333333: 622 case 320000: 623 case 266667: 624 case 200000: 625 break; 626 default: 627 MISSING_CASE(cdclk); 628 return; 629 } 630 631 /* There are cases where we can end up here with power domains 632 * off and a CDCLK frequency other than the minimum, like when 633 * issuing a modeset without actually changing any display after 634 * a system suspend. So grab the display core domain, which covers 635 * the HW blocks needed for the following programming. 636 */ 637 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); 638 639 vlv_punit_get(dev_priv); 640 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 641 val &= ~DSPFREQGUAR_MASK_CHV; 642 val |= (cmd << DSPFREQGUAR_SHIFT_CHV); 643 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); 644 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & 645 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 646 50)) { 647 DRM_ERROR("timed out waiting for CDclk change\n"); 648 } 649 650 vlv_punit_put(dev_priv); 651 652 intel_update_cdclk(dev_priv); 653 654 vlv_program_pfi_credits(dev_priv); 655 656 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); 657 } 658 659 static int bdw_calc_cdclk(int min_cdclk) 660 { 661 if (min_cdclk > 540000) 662 return 675000; 663 else if (min_cdclk > 450000) 664 return 540000; 665 else if (min_cdclk > 337500) 666 return 450000; 667 else 668 return 337500; 669 } 670 671 static u8 bdw_calc_voltage_level(int cdclk) 672 { 673 switch (cdclk) { 674 default: 675 case 337500: 676 return 2; 677 case 450000: 678 return 0; 679 case 540000: 680 return 1; 681 case 675000: 682 return 3; 683 } 684 } 685 686 static void bdw_get_cdclk(struct drm_i915_private *dev_priv, 687 struct intel_cdclk_state *cdclk_state) 688 { 689 u32 lcpll = I915_READ(LCPLL_CTL); 690 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 691 692 if (lcpll & LCPLL_CD_SOURCE_FCLK) 693 cdclk_state->cdclk = 800000; 694 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) 695 cdclk_state->cdclk = 450000; 696 else if (freq == LCPLL_CLK_FREQ_450) 697 cdclk_state->cdclk = 450000; 698 else if (freq == LCPLL_CLK_FREQ_54O_BDW) 699 cdclk_state->cdclk = 540000; 700 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 701 cdclk_state->cdclk = 337500; 702 else 703 cdclk_state->cdclk = 675000; 704 705 /* 706 * Can't read this out :( Let's assume it's 707 * at least what the CDCLK frequency requires. 708 */ 709 cdclk_state->voltage_level = 710 bdw_calc_voltage_level(cdclk_state->cdclk); 711 } 712 713 static void bdw_set_cdclk(struct drm_i915_private *dev_priv, 714 const struct intel_cdclk_state *cdclk_state, 715 enum pipe pipe) 716 { 717 int cdclk = cdclk_state->cdclk; 718 u32 val; 719 int ret; 720 721 if (WARN((I915_READ(LCPLL_CTL) & 722 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | 723 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | 724 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | 725 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, 726 "trying to change cdclk frequency with cdclk not enabled\n")) 727 return; 728 729 ret = sandybridge_pcode_write(dev_priv, 730 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); 731 if (ret) { 732 DRM_ERROR("failed to inform pcode about cdclk change\n"); 733 return; 734 } 735 736 val = I915_READ(LCPLL_CTL); 737 val |= LCPLL_CD_SOURCE_FCLK; 738 I915_WRITE(LCPLL_CTL, val); 739 740 /* 741 * According to the spec, it should be enough to poll for this 1 us. 742 * However, extensive testing shows that this can take longer. 743 */ 744 if (wait_for_us(I915_READ(LCPLL_CTL) & 745 LCPLL_CD_SOURCE_FCLK_DONE, 100)) 746 DRM_ERROR("Switching to FCLK failed\n"); 747 748 val = I915_READ(LCPLL_CTL); 749 val &= ~LCPLL_CLK_FREQ_MASK; 750 751 switch (cdclk) { 752 default: 753 MISSING_CASE(cdclk); 754 /* fall through */ 755 case 337500: 756 val |= LCPLL_CLK_FREQ_337_5_BDW; 757 break; 758 case 450000: 759 val |= LCPLL_CLK_FREQ_450; 760 break; 761 case 540000: 762 val |= LCPLL_CLK_FREQ_54O_BDW; 763 break; 764 case 675000: 765 val |= LCPLL_CLK_FREQ_675_BDW; 766 break; 767 } 768 769 I915_WRITE(LCPLL_CTL, val); 770 771 val = I915_READ(LCPLL_CTL); 772 val &= ~LCPLL_CD_SOURCE_FCLK; 773 I915_WRITE(LCPLL_CTL, val); 774 775 if (wait_for_us((I915_READ(LCPLL_CTL) & 776 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 777 DRM_ERROR("Switching back to LCPLL failed\n"); 778 779 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, 780 cdclk_state->voltage_level); 781 782 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); 783 784 intel_update_cdclk(dev_priv); 785 } 786 787 static int skl_calc_cdclk(int min_cdclk, int vco) 788 { 789 if (vco == 8640000) { 790 if (min_cdclk > 540000) 791 return 617143; 792 else if (min_cdclk > 432000) 793 return 540000; 794 else if (min_cdclk > 308571) 795 return 432000; 796 else 797 return 308571; 798 } else { 799 if (min_cdclk > 540000) 800 return 675000; 801 else if (min_cdclk > 450000) 802 return 540000; 803 else if (min_cdclk > 337500) 804 return 450000; 805 else 806 return 337500; 807 } 808 } 809 810 static u8 skl_calc_voltage_level(int cdclk) 811 { 812 if (cdclk > 540000) 813 return 3; 814 else if (cdclk > 450000) 815 return 2; 816 else if (cdclk > 337500) 817 return 1; 818 else 819 return 0; 820 } 821 822 static void skl_dpll0_update(struct drm_i915_private *dev_priv, 823 struct intel_cdclk_state *cdclk_state) 824 { 825 u32 val; 826 827 cdclk_state->ref = 24000; 828 cdclk_state->vco = 0; 829 830 val = I915_READ(LCPLL1_CTL); 831 if ((val & LCPLL_PLL_ENABLE) == 0) 832 return; 833 834 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0)) 835 return; 836 837 val = I915_READ(DPLL_CTRL1); 838 839 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 840 DPLL_CTRL1_SSC(SKL_DPLL0) | 841 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != 842 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) 843 return; 844 845 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { 846 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): 847 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): 848 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): 849 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): 850 cdclk_state->vco = 8100000; 851 break; 852 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): 853 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): 854 cdclk_state->vco = 8640000; 855 break; 856 default: 857 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 858 break; 859 } 860 } 861 862 static void skl_get_cdclk(struct drm_i915_private *dev_priv, 863 struct intel_cdclk_state *cdclk_state) 864 { 865 u32 cdctl; 866 867 skl_dpll0_update(dev_priv, cdclk_state); 868 869 cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref; 870 871 if (cdclk_state->vco == 0) 872 goto out; 873 874 cdctl = I915_READ(CDCLK_CTL); 875 876 if (cdclk_state->vco == 8640000) { 877 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 878 case CDCLK_FREQ_450_432: 879 cdclk_state->cdclk = 432000; 880 break; 881 case CDCLK_FREQ_337_308: 882 cdclk_state->cdclk = 308571; 883 break; 884 case CDCLK_FREQ_540: 885 cdclk_state->cdclk = 540000; 886 break; 887 case CDCLK_FREQ_675_617: 888 cdclk_state->cdclk = 617143; 889 break; 890 default: 891 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 892 break; 893 } 894 } else { 895 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 896 case CDCLK_FREQ_450_432: 897 cdclk_state->cdclk = 450000; 898 break; 899 case CDCLK_FREQ_337_308: 900 cdclk_state->cdclk = 337500; 901 break; 902 case CDCLK_FREQ_540: 903 cdclk_state->cdclk = 540000; 904 break; 905 case CDCLK_FREQ_675_617: 906 cdclk_state->cdclk = 675000; 907 break; 908 default: 909 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 910 break; 911 } 912 } 913 914 out: 915 /* 916 * Can't read this out :( Let's assume it's 917 * at least what the CDCLK frequency requires. 918 */ 919 cdclk_state->voltage_level = 920 skl_calc_voltage_level(cdclk_state->cdclk); 921 } 922 923 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ 924 static int skl_cdclk_decimal(int cdclk) 925 { 926 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); 927 } 928 929 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, 930 int vco) 931 { 932 bool changed = dev_priv->skl_preferred_vco_freq != vco; 933 934 dev_priv->skl_preferred_vco_freq = vco; 935 936 if (changed) 937 intel_update_max_cdclk(dev_priv); 938 } 939 940 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) 941 { 942 u32 val; 943 944 WARN_ON(vco != 8100000 && vco != 8640000); 945 946 /* 947 * We always enable DPLL0 with the lowest link rate possible, but still 948 * taking into account the VCO required to operate the eDP panel at the 949 * desired frequency. The usual DP link rates operate with a VCO of 950 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. 951 * The modeset code is responsible for the selection of the exact link 952 * rate later on, with the constraint of choosing a frequency that 953 * works with vco. 954 */ 955 val = I915_READ(DPLL_CTRL1); 956 957 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | 958 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 959 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); 960 if (vco == 8640000) 961 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 962 SKL_DPLL0); 963 else 964 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 965 SKL_DPLL0); 966 967 I915_WRITE(DPLL_CTRL1, val); 968 POSTING_READ(DPLL_CTRL1); 969 970 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); 971 972 if (intel_wait_for_register(&dev_priv->uncore, 973 LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, 974 5)) 975 DRM_ERROR("DPLL0 not locked\n"); 976 977 dev_priv->cdclk.hw.vco = vco; 978 979 /* We'll want to keep using the current vco from now on. */ 980 skl_set_preferred_cdclk_vco(dev_priv, vco); 981 } 982 983 static void skl_dpll0_disable(struct drm_i915_private *dev_priv) 984 { 985 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); 986 if (intel_wait_for_register(&dev_priv->uncore, 987 LCPLL1_CTL, LCPLL_PLL_LOCK, 0, 988 1)) 989 DRM_ERROR("Couldn't disable DPLL0\n"); 990 991 dev_priv->cdclk.hw.vco = 0; 992 } 993 994 static void skl_set_cdclk(struct drm_i915_private *dev_priv, 995 const struct intel_cdclk_state *cdclk_state, 996 enum pipe pipe) 997 { 998 int cdclk = cdclk_state->cdclk; 999 int vco = cdclk_state->vco; 1000 u32 freq_select, cdclk_ctl; 1001 int ret; 1002 1003 /* 1004 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are 1005 * unsupported on SKL. In theory this should never happen since only 1006 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not 1007 * supported on SKL either, see the above WA. WARN whenever trying to 1008 * use the corresponding VCO freq as that always leads to using the 1009 * minimum 308MHz CDCLK. 1010 */ 1011 WARN_ON_ONCE(IS_SKYLAKE(dev_priv) && vco == 8640000); 1012 1013 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, 1014 SKL_CDCLK_PREPARE_FOR_CHANGE, 1015 SKL_CDCLK_READY_FOR_CHANGE, 1016 SKL_CDCLK_READY_FOR_CHANGE, 3); 1017 if (ret) { 1018 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n", 1019 ret); 1020 return; 1021 } 1022 1023 /* Choose frequency for this cdclk */ 1024 switch (cdclk) { 1025 default: 1026 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass); 1027 WARN_ON(vco != 0); 1028 /* fall through */ 1029 case 308571: 1030 case 337500: 1031 freq_select = CDCLK_FREQ_337_308; 1032 break; 1033 case 450000: 1034 case 432000: 1035 freq_select = CDCLK_FREQ_450_432; 1036 break; 1037 case 540000: 1038 freq_select = CDCLK_FREQ_540; 1039 break; 1040 case 617143: 1041 case 675000: 1042 freq_select = CDCLK_FREQ_675_617; 1043 break; 1044 } 1045 1046 if (dev_priv->cdclk.hw.vco != 0 && 1047 dev_priv->cdclk.hw.vco != vco) 1048 skl_dpll0_disable(dev_priv); 1049 1050 cdclk_ctl = I915_READ(CDCLK_CTL); 1051 1052 if (dev_priv->cdclk.hw.vco != vco) { 1053 /* Wa Display #1183: skl,kbl,cfl */ 1054 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1055 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1056 I915_WRITE(CDCLK_CTL, cdclk_ctl); 1057 } 1058 1059 /* Wa Display #1183: skl,kbl,cfl */ 1060 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; 1061 I915_WRITE(CDCLK_CTL, cdclk_ctl); 1062 POSTING_READ(CDCLK_CTL); 1063 1064 if (dev_priv->cdclk.hw.vco != vco) 1065 skl_dpll0_enable(dev_priv, vco); 1066 1067 /* Wa Display #1183: skl,kbl,cfl */ 1068 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1069 I915_WRITE(CDCLK_CTL, cdclk_ctl); 1070 1071 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1072 I915_WRITE(CDCLK_CTL, cdclk_ctl); 1073 1074 /* Wa Display #1183: skl,kbl,cfl */ 1075 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; 1076 I915_WRITE(CDCLK_CTL, cdclk_ctl); 1077 POSTING_READ(CDCLK_CTL); 1078 1079 /* inform PCU of the change */ 1080 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, 1081 cdclk_state->voltage_level); 1082 1083 intel_update_cdclk(dev_priv); 1084 } 1085 1086 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) 1087 { 1088 u32 cdctl, expected; 1089 1090 /* 1091 * check if the pre-os initialized the display 1092 * There is SWF18 scratchpad register defined which is set by the 1093 * pre-os which can be used by the OS drivers to check the status 1094 */ 1095 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) 1096 goto sanitize; 1097 1098 intel_update_cdclk(dev_priv); 1099 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); 1100 1101 /* Is PLL enabled and locked ? */ 1102 if (dev_priv->cdclk.hw.vco == 0 || 1103 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) 1104 goto sanitize; 1105 1106 /* DPLL okay; verify the cdclock 1107 * 1108 * Noticed in some instances that the freq selection is correct but 1109 * decimal part is programmed wrong from BIOS where pre-os does not 1110 * enable display. Verify the same as well. 1111 */ 1112 cdctl = I915_READ(CDCLK_CTL); 1113 expected = (cdctl & CDCLK_FREQ_SEL_MASK) | 1114 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); 1115 if (cdctl == expected) 1116 /* All well; nothing to sanitize */ 1117 return; 1118 1119 sanitize: 1120 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); 1121 1122 /* force cdclk programming */ 1123 dev_priv->cdclk.hw.cdclk = 0; 1124 /* force full PLL disable + enable */ 1125 dev_priv->cdclk.hw.vco = -1; 1126 } 1127 1128 static void skl_init_cdclk(struct drm_i915_private *dev_priv) 1129 { 1130 struct intel_cdclk_state cdclk_state; 1131 1132 skl_sanitize_cdclk(dev_priv); 1133 1134 if (dev_priv->cdclk.hw.cdclk != 0 && 1135 dev_priv->cdclk.hw.vco != 0) { 1136 /* 1137 * Use the current vco as our initial 1138 * guess as to what the preferred vco is. 1139 */ 1140 if (dev_priv->skl_preferred_vco_freq == 0) 1141 skl_set_preferred_cdclk_vco(dev_priv, 1142 dev_priv->cdclk.hw.vco); 1143 return; 1144 } 1145 1146 cdclk_state = dev_priv->cdclk.hw; 1147 1148 cdclk_state.vco = dev_priv->skl_preferred_vco_freq; 1149 if (cdclk_state.vco == 0) 1150 cdclk_state.vco = 8100000; 1151 cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco); 1152 cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk); 1153 1154 skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); 1155 } 1156 1157 static void skl_uninit_cdclk(struct drm_i915_private *dev_priv) 1158 { 1159 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; 1160 1161 cdclk_state.cdclk = cdclk_state.bypass; 1162 cdclk_state.vco = 0; 1163 cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk); 1164 1165 skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); 1166 } 1167 1168 static int bxt_calc_cdclk(int min_cdclk) 1169 { 1170 if (min_cdclk > 576000) 1171 return 624000; 1172 else if (min_cdclk > 384000) 1173 return 576000; 1174 else if (min_cdclk > 288000) 1175 return 384000; 1176 else if (min_cdclk > 144000) 1177 return 288000; 1178 else 1179 return 144000; 1180 } 1181 1182 static int glk_calc_cdclk(int min_cdclk) 1183 { 1184 if (min_cdclk > 158400) 1185 return 316800; 1186 else if (min_cdclk > 79200) 1187 return 158400; 1188 else 1189 return 79200; 1190 } 1191 1192 static u8 bxt_calc_voltage_level(int cdclk) 1193 { 1194 return DIV_ROUND_UP(cdclk, 25000); 1195 } 1196 1197 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) 1198 { 1199 int ratio; 1200 1201 if (cdclk == dev_priv->cdclk.hw.bypass) 1202 return 0; 1203 1204 switch (cdclk) { 1205 default: 1206 MISSING_CASE(cdclk); 1207 /* fall through */ 1208 case 144000: 1209 case 288000: 1210 case 384000: 1211 case 576000: 1212 ratio = 60; 1213 break; 1214 case 624000: 1215 ratio = 65; 1216 break; 1217 } 1218 1219 return dev_priv->cdclk.hw.ref * ratio; 1220 } 1221 1222 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) 1223 { 1224 int ratio; 1225 1226 if (cdclk == dev_priv->cdclk.hw.bypass) 1227 return 0; 1228 1229 switch (cdclk) { 1230 default: 1231 MISSING_CASE(cdclk); 1232 /* fall through */ 1233 case 79200: 1234 case 158400: 1235 case 316800: 1236 ratio = 33; 1237 break; 1238 } 1239 1240 return dev_priv->cdclk.hw.ref * ratio; 1241 } 1242 1243 static void bxt_de_pll_update(struct drm_i915_private *dev_priv, 1244 struct intel_cdclk_state *cdclk_state) 1245 { 1246 u32 val; 1247 1248 cdclk_state->ref = 19200; 1249 cdclk_state->vco = 0; 1250 1251 val = I915_READ(BXT_DE_PLL_ENABLE); 1252 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) 1253 return; 1254 1255 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) 1256 return; 1257 1258 val = I915_READ(BXT_DE_PLL_CTL); 1259 cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref; 1260 } 1261 1262 static void bxt_get_cdclk(struct drm_i915_private *dev_priv, 1263 struct intel_cdclk_state *cdclk_state) 1264 { 1265 u32 divider; 1266 int div; 1267 1268 bxt_de_pll_update(dev_priv, cdclk_state); 1269 1270 cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref; 1271 1272 if (cdclk_state->vco == 0) 1273 goto out; 1274 1275 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; 1276 1277 switch (divider) { 1278 case BXT_CDCLK_CD2X_DIV_SEL_1: 1279 div = 2; 1280 break; 1281 case BXT_CDCLK_CD2X_DIV_SEL_1_5: 1282 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n"); 1283 div = 3; 1284 break; 1285 case BXT_CDCLK_CD2X_DIV_SEL_2: 1286 div = 4; 1287 break; 1288 case BXT_CDCLK_CD2X_DIV_SEL_4: 1289 div = 8; 1290 break; 1291 default: 1292 MISSING_CASE(divider); 1293 return; 1294 } 1295 1296 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div); 1297 1298 out: 1299 /* 1300 * Can't read this out :( Let's assume it's 1301 * at least what the CDCLK frequency requires. 1302 */ 1303 cdclk_state->voltage_level = 1304 bxt_calc_voltage_level(cdclk_state->cdclk); 1305 } 1306 1307 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) 1308 { 1309 I915_WRITE(BXT_DE_PLL_ENABLE, 0); 1310 1311 /* Timeout 200us */ 1312 if (intel_wait_for_register(&dev_priv->uncore, 1313 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0, 1314 1)) 1315 DRM_ERROR("timeout waiting for DE PLL unlock\n"); 1316 1317 dev_priv->cdclk.hw.vco = 0; 1318 } 1319 1320 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) 1321 { 1322 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); 1323 u32 val; 1324 1325 val = I915_READ(BXT_DE_PLL_CTL); 1326 val &= ~BXT_DE_PLL_RATIO_MASK; 1327 val |= BXT_DE_PLL_RATIO(ratio); 1328 I915_WRITE(BXT_DE_PLL_CTL, val); 1329 1330 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); 1331 1332 /* Timeout 200us */ 1333 if (intel_wait_for_register(&dev_priv->uncore, 1334 BXT_DE_PLL_ENABLE, 1335 BXT_DE_PLL_LOCK, 1336 BXT_DE_PLL_LOCK, 1337 1)) 1338 DRM_ERROR("timeout waiting for DE PLL lock\n"); 1339 1340 dev_priv->cdclk.hw.vco = vco; 1341 } 1342 1343 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 1344 const struct intel_cdclk_state *cdclk_state, 1345 enum pipe pipe) 1346 { 1347 int cdclk = cdclk_state->cdclk; 1348 int vco = cdclk_state->vco; 1349 u32 val, divider; 1350 int ret; 1351 1352 /* cdclk = vco / 2 / div{1,1.5,2,4} */ 1353 switch (DIV_ROUND_CLOSEST(vco, cdclk)) { 1354 default: 1355 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass); 1356 WARN_ON(vco != 0); 1357 /* fall through */ 1358 case 2: 1359 divider = BXT_CDCLK_CD2X_DIV_SEL_1; 1360 break; 1361 case 3: 1362 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n"); 1363 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; 1364 break; 1365 case 4: 1366 divider = BXT_CDCLK_CD2X_DIV_SEL_2; 1367 break; 1368 case 8: 1369 divider = BXT_CDCLK_CD2X_DIV_SEL_4; 1370 break; 1371 } 1372 1373 /* 1374 * Inform power controller of upcoming frequency change. BSpec 1375 * requires us to wait up to 150usec, but that leads to timeouts; 1376 * the 2ms used here is based on experiment. 1377 */ 1378 ret = sandybridge_pcode_write_timeout(dev_priv, 1379 HSW_PCODE_DE_WRITE_FREQ_REQ, 1380 0x80000000, 150, 2); 1381 if (ret) { 1382 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", 1383 ret, cdclk); 1384 return; 1385 } 1386 1387 if (dev_priv->cdclk.hw.vco != 0 && 1388 dev_priv->cdclk.hw.vco != vco) 1389 bxt_de_pll_disable(dev_priv); 1390 1391 if (dev_priv->cdclk.hw.vco != vco) 1392 bxt_de_pll_enable(dev_priv, vco); 1393 1394 val = divider | skl_cdclk_decimal(cdclk); 1395 if (pipe == INVALID_PIPE) 1396 val |= BXT_CDCLK_CD2X_PIPE_NONE; 1397 else 1398 val |= BXT_CDCLK_CD2X_PIPE(pipe); 1399 /* 1400 * Disable SSA Precharge when CD clock frequency < 500 MHz, 1401 * enable otherwise. 1402 */ 1403 if (cdclk >= 500000) 1404 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 1405 I915_WRITE(CDCLK_CTL, val); 1406 1407 if (pipe != INVALID_PIPE) 1408 intel_wait_for_vblank(dev_priv, pipe); 1409 1410 /* 1411 * The timeout isn't specified, the 2ms used here is based on 1412 * experiment. 1413 * FIXME: Waiting for the request completion could be delayed until 1414 * the next PCODE request based on BSpec. 1415 */ 1416 ret = sandybridge_pcode_write_timeout(dev_priv, 1417 HSW_PCODE_DE_WRITE_FREQ_REQ, 1418 cdclk_state->voltage_level, 150, 2); 1419 if (ret) { 1420 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", 1421 ret, cdclk); 1422 return; 1423 } 1424 1425 intel_update_cdclk(dev_priv); 1426 } 1427 1428 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) 1429 { 1430 u32 cdctl, expected; 1431 1432 intel_update_cdclk(dev_priv); 1433 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); 1434 1435 if (dev_priv->cdclk.hw.vco == 0 || 1436 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) 1437 goto sanitize; 1438 1439 /* DPLL okay; verify the cdclock 1440 * 1441 * Some BIOS versions leave an incorrect decimal frequency value and 1442 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, 1443 * so sanitize this register. 1444 */ 1445 cdctl = I915_READ(CDCLK_CTL); 1446 /* 1447 * Let's ignore the pipe field, since BIOS could have configured the 1448 * dividers both synching to an active pipe, or asynchronously 1449 * (PIPE_NONE). 1450 */ 1451 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE; 1452 1453 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) | 1454 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); 1455 /* 1456 * Disable SSA Precharge when CD clock frequency < 500 MHz, 1457 * enable otherwise. 1458 */ 1459 if (dev_priv->cdclk.hw.cdclk >= 500000) 1460 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 1461 1462 if (cdctl == expected) 1463 /* All well; nothing to sanitize */ 1464 return; 1465 1466 sanitize: 1467 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); 1468 1469 /* force cdclk programming */ 1470 dev_priv->cdclk.hw.cdclk = 0; 1471 1472 /* force full PLL disable + enable */ 1473 dev_priv->cdclk.hw.vco = -1; 1474 } 1475 1476 static void bxt_init_cdclk(struct drm_i915_private *dev_priv) 1477 { 1478 struct intel_cdclk_state cdclk_state; 1479 1480 bxt_sanitize_cdclk(dev_priv); 1481 1482 if (dev_priv->cdclk.hw.cdclk != 0 && 1483 dev_priv->cdclk.hw.vco != 0) 1484 return; 1485 1486 cdclk_state = dev_priv->cdclk.hw; 1487 1488 /* 1489 * FIXME: 1490 * - The initial CDCLK needs to be read from VBT. 1491 * Need to make this change after VBT has changes for BXT. 1492 */ 1493 if (IS_GEMINILAKE(dev_priv)) { 1494 cdclk_state.cdclk = glk_calc_cdclk(0); 1495 cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk); 1496 } else { 1497 cdclk_state.cdclk = bxt_calc_cdclk(0); 1498 cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk); 1499 } 1500 cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk); 1501 1502 bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); 1503 } 1504 1505 static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) 1506 { 1507 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; 1508 1509 cdclk_state.cdclk = cdclk_state.bypass; 1510 cdclk_state.vco = 0; 1511 cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk); 1512 1513 bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); 1514 } 1515 1516 static int cnl_calc_cdclk(int min_cdclk) 1517 { 1518 if (min_cdclk > 336000) 1519 return 528000; 1520 else if (min_cdclk > 168000) 1521 return 336000; 1522 else 1523 return 168000; 1524 } 1525 1526 static u8 cnl_calc_voltage_level(int cdclk) 1527 { 1528 if (cdclk > 336000) 1529 return 2; 1530 else if (cdclk > 168000) 1531 return 1; 1532 else 1533 return 0; 1534 } 1535 1536 static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv, 1537 struct intel_cdclk_state *cdclk_state) 1538 { 1539 u32 val; 1540 1541 if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz) 1542 cdclk_state->ref = 24000; 1543 else 1544 cdclk_state->ref = 19200; 1545 1546 cdclk_state->vco = 0; 1547 1548 val = I915_READ(BXT_DE_PLL_ENABLE); 1549 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) 1550 return; 1551 1552 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) 1553 return; 1554 1555 cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref; 1556 } 1557 1558 static void cnl_get_cdclk(struct drm_i915_private *dev_priv, 1559 struct intel_cdclk_state *cdclk_state) 1560 { 1561 u32 divider; 1562 int div; 1563 1564 cnl_cdclk_pll_update(dev_priv, cdclk_state); 1565 1566 cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref; 1567 1568 if (cdclk_state->vco == 0) 1569 goto out; 1570 1571 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; 1572 1573 switch (divider) { 1574 case BXT_CDCLK_CD2X_DIV_SEL_1: 1575 div = 2; 1576 break; 1577 case BXT_CDCLK_CD2X_DIV_SEL_2: 1578 div = 4; 1579 break; 1580 default: 1581 MISSING_CASE(divider); 1582 return; 1583 } 1584 1585 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div); 1586 1587 out: 1588 /* 1589 * Can't read this out :( Let's assume it's 1590 * at least what the CDCLK frequency requires. 1591 */ 1592 cdclk_state->voltage_level = 1593 cnl_calc_voltage_level(cdclk_state->cdclk); 1594 } 1595 1596 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv) 1597 { 1598 u32 val; 1599 1600 val = I915_READ(BXT_DE_PLL_ENABLE); 1601 val &= ~BXT_DE_PLL_PLL_ENABLE; 1602 I915_WRITE(BXT_DE_PLL_ENABLE, val); 1603 1604 /* Timeout 200us */ 1605 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1)) 1606 DRM_ERROR("timeout waiting for CDCLK PLL unlock\n"); 1607 1608 dev_priv->cdclk.hw.vco = 0; 1609 } 1610 1611 static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) 1612 { 1613 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); 1614 u32 val; 1615 1616 val = CNL_CDCLK_PLL_RATIO(ratio); 1617 I915_WRITE(BXT_DE_PLL_ENABLE, val); 1618 1619 val |= BXT_DE_PLL_PLL_ENABLE; 1620 I915_WRITE(BXT_DE_PLL_ENABLE, val); 1621 1622 /* Timeout 200us */ 1623 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1)) 1624 DRM_ERROR("timeout waiting for CDCLK PLL lock\n"); 1625 1626 dev_priv->cdclk.hw.vco = vco; 1627 } 1628 1629 static void cnl_set_cdclk(struct drm_i915_private *dev_priv, 1630 const struct intel_cdclk_state *cdclk_state, 1631 enum pipe pipe) 1632 { 1633 int cdclk = cdclk_state->cdclk; 1634 int vco = cdclk_state->vco; 1635 u32 val, divider; 1636 int ret; 1637 1638 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, 1639 SKL_CDCLK_PREPARE_FOR_CHANGE, 1640 SKL_CDCLK_READY_FOR_CHANGE, 1641 SKL_CDCLK_READY_FOR_CHANGE, 3); 1642 if (ret) { 1643 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n", 1644 ret); 1645 return; 1646 } 1647 1648 /* cdclk = vco / 2 / div{1,2} */ 1649 switch (DIV_ROUND_CLOSEST(vco, cdclk)) { 1650 default: 1651 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass); 1652 WARN_ON(vco != 0); 1653 /* fall through */ 1654 case 2: 1655 divider = BXT_CDCLK_CD2X_DIV_SEL_1; 1656 break; 1657 case 4: 1658 divider = BXT_CDCLK_CD2X_DIV_SEL_2; 1659 break; 1660 } 1661 1662 if (dev_priv->cdclk.hw.vco != 0 && 1663 dev_priv->cdclk.hw.vco != vco) 1664 cnl_cdclk_pll_disable(dev_priv); 1665 1666 if (dev_priv->cdclk.hw.vco != vco) 1667 cnl_cdclk_pll_enable(dev_priv, vco); 1668 1669 val = divider | skl_cdclk_decimal(cdclk); 1670 if (pipe == INVALID_PIPE) 1671 val |= BXT_CDCLK_CD2X_PIPE_NONE; 1672 else 1673 val |= BXT_CDCLK_CD2X_PIPE(pipe); 1674 I915_WRITE(CDCLK_CTL, val); 1675 1676 if (pipe != INVALID_PIPE) 1677 intel_wait_for_vblank(dev_priv, pipe); 1678 1679 /* inform PCU of the change */ 1680 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, 1681 cdclk_state->voltage_level); 1682 1683 intel_update_cdclk(dev_priv); 1684 1685 /* 1686 * Can't read out the voltage level :( 1687 * Let's just assume everything is as expected. 1688 */ 1689 dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level; 1690 } 1691 1692 static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) 1693 { 1694 int ratio; 1695 1696 if (cdclk == dev_priv->cdclk.hw.bypass) 1697 return 0; 1698 1699 switch (cdclk) { 1700 default: 1701 MISSING_CASE(cdclk); 1702 /* fall through */ 1703 case 168000: 1704 case 336000: 1705 ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28; 1706 break; 1707 case 528000: 1708 ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44; 1709 break; 1710 } 1711 1712 return dev_priv->cdclk.hw.ref * ratio; 1713 } 1714 1715 static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv) 1716 { 1717 u32 cdctl, expected; 1718 1719 intel_update_cdclk(dev_priv); 1720 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); 1721 1722 if (dev_priv->cdclk.hw.vco == 0 || 1723 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) 1724 goto sanitize; 1725 1726 /* DPLL okay; verify the cdclock 1727 * 1728 * Some BIOS versions leave an incorrect decimal frequency value and 1729 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, 1730 * so sanitize this register. 1731 */ 1732 cdctl = I915_READ(CDCLK_CTL); 1733 /* 1734 * Let's ignore the pipe field, since BIOS could have configured the 1735 * dividers both synching to an active pipe, or asynchronously 1736 * (PIPE_NONE). 1737 */ 1738 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE; 1739 1740 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) | 1741 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); 1742 1743 if (cdctl == expected) 1744 /* All well; nothing to sanitize */ 1745 return; 1746 1747 sanitize: 1748 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); 1749 1750 /* force cdclk programming */ 1751 dev_priv->cdclk.hw.cdclk = 0; 1752 1753 /* force full PLL disable + enable */ 1754 dev_priv->cdclk.hw.vco = -1; 1755 } 1756 1757 static int icl_calc_cdclk(int min_cdclk, unsigned int ref) 1758 { 1759 static const int ranges_24[] = { 180000, 192000, 312000, 552000, 648000 }; 1760 static const int ranges_19_38[] = { 172800, 192000, 307200, 556800, 652800 }; 1761 const int *ranges; 1762 int len, i; 1763 1764 switch (ref) { 1765 default: 1766 MISSING_CASE(ref); 1767 /* fall through */ 1768 case 24000: 1769 ranges = ranges_24; 1770 len = ARRAY_SIZE(ranges_24); 1771 break; 1772 case 19200: 1773 case 38400: 1774 ranges = ranges_19_38; 1775 len = ARRAY_SIZE(ranges_19_38); 1776 break; 1777 } 1778 1779 for (i = 0; i < len; i++) { 1780 if (min_cdclk <= ranges[i]) 1781 return ranges[i]; 1782 } 1783 1784 WARN_ON(min_cdclk > ranges[len - 1]); 1785 return ranges[len - 1]; 1786 } 1787 1788 static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) 1789 { 1790 int ratio; 1791 1792 if (cdclk == dev_priv->cdclk.hw.bypass) 1793 return 0; 1794 1795 switch (cdclk) { 1796 default: 1797 MISSING_CASE(cdclk); 1798 /* fall through */ 1799 case 172800: 1800 case 307200: 1801 case 556800: 1802 case 652800: 1803 WARN_ON(dev_priv->cdclk.hw.ref != 19200 && 1804 dev_priv->cdclk.hw.ref != 38400); 1805 break; 1806 case 180000: 1807 case 312000: 1808 case 552000: 1809 case 648000: 1810 WARN_ON(dev_priv->cdclk.hw.ref != 24000); 1811 break; 1812 case 192000: 1813 WARN_ON(dev_priv->cdclk.hw.ref != 19200 && 1814 dev_priv->cdclk.hw.ref != 38400 && 1815 dev_priv->cdclk.hw.ref != 24000); 1816 break; 1817 } 1818 1819 ratio = cdclk / (dev_priv->cdclk.hw.ref / 2); 1820 1821 return dev_priv->cdclk.hw.ref * ratio; 1822 } 1823 1824 static void icl_set_cdclk(struct drm_i915_private *dev_priv, 1825 const struct intel_cdclk_state *cdclk_state, 1826 enum pipe pipe) 1827 { 1828 unsigned int cdclk = cdclk_state->cdclk; 1829 unsigned int vco = cdclk_state->vco; 1830 int ret; 1831 1832 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, 1833 SKL_CDCLK_PREPARE_FOR_CHANGE, 1834 SKL_CDCLK_READY_FOR_CHANGE, 1835 SKL_CDCLK_READY_FOR_CHANGE, 3); 1836 if (ret) { 1837 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n", 1838 ret); 1839 return; 1840 } 1841 1842 if (dev_priv->cdclk.hw.vco != 0 && 1843 dev_priv->cdclk.hw.vco != vco) 1844 cnl_cdclk_pll_disable(dev_priv); 1845 1846 if (dev_priv->cdclk.hw.vco != vco) 1847 cnl_cdclk_pll_enable(dev_priv, vco); 1848 1849 /* 1850 * On ICL CD2X_DIV can only be 1, so we'll never end up changing the 1851 * divider here synchronized to a pipe while CDCLK is on, nor will we 1852 * need the corresponding vblank wait. 1853 */ 1854 I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE | 1855 skl_cdclk_decimal(cdclk)); 1856 1857 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, 1858 cdclk_state->voltage_level); 1859 1860 intel_update_cdclk(dev_priv); 1861 1862 /* 1863 * Can't read out the voltage level :( 1864 * Let's just assume everything is as expected. 1865 */ 1866 dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level; 1867 } 1868 1869 static u8 icl_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) 1870 { 1871 if (IS_ELKHARTLAKE(dev_priv)) { 1872 if (cdclk > 312000) 1873 return 2; 1874 else if (cdclk > 180000) 1875 return 1; 1876 else 1877 return 0; 1878 } else { 1879 if (cdclk > 556800) 1880 return 2; 1881 else if (cdclk > 312000) 1882 return 1; 1883 else 1884 return 0; 1885 } 1886 } 1887 1888 static void icl_get_cdclk(struct drm_i915_private *dev_priv, 1889 struct intel_cdclk_state *cdclk_state) 1890 { 1891 u32 val; 1892 1893 cdclk_state->bypass = 50000; 1894 1895 val = I915_READ(SKL_DSSM); 1896 switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) { 1897 default: 1898 MISSING_CASE(val); 1899 /* fall through */ 1900 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz: 1901 cdclk_state->ref = 24000; 1902 break; 1903 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz: 1904 cdclk_state->ref = 19200; 1905 break; 1906 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz: 1907 cdclk_state->ref = 38400; 1908 break; 1909 } 1910 1911 val = I915_READ(BXT_DE_PLL_ENABLE); 1912 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || 1913 (val & BXT_DE_PLL_LOCK) == 0) { 1914 /* 1915 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but 1916 * setting it to zero is a way to signal that. 1917 */ 1918 cdclk_state->vco = 0; 1919 cdclk_state->cdclk = cdclk_state->bypass; 1920 goto out; 1921 } 1922 1923 cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref; 1924 1925 val = I915_READ(CDCLK_CTL); 1926 WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0); 1927 1928 cdclk_state->cdclk = cdclk_state->vco / 2; 1929 1930 out: 1931 /* 1932 * Can't read this out :( Let's assume it's 1933 * at least what the CDCLK frequency requires. 1934 */ 1935 cdclk_state->voltage_level = 1936 icl_calc_voltage_level(dev_priv, cdclk_state->cdclk); 1937 } 1938 1939 static void icl_init_cdclk(struct drm_i915_private *dev_priv) 1940 { 1941 struct intel_cdclk_state sanitized_state; 1942 u32 val; 1943 1944 /* This sets dev_priv->cdclk.hw. */ 1945 intel_update_cdclk(dev_priv); 1946 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); 1947 1948 /* This means CDCLK disabled. */ 1949 if (dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) 1950 goto sanitize; 1951 1952 val = I915_READ(CDCLK_CTL); 1953 1954 if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0) 1955 goto sanitize; 1956 1957 if ((val & CDCLK_FREQ_DECIMAL_MASK) != 1958 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk)) 1959 goto sanitize; 1960 1961 return; 1962 1963 sanitize: 1964 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); 1965 1966 sanitized_state.ref = dev_priv->cdclk.hw.ref; 1967 sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref); 1968 sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv, 1969 sanitized_state.cdclk); 1970 sanitized_state.voltage_level = 1971 icl_calc_voltage_level(dev_priv, 1972 sanitized_state.cdclk); 1973 1974 icl_set_cdclk(dev_priv, &sanitized_state, INVALID_PIPE); 1975 } 1976 1977 static void icl_uninit_cdclk(struct drm_i915_private *dev_priv) 1978 { 1979 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; 1980 1981 cdclk_state.cdclk = cdclk_state.bypass; 1982 cdclk_state.vco = 0; 1983 cdclk_state.voltage_level = icl_calc_voltage_level(dev_priv, 1984 cdclk_state.cdclk); 1985 1986 icl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); 1987 } 1988 1989 static void cnl_init_cdclk(struct drm_i915_private *dev_priv) 1990 { 1991 struct intel_cdclk_state cdclk_state; 1992 1993 cnl_sanitize_cdclk(dev_priv); 1994 1995 if (dev_priv->cdclk.hw.cdclk != 0 && 1996 dev_priv->cdclk.hw.vco != 0) 1997 return; 1998 1999 cdclk_state = dev_priv->cdclk.hw; 2000 2001 cdclk_state.cdclk = cnl_calc_cdclk(0); 2002 cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk); 2003 cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk); 2004 2005 cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); 2006 } 2007 2008 static void cnl_uninit_cdclk(struct drm_i915_private *dev_priv) 2009 { 2010 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; 2011 2012 cdclk_state.cdclk = cdclk_state.bypass; 2013 cdclk_state.vco = 0; 2014 cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk); 2015 2016 cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); 2017 } 2018 2019 /** 2020 * intel_cdclk_init - Initialize CDCLK 2021 * @i915: i915 device 2022 * 2023 * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and 2024 * sanitizing the state of the hardware if needed. This is generally done only 2025 * during the display core initialization sequence, after which the DMC will 2026 * take care of turning CDCLK off/on as needed. 2027 */ 2028 void intel_cdclk_init(struct drm_i915_private *i915) 2029 { 2030 if (INTEL_GEN(i915) >= 11) 2031 icl_init_cdclk(i915); 2032 else if (IS_CANNONLAKE(i915)) 2033 cnl_init_cdclk(i915); 2034 else if (IS_GEN9_BC(i915)) 2035 skl_init_cdclk(i915); 2036 else if (IS_GEN9_LP(i915)) 2037 bxt_init_cdclk(i915); 2038 } 2039 2040 /** 2041 * intel_cdclk_uninit - Uninitialize CDCLK 2042 * @i915: i915 device 2043 * 2044 * Uninitialize CDCLK. This is done only during the display core 2045 * uninitialization sequence. 2046 */ 2047 void intel_cdclk_uninit(struct drm_i915_private *i915) 2048 { 2049 if (INTEL_GEN(i915) >= 11) 2050 icl_uninit_cdclk(i915); 2051 else if (IS_CANNONLAKE(i915)) 2052 cnl_uninit_cdclk(i915); 2053 else if (IS_GEN9_BC(i915)) 2054 skl_uninit_cdclk(i915); 2055 else if (IS_GEN9_LP(i915)) 2056 bxt_uninit_cdclk(i915); 2057 } 2058 2059 /** 2060 * intel_cdclk_needs_modeset - Determine if two CDCLK states require a modeset on all pipes 2061 * @a: first CDCLK state 2062 * @b: second CDCLK state 2063 * 2064 * Returns: 2065 * True if the CDCLK states require pipes to be off during reprogramming, false if not. 2066 */ 2067 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a, 2068 const struct intel_cdclk_state *b) 2069 { 2070 return a->cdclk != b->cdclk || 2071 a->vco != b->vco || 2072 a->ref != b->ref; 2073 } 2074 2075 /** 2076 * intel_cdclk_needs_cd2x_update - Determine if two CDCLK states require a cd2x divider update 2077 * @dev_priv: Not a CDCLK state, it's the drm_i915_private! 2078 * @a: first CDCLK state 2079 * @b: second CDCLK state 2080 * 2081 * Returns: 2082 * True if the CDCLK states require just a cd2x divider update, false if not. 2083 */ 2084 bool intel_cdclk_needs_cd2x_update(struct drm_i915_private *dev_priv, 2085 const struct intel_cdclk_state *a, 2086 const struct intel_cdclk_state *b) 2087 { 2088 /* Older hw doesn't have the capability */ 2089 if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv)) 2090 return false; 2091 2092 return a->cdclk != b->cdclk && 2093 a->vco == b->vco && 2094 a->ref == b->ref; 2095 } 2096 2097 /** 2098 * intel_cdclk_changed - Determine if two CDCLK states are different 2099 * @a: first CDCLK state 2100 * @b: second CDCLK state 2101 * 2102 * Returns: 2103 * True if the CDCLK states don't match, false if they do. 2104 */ 2105 bool intel_cdclk_changed(const struct intel_cdclk_state *a, 2106 const struct intel_cdclk_state *b) 2107 { 2108 return intel_cdclk_needs_modeset(a, b) || 2109 a->voltage_level != b->voltage_level; 2110 } 2111 2112 /** 2113 * intel_cdclk_swap_state - make atomic CDCLK configuration effective 2114 * @state: atomic state 2115 * 2116 * This is the CDCLK version of drm_atomic_helper_swap_state() since the 2117 * helper does not handle driver-specific global state. 2118 * 2119 * Similarly to the atomic helpers this function does a complete swap, 2120 * i.e. it also puts the old state into @state. This is used by the commit 2121 * code to determine how CDCLK has changed (for instance did it increase or 2122 * decrease). 2123 */ 2124 void intel_cdclk_swap_state(struct intel_atomic_state *state) 2125 { 2126 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2127 2128 swap(state->cdclk.logical, dev_priv->cdclk.logical); 2129 swap(state->cdclk.actual, dev_priv->cdclk.actual); 2130 } 2131 2132 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state, 2133 const char *context) 2134 { 2135 DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", 2136 context, cdclk_state->cdclk, cdclk_state->vco, 2137 cdclk_state->ref, cdclk_state->bypass, 2138 cdclk_state->voltage_level); 2139 } 2140 2141 /** 2142 * intel_set_cdclk - Push the CDCLK state to the hardware 2143 * @dev_priv: i915 device 2144 * @cdclk_state: new CDCLK state 2145 * @pipe: pipe with which to synchronize the update 2146 * 2147 * Program the hardware based on the passed in CDCLK state, 2148 * if necessary. 2149 */ 2150 static void intel_set_cdclk(struct drm_i915_private *dev_priv, 2151 const struct intel_cdclk_state *cdclk_state, 2152 enum pipe pipe) 2153 { 2154 if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state)) 2155 return; 2156 2157 if (WARN_ON_ONCE(!dev_priv->display.set_cdclk)) 2158 return; 2159 2160 intel_dump_cdclk_state(cdclk_state, "Changing CDCLK to"); 2161 2162 dev_priv->display.set_cdclk(dev_priv, cdclk_state, pipe); 2163 2164 if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state), 2165 "cdclk state doesn't match!\n")) { 2166 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "[hw state]"); 2167 intel_dump_cdclk_state(cdclk_state, "[sw state]"); 2168 } 2169 } 2170 2171 /** 2172 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware 2173 * @dev_priv: i915 device 2174 * @old_state: old CDCLK state 2175 * @new_state: new CDCLK state 2176 * @pipe: pipe with which to synchronize the update 2177 * 2178 * Program the hardware before updating the HW plane state based on the passed 2179 * in CDCLK state, if necessary. 2180 */ 2181 void 2182 intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv, 2183 const struct intel_cdclk_state *old_state, 2184 const struct intel_cdclk_state *new_state, 2185 enum pipe pipe) 2186 { 2187 if (pipe == INVALID_PIPE || old_state->cdclk <= new_state->cdclk) 2188 intel_set_cdclk(dev_priv, new_state, pipe); 2189 } 2190 2191 /** 2192 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware 2193 * @dev_priv: i915 device 2194 * @old_state: old CDCLK state 2195 * @new_state: new CDCLK state 2196 * @pipe: pipe with which to synchronize the update 2197 * 2198 * Program the hardware after updating the HW plane state based on the passed 2199 * in CDCLK state, if necessary. 2200 */ 2201 void 2202 intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv, 2203 const struct intel_cdclk_state *old_state, 2204 const struct intel_cdclk_state *new_state, 2205 enum pipe pipe) 2206 { 2207 if (pipe != INVALID_PIPE && old_state->cdclk > new_state->cdclk) 2208 intel_set_cdclk(dev_priv, new_state, pipe); 2209 } 2210 2211 static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv, 2212 int pixel_rate) 2213 { 2214 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 2215 return DIV_ROUND_UP(pixel_rate, 2); 2216 else if (IS_GEN(dev_priv, 9) || 2217 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2218 return pixel_rate; 2219 else if (IS_CHERRYVIEW(dev_priv)) 2220 return DIV_ROUND_UP(pixel_rate * 100, 95); 2221 else 2222 return DIV_ROUND_UP(pixel_rate * 100, 90); 2223 } 2224 2225 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) 2226 { 2227 struct drm_i915_private *dev_priv = 2228 to_i915(crtc_state->base.crtc->dev); 2229 int min_cdclk; 2230 2231 if (!crtc_state->base.enable) 2232 return 0; 2233 2234 min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate); 2235 2236 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ 2237 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state)) 2238 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95); 2239 2240 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, 2241 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else 2242 * there may be audio corruption or screen corruption." This cdclk 2243 * restriction for GLK is 316.8 MHz. 2244 */ 2245 if (intel_crtc_has_dp_encoder(crtc_state) && 2246 crtc_state->has_audio && 2247 crtc_state->port_clock >= 540000 && 2248 crtc_state->lane_count == 4) { 2249 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { 2250 /* Display WA #1145: glk,cnl */ 2251 min_cdclk = max(316800, min_cdclk); 2252 } else if (IS_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv)) { 2253 /* Display WA #1144: skl,bxt */ 2254 min_cdclk = max(432000, min_cdclk); 2255 } 2256 } 2257 2258 /* 2259 * According to BSpec, "The CD clock frequency must be at least twice 2260 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. 2261 */ 2262 if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) 2263 min_cdclk = max(2 * 96000, min_cdclk); 2264 2265 /* 2266 * "For DP audio configuration, cdclk frequency shall be set to 2267 * meet the following requirements: 2268 * DP Link Frequency(MHz) | Cdclk frequency(MHz) 2269 * 270 | 320 or higher 2270 * 162 | 200 or higher" 2271 */ 2272 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2273 intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio) 2274 min_cdclk = max(crtc_state->port_clock, min_cdclk); 2275 2276 /* 2277 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower 2278 * than 320000KHz. 2279 */ 2280 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 2281 IS_VALLEYVIEW(dev_priv)) 2282 min_cdclk = max(320000, min_cdclk); 2283 2284 /* 2285 * On Geminilake once the CDCLK gets as low as 79200 2286 * picture gets unstable, despite that values are 2287 * correct for DSI PLL and DE PLL. 2288 */ 2289 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 2290 IS_GEMINILAKE(dev_priv)) 2291 min_cdclk = max(158400, min_cdclk); 2292 2293 if (min_cdclk > dev_priv->max_cdclk_freq) { 2294 DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n", 2295 min_cdclk, dev_priv->max_cdclk_freq); 2296 return -EINVAL; 2297 } 2298 2299 return min_cdclk; 2300 } 2301 2302 static int intel_compute_min_cdclk(struct intel_atomic_state *state) 2303 { 2304 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2305 struct intel_crtc *crtc; 2306 struct intel_crtc_state *crtc_state; 2307 int min_cdclk, i; 2308 enum pipe pipe; 2309 2310 memcpy(state->min_cdclk, dev_priv->min_cdclk, 2311 sizeof(state->min_cdclk)); 2312 2313 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2314 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 2315 if (min_cdclk < 0) 2316 return min_cdclk; 2317 2318 state->min_cdclk[i] = min_cdclk; 2319 } 2320 2321 min_cdclk = state->cdclk.force_min_cdclk; 2322 for_each_pipe(dev_priv, pipe) 2323 min_cdclk = max(state->min_cdclk[pipe], min_cdclk); 2324 2325 return min_cdclk; 2326 } 2327 2328 /* 2329 * Note that this functions assumes that 0 is 2330 * the lowest voltage value, and higher values 2331 * correspond to increasingly higher voltages. 2332 * 2333 * Should that relationship no longer hold on 2334 * future platforms this code will need to be 2335 * adjusted. 2336 */ 2337 static u8 cnl_compute_min_voltage_level(struct intel_atomic_state *state) 2338 { 2339 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2340 struct intel_crtc *crtc; 2341 struct intel_crtc_state *crtc_state; 2342 u8 min_voltage_level; 2343 int i; 2344 enum pipe pipe; 2345 2346 memcpy(state->min_voltage_level, dev_priv->min_voltage_level, 2347 sizeof(state->min_voltage_level)); 2348 2349 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2350 if (crtc_state->base.enable) 2351 state->min_voltage_level[i] = 2352 crtc_state->min_voltage_level; 2353 else 2354 state->min_voltage_level[i] = 0; 2355 } 2356 2357 min_voltage_level = 0; 2358 for_each_pipe(dev_priv, pipe) 2359 min_voltage_level = max(state->min_voltage_level[pipe], 2360 min_voltage_level); 2361 2362 return min_voltage_level; 2363 } 2364 2365 static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state) 2366 { 2367 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2368 int min_cdclk, cdclk; 2369 2370 min_cdclk = intel_compute_min_cdclk(state); 2371 if (min_cdclk < 0) 2372 return min_cdclk; 2373 2374 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); 2375 2376 state->cdclk.logical.cdclk = cdclk; 2377 state->cdclk.logical.voltage_level = 2378 vlv_calc_voltage_level(dev_priv, cdclk); 2379 2380 if (!state->active_crtcs) { 2381 cdclk = vlv_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk); 2382 2383 state->cdclk.actual.cdclk = cdclk; 2384 state->cdclk.actual.voltage_level = 2385 vlv_calc_voltage_level(dev_priv, cdclk); 2386 } else { 2387 state->cdclk.actual = state->cdclk.logical; 2388 } 2389 2390 return 0; 2391 } 2392 2393 static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state) 2394 { 2395 int min_cdclk, cdclk; 2396 2397 min_cdclk = intel_compute_min_cdclk(state); 2398 if (min_cdclk < 0) 2399 return min_cdclk; 2400 2401 /* 2402 * FIXME should also account for plane ratio 2403 * once 64bpp pixel formats are supported. 2404 */ 2405 cdclk = bdw_calc_cdclk(min_cdclk); 2406 2407 state->cdclk.logical.cdclk = cdclk; 2408 state->cdclk.logical.voltage_level = 2409 bdw_calc_voltage_level(cdclk); 2410 2411 if (!state->active_crtcs) { 2412 cdclk = bdw_calc_cdclk(state->cdclk.force_min_cdclk); 2413 2414 state->cdclk.actual.cdclk = cdclk; 2415 state->cdclk.actual.voltage_level = 2416 bdw_calc_voltage_level(cdclk); 2417 } else { 2418 state->cdclk.actual = state->cdclk.logical; 2419 } 2420 2421 return 0; 2422 } 2423 2424 static int skl_dpll0_vco(struct intel_atomic_state *state) 2425 { 2426 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2427 struct intel_crtc *crtc; 2428 struct intel_crtc_state *crtc_state; 2429 int vco, i; 2430 2431 vco = state->cdclk.logical.vco; 2432 if (!vco) 2433 vco = dev_priv->skl_preferred_vco_freq; 2434 2435 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2436 if (!crtc_state->base.enable) 2437 continue; 2438 2439 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 2440 continue; 2441 2442 /* 2443 * DPLL0 VCO may need to be adjusted to get the correct 2444 * clock for eDP. This will affect cdclk as well. 2445 */ 2446 switch (crtc_state->port_clock / 2) { 2447 case 108000: 2448 case 216000: 2449 vco = 8640000; 2450 break; 2451 default: 2452 vco = 8100000; 2453 break; 2454 } 2455 } 2456 2457 return vco; 2458 } 2459 2460 static int skl_modeset_calc_cdclk(struct intel_atomic_state *state) 2461 { 2462 int min_cdclk, cdclk, vco; 2463 2464 min_cdclk = intel_compute_min_cdclk(state); 2465 if (min_cdclk < 0) 2466 return min_cdclk; 2467 2468 vco = skl_dpll0_vco(state); 2469 2470 /* 2471 * FIXME should also account for plane ratio 2472 * once 64bpp pixel formats are supported. 2473 */ 2474 cdclk = skl_calc_cdclk(min_cdclk, vco); 2475 2476 state->cdclk.logical.vco = vco; 2477 state->cdclk.logical.cdclk = cdclk; 2478 state->cdclk.logical.voltage_level = 2479 skl_calc_voltage_level(cdclk); 2480 2481 if (!state->active_crtcs) { 2482 cdclk = skl_calc_cdclk(state->cdclk.force_min_cdclk, vco); 2483 2484 state->cdclk.actual.vco = vco; 2485 state->cdclk.actual.cdclk = cdclk; 2486 state->cdclk.actual.voltage_level = 2487 skl_calc_voltage_level(cdclk); 2488 } else { 2489 state->cdclk.actual = state->cdclk.logical; 2490 } 2491 2492 return 0; 2493 } 2494 2495 static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state) 2496 { 2497 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2498 int min_cdclk, cdclk, vco; 2499 2500 min_cdclk = intel_compute_min_cdclk(state); 2501 if (min_cdclk < 0) 2502 return min_cdclk; 2503 2504 if (IS_GEMINILAKE(dev_priv)) { 2505 cdclk = glk_calc_cdclk(min_cdclk); 2506 vco = glk_de_pll_vco(dev_priv, cdclk); 2507 } else { 2508 cdclk = bxt_calc_cdclk(min_cdclk); 2509 vco = bxt_de_pll_vco(dev_priv, cdclk); 2510 } 2511 2512 state->cdclk.logical.vco = vco; 2513 state->cdclk.logical.cdclk = cdclk; 2514 state->cdclk.logical.voltage_level = 2515 bxt_calc_voltage_level(cdclk); 2516 2517 if (!state->active_crtcs) { 2518 if (IS_GEMINILAKE(dev_priv)) { 2519 cdclk = glk_calc_cdclk(state->cdclk.force_min_cdclk); 2520 vco = glk_de_pll_vco(dev_priv, cdclk); 2521 } else { 2522 cdclk = bxt_calc_cdclk(state->cdclk.force_min_cdclk); 2523 vco = bxt_de_pll_vco(dev_priv, cdclk); 2524 } 2525 2526 state->cdclk.actual.vco = vco; 2527 state->cdclk.actual.cdclk = cdclk; 2528 state->cdclk.actual.voltage_level = 2529 bxt_calc_voltage_level(cdclk); 2530 } else { 2531 state->cdclk.actual = state->cdclk.logical; 2532 } 2533 2534 return 0; 2535 } 2536 2537 static int cnl_modeset_calc_cdclk(struct intel_atomic_state *state) 2538 { 2539 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2540 int min_cdclk, cdclk, vco; 2541 2542 min_cdclk = intel_compute_min_cdclk(state); 2543 if (min_cdclk < 0) 2544 return min_cdclk; 2545 2546 cdclk = cnl_calc_cdclk(min_cdclk); 2547 vco = cnl_cdclk_pll_vco(dev_priv, cdclk); 2548 2549 state->cdclk.logical.vco = vco; 2550 state->cdclk.logical.cdclk = cdclk; 2551 state->cdclk.logical.voltage_level = 2552 max(cnl_calc_voltage_level(cdclk), 2553 cnl_compute_min_voltage_level(state)); 2554 2555 if (!state->active_crtcs) { 2556 cdclk = cnl_calc_cdclk(state->cdclk.force_min_cdclk); 2557 vco = cnl_cdclk_pll_vco(dev_priv, cdclk); 2558 2559 state->cdclk.actual.vco = vco; 2560 state->cdclk.actual.cdclk = cdclk; 2561 state->cdclk.actual.voltage_level = 2562 cnl_calc_voltage_level(cdclk); 2563 } else { 2564 state->cdclk.actual = state->cdclk.logical; 2565 } 2566 2567 return 0; 2568 } 2569 2570 static int icl_modeset_calc_cdclk(struct intel_atomic_state *state) 2571 { 2572 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2573 unsigned int ref = state->cdclk.logical.ref; 2574 int min_cdclk, cdclk, vco; 2575 2576 min_cdclk = intel_compute_min_cdclk(state); 2577 if (min_cdclk < 0) 2578 return min_cdclk; 2579 2580 cdclk = icl_calc_cdclk(min_cdclk, ref); 2581 vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk); 2582 2583 state->cdclk.logical.vco = vco; 2584 state->cdclk.logical.cdclk = cdclk; 2585 state->cdclk.logical.voltage_level = 2586 max(icl_calc_voltage_level(dev_priv, cdclk), 2587 cnl_compute_min_voltage_level(state)); 2588 2589 if (!state->active_crtcs) { 2590 cdclk = icl_calc_cdclk(state->cdclk.force_min_cdclk, ref); 2591 vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk); 2592 2593 state->cdclk.actual.vco = vco; 2594 state->cdclk.actual.cdclk = cdclk; 2595 state->cdclk.actual.voltage_level = 2596 icl_calc_voltage_level(dev_priv, cdclk); 2597 } else { 2598 state->cdclk.actual = state->cdclk.logical; 2599 } 2600 2601 return 0; 2602 } 2603 2604 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) 2605 { 2606 int max_cdclk_freq = dev_priv->max_cdclk_freq; 2607 2608 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 2609 return 2 * max_cdclk_freq; 2610 else if (IS_GEN(dev_priv, 9) || 2611 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2612 return max_cdclk_freq; 2613 else if (IS_CHERRYVIEW(dev_priv)) 2614 return max_cdclk_freq*95/100; 2615 else if (INTEL_GEN(dev_priv) < 4) 2616 return 2*max_cdclk_freq*90/100; 2617 else 2618 return max_cdclk_freq*90/100; 2619 } 2620 2621 /** 2622 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency 2623 * @dev_priv: i915 device 2624 * 2625 * Determine the maximum CDCLK frequency the platform supports, and also 2626 * derive the maximum dot clock frequency the maximum CDCLK frequency 2627 * allows. 2628 */ 2629 void intel_update_max_cdclk(struct drm_i915_private *dev_priv) 2630 { 2631 if (IS_ELKHARTLAKE(dev_priv)) { 2632 if (dev_priv->cdclk.hw.ref == 24000) 2633 dev_priv->max_cdclk_freq = 552000; 2634 else 2635 dev_priv->max_cdclk_freq = 556800; 2636 } else if (INTEL_GEN(dev_priv) >= 11) { 2637 if (dev_priv->cdclk.hw.ref == 24000) 2638 dev_priv->max_cdclk_freq = 648000; 2639 else 2640 dev_priv->max_cdclk_freq = 652800; 2641 } else if (IS_CANNONLAKE(dev_priv)) { 2642 dev_priv->max_cdclk_freq = 528000; 2643 } else if (IS_GEN9_BC(dev_priv)) { 2644 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; 2645 int max_cdclk, vco; 2646 2647 vco = dev_priv->skl_preferred_vco_freq; 2648 WARN_ON(vco != 8100000 && vco != 8640000); 2649 2650 /* 2651 * Use the lower (vco 8640) cdclk values as a 2652 * first guess. skl_calc_cdclk() will correct it 2653 * if the preferred vco is 8100 instead. 2654 */ 2655 if (limit == SKL_DFSM_CDCLK_LIMIT_675) 2656 max_cdclk = 617143; 2657 else if (limit == SKL_DFSM_CDCLK_LIMIT_540) 2658 max_cdclk = 540000; 2659 else if (limit == SKL_DFSM_CDCLK_LIMIT_450) 2660 max_cdclk = 432000; 2661 else 2662 max_cdclk = 308571; 2663 2664 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); 2665 } else if (IS_GEMINILAKE(dev_priv)) { 2666 dev_priv->max_cdclk_freq = 316800; 2667 } else if (IS_BROXTON(dev_priv)) { 2668 dev_priv->max_cdclk_freq = 624000; 2669 } else if (IS_BROADWELL(dev_priv)) { 2670 /* 2671 * FIXME with extra cooling we can allow 2672 * 540 MHz for ULX and 675 Mhz for ULT. 2673 * How can we know if extra cooling is 2674 * available? PCI ID, VTB, something else? 2675 */ 2676 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) 2677 dev_priv->max_cdclk_freq = 450000; 2678 else if (IS_BDW_ULX(dev_priv)) 2679 dev_priv->max_cdclk_freq = 450000; 2680 else if (IS_BDW_ULT(dev_priv)) 2681 dev_priv->max_cdclk_freq = 540000; 2682 else 2683 dev_priv->max_cdclk_freq = 675000; 2684 } else if (IS_CHERRYVIEW(dev_priv)) { 2685 dev_priv->max_cdclk_freq = 320000; 2686 } else if (IS_VALLEYVIEW(dev_priv)) { 2687 dev_priv->max_cdclk_freq = 400000; 2688 } else { 2689 /* otherwise assume cdclk is fixed */ 2690 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk; 2691 } 2692 2693 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); 2694 2695 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", 2696 dev_priv->max_cdclk_freq); 2697 2698 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", 2699 dev_priv->max_dotclk_freq); 2700 } 2701 2702 /** 2703 * intel_update_cdclk - Determine the current CDCLK frequency 2704 * @dev_priv: i915 device 2705 * 2706 * Determine the current CDCLK frequency. 2707 */ 2708 void intel_update_cdclk(struct drm_i915_private *dev_priv) 2709 { 2710 dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw); 2711 2712 /* 2713 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): 2714 * Programmng [sic] note: bit[9:2] should be programmed to the number 2715 * of cdclk that generates 4MHz reference clock freq which is used to 2716 * generate GMBus clock. This will vary with the cdclk freq. 2717 */ 2718 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 2719 I915_WRITE(GMBUSFREQ_VLV, 2720 DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000)); 2721 } 2722 2723 static int cnp_rawclk(struct drm_i915_private *dev_priv) 2724 { 2725 u32 rawclk; 2726 int divider, fraction; 2727 2728 if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { 2729 /* 24 MHz */ 2730 divider = 24000; 2731 fraction = 0; 2732 } else { 2733 /* 19.2 MHz */ 2734 divider = 19000; 2735 fraction = 200; 2736 } 2737 2738 rawclk = CNP_RAWCLK_DIV(divider / 1000); 2739 if (fraction) { 2740 int numerator = 1; 2741 2742 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000, 2743 fraction) - 1); 2744 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 2745 rawclk |= ICP_RAWCLK_NUM(numerator); 2746 } 2747 2748 I915_WRITE(PCH_RAWCLK_FREQ, rawclk); 2749 return divider + fraction; 2750 } 2751 2752 static int pch_rawclk(struct drm_i915_private *dev_priv) 2753 { 2754 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; 2755 } 2756 2757 static int vlv_hrawclk(struct drm_i915_private *dev_priv) 2758 { 2759 /* RAWCLK_FREQ_VLV register updated from power well code */ 2760 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", 2761 CCK_DISPLAY_REF_CLOCK_CONTROL); 2762 } 2763 2764 static int g4x_hrawclk(struct drm_i915_private *dev_priv) 2765 { 2766 u32 clkcfg; 2767 2768 /* hrawclock is 1/4 the FSB frequency */ 2769 clkcfg = I915_READ(CLKCFG); 2770 switch (clkcfg & CLKCFG_FSB_MASK) { 2771 case CLKCFG_FSB_400: 2772 return 100000; 2773 case CLKCFG_FSB_533: 2774 return 133333; 2775 case CLKCFG_FSB_667: 2776 return 166667; 2777 case CLKCFG_FSB_800: 2778 return 200000; 2779 case CLKCFG_FSB_1067: 2780 case CLKCFG_FSB_1067_ALT: 2781 return 266667; 2782 case CLKCFG_FSB_1333: 2783 case CLKCFG_FSB_1333_ALT: 2784 return 333333; 2785 default: 2786 return 133333; 2787 } 2788 } 2789 2790 /** 2791 * intel_update_rawclk - Determine the current RAWCLK frequency 2792 * @dev_priv: i915 device 2793 * 2794 * Determine the current RAWCLK frequency. RAWCLK is a fixed 2795 * frequency clock so this needs to done only once. 2796 */ 2797 void intel_update_rawclk(struct drm_i915_private *dev_priv) 2798 { 2799 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) 2800 dev_priv->rawclk_freq = cnp_rawclk(dev_priv); 2801 else if (HAS_PCH_SPLIT(dev_priv)) 2802 dev_priv->rawclk_freq = pch_rawclk(dev_priv); 2803 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 2804 dev_priv->rawclk_freq = vlv_hrawclk(dev_priv); 2805 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) 2806 dev_priv->rawclk_freq = g4x_hrawclk(dev_priv); 2807 else 2808 /* no rawclk on other platforms, or no need to know it */ 2809 return; 2810 2811 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); 2812 } 2813 2814 /** 2815 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks 2816 * @dev_priv: i915 device 2817 */ 2818 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) 2819 { 2820 if (INTEL_GEN(dev_priv) >= 11) { 2821 dev_priv->display.set_cdclk = icl_set_cdclk; 2822 dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk; 2823 } else if (IS_CANNONLAKE(dev_priv)) { 2824 dev_priv->display.set_cdclk = cnl_set_cdclk; 2825 dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk; 2826 } else if (IS_GEN9_LP(dev_priv)) { 2827 dev_priv->display.set_cdclk = bxt_set_cdclk; 2828 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; 2829 } else if (IS_GEN9_BC(dev_priv)) { 2830 dev_priv->display.set_cdclk = skl_set_cdclk; 2831 dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk; 2832 } else if (IS_BROADWELL(dev_priv)) { 2833 dev_priv->display.set_cdclk = bdw_set_cdclk; 2834 dev_priv->display.modeset_calc_cdclk = bdw_modeset_calc_cdclk; 2835 } else if (IS_CHERRYVIEW(dev_priv)) { 2836 dev_priv->display.set_cdclk = chv_set_cdclk; 2837 dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk; 2838 } else if (IS_VALLEYVIEW(dev_priv)) { 2839 dev_priv->display.set_cdclk = vlv_set_cdclk; 2840 dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk; 2841 } 2842 2843 if (INTEL_GEN(dev_priv) >= 11) 2844 dev_priv->display.get_cdclk = icl_get_cdclk; 2845 else if (IS_CANNONLAKE(dev_priv)) 2846 dev_priv->display.get_cdclk = cnl_get_cdclk; 2847 else if (IS_GEN9_LP(dev_priv)) 2848 dev_priv->display.get_cdclk = bxt_get_cdclk; 2849 else if (IS_GEN9_BC(dev_priv)) 2850 dev_priv->display.get_cdclk = skl_get_cdclk; 2851 else if (IS_BROADWELL(dev_priv)) 2852 dev_priv->display.get_cdclk = bdw_get_cdclk; 2853 else if (IS_HASWELL(dev_priv)) 2854 dev_priv->display.get_cdclk = hsw_get_cdclk; 2855 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 2856 dev_priv->display.get_cdclk = vlv_get_cdclk; 2857 else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) 2858 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; 2859 else if (IS_GEN(dev_priv, 5)) 2860 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk; 2861 else if (IS_GM45(dev_priv)) 2862 dev_priv->display.get_cdclk = gm45_get_cdclk; 2863 else if (IS_G45(dev_priv)) 2864 dev_priv->display.get_cdclk = g33_get_cdclk; 2865 else if (IS_I965GM(dev_priv)) 2866 dev_priv->display.get_cdclk = i965gm_get_cdclk; 2867 else if (IS_I965G(dev_priv)) 2868 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; 2869 else if (IS_PINEVIEW(dev_priv)) 2870 dev_priv->display.get_cdclk = pnv_get_cdclk; 2871 else if (IS_G33(dev_priv)) 2872 dev_priv->display.get_cdclk = g33_get_cdclk; 2873 else if (IS_I945GM(dev_priv)) 2874 dev_priv->display.get_cdclk = i945gm_get_cdclk; 2875 else if (IS_I945G(dev_priv)) 2876 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; 2877 else if (IS_I915GM(dev_priv)) 2878 dev_priv->display.get_cdclk = i915gm_get_cdclk; 2879 else if (IS_I915G(dev_priv)) 2880 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk; 2881 else if (IS_I865G(dev_priv)) 2882 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk; 2883 else if (IS_I85X(dev_priv)) 2884 dev_priv->display.get_cdclk = i85x_get_cdclk; 2885 else if (IS_I845G(dev_priv)) 2886 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk; 2887 else { /* 830 */ 2888 WARN(!IS_I830(dev_priv), 2889 "Unknown platform. Assuming 133 MHz CDCLK\n"); 2890 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk; 2891 } 2892 } 2893