1 /* 2 * Copyright © 2006-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/time.h> 25 26 #include "intel_atomic.h" 27 #include "intel_atomic_plane.h" 28 #include "intel_audio.h" 29 #include "intel_bw.h" 30 #include "intel_cdclk.h" 31 #include "intel_crtc.h" 32 #include "intel_de.h" 33 #include "intel_display_types.h" 34 #include "intel_pcode.h" 35 #include "intel_psr.h" 36 #include "vlv_sideband.h" 37 38 /** 39 * DOC: CDCLK / RAWCLK 40 * 41 * The display engine uses several different clocks to do its work. There 42 * are two main clocks involved that aren't directly related to the actual 43 * pixel clock or any symbol/bit clock of the actual output port. These 44 * are the core display clock (CDCLK) and RAWCLK. 45 * 46 * CDCLK clocks most of the display pipe logic, and thus its frequency 47 * must be high enough to support the rate at which pixels are flowing 48 * through the pipes. Downscaling must also be accounted as that increases 49 * the effective pixel rate. 50 * 51 * On several platforms the CDCLK frequency can be changed dynamically 52 * to minimize power consumption for a given display configuration. 53 * Typically changes to the CDCLK frequency require all the display pipes 54 * to be shut down while the frequency is being changed. 55 * 56 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. 57 * DMC will not change the active CDCLK frequency however, so that part 58 * will still be performed by the driver directly. 59 * 60 * RAWCLK is a fixed frequency clock, often used by various auxiliary 61 * blocks such as AUX CH or backlight PWM. Hence the only thing we 62 * really need to know about RAWCLK is its frequency so that various 63 * dividers can be programmed correctly. 64 */ 65 66 void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv, 67 struct intel_cdclk_config *cdclk_config) 68 { 69 dev_priv->cdclk_funcs->get_cdclk(dev_priv, cdclk_config); 70 } 71 72 static int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state) 73 { 74 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 75 return dev_priv->cdclk_funcs->bw_calc_min_cdclk(state); 76 } 77 78 static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv, 79 const struct intel_cdclk_config *cdclk_config, 80 enum pipe pipe) 81 { 82 dev_priv->cdclk_funcs->set_cdclk(dev_priv, cdclk_config, pipe); 83 } 84 85 static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv, 86 struct intel_cdclk_state *cdclk_config) 87 { 88 return dev_priv->cdclk_funcs->modeset_calc_cdclk(cdclk_config); 89 } 90 91 static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv, 92 int cdclk) 93 { 94 return dev_priv->cdclk_funcs->calc_voltage_level(cdclk); 95 } 96 97 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, 98 struct intel_cdclk_config *cdclk_config) 99 { 100 cdclk_config->cdclk = 133333; 101 } 102 103 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, 104 struct intel_cdclk_config *cdclk_config) 105 { 106 cdclk_config->cdclk = 200000; 107 } 108 109 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, 110 struct intel_cdclk_config *cdclk_config) 111 { 112 cdclk_config->cdclk = 266667; 113 } 114 115 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, 116 struct intel_cdclk_config *cdclk_config) 117 { 118 cdclk_config->cdclk = 333333; 119 } 120 121 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, 122 struct intel_cdclk_config *cdclk_config) 123 { 124 cdclk_config->cdclk = 400000; 125 } 126 127 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, 128 struct intel_cdclk_config *cdclk_config) 129 { 130 cdclk_config->cdclk = 450000; 131 } 132 133 static void i85x_get_cdclk(struct drm_i915_private *dev_priv, 134 struct intel_cdclk_config *cdclk_config) 135 { 136 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 137 u16 hpllcc = 0; 138 139 /* 140 * 852GM/852GMV only supports 133 MHz and the HPLLCC 141 * encoding is different :( 142 * FIXME is this the right way to detect 852GM/852GMV? 143 */ 144 if (pdev->revision == 0x1) { 145 cdclk_config->cdclk = 133333; 146 return; 147 } 148 149 pci_bus_read_config_word(pdev->bus, 150 PCI_DEVFN(0, 3), HPLLCC, &hpllcc); 151 152 /* Assume that the hardware is in the high speed state. This 153 * should be the default. 154 */ 155 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 156 case GC_CLOCK_133_200: 157 case GC_CLOCK_133_200_2: 158 case GC_CLOCK_100_200: 159 cdclk_config->cdclk = 200000; 160 break; 161 case GC_CLOCK_166_250: 162 cdclk_config->cdclk = 250000; 163 break; 164 case GC_CLOCK_100_133: 165 cdclk_config->cdclk = 133333; 166 break; 167 case GC_CLOCK_133_266: 168 case GC_CLOCK_133_266_2: 169 case GC_CLOCK_166_266: 170 cdclk_config->cdclk = 266667; 171 break; 172 } 173 } 174 175 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, 176 struct intel_cdclk_config *cdclk_config) 177 { 178 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 179 u16 gcfgc = 0; 180 181 pci_read_config_word(pdev, GCFGC, &gcfgc); 182 183 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 184 cdclk_config->cdclk = 133333; 185 return; 186 } 187 188 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 189 case GC_DISPLAY_CLOCK_333_320_MHZ: 190 cdclk_config->cdclk = 333333; 191 break; 192 default: 193 case GC_DISPLAY_CLOCK_190_200_MHZ: 194 cdclk_config->cdclk = 190000; 195 break; 196 } 197 } 198 199 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, 200 struct intel_cdclk_config *cdclk_config) 201 { 202 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 203 u16 gcfgc = 0; 204 205 pci_read_config_word(pdev, GCFGC, &gcfgc); 206 207 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 208 cdclk_config->cdclk = 133333; 209 return; 210 } 211 212 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 213 case GC_DISPLAY_CLOCK_333_320_MHZ: 214 cdclk_config->cdclk = 320000; 215 break; 216 default: 217 case GC_DISPLAY_CLOCK_190_200_MHZ: 218 cdclk_config->cdclk = 200000; 219 break; 220 } 221 } 222 223 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) 224 { 225 static const unsigned int blb_vco[8] = { 226 [0] = 3200000, 227 [1] = 4000000, 228 [2] = 5333333, 229 [3] = 4800000, 230 [4] = 6400000, 231 }; 232 static const unsigned int pnv_vco[8] = { 233 [0] = 3200000, 234 [1] = 4000000, 235 [2] = 5333333, 236 [3] = 4800000, 237 [4] = 2666667, 238 }; 239 static const unsigned int cl_vco[8] = { 240 [0] = 3200000, 241 [1] = 4000000, 242 [2] = 5333333, 243 [3] = 6400000, 244 [4] = 3333333, 245 [5] = 3566667, 246 [6] = 4266667, 247 }; 248 static const unsigned int elk_vco[8] = { 249 [0] = 3200000, 250 [1] = 4000000, 251 [2] = 5333333, 252 [3] = 4800000, 253 }; 254 static const unsigned int ctg_vco[8] = { 255 [0] = 3200000, 256 [1] = 4000000, 257 [2] = 5333333, 258 [3] = 6400000, 259 [4] = 2666667, 260 [5] = 4266667, 261 }; 262 const unsigned int *vco_table; 263 unsigned int vco; 264 u8 tmp = 0; 265 266 /* FIXME other chipsets? */ 267 if (IS_GM45(dev_priv)) 268 vco_table = ctg_vco; 269 else if (IS_G45(dev_priv)) 270 vco_table = elk_vco; 271 else if (IS_I965GM(dev_priv)) 272 vco_table = cl_vco; 273 else if (IS_PINEVIEW(dev_priv)) 274 vco_table = pnv_vco; 275 else if (IS_G33(dev_priv)) 276 vco_table = blb_vco; 277 else 278 return 0; 279 280 tmp = intel_de_read(dev_priv, 281 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); 282 283 vco = vco_table[tmp & 0x7]; 284 if (vco == 0) 285 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", 286 tmp); 287 else 288 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); 289 290 return vco; 291 } 292 293 static void g33_get_cdclk(struct drm_i915_private *dev_priv, 294 struct intel_cdclk_config *cdclk_config) 295 { 296 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 297 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 }; 298 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 }; 299 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 }; 300 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 }; 301 const u8 *div_table; 302 unsigned int cdclk_sel; 303 u16 tmp = 0; 304 305 cdclk_config->vco = intel_hpll_vco(dev_priv); 306 307 pci_read_config_word(pdev, GCFGC, &tmp); 308 309 cdclk_sel = (tmp >> 4) & 0x7; 310 311 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 312 goto fail; 313 314 switch (cdclk_config->vco) { 315 case 3200000: 316 div_table = div_3200; 317 break; 318 case 4000000: 319 div_table = div_4000; 320 break; 321 case 4800000: 322 div_table = div_4800; 323 break; 324 case 5333333: 325 div_table = div_5333; 326 break; 327 default: 328 goto fail; 329 } 330 331 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 332 div_table[cdclk_sel]); 333 return; 334 335 fail: 336 drm_err(&dev_priv->drm, 337 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", 338 cdclk_config->vco, tmp); 339 cdclk_config->cdclk = 190476; 340 } 341 342 static void pnv_get_cdclk(struct drm_i915_private *dev_priv, 343 struct intel_cdclk_config *cdclk_config) 344 { 345 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 346 u16 gcfgc = 0; 347 348 pci_read_config_word(pdev, GCFGC, &gcfgc); 349 350 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 351 case GC_DISPLAY_CLOCK_267_MHZ_PNV: 352 cdclk_config->cdclk = 266667; 353 break; 354 case GC_DISPLAY_CLOCK_333_MHZ_PNV: 355 cdclk_config->cdclk = 333333; 356 break; 357 case GC_DISPLAY_CLOCK_444_MHZ_PNV: 358 cdclk_config->cdclk = 444444; 359 break; 360 case GC_DISPLAY_CLOCK_200_MHZ_PNV: 361 cdclk_config->cdclk = 200000; 362 break; 363 default: 364 drm_err(&dev_priv->drm, 365 "Unknown pnv display core clock 0x%04x\n", gcfgc); 366 fallthrough; 367 case GC_DISPLAY_CLOCK_133_MHZ_PNV: 368 cdclk_config->cdclk = 133333; 369 break; 370 case GC_DISPLAY_CLOCK_167_MHZ_PNV: 371 cdclk_config->cdclk = 166667; 372 break; 373 } 374 } 375 376 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, 377 struct intel_cdclk_config *cdclk_config) 378 { 379 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 380 static const u8 div_3200[] = { 16, 10, 8 }; 381 static const u8 div_4000[] = { 20, 12, 10 }; 382 static const u8 div_5333[] = { 24, 16, 14 }; 383 const u8 *div_table; 384 unsigned int cdclk_sel; 385 u16 tmp = 0; 386 387 cdclk_config->vco = intel_hpll_vco(dev_priv); 388 389 pci_read_config_word(pdev, GCFGC, &tmp); 390 391 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; 392 393 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 394 goto fail; 395 396 switch (cdclk_config->vco) { 397 case 3200000: 398 div_table = div_3200; 399 break; 400 case 4000000: 401 div_table = div_4000; 402 break; 403 case 5333333: 404 div_table = div_5333; 405 break; 406 default: 407 goto fail; 408 } 409 410 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 411 div_table[cdclk_sel]); 412 return; 413 414 fail: 415 drm_err(&dev_priv->drm, 416 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", 417 cdclk_config->vco, tmp); 418 cdclk_config->cdclk = 200000; 419 } 420 421 static void gm45_get_cdclk(struct drm_i915_private *dev_priv, 422 struct intel_cdclk_config *cdclk_config) 423 { 424 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 425 unsigned int cdclk_sel; 426 u16 tmp = 0; 427 428 cdclk_config->vco = intel_hpll_vco(dev_priv); 429 430 pci_read_config_word(pdev, GCFGC, &tmp); 431 432 cdclk_sel = (tmp >> 12) & 0x1; 433 434 switch (cdclk_config->vco) { 435 case 2666667: 436 case 4000000: 437 case 5333333: 438 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; 439 break; 440 case 3200000: 441 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; 442 break; 443 default: 444 drm_err(&dev_priv->drm, 445 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", 446 cdclk_config->vco, tmp); 447 cdclk_config->cdclk = 222222; 448 break; 449 } 450 } 451 452 static void hsw_get_cdclk(struct drm_i915_private *dev_priv, 453 struct intel_cdclk_config *cdclk_config) 454 { 455 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); 456 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 457 458 if (lcpll & LCPLL_CD_SOURCE_FCLK) 459 cdclk_config->cdclk = 800000; 460 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 461 cdclk_config->cdclk = 450000; 462 else if (freq == LCPLL_CLK_FREQ_450) 463 cdclk_config->cdclk = 450000; 464 else if (IS_HSW_ULT(dev_priv)) 465 cdclk_config->cdclk = 337500; 466 else 467 cdclk_config->cdclk = 540000; 468 } 469 470 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) 471 { 472 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 473 333333 : 320000; 474 475 /* 476 * We seem to get an unstable or solid color picture at 200MHz. 477 * Not sure what's wrong. For now use 200MHz only when all pipes 478 * are off. 479 */ 480 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) 481 return 400000; 482 else if (min_cdclk > 266667) 483 return freq_320; 484 else if (min_cdclk > 0) 485 return 266667; 486 else 487 return 200000; 488 } 489 490 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) 491 { 492 if (IS_VALLEYVIEW(dev_priv)) { 493 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ 494 return 2; 495 else if (cdclk >= 266667) 496 return 1; 497 else 498 return 0; 499 } else { 500 /* 501 * Specs are full of misinformation, but testing on actual 502 * hardware has shown that we just need to write the desired 503 * CCK divider into the Punit register. 504 */ 505 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; 506 } 507 } 508 509 static void vlv_get_cdclk(struct drm_i915_private *dev_priv, 510 struct intel_cdclk_config *cdclk_config) 511 { 512 u32 val; 513 514 vlv_iosf_sb_get(dev_priv, 515 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 516 517 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); 518 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", 519 CCK_DISPLAY_CLOCK_CONTROL, 520 cdclk_config->vco); 521 522 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 523 524 vlv_iosf_sb_put(dev_priv, 525 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 526 527 if (IS_VALLEYVIEW(dev_priv)) 528 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> 529 DSPFREQGUAR_SHIFT; 530 else 531 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> 532 DSPFREQGUAR_SHIFT_CHV; 533 } 534 535 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) 536 { 537 unsigned int credits, default_credits; 538 539 if (IS_CHERRYVIEW(dev_priv)) 540 default_credits = PFI_CREDIT(12); 541 else 542 default_credits = PFI_CREDIT(8); 543 544 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) { 545 /* CHV suggested value is 31 or 63 */ 546 if (IS_CHERRYVIEW(dev_priv)) 547 credits = PFI_CREDIT_63; 548 else 549 credits = PFI_CREDIT(15); 550 } else { 551 credits = default_credits; 552 } 553 554 /* 555 * WA - write default credits before re-programming 556 * FIXME: should we also set the resend bit here? 557 */ 558 intel_de_write(dev_priv, GCI_CONTROL, 559 VGA_FAST_MODE_DISABLE | default_credits); 560 561 intel_de_write(dev_priv, GCI_CONTROL, 562 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND); 563 564 /* 565 * FIXME is this guaranteed to clear 566 * immediately or should we poll for it? 567 */ 568 drm_WARN_ON(&dev_priv->drm, 569 intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND); 570 } 571 572 static void vlv_set_cdclk(struct drm_i915_private *dev_priv, 573 const struct intel_cdclk_config *cdclk_config, 574 enum pipe pipe) 575 { 576 int cdclk = cdclk_config->cdclk; 577 u32 val, cmd = cdclk_config->voltage_level; 578 intel_wakeref_t wakeref; 579 580 switch (cdclk) { 581 case 400000: 582 case 333333: 583 case 320000: 584 case 266667: 585 case 200000: 586 break; 587 default: 588 MISSING_CASE(cdclk); 589 return; 590 } 591 592 /* There are cases where we can end up here with power domains 593 * off and a CDCLK frequency other than the minimum, like when 594 * issuing a modeset without actually changing any display after 595 * a system suspend. So grab the display core domain, which covers 596 * the HW blocks needed for the following programming. 597 */ 598 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); 599 600 vlv_iosf_sb_get(dev_priv, 601 BIT(VLV_IOSF_SB_CCK) | 602 BIT(VLV_IOSF_SB_BUNIT) | 603 BIT(VLV_IOSF_SB_PUNIT)); 604 605 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 606 val &= ~DSPFREQGUAR_MASK; 607 val |= (cmd << DSPFREQGUAR_SHIFT); 608 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); 609 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & 610 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 611 50)) { 612 drm_err(&dev_priv->drm, 613 "timed out waiting for CDclk change\n"); 614 } 615 616 if (cdclk == 400000) { 617 u32 divider; 618 619 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, 620 cdclk) - 1; 621 622 /* adjust cdclk divider */ 623 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); 624 val &= ~CCK_FREQUENCY_VALUES; 625 val |= divider; 626 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); 627 628 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & 629 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 630 50)) 631 drm_err(&dev_priv->drm, 632 "timed out waiting for CDclk change\n"); 633 } 634 635 /* adjust self-refresh exit latency value */ 636 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); 637 val &= ~0x7f; 638 639 /* 640 * For high bandwidth configs, we set a higher latency in the bunit 641 * so that the core display fetch happens in time to avoid underruns. 642 */ 643 if (cdclk == 400000) 644 val |= 4500 / 250; /* 4.5 usec */ 645 else 646 val |= 3000 / 250; /* 3.0 usec */ 647 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); 648 649 vlv_iosf_sb_put(dev_priv, 650 BIT(VLV_IOSF_SB_CCK) | 651 BIT(VLV_IOSF_SB_BUNIT) | 652 BIT(VLV_IOSF_SB_PUNIT)); 653 654 intel_update_cdclk(dev_priv); 655 656 vlv_program_pfi_credits(dev_priv); 657 658 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); 659 } 660 661 static void chv_set_cdclk(struct drm_i915_private *dev_priv, 662 const struct intel_cdclk_config *cdclk_config, 663 enum pipe pipe) 664 { 665 int cdclk = cdclk_config->cdclk; 666 u32 val, cmd = cdclk_config->voltage_level; 667 intel_wakeref_t wakeref; 668 669 switch (cdclk) { 670 case 333333: 671 case 320000: 672 case 266667: 673 case 200000: 674 break; 675 default: 676 MISSING_CASE(cdclk); 677 return; 678 } 679 680 /* There are cases where we can end up here with power domains 681 * off and a CDCLK frequency other than the minimum, like when 682 * issuing a modeset without actually changing any display after 683 * a system suspend. So grab the display core domain, which covers 684 * the HW blocks needed for the following programming. 685 */ 686 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); 687 688 vlv_punit_get(dev_priv); 689 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 690 val &= ~DSPFREQGUAR_MASK_CHV; 691 val |= (cmd << DSPFREQGUAR_SHIFT_CHV); 692 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); 693 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & 694 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 695 50)) { 696 drm_err(&dev_priv->drm, 697 "timed out waiting for CDclk change\n"); 698 } 699 700 vlv_punit_put(dev_priv); 701 702 intel_update_cdclk(dev_priv); 703 704 vlv_program_pfi_credits(dev_priv); 705 706 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); 707 } 708 709 static int bdw_calc_cdclk(int min_cdclk) 710 { 711 if (min_cdclk > 540000) 712 return 675000; 713 else if (min_cdclk > 450000) 714 return 540000; 715 else if (min_cdclk > 337500) 716 return 450000; 717 else 718 return 337500; 719 } 720 721 static u8 bdw_calc_voltage_level(int cdclk) 722 { 723 switch (cdclk) { 724 default: 725 case 337500: 726 return 2; 727 case 450000: 728 return 0; 729 case 540000: 730 return 1; 731 case 675000: 732 return 3; 733 } 734 } 735 736 static void bdw_get_cdclk(struct drm_i915_private *dev_priv, 737 struct intel_cdclk_config *cdclk_config) 738 { 739 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); 740 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 741 742 if (lcpll & LCPLL_CD_SOURCE_FCLK) 743 cdclk_config->cdclk = 800000; 744 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 745 cdclk_config->cdclk = 450000; 746 else if (freq == LCPLL_CLK_FREQ_450) 747 cdclk_config->cdclk = 450000; 748 else if (freq == LCPLL_CLK_FREQ_54O_BDW) 749 cdclk_config->cdclk = 540000; 750 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 751 cdclk_config->cdclk = 337500; 752 else 753 cdclk_config->cdclk = 675000; 754 755 /* 756 * Can't read this out :( Let's assume it's 757 * at least what the CDCLK frequency requires. 758 */ 759 cdclk_config->voltage_level = 760 bdw_calc_voltage_level(cdclk_config->cdclk); 761 } 762 763 static u32 bdw_cdclk_freq_sel(int cdclk) 764 { 765 switch (cdclk) { 766 default: 767 MISSING_CASE(cdclk); 768 fallthrough; 769 case 337500: 770 return LCPLL_CLK_FREQ_337_5_BDW; 771 case 450000: 772 return LCPLL_CLK_FREQ_450; 773 case 540000: 774 return LCPLL_CLK_FREQ_54O_BDW; 775 case 675000: 776 return LCPLL_CLK_FREQ_675_BDW; 777 } 778 } 779 780 static void bdw_set_cdclk(struct drm_i915_private *dev_priv, 781 const struct intel_cdclk_config *cdclk_config, 782 enum pipe pipe) 783 { 784 int cdclk = cdclk_config->cdclk; 785 int ret; 786 787 if (drm_WARN(&dev_priv->drm, 788 (intel_de_read(dev_priv, LCPLL_CTL) & 789 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | 790 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | 791 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | 792 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, 793 "trying to change cdclk frequency with cdclk not enabled\n")) 794 return; 795 796 ret = sandybridge_pcode_write(dev_priv, 797 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); 798 if (ret) { 799 drm_err(&dev_priv->drm, 800 "failed to inform pcode about cdclk change\n"); 801 return; 802 } 803 804 intel_de_rmw(dev_priv, LCPLL_CTL, 805 0, LCPLL_CD_SOURCE_FCLK); 806 807 /* 808 * According to the spec, it should be enough to poll for this 1 us. 809 * However, extensive testing shows that this can take longer. 810 */ 811 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) & 812 LCPLL_CD_SOURCE_FCLK_DONE, 100)) 813 drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); 814 815 intel_de_rmw(dev_priv, LCPLL_CTL, 816 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk)); 817 818 intel_de_rmw(dev_priv, LCPLL_CTL, 819 LCPLL_CD_SOURCE_FCLK, 0); 820 821 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) & 822 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 823 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n"); 824 825 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, 826 cdclk_config->voltage_level); 827 828 intel_de_write(dev_priv, CDCLK_FREQ, 829 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); 830 831 intel_update_cdclk(dev_priv); 832 } 833 834 static int skl_calc_cdclk(int min_cdclk, int vco) 835 { 836 if (vco == 8640000) { 837 if (min_cdclk > 540000) 838 return 617143; 839 else if (min_cdclk > 432000) 840 return 540000; 841 else if (min_cdclk > 308571) 842 return 432000; 843 else 844 return 308571; 845 } else { 846 if (min_cdclk > 540000) 847 return 675000; 848 else if (min_cdclk > 450000) 849 return 540000; 850 else if (min_cdclk > 337500) 851 return 450000; 852 else 853 return 337500; 854 } 855 } 856 857 static u8 skl_calc_voltage_level(int cdclk) 858 { 859 if (cdclk > 540000) 860 return 3; 861 else if (cdclk > 450000) 862 return 2; 863 else if (cdclk > 337500) 864 return 1; 865 else 866 return 0; 867 } 868 869 static void skl_dpll0_update(struct drm_i915_private *dev_priv, 870 struct intel_cdclk_config *cdclk_config) 871 { 872 u32 val; 873 874 cdclk_config->ref = 24000; 875 cdclk_config->vco = 0; 876 877 val = intel_de_read(dev_priv, LCPLL1_CTL); 878 if ((val & LCPLL_PLL_ENABLE) == 0) 879 return; 880 881 if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0)) 882 return; 883 884 val = intel_de_read(dev_priv, DPLL_CTRL1); 885 886 if (drm_WARN_ON(&dev_priv->drm, 887 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 888 DPLL_CTRL1_SSC(SKL_DPLL0) | 889 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != 890 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) 891 return; 892 893 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { 894 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): 895 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): 896 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): 897 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): 898 cdclk_config->vco = 8100000; 899 break; 900 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): 901 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): 902 cdclk_config->vco = 8640000; 903 break; 904 default: 905 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 906 break; 907 } 908 } 909 910 static void skl_get_cdclk(struct drm_i915_private *dev_priv, 911 struct intel_cdclk_config *cdclk_config) 912 { 913 u32 cdctl; 914 915 skl_dpll0_update(dev_priv, cdclk_config); 916 917 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; 918 919 if (cdclk_config->vco == 0) 920 goto out; 921 922 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 923 924 if (cdclk_config->vco == 8640000) { 925 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 926 case CDCLK_FREQ_450_432: 927 cdclk_config->cdclk = 432000; 928 break; 929 case CDCLK_FREQ_337_308: 930 cdclk_config->cdclk = 308571; 931 break; 932 case CDCLK_FREQ_540: 933 cdclk_config->cdclk = 540000; 934 break; 935 case CDCLK_FREQ_675_617: 936 cdclk_config->cdclk = 617143; 937 break; 938 default: 939 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 940 break; 941 } 942 } else { 943 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 944 case CDCLK_FREQ_450_432: 945 cdclk_config->cdclk = 450000; 946 break; 947 case CDCLK_FREQ_337_308: 948 cdclk_config->cdclk = 337500; 949 break; 950 case CDCLK_FREQ_540: 951 cdclk_config->cdclk = 540000; 952 break; 953 case CDCLK_FREQ_675_617: 954 cdclk_config->cdclk = 675000; 955 break; 956 default: 957 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 958 break; 959 } 960 } 961 962 out: 963 /* 964 * Can't read this out :( Let's assume it's 965 * at least what the CDCLK frequency requires. 966 */ 967 cdclk_config->voltage_level = 968 skl_calc_voltage_level(cdclk_config->cdclk); 969 } 970 971 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ 972 static int skl_cdclk_decimal(int cdclk) 973 { 974 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); 975 } 976 977 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, 978 int vco) 979 { 980 bool changed = dev_priv->skl_preferred_vco_freq != vco; 981 982 dev_priv->skl_preferred_vco_freq = vco; 983 984 if (changed) 985 intel_update_max_cdclk(dev_priv); 986 } 987 988 static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco) 989 { 990 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); 991 992 /* 993 * We always enable DPLL0 with the lowest link rate possible, but still 994 * taking into account the VCO required to operate the eDP panel at the 995 * desired frequency. The usual DP link rates operate with a VCO of 996 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. 997 * The modeset code is responsible for the selection of the exact link 998 * rate later on, with the constraint of choosing a frequency that 999 * works with vco. 1000 */ 1001 if (vco == 8640000) 1002 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0); 1003 else 1004 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0); 1005 } 1006 1007 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) 1008 { 1009 intel_de_rmw(dev_priv, DPLL_CTRL1, 1010 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 1011 DPLL_CTRL1_SSC(SKL_DPLL0) | 1012 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0), 1013 DPLL_CTRL1_OVERRIDE(SKL_DPLL0) | 1014 skl_dpll0_link_rate(dev_priv, vco)); 1015 intel_de_posting_read(dev_priv, DPLL_CTRL1); 1016 1017 intel_de_rmw(dev_priv, LCPLL1_CTL, 1018 0, LCPLL_PLL_ENABLE); 1019 1020 if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) 1021 drm_err(&dev_priv->drm, "DPLL0 not locked\n"); 1022 1023 dev_priv->cdclk.hw.vco = vco; 1024 1025 /* We'll want to keep using the current vco from now on. */ 1026 skl_set_preferred_cdclk_vco(dev_priv, vco); 1027 } 1028 1029 static void skl_dpll0_disable(struct drm_i915_private *dev_priv) 1030 { 1031 intel_de_rmw(dev_priv, LCPLL1_CTL, 1032 LCPLL_PLL_ENABLE, 0); 1033 1034 if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) 1035 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n"); 1036 1037 dev_priv->cdclk.hw.vco = 0; 1038 } 1039 1040 static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv, 1041 int cdclk, int vco) 1042 { 1043 switch (cdclk) { 1044 default: 1045 drm_WARN_ON(&dev_priv->drm, 1046 cdclk != dev_priv->cdclk.hw.bypass); 1047 drm_WARN_ON(&dev_priv->drm, vco != 0); 1048 fallthrough; 1049 case 308571: 1050 case 337500: 1051 return CDCLK_FREQ_337_308; 1052 case 450000: 1053 case 432000: 1054 return CDCLK_FREQ_450_432; 1055 case 540000: 1056 return CDCLK_FREQ_540; 1057 case 617143: 1058 case 675000: 1059 return CDCLK_FREQ_675_617; 1060 } 1061 } 1062 1063 static void skl_set_cdclk(struct drm_i915_private *dev_priv, 1064 const struct intel_cdclk_config *cdclk_config, 1065 enum pipe pipe) 1066 { 1067 int cdclk = cdclk_config->cdclk; 1068 int vco = cdclk_config->vco; 1069 u32 freq_select, cdclk_ctl; 1070 int ret; 1071 1072 /* 1073 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are 1074 * unsupported on SKL. In theory this should never happen since only 1075 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not 1076 * supported on SKL either, see the above WA. WARN whenever trying to 1077 * use the corresponding VCO freq as that always leads to using the 1078 * minimum 308MHz CDCLK. 1079 */ 1080 drm_WARN_ON_ONCE(&dev_priv->drm, 1081 IS_SKYLAKE(dev_priv) && vco == 8640000); 1082 1083 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, 1084 SKL_CDCLK_PREPARE_FOR_CHANGE, 1085 SKL_CDCLK_READY_FOR_CHANGE, 1086 SKL_CDCLK_READY_FOR_CHANGE, 3); 1087 if (ret) { 1088 drm_err(&dev_priv->drm, 1089 "Failed to inform PCU about cdclk change (%d)\n", ret); 1090 return; 1091 } 1092 1093 freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco); 1094 1095 if (dev_priv->cdclk.hw.vco != 0 && 1096 dev_priv->cdclk.hw.vco != vco) 1097 skl_dpll0_disable(dev_priv); 1098 1099 cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL); 1100 1101 if (dev_priv->cdclk.hw.vco != vco) { 1102 /* Wa Display #1183: skl,kbl,cfl */ 1103 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1104 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1105 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1106 } 1107 1108 /* Wa Display #1183: skl,kbl,cfl */ 1109 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; 1110 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1111 intel_de_posting_read(dev_priv, CDCLK_CTL); 1112 1113 if (dev_priv->cdclk.hw.vco != vco) 1114 skl_dpll0_enable(dev_priv, vco); 1115 1116 /* Wa Display #1183: skl,kbl,cfl */ 1117 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1118 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1119 1120 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1121 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1122 1123 /* Wa Display #1183: skl,kbl,cfl */ 1124 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; 1125 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1126 intel_de_posting_read(dev_priv, CDCLK_CTL); 1127 1128 /* inform PCU of the change */ 1129 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, 1130 cdclk_config->voltage_level); 1131 1132 intel_update_cdclk(dev_priv); 1133 } 1134 1135 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) 1136 { 1137 u32 cdctl, expected; 1138 1139 /* 1140 * check if the pre-os initialized the display 1141 * There is SWF18 scratchpad register defined which is set by the 1142 * pre-os which can be used by the OS drivers to check the status 1143 */ 1144 if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) 1145 goto sanitize; 1146 1147 intel_update_cdclk(dev_priv); 1148 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK"); 1149 1150 /* Is PLL enabled and locked ? */ 1151 if (dev_priv->cdclk.hw.vco == 0 || 1152 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) 1153 goto sanitize; 1154 1155 /* DPLL okay; verify the cdclock 1156 * 1157 * Noticed in some instances that the freq selection is correct but 1158 * decimal part is programmed wrong from BIOS where pre-os does not 1159 * enable display. Verify the same as well. 1160 */ 1161 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 1162 expected = (cdctl & CDCLK_FREQ_SEL_MASK) | 1163 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); 1164 if (cdctl == expected) 1165 /* All well; nothing to sanitize */ 1166 return; 1167 1168 sanitize: 1169 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); 1170 1171 /* force cdclk programming */ 1172 dev_priv->cdclk.hw.cdclk = 0; 1173 /* force full PLL disable + enable */ 1174 dev_priv->cdclk.hw.vco = -1; 1175 } 1176 1177 static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv) 1178 { 1179 struct intel_cdclk_config cdclk_config; 1180 1181 skl_sanitize_cdclk(dev_priv); 1182 1183 if (dev_priv->cdclk.hw.cdclk != 0 && 1184 dev_priv->cdclk.hw.vco != 0) { 1185 /* 1186 * Use the current vco as our initial 1187 * guess as to what the preferred vco is. 1188 */ 1189 if (dev_priv->skl_preferred_vco_freq == 0) 1190 skl_set_preferred_cdclk_vco(dev_priv, 1191 dev_priv->cdclk.hw.vco); 1192 return; 1193 } 1194 1195 cdclk_config = dev_priv->cdclk.hw; 1196 1197 cdclk_config.vco = dev_priv->skl_preferred_vco_freq; 1198 if (cdclk_config.vco == 0) 1199 cdclk_config.vco = 8100000; 1200 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); 1201 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1202 1203 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1204 } 1205 1206 static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv) 1207 { 1208 struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw; 1209 1210 cdclk_config.cdclk = cdclk_config.bypass; 1211 cdclk_config.vco = 0; 1212 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1213 1214 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1215 } 1216 1217 static bool has_cdclk_squasher(struct drm_i915_private *i915) 1218 { 1219 return IS_DG2(i915); 1220 } 1221 1222 struct intel_cdclk_vals { 1223 u32 cdclk; 1224 u16 refclk; 1225 u16 waveform; 1226 u8 divider; /* CD2X divider * 2 */ 1227 u8 ratio; 1228 }; 1229 1230 static const struct intel_cdclk_vals bxt_cdclk_table[] = { 1231 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 }, 1232 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 }, 1233 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 }, 1234 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 }, 1235 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 }, 1236 {} 1237 }; 1238 1239 static const struct intel_cdclk_vals glk_cdclk_table[] = { 1240 { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 }, 1241 { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 }, 1242 { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 }, 1243 {} 1244 }; 1245 1246 static const struct intel_cdclk_vals icl_cdclk_table[] = { 1247 { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 }, 1248 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 }, 1249 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 }, 1250 { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 }, 1251 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 }, 1252 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 }, 1253 1254 { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 }, 1255 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 }, 1256 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 }, 1257 { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 }, 1258 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 }, 1259 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 }, 1260 1261 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 }, 1262 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 }, 1263 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 }, 1264 { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 }, 1265 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 }, 1266 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 }, 1267 {} 1268 }; 1269 1270 static const struct intel_cdclk_vals rkl_cdclk_table[] = { 1271 { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 }, 1272 { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 }, 1273 { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 }, 1274 { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 }, 1275 { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 }, 1276 { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 }, 1277 1278 { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 }, 1279 { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 }, 1280 { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 }, 1281 { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 }, 1282 { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 }, 1283 { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 }, 1284 1285 { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 }, 1286 { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 }, 1287 { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 }, 1288 { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 }, 1289 { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 }, 1290 { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 }, 1291 {} 1292 }; 1293 1294 static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = { 1295 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 }, 1296 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 }, 1297 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 }, 1298 1299 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 }, 1300 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 }, 1301 { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 }, 1302 1303 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 }, 1304 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 }, 1305 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 }, 1306 {} 1307 }; 1308 1309 static const struct intel_cdclk_vals adlp_cdclk_table[] = { 1310 { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 }, 1311 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 }, 1312 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 }, 1313 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 }, 1314 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 }, 1315 1316 { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 }, 1317 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 }, 1318 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 }, 1319 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 }, 1320 { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 }, 1321 1322 { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 }, 1323 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 }, 1324 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 }, 1325 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 }, 1326 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 }, 1327 {} 1328 }; 1329 1330 static const struct intel_cdclk_vals dg2_cdclk_table[] = { 1331 { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 }, 1332 { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 }, 1333 { .refclk = 38400, .cdclk = 244800, .divider = 2, .ratio = 34, .waveform = 0xa4a4 }, 1334 { .refclk = 38400, .cdclk = 285600, .divider = 2, .ratio = 34, .waveform = 0xa54a }, 1335 { .refclk = 38400, .cdclk = 326400, .divider = 2, .ratio = 34, .waveform = 0xaaaa }, 1336 { .refclk = 38400, .cdclk = 367200, .divider = 2, .ratio = 34, .waveform = 0xad5a }, 1337 { .refclk = 38400, .cdclk = 408000, .divider = 2, .ratio = 34, .waveform = 0xb6b6 }, 1338 { .refclk = 38400, .cdclk = 448800, .divider = 2, .ratio = 34, .waveform = 0xdbb6 }, 1339 { .refclk = 38400, .cdclk = 489600, .divider = 2, .ratio = 34, .waveform = 0xeeee }, 1340 { .refclk = 38400, .cdclk = 530400, .divider = 2, .ratio = 34, .waveform = 0xf7de }, 1341 { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe }, 1342 { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe }, 1343 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff }, 1344 {} 1345 }; 1346 1347 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) 1348 { 1349 const struct intel_cdclk_vals *table = dev_priv->cdclk.table; 1350 int i; 1351 1352 for (i = 0; table[i].refclk; i++) 1353 if (table[i].refclk == dev_priv->cdclk.hw.ref && 1354 table[i].cdclk >= min_cdclk) 1355 return table[i].cdclk; 1356 1357 drm_WARN(&dev_priv->drm, 1, 1358 "Cannot satisfy minimum cdclk %d with refclk %u\n", 1359 min_cdclk, dev_priv->cdclk.hw.ref); 1360 return 0; 1361 } 1362 1363 static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) 1364 { 1365 const struct intel_cdclk_vals *table = dev_priv->cdclk.table; 1366 int i; 1367 1368 if (cdclk == dev_priv->cdclk.hw.bypass) 1369 return 0; 1370 1371 for (i = 0; table[i].refclk; i++) 1372 if (table[i].refclk == dev_priv->cdclk.hw.ref && 1373 table[i].cdclk == cdclk) 1374 return dev_priv->cdclk.hw.ref * table[i].ratio; 1375 1376 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", 1377 cdclk, dev_priv->cdclk.hw.ref); 1378 return 0; 1379 } 1380 1381 static u8 bxt_calc_voltage_level(int cdclk) 1382 { 1383 return DIV_ROUND_UP(cdclk, 25000); 1384 } 1385 1386 static u8 icl_calc_voltage_level(int cdclk) 1387 { 1388 if (cdclk > 556800) 1389 return 2; 1390 else if (cdclk > 312000) 1391 return 1; 1392 else 1393 return 0; 1394 } 1395 1396 static u8 ehl_calc_voltage_level(int cdclk) 1397 { 1398 if (cdclk > 326400) 1399 return 3; 1400 else if (cdclk > 312000) 1401 return 2; 1402 else if (cdclk > 180000) 1403 return 1; 1404 else 1405 return 0; 1406 } 1407 1408 static u8 tgl_calc_voltage_level(int cdclk) 1409 { 1410 if (cdclk > 556800) 1411 return 3; 1412 else if (cdclk > 326400) 1413 return 2; 1414 else if (cdclk > 312000) 1415 return 1; 1416 else 1417 return 0; 1418 } 1419 1420 static void icl_readout_refclk(struct drm_i915_private *dev_priv, 1421 struct intel_cdclk_config *cdclk_config) 1422 { 1423 u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; 1424 1425 switch (dssm) { 1426 default: 1427 MISSING_CASE(dssm); 1428 fallthrough; 1429 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz: 1430 cdclk_config->ref = 24000; 1431 break; 1432 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz: 1433 cdclk_config->ref = 19200; 1434 break; 1435 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz: 1436 cdclk_config->ref = 38400; 1437 break; 1438 } 1439 } 1440 1441 static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, 1442 struct intel_cdclk_config *cdclk_config) 1443 { 1444 u32 val, ratio; 1445 1446 if (IS_DG2(dev_priv)) 1447 cdclk_config->ref = 38400; 1448 else if (DISPLAY_VER(dev_priv) >= 11) 1449 icl_readout_refclk(dev_priv, cdclk_config); 1450 else 1451 cdclk_config->ref = 19200; 1452 1453 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE); 1454 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || 1455 (val & BXT_DE_PLL_LOCK) == 0) { 1456 /* 1457 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but 1458 * setting it to zero is a way to signal that. 1459 */ 1460 cdclk_config->vco = 0; 1461 return; 1462 } 1463 1464 /* 1465 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register, 1466 * gen9lp had it in a separate PLL control register. 1467 */ 1468 if (DISPLAY_VER(dev_priv) >= 11) 1469 ratio = val & ICL_CDCLK_PLL_RATIO_MASK; 1470 else 1471 ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; 1472 1473 cdclk_config->vco = ratio * cdclk_config->ref; 1474 } 1475 1476 static void bxt_get_cdclk(struct drm_i915_private *dev_priv, 1477 struct intel_cdclk_config *cdclk_config) 1478 { 1479 u32 squash_ctl = 0; 1480 u32 divider; 1481 int div; 1482 1483 bxt_de_pll_readout(dev_priv, cdclk_config); 1484 1485 if (DISPLAY_VER(dev_priv) >= 12) 1486 cdclk_config->bypass = cdclk_config->ref / 2; 1487 else if (DISPLAY_VER(dev_priv) >= 11) 1488 cdclk_config->bypass = 50000; 1489 else 1490 cdclk_config->bypass = cdclk_config->ref; 1491 1492 if (cdclk_config->vco == 0) { 1493 cdclk_config->cdclk = cdclk_config->bypass; 1494 goto out; 1495 } 1496 1497 divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; 1498 1499 switch (divider) { 1500 case BXT_CDCLK_CD2X_DIV_SEL_1: 1501 div = 2; 1502 break; 1503 case BXT_CDCLK_CD2X_DIV_SEL_1_5: 1504 div = 3; 1505 break; 1506 case BXT_CDCLK_CD2X_DIV_SEL_2: 1507 div = 4; 1508 break; 1509 case BXT_CDCLK_CD2X_DIV_SEL_4: 1510 div = 8; 1511 break; 1512 default: 1513 MISSING_CASE(divider); 1514 return; 1515 } 1516 1517 if (has_cdclk_squasher(dev_priv)) 1518 squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL); 1519 1520 if (squash_ctl & CDCLK_SQUASH_ENABLE) { 1521 u16 waveform; 1522 int size; 1523 1524 size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1; 1525 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size); 1526 1527 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * 1528 cdclk_config->vco, size * div); 1529 } else { 1530 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); 1531 } 1532 1533 out: 1534 /* 1535 * Can't read this out :( Let's assume it's 1536 * at least what the CDCLK frequency requires. 1537 */ 1538 cdclk_config->voltage_level = 1539 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk); 1540 } 1541 1542 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) 1543 { 1544 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0); 1545 1546 /* Timeout 200us */ 1547 if (intel_de_wait_for_clear(dev_priv, 1548 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1549 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n"); 1550 1551 dev_priv->cdclk.hw.vco = 0; 1552 } 1553 1554 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) 1555 { 1556 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); 1557 1558 intel_de_rmw(dev_priv, BXT_DE_PLL_CTL, 1559 BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio)); 1560 1561 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); 1562 1563 /* Timeout 200us */ 1564 if (intel_de_wait_for_set(dev_priv, 1565 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1566 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n"); 1567 1568 dev_priv->cdclk.hw.vco = vco; 1569 } 1570 1571 static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv) 1572 { 1573 intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE, 1574 BXT_DE_PLL_PLL_ENABLE, 0); 1575 1576 /* Timeout 200us */ 1577 if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1578 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n"); 1579 1580 dev_priv->cdclk.hw.vco = 0; 1581 } 1582 1583 static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) 1584 { 1585 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); 1586 u32 val; 1587 1588 val = ICL_CDCLK_PLL_RATIO(ratio); 1589 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1590 1591 val |= BXT_DE_PLL_PLL_ENABLE; 1592 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1593 1594 /* Timeout 200us */ 1595 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1596 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n"); 1597 1598 dev_priv->cdclk.hw.vco = vco; 1599 } 1600 1601 static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco) 1602 { 1603 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); 1604 u32 val; 1605 1606 /* Write PLL ratio without disabling */ 1607 val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE; 1608 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1609 1610 /* Submit freq change request */ 1611 val |= BXT_DE_PLL_FREQ_REQ; 1612 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1613 1614 /* Timeout 200us */ 1615 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, 1616 BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1)) 1617 DRM_ERROR("timeout waiting for FREQ change request ack\n"); 1618 1619 val &= ~BXT_DE_PLL_FREQ_REQ; 1620 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1621 1622 dev_priv->cdclk.hw.vco = vco; 1623 } 1624 1625 static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 1626 { 1627 if (DISPLAY_VER(dev_priv) >= 12) { 1628 if (pipe == INVALID_PIPE) 1629 return TGL_CDCLK_CD2X_PIPE_NONE; 1630 else 1631 return TGL_CDCLK_CD2X_PIPE(pipe); 1632 } else if (DISPLAY_VER(dev_priv) >= 11) { 1633 if (pipe == INVALID_PIPE) 1634 return ICL_CDCLK_CD2X_PIPE_NONE; 1635 else 1636 return ICL_CDCLK_CD2X_PIPE(pipe); 1637 } else { 1638 if (pipe == INVALID_PIPE) 1639 return BXT_CDCLK_CD2X_PIPE_NONE; 1640 else 1641 return BXT_CDCLK_CD2X_PIPE(pipe); 1642 } 1643 } 1644 1645 static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv, 1646 int cdclk, int vco) 1647 { 1648 /* cdclk = vco / 2 / div{1,1.5,2,4} */ 1649 switch (DIV_ROUND_CLOSEST(vco, cdclk)) { 1650 default: 1651 drm_WARN_ON(&dev_priv->drm, 1652 cdclk != dev_priv->cdclk.hw.bypass); 1653 drm_WARN_ON(&dev_priv->drm, vco != 0); 1654 fallthrough; 1655 case 2: 1656 return BXT_CDCLK_CD2X_DIV_SEL_1; 1657 case 3: 1658 return BXT_CDCLK_CD2X_DIV_SEL_1_5; 1659 case 4: 1660 return BXT_CDCLK_CD2X_DIV_SEL_2; 1661 case 8: 1662 return BXT_CDCLK_CD2X_DIV_SEL_4; 1663 } 1664 } 1665 1666 static u32 cdclk_squash_waveform(struct drm_i915_private *dev_priv, 1667 int cdclk) 1668 { 1669 const struct intel_cdclk_vals *table = dev_priv->cdclk.table; 1670 int i; 1671 1672 if (cdclk == dev_priv->cdclk.hw.bypass) 1673 return 0; 1674 1675 for (i = 0; table[i].refclk; i++) 1676 if (table[i].refclk == dev_priv->cdclk.hw.ref && 1677 table[i].cdclk == cdclk) 1678 return table[i].waveform; 1679 1680 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", 1681 cdclk, dev_priv->cdclk.hw.ref); 1682 1683 return 0xffff; 1684 } 1685 1686 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 1687 const struct intel_cdclk_config *cdclk_config, 1688 enum pipe pipe) 1689 { 1690 int cdclk = cdclk_config->cdclk; 1691 int vco = cdclk_config->vco; 1692 u32 val; 1693 u16 waveform; 1694 int clock; 1695 int ret; 1696 1697 /* Inform power controller of upcoming frequency change. */ 1698 if (DISPLAY_VER(dev_priv) >= 11) 1699 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, 1700 SKL_CDCLK_PREPARE_FOR_CHANGE, 1701 SKL_CDCLK_READY_FOR_CHANGE, 1702 SKL_CDCLK_READY_FOR_CHANGE, 3); 1703 else 1704 /* 1705 * BSpec requires us to wait up to 150usec, but that leads to 1706 * timeouts; the 2ms used here is based on experiment. 1707 */ 1708 ret = sandybridge_pcode_write_timeout(dev_priv, 1709 HSW_PCODE_DE_WRITE_FREQ_REQ, 1710 0x80000000, 150, 2); 1711 1712 if (ret) { 1713 drm_err(&dev_priv->drm, 1714 "Failed to inform PCU about cdclk change (err %d, freq %d)\n", 1715 ret, cdclk); 1716 return; 1717 } 1718 1719 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) { 1720 if (dev_priv->cdclk.hw.vco != vco) 1721 adlp_cdclk_pll_crawl(dev_priv, vco); 1722 } else if (DISPLAY_VER(dev_priv) >= 11) { 1723 if (dev_priv->cdclk.hw.vco != 0 && 1724 dev_priv->cdclk.hw.vco != vco) 1725 icl_cdclk_pll_disable(dev_priv); 1726 1727 if (dev_priv->cdclk.hw.vco != vco) 1728 icl_cdclk_pll_enable(dev_priv, vco); 1729 } else { 1730 if (dev_priv->cdclk.hw.vco != 0 && 1731 dev_priv->cdclk.hw.vco != vco) 1732 bxt_de_pll_disable(dev_priv); 1733 1734 if (dev_priv->cdclk.hw.vco != vco) 1735 bxt_de_pll_enable(dev_priv, vco); 1736 } 1737 1738 waveform = cdclk_squash_waveform(dev_priv, cdclk); 1739 1740 if (waveform) 1741 clock = vco / 2; 1742 else 1743 clock = cdclk; 1744 1745 if (has_cdclk_squasher(dev_priv)) { 1746 u32 squash_ctl = 0; 1747 1748 if (waveform) 1749 squash_ctl = CDCLK_SQUASH_ENABLE | 1750 CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; 1751 1752 intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl); 1753 } 1754 1755 val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) | 1756 bxt_cdclk_cd2x_pipe(dev_priv, pipe) | 1757 skl_cdclk_decimal(cdclk); 1758 1759 /* 1760 * Disable SSA Precharge when CD clock frequency < 500 MHz, 1761 * enable otherwise. 1762 */ 1763 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1764 cdclk >= 500000) 1765 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 1766 intel_de_write(dev_priv, CDCLK_CTL, val); 1767 1768 if (pipe != INVALID_PIPE) 1769 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe)); 1770 1771 if (DISPLAY_VER(dev_priv) >= 11) { 1772 ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, 1773 cdclk_config->voltage_level); 1774 } else { 1775 /* 1776 * The timeout isn't specified, the 2ms used here is based on 1777 * experiment. 1778 * FIXME: Waiting for the request completion could be delayed 1779 * until the next PCODE request based on BSpec. 1780 */ 1781 ret = sandybridge_pcode_write_timeout(dev_priv, 1782 HSW_PCODE_DE_WRITE_FREQ_REQ, 1783 cdclk_config->voltage_level, 1784 150, 2); 1785 } 1786 1787 if (ret) { 1788 drm_err(&dev_priv->drm, 1789 "PCode CDCLK freq set failed, (err %d, freq %d)\n", 1790 ret, cdclk); 1791 return; 1792 } 1793 1794 intel_update_cdclk(dev_priv); 1795 1796 if (DISPLAY_VER(dev_priv) >= 11) 1797 /* 1798 * Can't read out the voltage level :( 1799 * Let's just assume everything is as expected. 1800 */ 1801 dev_priv->cdclk.hw.voltage_level = cdclk_config->voltage_level; 1802 } 1803 1804 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) 1805 { 1806 u32 cdctl, expected; 1807 int cdclk, clock, vco; 1808 1809 intel_update_cdclk(dev_priv); 1810 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK"); 1811 1812 if (dev_priv->cdclk.hw.vco == 0 || 1813 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) 1814 goto sanitize; 1815 1816 /* DPLL okay; verify the cdclock 1817 * 1818 * Some BIOS versions leave an incorrect decimal frequency value and 1819 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, 1820 * so sanitize this register. 1821 */ 1822 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 1823 /* 1824 * Let's ignore the pipe field, since BIOS could have configured the 1825 * dividers both synching to an active pipe, or asynchronously 1826 * (PIPE_NONE). 1827 */ 1828 cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); 1829 1830 /* Make sure this is a legal cdclk value for the platform */ 1831 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk); 1832 if (cdclk != dev_priv->cdclk.hw.cdclk) 1833 goto sanitize; 1834 1835 /* Make sure the VCO is correct for the cdclk */ 1836 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 1837 if (vco != dev_priv->cdclk.hw.vco) 1838 goto sanitize; 1839 1840 expected = skl_cdclk_decimal(cdclk); 1841 1842 /* Figure out what CD2X divider we should be using for this cdclk */ 1843 if (has_cdclk_squasher(dev_priv)) 1844 clock = dev_priv->cdclk.hw.vco / 2; 1845 else 1846 clock = dev_priv->cdclk.hw.cdclk; 1847 1848 expected |= bxt_cdclk_cd2x_div_sel(dev_priv, clock, 1849 dev_priv->cdclk.hw.vco); 1850 1851 /* 1852 * Disable SSA Precharge when CD clock frequency < 500 MHz, 1853 * enable otherwise. 1854 */ 1855 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1856 dev_priv->cdclk.hw.cdclk >= 500000) 1857 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 1858 1859 if (cdctl == expected) 1860 /* All well; nothing to sanitize */ 1861 return; 1862 1863 sanitize: 1864 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); 1865 1866 /* force cdclk programming */ 1867 dev_priv->cdclk.hw.cdclk = 0; 1868 1869 /* force full PLL disable + enable */ 1870 dev_priv->cdclk.hw.vco = -1; 1871 } 1872 1873 static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv) 1874 { 1875 struct intel_cdclk_config cdclk_config; 1876 1877 bxt_sanitize_cdclk(dev_priv); 1878 1879 if (dev_priv->cdclk.hw.cdclk != 0 && 1880 dev_priv->cdclk.hw.vco != 0) 1881 return; 1882 1883 cdclk_config = dev_priv->cdclk.hw; 1884 1885 /* 1886 * FIXME: 1887 * - The initial CDCLK needs to be read from VBT. 1888 * Need to make this change after VBT has changes for BXT. 1889 */ 1890 cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0); 1891 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); 1892 cdclk_config.voltage_level = 1893 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); 1894 1895 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1896 } 1897 1898 static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv) 1899 { 1900 struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw; 1901 1902 cdclk_config.cdclk = cdclk_config.bypass; 1903 cdclk_config.vco = 0; 1904 cdclk_config.voltage_level = 1905 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); 1906 1907 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1908 } 1909 1910 /** 1911 * intel_cdclk_init_hw - Initialize CDCLK hardware 1912 * @i915: i915 device 1913 * 1914 * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and 1915 * sanitizing the state of the hardware if needed. This is generally done only 1916 * during the display core initialization sequence, after which the DMC will 1917 * take care of turning CDCLK off/on as needed. 1918 */ 1919 void intel_cdclk_init_hw(struct drm_i915_private *i915) 1920 { 1921 if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915)) 1922 bxt_cdclk_init_hw(i915); 1923 else if (DISPLAY_VER(i915) == 9) 1924 skl_cdclk_init_hw(i915); 1925 } 1926 1927 /** 1928 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware 1929 * @i915: i915 device 1930 * 1931 * Uninitialize CDCLK. This is done only during the display core 1932 * uninitialization sequence. 1933 */ 1934 void intel_cdclk_uninit_hw(struct drm_i915_private *i915) 1935 { 1936 if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915)) 1937 bxt_cdclk_uninit_hw(i915); 1938 else if (DISPLAY_VER(i915) == 9) 1939 skl_cdclk_uninit_hw(i915); 1940 } 1941 1942 static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, 1943 const struct intel_cdclk_config *a, 1944 const struct intel_cdclk_config *b) 1945 { 1946 int a_div, b_div; 1947 1948 if (!HAS_CDCLK_CRAWL(dev_priv)) 1949 return false; 1950 1951 /* 1952 * The vco and cd2x divider will change independently 1953 * from each, so we disallow cd2x change when crawling. 1954 */ 1955 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); 1956 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); 1957 1958 return a->vco != 0 && b->vco != 0 && 1959 a->vco != b->vco && 1960 a_div == b_div && 1961 a->ref == b->ref; 1962 } 1963 1964 static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, 1965 const struct intel_cdclk_config *a, 1966 const struct intel_cdclk_config *b) 1967 { 1968 /* 1969 * FIXME should store a bit more state in intel_cdclk_config 1970 * to differentiate squasher vs. cd2x divider properly. For 1971 * the moment all platforms with squasher use a fixed cd2x 1972 * divider. 1973 */ 1974 if (!has_cdclk_squasher(dev_priv)) 1975 return false; 1976 1977 return a->cdclk != b->cdclk && 1978 a->vco != 0 && 1979 a->vco == b->vco && 1980 a->ref == b->ref; 1981 } 1982 1983 /** 1984 * intel_cdclk_needs_modeset - Determine if changong between the CDCLK 1985 * configurations requires a modeset on all pipes 1986 * @a: first CDCLK configuration 1987 * @b: second CDCLK configuration 1988 * 1989 * Returns: 1990 * True if changing between the two CDCLK configurations 1991 * requires all pipes to be off, false if not. 1992 */ 1993 bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a, 1994 const struct intel_cdclk_config *b) 1995 { 1996 return a->cdclk != b->cdclk || 1997 a->vco != b->vco || 1998 a->ref != b->ref; 1999 } 2000 2001 /** 2002 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK 2003 * configurations requires only a cd2x divider update 2004 * @dev_priv: i915 device 2005 * @a: first CDCLK configuration 2006 * @b: second CDCLK configuration 2007 * 2008 * Returns: 2009 * True if changing between the two CDCLK configurations 2010 * can be done with just a cd2x divider update, false if not. 2011 */ 2012 static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, 2013 const struct intel_cdclk_config *a, 2014 const struct intel_cdclk_config *b) 2015 { 2016 /* Older hw doesn't have the capability */ 2017 if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv)) 2018 return false; 2019 2020 /* 2021 * FIXME should store a bit more state in intel_cdclk_config 2022 * to differentiate squasher vs. cd2x divider properly. For 2023 * the moment all platforms with squasher use a fixed cd2x 2024 * divider. 2025 */ 2026 if (has_cdclk_squasher(dev_priv)) 2027 return false; 2028 2029 return a->cdclk != b->cdclk && 2030 a->vco != 0 && 2031 a->vco == b->vco && 2032 a->ref == b->ref; 2033 } 2034 2035 /** 2036 * intel_cdclk_changed - Determine if two CDCLK configurations are different 2037 * @a: first CDCLK configuration 2038 * @b: second CDCLK configuration 2039 * 2040 * Returns: 2041 * True if the CDCLK configurations don't match, false if they do. 2042 */ 2043 static bool intel_cdclk_changed(const struct intel_cdclk_config *a, 2044 const struct intel_cdclk_config *b) 2045 { 2046 return intel_cdclk_needs_modeset(a, b) || 2047 a->voltage_level != b->voltage_level; 2048 } 2049 2050 void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config, 2051 const char *context) 2052 { 2053 DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", 2054 context, cdclk_config->cdclk, cdclk_config->vco, 2055 cdclk_config->ref, cdclk_config->bypass, 2056 cdclk_config->voltage_level); 2057 } 2058 2059 /** 2060 * intel_set_cdclk - Push the CDCLK configuration to the hardware 2061 * @dev_priv: i915 device 2062 * @cdclk_config: new CDCLK configuration 2063 * @pipe: pipe with which to synchronize the update 2064 * 2065 * Program the hardware based on the passed in CDCLK state, 2066 * if necessary. 2067 */ 2068 static void intel_set_cdclk(struct drm_i915_private *dev_priv, 2069 const struct intel_cdclk_config *cdclk_config, 2070 enum pipe pipe) 2071 { 2072 struct intel_encoder *encoder; 2073 2074 if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config)) 2075 return; 2076 2077 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->cdclk_funcs->set_cdclk)) 2078 return; 2079 2080 intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to"); 2081 2082 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2083 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2084 2085 intel_psr_pause(intel_dp); 2086 } 2087 2088 intel_audio_cdclk_change_pre(dev_priv); 2089 2090 /* 2091 * Lock aux/gmbus while we change cdclk in case those 2092 * functions use cdclk. Not all platforms/ports do, 2093 * but we'll lock them all for simplicity. 2094 */ 2095 mutex_lock(&dev_priv->gmbus_mutex); 2096 for_each_intel_dp(&dev_priv->drm, encoder) { 2097 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2098 2099 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, 2100 &dev_priv->gmbus_mutex); 2101 } 2102 2103 intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe); 2104 2105 for_each_intel_dp(&dev_priv->drm, encoder) { 2106 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2107 2108 mutex_unlock(&intel_dp->aux.hw_mutex); 2109 } 2110 mutex_unlock(&dev_priv->gmbus_mutex); 2111 2112 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2113 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2114 2115 intel_psr_resume(intel_dp); 2116 } 2117 2118 intel_audio_cdclk_change_post(dev_priv); 2119 2120 if (drm_WARN(&dev_priv->drm, 2121 intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config), 2122 "cdclk state doesn't match!\n")) { 2123 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "[hw state]"); 2124 intel_dump_cdclk_config(cdclk_config, "[sw state]"); 2125 } 2126 } 2127 2128 /** 2129 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware 2130 * @state: intel atomic state 2131 * 2132 * Program the hardware before updating the HW plane state based on the 2133 * new CDCLK state, if necessary. 2134 */ 2135 void 2136 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) 2137 { 2138 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2139 const struct intel_cdclk_state *old_cdclk_state = 2140 intel_atomic_get_old_cdclk_state(state); 2141 const struct intel_cdclk_state *new_cdclk_state = 2142 intel_atomic_get_new_cdclk_state(state); 2143 enum pipe pipe = new_cdclk_state->pipe; 2144 2145 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2146 &new_cdclk_state->actual)) 2147 return; 2148 2149 if (pipe == INVALID_PIPE || 2150 old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) { 2151 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); 2152 2153 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); 2154 } 2155 } 2156 2157 /** 2158 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware 2159 * @state: intel atomic state 2160 * 2161 * Program the hardware after updating the HW plane state based on the 2162 * new CDCLK state, if necessary. 2163 */ 2164 void 2165 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) 2166 { 2167 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2168 const struct intel_cdclk_state *old_cdclk_state = 2169 intel_atomic_get_old_cdclk_state(state); 2170 const struct intel_cdclk_state *new_cdclk_state = 2171 intel_atomic_get_new_cdclk_state(state); 2172 enum pipe pipe = new_cdclk_state->pipe; 2173 2174 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2175 &new_cdclk_state->actual)) 2176 return; 2177 2178 if (pipe != INVALID_PIPE && 2179 old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) { 2180 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); 2181 2182 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); 2183 } 2184 } 2185 2186 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) 2187 { 2188 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2189 int pixel_rate = crtc_state->pixel_rate; 2190 2191 if (DISPLAY_VER(dev_priv) >= 10) 2192 return DIV_ROUND_UP(pixel_rate, 2); 2193 else if (DISPLAY_VER(dev_priv) == 9 || 2194 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2195 return pixel_rate; 2196 else if (IS_CHERRYVIEW(dev_priv)) 2197 return DIV_ROUND_UP(pixel_rate * 100, 95); 2198 else if (crtc_state->double_wide) 2199 return DIV_ROUND_UP(pixel_rate * 100, 90 * 2); 2200 else 2201 return DIV_ROUND_UP(pixel_rate * 100, 90); 2202 } 2203 2204 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) 2205 { 2206 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2207 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2208 struct intel_plane *plane; 2209 int min_cdclk = 0; 2210 2211 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 2212 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk); 2213 2214 return min_cdclk; 2215 } 2216 2217 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) 2218 { 2219 struct drm_i915_private *dev_priv = 2220 to_i915(crtc_state->uapi.crtc->dev); 2221 int min_cdclk; 2222 2223 if (!crtc_state->hw.enable) 2224 return 0; 2225 2226 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state); 2227 2228 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ 2229 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state)) 2230 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95); 2231 2232 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, 2233 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else 2234 * there may be audio corruption or screen corruption." This cdclk 2235 * restriction for GLK is 316.8 MHz. 2236 */ 2237 if (intel_crtc_has_dp_encoder(crtc_state) && 2238 crtc_state->has_audio && 2239 crtc_state->port_clock >= 540000 && 2240 crtc_state->lane_count == 4) { 2241 if (DISPLAY_VER(dev_priv) == 10) { 2242 /* Display WA #1145: glk */ 2243 min_cdclk = max(316800, min_cdclk); 2244 } else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) { 2245 /* Display WA #1144: skl,bxt */ 2246 min_cdclk = max(432000, min_cdclk); 2247 } 2248 } 2249 2250 /* 2251 * According to BSpec, "The CD clock frequency must be at least twice 2252 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. 2253 */ 2254 if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9) 2255 min_cdclk = max(2 * 96000, min_cdclk); 2256 2257 /* 2258 * "For DP audio configuration, cdclk frequency shall be set to 2259 * meet the following requirements: 2260 * DP Link Frequency(MHz) | Cdclk frequency(MHz) 2261 * 270 | 320 or higher 2262 * 162 | 200 or higher" 2263 */ 2264 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2265 intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio) 2266 min_cdclk = max(crtc_state->port_clock, min_cdclk); 2267 2268 /* 2269 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower 2270 * than 320000KHz. 2271 */ 2272 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 2273 IS_VALLEYVIEW(dev_priv)) 2274 min_cdclk = max(320000, min_cdclk); 2275 2276 /* 2277 * On Geminilake once the CDCLK gets as low as 79200 2278 * picture gets unstable, despite that values are 2279 * correct for DSI PLL and DE PLL. 2280 */ 2281 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 2282 IS_GEMINILAKE(dev_priv)) 2283 min_cdclk = max(158400, min_cdclk); 2284 2285 /* Account for additional needs from the planes */ 2286 min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); 2287 2288 /* 2289 * When we decide to use only one VDSC engine, since 2290 * each VDSC operates with 1 ppc throughput, pixel clock 2291 * cannot be higher than the VDSC clock (cdclk) 2292 */ 2293 if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split) 2294 min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); 2295 2296 /* 2297 * HACK. Currently for TGL platforms we calculate 2298 * min_cdclk initially based on pixel_rate divided 2299 * by 2, accounting for also plane requirements, 2300 * however in some cases the lowest possible CDCLK 2301 * doesn't work and causing the underruns. 2302 * Explicitly stating here that this seems to be currently 2303 * rather a Hack, than final solution. 2304 */ 2305 if (IS_TIGERLAKE(dev_priv)) { 2306 /* 2307 * Clamp to max_cdclk_freq in case pixel rate is higher, 2308 * in order not to break an 8K, but still leave W/A at place. 2309 */ 2310 min_cdclk = max_t(int, min_cdclk, 2311 min_t(int, crtc_state->pixel_rate, 2312 dev_priv->max_cdclk_freq)); 2313 } 2314 2315 if (min_cdclk > dev_priv->max_cdclk_freq) { 2316 drm_dbg_kms(&dev_priv->drm, 2317 "required cdclk (%d kHz) exceeds max (%d kHz)\n", 2318 min_cdclk, dev_priv->max_cdclk_freq); 2319 return -EINVAL; 2320 } 2321 2322 return min_cdclk; 2323 } 2324 2325 static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) 2326 { 2327 struct intel_atomic_state *state = cdclk_state->base.state; 2328 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2329 struct intel_bw_state *bw_state = NULL; 2330 struct intel_crtc *crtc; 2331 struct intel_crtc_state *crtc_state; 2332 int min_cdclk, i; 2333 enum pipe pipe; 2334 2335 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2336 int ret; 2337 2338 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 2339 if (min_cdclk < 0) 2340 return min_cdclk; 2341 2342 bw_state = intel_atomic_get_bw_state(state); 2343 if (IS_ERR(bw_state)) 2344 return PTR_ERR(bw_state); 2345 2346 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk) 2347 continue; 2348 2349 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 2350 2351 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2352 if (ret) 2353 return ret; 2354 } 2355 2356 min_cdclk = cdclk_state->force_min_cdclk; 2357 for_each_pipe(dev_priv, pipe) { 2358 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); 2359 2360 if (!bw_state) 2361 continue; 2362 2363 min_cdclk = max(bw_state->min_cdclk, min_cdclk); 2364 } 2365 2366 return min_cdclk; 2367 } 2368 2369 /* 2370 * Account for port clock min voltage level requirements. 2371 * This only really does something on DISPLA_VER >= 11 but can be 2372 * called on earlier platforms as well. 2373 * 2374 * Note that this functions assumes that 0 is 2375 * the lowest voltage value, and higher values 2376 * correspond to increasingly higher voltages. 2377 * 2378 * Should that relationship no longer hold on 2379 * future platforms this code will need to be 2380 * adjusted. 2381 */ 2382 static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state) 2383 { 2384 struct intel_atomic_state *state = cdclk_state->base.state; 2385 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2386 struct intel_crtc *crtc; 2387 struct intel_crtc_state *crtc_state; 2388 u8 min_voltage_level; 2389 int i; 2390 enum pipe pipe; 2391 2392 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2393 int ret; 2394 2395 if (crtc_state->hw.enable) 2396 min_voltage_level = crtc_state->min_voltage_level; 2397 else 2398 min_voltage_level = 0; 2399 2400 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level) 2401 continue; 2402 2403 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level; 2404 2405 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2406 if (ret) 2407 return ret; 2408 } 2409 2410 min_voltage_level = 0; 2411 for_each_pipe(dev_priv, pipe) 2412 min_voltage_level = max(cdclk_state->min_voltage_level[pipe], 2413 min_voltage_level); 2414 2415 return min_voltage_level; 2416 } 2417 2418 static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2419 { 2420 struct intel_atomic_state *state = cdclk_state->base.state; 2421 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2422 int min_cdclk, cdclk; 2423 2424 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2425 if (min_cdclk < 0) 2426 return min_cdclk; 2427 2428 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); 2429 2430 cdclk_state->logical.cdclk = cdclk; 2431 cdclk_state->logical.voltage_level = 2432 vlv_calc_voltage_level(dev_priv, cdclk); 2433 2434 if (!cdclk_state->active_pipes) { 2435 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); 2436 2437 cdclk_state->actual.cdclk = cdclk; 2438 cdclk_state->actual.voltage_level = 2439 vlv_calc_voltage_level(dev_priv, cdclk); 2440 } else { 2441 cdclk_state->actual = cdclk_state->logical; 2442 } 2443 2444 return 0; 2445 } 2446 2447 static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2448 { 2449 int min_cdclk, cdclk; 2450 2451 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2452 if (min_cdclk < 0) 2453 return min_cdclk; 2454 2455 /* 2456 * FIXME should also account for plane ratio 2457 * once 64bpp pixel formats are supported. 2458 */ 2459 cdclk = bdw_calc_cdclk(min_cdclk); 2460 2461 cdclk_state->logical.cdclk = cdclk; 2462 cdclk_state->logical.voltage_level = 2463 bdw_calc_voltage_level(cdclk); 2464 2465 if (!cdclk_state->active_pipes) { 2466 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); 2467 2468 cdclk_state->actual.cdclk = cdclk; 2469 cdclk_state->actual.voltage_level = 2470 bdw_calc_voltage_level(cdclk); 2471 } else { 2472 cdclk_state->actual = cdclk_state->logical; 2473 } 2474 2475 return 0; 2476 } 2477 2478 static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state) 2479 { 2480 struct intel_atomic_state *state = cdclk_state->base.state; 2481 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2482 struct intel_crtc *crtc; 2483 struct intel_crtc_state *crtc_state; 2484 int vco, i; 2485 2486 vco = cdclk_state->logical.vco; 2487 if (!vco) 2488 vco = dev_priv->skl_preferred_vco_freq; 2489 2490 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2491 if (!crtc_state->hw.enable) 2492 continue; 2493 2494 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 2495 continue; 2496 2497 /* 2498 * DPLL0 VCO may need to be adjusted to get the correct 2499 * clock for eDP. This will affect cdclk as well. 2500 */ 2501 switch (crtc_state->port_clock / 2) { 2502 case 108000: 2503 case 216000: 2504 vco = 8640000; 2505 break; 2506 default: 2507 vco = 8100000; 2508 break; 2509 } 2510 } 2511 2512 return vco; 2513 } 2514 2515 static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2516 { 2517 int min_cdclk, cdclk, vco; 2518 2519 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2520 if (min_cdclk < 0) 2521 return min_cdclk; 2522 2523 vco = skl_dpll0_vco(cdclk_state); 2524 2525 /* 2526 * FIXME should also account for plane ratio 2527 * once 64bpp pixel formats are supported. 2528 */ 2529 cdclk = skl_calc_cdclk(min_cdclk, vco); 2530 2531 cdclk_state->logical.vco = vco; 2532 cdclk_state->logical.cdclk = cdclk; 2533 cdclk_state->logical.voltage_level = 2534 skl_calc_voltage_level(cdclk); 2535 2536 if (!cdclk_state->active_pipes) { 2537 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); 2538 2539 cdclk_state->actual.vco = vco; 2540 cdclk_state->actual.cdclk = cdclk; 2541 cdclk_state->actual.voltage_level = 2542 skl_calc_voltage_level(cdclk); 2543 } else { 2544 cdclk_state->actual = cdclk_state->logical; 2545 } 2546 2547 return 0; 2548 } 2549 2550 static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2551 { 2552 struct intel_atomic_state *state = cdclk_state->base.state; 2553 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2554 int min_cdclk, min_voltage_level, cdclk, vco; 2555 2556 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2557 if (min_cdclk < 0) 2558 return min_cdclk; 2559 2560 min_voltage_level = bxt_compute_min_voltage_level(cdclk_state); 2561 if (min_voltage_level < 0) 2562 return min_voltage_level; 2563 2564 cdclk = bxt_calc_cdclk(dev_priv, min_cdclk); 2565 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 2566 2567 cdclk_state->logical.vco = vco; 2568 cdclk_state->logical.cdclk = cdclk; 2569 cdclk_state->logical.voltage_level = 2570 max_t(int, min_voltage_level, 2571 intel_cdclk_calc_voltage_level(dev_priv, cdclk)); 2572 2573 if (!cdclk_state->active_pipes) { 2574 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); 2575 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 2576 2577 cdclk_state->actual.vco = vco; 2578 cdclk_state->actual.cdclk = cdclk; 2579 cdclk_state->actual.voltage_level = 2580 intel_cdclk_calc_voltage_level(dev_priv, cdclk); 2581 } else { 2582 cdclk_state->actual = cdclk_state->logical; 2583 } 2584 2585 return 0; 2586 } 2587 2588 static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2589 { 2590 int min_cdclk; 2591 2592 /* 2593 * We can't change the cdclk frequency, but we still want to 2594 * check that the required minimum frequency doesn't exceed 2595 * the actual cdclk frequency. 2596 */ 2597 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2598 if (min_cdclk < 0) 2599 return min_cdclk; 2600 2601 return 0; 2602 } 2603 2604 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj) 2605 { 2606 struct intel_cdclk_state *cdclk_state; 2607 2608 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); 2609 if (!cdclk_state) 2610 return NULL; 2611 2612 cdclk_state->pipe = INVALID_PIPE; 2613 2614 return &cdclk_state->base; 2615 } 2616 2617 static void intel_cdclk_destroy_state(struct intel_global_obj *obj, 2618 struct intel_global_state *state) 2619 { 2620 kfree(state); 2621 } 2622 2623 static const struct intel_global_state_funcs intel_cdclk_funcs = { 2624 .atomic_duplicate_state = intel_cdclk_duplicate_state, 2625 .atomic_destroy_state = intel_cdclk_destroy_state, 2626 }; 2627 2628 struct intel_cdclk_state * 2629 intel_atomic_get_cdclk_state(struct intel_atomic_state *state) 2630 { 2631 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2632 struct intel_global_state *cdclk_state; 2633 2634 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->cdclk.obj); 2635 if (IS_ERR(cdclk_state)) 2636 return ERR_CAST(cdclk_state); 2637 2638 return to_intel_cdclk_state(cdclk_state); 2639 } 2640 2641 int intel_cdclk_atomic_check(struct intel_atomic_state *state, 2642 bool *need_cdclk_calc) 2643 { 2644 struct drm_i915_private *i915 = to_i915(state->base.dev); 2645 const struct intel_cdclk_state *old_cdclk_state; 2646 const struct intel_cdclk_state *new_cdclk_state; 2647 struct intel_plane_state *plane_state; 2648 struct intel_bw_state *new_bw_state; 2649 struct intel_plane *plane; 2650 int min_cdclk = 0; 2651 enum pipe pipe; 2652 int ret; 2653 int i; 2654 2655 /* 2656 * active_planes bitmask has been updated, and potentially affected 2657 * planes are part of the state. We can now compute the minimum cdclk 2658 * for each plane. 2659 */ 2660 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 2661 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc); 2662 if (ret) 2663 return ret; 2664 } 2665 2666 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 2667 new_cdclk_state = intel_atomic_get_new_cdclk_state(state); 2668 2669 if (new_cdclk_state && 2670 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) 2671 *need_cdclk_calc = true; 2672 2673 ret = intel_cdclk_bw_calc_min_cdclk(state); 2674 if (ret) 2675 return ret; 2676 2677 new_bw_state = intel_atomic_get_new_bw_state(state); 2678 2679 if (!new_cdclk_state || !new_bw_state) 2680 return 0; 2681 2682 for_each_pipe(i915, pipe) { 2683 min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk); 2684 2685 /* Currently do this change only if we need to increase */ 2686 if (new_bw_state->min_cdclk > min_cdclk) 2687 *need_cdclk_calc = true; 2688 } 2689 2690 return 0; 2691 } 2692 2693 int intel_cdclk_init(struct drm_i915_private *dev_priv) 2694 { 2695 struct intel_cdclk_state *cdclk_state; 2696 2697 cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL); 2698 if (!cdclk_state) 2699 return -ENOMEM; 2700 2701 intel_atomic_global_obj_init(dev_priv, &dev_priv->cdclk.obj, 2702 &cdclk_state->base, &intel_cdclk_funcs); 2703 2704 return 0; 2705 } 2706 2707 int intel_modeset_calc_cdclk(struct intel_atomic_state *state) 2708 { 2709 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2710 const struct intel_cdclk_state *old_cdclk_state; 2711 struct intel_cdclk_state *new_cdclk_state; 2712 enum pipe pipe = INVALID_PIPE; 2713 int ret; 2714 2715 new_cdclk_state = intel_atomic_get_cdclk_state(state); 2716 if (IS_ERR(new_cdclk_state)) 2717 return PTR_ERR(new_cdclk_state); 2718 2719 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 2720 2721 new_cdclk_state->active_pipes = 2722 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); 2723 2724 ret = intel_cdclk_modeset_calc_cdclk(dev_priv, new_cdclk_state); 2725 if (ret) 2726 return ret; 2727 2728 if (intel_cdclk_changed(&old_cdclk_state->actual, 2729 &new_cdclk_state->actual)) { 2730 /* 2731 * Also serialize commits across all crtcs 2732 * if the actual hw needs to be poked. 2733 */ 2734 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); 2735 if (ret) 2736 return ret; 2737 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes || 2738 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk || 2739 intel_cdclk_changed(&old_cdclk_state->logical, 2740 &new_cdclk_state->logical)) { 2741 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 2742 if (ret) 2743 return ret; 2744 } else { 2745 return 0; 2746 } 2747 2748 if (is_power_of_2(new_cdclk_state->active_pipes) && 2749 intel_cdclk_can_cd2x_update(dev_priv, 2750 &old_cdclk_state->actual, 2751 &new_cdclk_state->actual)) { 2752 struct intel_crtc *crtc; 2753 struct intel_crtc_state *crtc_state; 2754 2755 pipe = ilog2(new_cdclk_state->active_pipes); 2756 crtc = intel_crtc_for_pipe(dev_priv, pipe); 2757 2758 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 2759 if (IS_ERR(crtc_state)) 2760 return PTR_ERR(crtc_state); 2761 2762 if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) 2763 pipe = INVALID_PIPE; 2764 } 2765 2766 if (intel_cdclk_can_squash(dev_priv, 2767 &old_cdclk_state->actual, 2768 &new_cdclk_state->actual)) { 2769 drm_dbg_kms(&dev_priv->drm, 2770 "Can change cdclk via squasher\n"); 2771 } else if (intel_cdclk_can_crawl(dev_priv, 2772 &old_cdclk_state->actual, 2773 &new_cdclk_state->actual)) { 2774 drm_dbg_kms(&dev_priv->drm, 2775 "Can change cdclk via crawl\n"); 2776 } else if (pipe != INVALID_PIPE) { 2777 new_cdclk_state->pipe = pipe; 2778 2779 drm_dbg_kms(&dev_priv->drm, 2780 "Can change cdclk cd2x divider with pipe %c active\n", 2781 pipe_name(pipe)); 2782 } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual, 2783 &new_cdclk_state->actual)) { 2784 /* All pipes must be switched off while we change the cdclk. */ 2785 ret = intel_modeset_all_pipes(state); 2786 if (ret) 2787 return ret; 2788 2789 drm_dbg_kms(&dev_priv->drm, 2790 "Modeset required for cdclk change\n"); 2791 } 2792 2793 drm_dbg_kms(&dev_priv->drm, 2794 "New cdclk calculated to be logical %u kHz, actual %u kHz\n", 2795 new_cdclk_state->logical.cdclk, 2796 new_cdclk_state->actual.cdclk); 2797 drm_dbg_kms(&dev_priv->drm, 2798 "New voltage level calculated to be logical %u, actual %u\n", 2799 new_cdclk_state->logical.voltage_level, 2800 new_cdclk_state->actual.voltage_level); 2801 2802 return 0; 2803 } 2804 2805 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) 2806 { 2807 int max_cdclk_freq = dev_priv->max_cdclk_freq; 2808 2809 if (DISPLAY_VER(dev_priv) >= 10) 2810 return 2 * max_cdclk_freq; 2811 else if (DISPLAY_VER(dev_priv) == 9 || 2812 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2813 return max_cdclk_freq; 2814 else if (IS_CHERRYVIEW(dev_priv)) 2815 return max_cdclk_freq*95/100; 2816 else if (DISPLAY_VER(dev_priv) < 4) 2817 return 2*max_cdclk_freq*90/100; 2818 else 2819 return max_cdclk_freq*90/100; 2820 } 2821 2822 /** 2823 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency 2824 * @dev_priv: i915 device 2825 * 2826 * Determine the maximum CDCLK frequency the platform supports, and also 2827 * derive the maximum dot clock frequency the maximum CDCLK frequency 2828 * allows. 2829 */ 2830 void intel_update_max_cdclk(struct drm_i915_private *dev_priv) 2831 { 2832 if (IS_JSL_EHL(dev_priv)) { 2833 if (dev_priv->cdclk.hw.ref == 24000) 2834 dev_priv->max_cdclk_freq = 552000; 2835 else 2836 dev_priv->max_cdclk_freq = 556800; 2837 } else if (DISPLAY_VER(dev_priv) >= 11) { 2838 if (dev_priv->cdclk.hw.ref == 24000) 2839 dev_priv->max_cdclk_freq = 648000; 2840 else 2841 dev_priv->max_cdclk_freq = 652800; 2842 } else if (IS_GEMINILAKE(dev_priv)) { 2843 dev_priv->max_cdclk_freq = 316800; 2844 } else if (IS_BROXTON(dev_priv)) { 2845 dev_priv->max_cdclk_freq = 624000; 2846 } else if (DISPLAY_VER(dev_priv) == 9) { 2847 u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; 2848 int max_cdclk, vco; 2849 2850 vco = dev_priv->skl_preferred_vco_freq; 2851 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); 2852 2853 /* 2854 * Use the lower (vco 8640) cdclk values as a 2855 * first guess. skl_calc_cdclk() will correct it 2856 * if the preferred vco is 8100 instead. 2857 */ 2858 if (limit == SKL_DFSM_CDCLK_LIMIT_675) 2859 max_cdclk = 617143; 2860 else if (limit == SKL_DFSM_CDCLK_LIMIT_540) 2861 max_cdclk = 540000; 2862 else if (limit == SKL_DFSM_CDCLK_LIMIT_450) 2863 max_cdclk = 432000; 2864 else 2865 max_cdclk = 308571; 2866 2867 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); 2868 } else if (IS_BROADWELL(dev_priv)) { 2869 /* 2870 * FIXME with extra cooling we can allow 2871 * 540 MHz for ULX and 675 Mhz for ULT. 2872 * How can we know if extra cooling is 2873 * available? PCI ID, VTB, something else? 2874 */ 2875 if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 2876 dev_priv->max_cdclk_freq = 450000; 2877 else if (IS_BDW_ULX(dev_priv)) 2878 dev_priv->max_cdclk_freq = 450000; 2879 else if (IS_BDW_ULT(dev_priv)) 2880 dev_priv->max_cdclk_freq = 540000; 2881 else 2882 dev_priv->max_cdclk_freq = 675000; 2883 } else if (IS_CHERRYVIEW(dev_priv)) { 2884 dev_priv->max_cdclk_freq = 320000; 2885 } else if (IS_VALLEYVIEW(dev_priv)) { 2886 dev_priv->max_cdclk_freq = 400000; 2887 } else { 2888 /* otherwise assume cdclk is fixed */ 2889 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk; 2890 } 2891 2892 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); 2893 2894 drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n", 2895 dev_priv->max_cdclk_freq); 2896 2897 drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n", 2898 dev_priv->max_dotclk_freq); 2899 } 2900 2901 /** 2902 * intel_update_cdclk - Determine the current CDCLK frequency 2903 * @dev_priv: i915 device 2904 * 2905 * Determine the current CDCLK frequency. 2906 */ 2907 void intel_update_cdclk(struct drm_i915_private *dev_priv) 2908 { 2909 intel_cdclk_get_cdclk(dev_priv, &dev_priv->cdclk.hw); 2910 2911 /* 2912 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): 2913 * Programmng [sic] note: bit[9:2] should be programmed to the number 2914 * of cdclk that generates 4MHz reference clock freq which is used to 2915 * generate GMBus clock. This will vary with the cdclk freq. 2916 */ 2917 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 2918 intel_de_write(dev_priv, GMBUSFREQ_VLV, 2919 DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000)); 2920 } 2921 2922 static int dg1_rawclk(struct drm_i915_private *dev_priv) 2923 { 2924 /* 2925 * DG1 always uses a 38.4 MHz rawclk. The bspec tells us 2926 * "Program Numerator=2, Denominator=4, Divider=37 decimal." 2927 */ 2928 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, 2929 CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2)); 2930 2931 return 38400; 2932 } 2933 2934 static int cnp_rawclk(struct drm_i915_private *dev_priv) 2935 { 2936 u32 rawclk; 2937 int divider, fraction; 2938 2939 if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { 2940 /* 24 MHz */ 2941 divider = 24000; 2942 fraction = 0; 2943 } else { 2944 /* 19.2 MHz */ 2945 divider = 19000; 2946 fraction = 200; 2947 } 2948 2949 rawclk = CNP_RAWCLK_DIV(divider / 1000); 2950 if (fraction) { 2951 int numerator = 1; 2952 2953 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000, 2954 fraction) - 1); 2955 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 2956 rawclk |= ICP_RAWCLK_NUM(numerator); 2957 } 2958 2959 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk); 2960 return divider + fraction; 2961 } 2962 2963 static int pch_rawclk(struct drm_i915_private *dev_priv) 2964 { 2965 return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; 2966 } 2967 2968 static int vlv_hrawclk(struct drm_i915_private *dev_priv) 2969 { 2970 /* RAWCLK_FREQ_VLV register updated from power well code */ 2971 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", 2972 CCK_DISPLAY_REF_CLOCK_CONTROL); 2973 } 2974 2975 static int i9xx_hrawclk(struct drm_i915_private *dev_priv) 2976 { 2977 u32 clkcfg; 2978 2979 /* 2980 * hrawclock is 1/4 the FSB frequency 2981 * 2982 * Note that this only reads the state of the FSB 2983 * straps, not the actual FSB frequency. Some BIOSen 2984 * let you configure each independently. Ideally we'd 2985 * read out the actual FSB frequency but sadly we 2986 * don't know which registers have that information, 2987 * and all the relevant docs have gone to bit heaven :( 2988 */ 2989 clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK; 2990 2991 if (IS_MOBILE(dev_priv)) { 2992 switch (clkcfg) { 2993 case CLKCFG_FSB_400: 2994 return 100000; 2995 case CLKCFG_FSB_533: 2996 return 133333; 2997 case CLKCFG_FSB_667: 2998 return 166667; 2999 case CLKCFG_FSB_800: 3000 return 200000; 3001 case CLKCFG_FSB_1067: 3002 return 266667; 3003 case CLKCFG_FSB_1333: 3004 return 333333; 3005 default: 3006 MISSING_CASE(clkcfg); 3007 return 133333; 3008 } 3009 } else { 3010 switch (clkcfg) { 3011 case CLKCFG_FSB_400_ALT: 3012 return 100000; 3013 case CLKCFG_FSB_533: 3014 return 133333; 3015 case CLKCFG_FSB_667: 3016 return 166667; 3017 case CLKCFG_FSB_800: 3018 return 200000; 3019 case CLKCFG_FSB_1067_ALT: 3020 return 266667; 3021 case CLKCFG_FSB_1333_ALT: 3022 return 333333; 3023 case CLKCFG_FSB_1600_ALT: 3024 return 400000; 3025 default: 3026 return 133333; 3027 } 3028 } 3029 } 3030 3031 /** 3032 * intel_read_rawclk - Determine the current RAWCLK frequency 3033 * @dev_priv: i915 device 3034 * 3035 * Determine the current RAWCLK frequency. RAWCLK is a fixed 3036 * frequency clock so this needs to done only once. 3037 */ 3038 u32 intel_read_rawclk(struct drm_i915_private *dev_priv) 3039 { 3040 u32 freq; 3041 3042 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 3043 freq = dg1_rawclk(dev_priv); 3044 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) 3045 freq = cnp_rawclk(dev_priv); 3046 else if (HAS_PCH_SPLIT(dev_priv)) 3047 freq = pch_rawclk(dev_priv); 3048 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 3049 freq = vlv_hrawclk(dev_priv); 3050 else if (DISPLAY_VER(dev_priv) >= 3) 3051 freq = i9xx_hrawclk(dev_priv); 3052 else 3053 /* no rawclk on other platforms, or no need to know it */ 3054 return 0; 3055 3056 return freq; 3057 } 3058 3059 static const struct intel_cdclk_funcs tgl_cdclk_funcs = { 3060 .get_cdclk = bxt_get_cdclk, 3061 .set_cdclk = bxt_set_cdclk, 3062 .bw_calc_min_cdclk = skl_bw_calc_min_cdclk, 3063 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3064 .calc_voltage_level = tgl_calc_voltage_level, 3065 }; 3066 3067 static const struct intel_cdclk_funcs ehl_cdclk_funcs = { 3068 .get_cdclk = bxt_get_cdclk, 3069 .set_cdclk = bxt_set_cdclk, 3070 .bw_calc_min_cdclk = skl_bw_calc_min_cdclk, 3071 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3072 .calc_voltage_level = ehl_calc_voltage_level, 3073 }; 3074 3075 static const struct intel_cdclk_funcs icl_cdclk_funcs = { 3076 .get_cdclk = bxt_get_cdclk, 3077 .set_cdclk = bxt_set_cdclk, 3078 .bw_calc_min_cdclk = skl_bw_calc_min_cdclk, 3079 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3080 .calc_voltage_level = icl_calc_voltage_level, 3081 }; 3082 3083 static const struct intel_cdclk_funcs bxt_cdclk_funcs = { 3084 .get_cdclk = bxt_get_cdclk, 3085 .set_cdclk = bxt_set_cdclk, 3086 .bw_calc_min_cdclk = skl_bw_calc_min_cdclk, 3087 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3088 .calc_voltage_level = bxt_calc_voltage_level, 3089 }; 3090 3091 static const struct intel_cdclk_funcs skl_cdclk_funcs = { 3092 .get_cdclk = skl_get_cdclk, 3093 .set_cdclk = skl_set_cdclk, 3094 .bw_calc_min_cdclk = skl_bw_calc_min_cdclk, 3095 .modeset_calc_cdclk = skl_modeset_calc_cdclk, 3096 }; 3097 3098 static const struct intel_cdclk_funcs bdw_cdclk_funcs = { 3099 .get_cdclk = bdw_get_cdclk, 3100 .set_cdclk = bdw_set_cdclk, 3101 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3102 .modeset_calc_cdclk = bdw_modeset_calc_cdclk, 3103 }; 3104 3105 static const struct intel_cdclk_funcs chv_cdclk_funcs = { 3106 .get_cdclk = vlv_get_cdclk, 3107 .set_cdclk = chv_set_cdclk, 3108 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3109 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3110 }; 3111 3112 static const struct intel_cdclk_funcs vlv_cdclk_funcs = { 3113 .get_cdclk = vlv_get_cdclk, 3114 .set_cdclk = vlv_set_cdclk, 3115 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3116 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3117 }; 3118 3119 static const struct intel_cdclk_funcs hsw_cdclk_funcs = { 3120 .get_cdclk = hsw_get_cdclk, 3121 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3122 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3123 }; 3124 3125 /* SNB, IVB, 965G, 945G */ 3126 static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = { 3127 .get_cdclk = fixed_400mhz_get_cdclk, 3128 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3129 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3130 }; 3131 3132 static const struct intel_cdclk_funcs ilk_cdclk_funcs = { 3133 .get_cdclk = fixed_450mhz_get_cdclk, 3134 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3135 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3136 }; 3137 3138 static const struct intel_cdclk_funcs gm45_cdclk_funcs = { 3139 .get_cdclk = gm45_get_cdclk, 3140 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3141 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3142 }; 3143 3144 /* G45 uses G33 */ 3145 3146 static const struct intel_cdclk_funcs i965gm_cdclk_funcs = { 3147 .get_cdclk = i965gm_get_cdclk, 3148 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3149 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3150 }; 3151 3152 /* i965G uses fixed 400 */ 3153 3154 static const struct intel_cdclk_funcs pnv_cdclk_funcs = { 3155 .get_cdclk = pnv_get_cdclk, 3156 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3157 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3158 }; 3159 3160 static const struct intel_cdclk_funcs g33_cdclk_funcs = { 3161 .get_cdclk = g33_get_cdclk, 3162 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3163 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3164 }; 3165 3166 static const struct intel_cdclk_funcs i945gm_cdclk_funcs = { 3167 .get_cdclk = i945gm_get_cdclk, 3168 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3169 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3170 }; 3171 3172 /* i945G uses fixed 400 */ 3173 3174 static const struct intel_cdclk_funcs i915gm_cdclk_funcs = { 3175 .get_cdclk = i915gm_get_cdclk, 3176 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3177 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3178 }; 3179 3180 static const struct intel_cdclk_funcs i915g_cdclk_funcs = { 3181 .get_cdclk = fixed_333mhz_get_cdclk, 3182 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3183 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3184 }; 3185 3186 static const struct intel_cdclk_funcs i865g_cdclk_funcs = { 3187 .get_cdclk = fixed_266mhz_get_cdclk, 3188 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3189 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3190 }; 3191 3192 static const struct intel_cdclk_funcs i85x_cdclk_funcs = { 3193 .get_cdclk = i85x_get_cdclk, 3194 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3195 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3196 }; 3197 3198 static const struct intel_cdclk_funcs i845g_cdclk_funcs = { 3199 .get_cdclk = fixed_200mhz_get_cdclk, 3200 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3201 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3202 }; 3203 3204 static const struct intel_cdclk_funcs i830_cdclk_funcs = { 3205 .get_cdclk = fixed_133mhz_get_cdclk, 3206 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3207 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3208 }; 3209 3210 /** 3211 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks 3212 * @dev_priv: i915 device 3213 */ 3214 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) 3215 { 3216 if (IS_DG2(dev_priv)) { 3217 dev_priv->cdclk_funcs = &tgl_cdclk_funcs; 3218 dev_priv->cdclk.table = dg2_cdclk_table; 3219 } else if (IS_ALDERLAKE_P(dev_priv)) { 3220 dev_priv->cdclk_funcs = &tgl_cdclk_funcs; 3221 /* Wa_22011320316:adl-p[a0] */ 3222 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 3223 dev_priv->cdclk.table = adlp_a_step_cdclk_table; 3224 else 3225 dev_priv->cdclk.table = adlp_cdclk_table; 3226 } else if (IS_ROCKETLAKE(dev_priv)) { 3227 dev_priv->cdclk_funcs = &tgl_cdclk_funcs; 3228 dev_priv->cdclk.table = rkl_cdclk_table; 3229 } else if (DISPLAY_VER(dev_priv) >= 12) { 3230 dev_priv->cdclk_funcs = &tgl_cdclk_funcs; 3231 dev_priv->cdclk.table = icl_cdclk_table; 3232 } else if (IS_JSL_EHL(dev_priv)) { 3233 dev_priv->cdclk_funcs = &ehl_cdclk_funcs; 3234 dev_priv->cdclk.table = icl_cdclk_table; 3235 } else if (DISPLAY_VER(dev_priv) >= 11) { 3236 dev_priv->cdclk_funcs = &icl_cdclk_funcs; 3237 dev_priv->cdclk.table = icl_cdclk_table; 3238 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 3239 dev_priv->cdclk_funcs = &bxt_cdclk_funcs; 3240 if (IS_GEMINILAKE(dev_priv)) 3241 dev_priv->cdclk.table = glk_cdclk_table; 3242 else 3243 dev_priv->cdclk.table = bxt_cdclk_table; 3244 } else if (DISPLAY_VER(dev_priv) == 9) { 3245 dev_priv->cdclk_funcs = &skl_cdclk_funcs; 3246 } else if (IS_BROADWELL(dev_priv)) { 3247 dev_priv->cdclk_funcs = &bdw_cdclk_funcs; 3248 } else if (IS_HASWELL(dev_priv)) { 3249 dev_priv->cdclk_funcs = &hsw_cdclk_funcs; 3250 } else if (IS_CHERRYVIEW(dev_priv)) { 3251 dev_priv->cdclk_funcs = &chv_cdclk_funcs; 3252 } else if (IS_VALLEYVIEW(dev_priv)) { 3253 dev_priv->cdclk_funcs = &vlv_cdclk_funcs; 3254 } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) { 3255 dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs; 3256 } else if (IS_IRONLAKE(dev_priv)) { 3257 dev_priv->cdclk_funcs = &ilk_cdclk_funcs; 3258 } else if (IS_GM45(dev_priv)) { 3259 dev_priv->cdclk_funcs = &gm45_cdclk_funcs; 3260 } else if (IS_G45(dev_priv)) { 3261 dev_priv->cdclk_funcs = &g33_cdclk_funcs; 3262 } else if (IS_I965GM(dev_priv)) { 3263 dev_priv->cdclk_funcs = &i965gm_cdclk_funcs; 3264 } else if (IS_I965G(dev_priv)) { 3265 dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs; 3266 } else if (IS_PINEVIEW(dev_priv)) { 3267 dev_priv->cdclk_funcs = &pnv_cdclk_funcs; 3268 } else if (IS_G33(dev_priv)) { 3269 dev_priv->cdclk_funcs = &g33_cdclk_funcs; 3270 } else if (IS_I945GM(dev_priv)) { 3271 dev_priv->cdclk_funcs = &i945gm_cdclk_funcs; 3272 } else if (IS_I945G(dev_priv)) { 3273 dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs; 3274 } else if (IS_I915GM(dev_priv)) { 3275 dev_priv->cdclk_funcs = &i915gm_cdclk_funcs; 3276 } else if (IS_I915G(dev_priv)) { 3277 dev_priv->cdclk_funcs = &i915g_cdclk_funcs; 3278 } else if (IS_I865G(dev_priv)) { 3279 dev_priv->cdclk_funcs = &i865g_cdclk_funcs; 3280 } else if (IS_I85X(dev_priv)) { 3281 dev_priv->cdclk_funcs = &i85x_cdclk_funcs; 3282 } else if (IS_I845G(dev_priv)) { 3283 dev_priv->cdclk_funcs = &i845g_cdclk_funcs; 3284 } else if (IS_I830(dev_priv)) { 3285 dev_priv->cdclk_funcs = &i830_cdclk_funcs; 3286 } 3287 3288 if (drm_WARN(&dev_priv->drm, !dev_priv->cdclk_funcs, 3289 "Unknown platform. Assuming i830\n")) 3290 dev_priv->cdclk_funcs = &i830_cdclk_funcs; 3291 } 3292