1 /* 2 * Copyright © 2006-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/time.h> 25 26 #include "hsw_ips.h" 27 #include "intel_atomic.h" 28 #include "intel_atomic_plane.h" 29 #include "intel_audio.h" 30 #include "intel_bw.h" 31 #include "intel_cdclk.h" 32 #include "intel_crtc.h" 33 #include "intel_de.h" 34 #include "intel_display_types.h" 35 #include "intel_mchbar_regs.h" 36 #include "intel_pci_config.h" 37 #include "intel_pcode.h" 38 #include "intel_psr.h" 39 #include "vlv_sideband.h" 40 41 /** 42 * DOC: CDCLK / RAWCLK 43 * 44 * The display engine uses several different clocks to do its work. There 45 * are two main clocks involved that aren't directly related to the actual 46 * pixel clock or any symbol/bit clock of the actual output port. These 47 * are the core display clock (CDCLK) and RAWCLK. 48 * 49 * CDCLK clocks most of the display pipe logic, and thus its frequency 50 * must be high enough to support the rate at which pixels are flowing 51 * through the pipes. Downscaling must also be accounted as that increases 52 * the effective pixel rate. 53 * 54 * On several platforms the CDCLK frequency can be changed dynamically 55 * to minimize power consumption for a given display configuration. 56 * Typically changes to the CDCLK frequency require all the display pipes 57 * to be shut down while the frequency is being changed. 58 * 59 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. 60 * DMC will not change the active CDCLK frequency however, so that part 61 * will still be performed by the driver directly. 62 * 63 * RAWCLK is a fixed frequency clock, often used by various auxiliary 64 * blocks such as AUX CH or backlight PWM. Hence the only thing we 65 * really need to know about RAWCLK is its frequency so that various 66 * dividers can be programmed correctly. 67 */ 68 69 struct intel_cdclk_funcs { 70 void (*get_cdclk)(struct drm_i915_private *i915, 71 struct intel_cdclk_config *cdclk_config); 72 void (*set_cdclk)(struct drm_i915_private *i915, 73 const struct intel_cdclk_config *cdclk_config, 74 enum pipe pipe); 75 int (*bw_calc_min_cdclk)(struct intel_atomic_state *state); 76 int (*modeset_calc_cdclk)(struct intel_cdclk_state *state); 77 u8 (*calc_voltage_level)(int cdclk); 78 }; 79 80 void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv, 81 struct intel_cdclk_config *cdclk_config) 82 { 83 dev_priv->cdclk_funcs->get_cdclk(dev_priv, cdclk_config); 84 } 85 86 static int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state) 87 { 88 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 89 return dev_priv->cdclk_funcs->bw_calc_min_cdclk(state); 90 } 91 92 static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv, 93 const struct intel_cdclk_config *cdclk_config, 94 enum pipe pipe) 95 { 96 dev_priv->cdclk_funcs->set_cdclk(dev_priv, cdclk_config, pipe); 97 } 98 99 static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv, 100 struct intel_cdclk_state *cdclk_config) 101 { 102 return dev_priv->cdclk_funcs->modeset_calc_cdclk(cdclk_config); 103 } 104 105 static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv, 106 int cdclk) 107 { 108 return dev_priv->cdclk_funcs->calc_voltage_level(cdclk); 109 } 110 111 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, 112 struct intel_cdclk_config *cdclk_config) 113 { 114 cdclk_config->cdclk = 133333; 115 } 116 117 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, 118 struct intel_cdclk_config *cdclk_config) 119 { 120 cdclk_config->cdclk = 200000; 121 } 122 123 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, 124 struct intel_cdclk_config *cdclk_config) 125 { 126 cdclk_config->cdclk = 266667; 127 } 128 129 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, 130 struct intel_cdclk_config *cdclk_config) 131 { 132 cdclk_config->cdclk = 333333; 133 } 134 135 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, 136 struct intel_cdclk_config *cdclk_config) 137 { 138 cdclk_config->cdclk = 400000; 139 } 140 141 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, 142 struct intel_cdclk_config *cdclk_config) 143 { 144 cdclk_config->cdclk = 450000; 145 } 146 147 static void i85x_get_cdclk(struct drm_i915_private *dev_priv, 148 struct intel_cdclk_config *cdclk_config) 149 { 150 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 151 u16 hpllcc = 0; 152 153 /* 154 * 852GM/852GMV only supports 133 MHz and the HPLLCC 155 * encoding is different :( 156 * FIXME is this the right way to detect 852GM/852GMV? 157 */ 158 if (pdev->revision == 0x1) { 159 cdclk_config->cdclk = 133333; 160 return; 161 } 162 163 pci_bus_read_config_word(pdev->bus, 164 PCI_DEVFN(0, 3), HPLLCC, &hpllcc); 165 166 /* Assume that the hardware is in the high speed state. This 167 * should be the default. 168 */ 169 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 170 case GC_CLOCK_133_200: 171 case GC_CLOCK_133_200_2: 172 case GC_CLOCK_100_200: 173 cdclk_config->cdclk = 200000; 174 break; 175 case GC_CLOCK_166_250: 176 cdclk_config->cdclk = 250000; 177 break; 178 case GC_CLOCK_100_133: 179 cdclk_config->cdclk = 133333; 180 break; 181 case GC_CLOCK_133_266: 182 case GC_CLOCK_133_266_2: 183 case GC_CLOCK_166_266: 184 cdclk_config->cdclk = 266667; 185 break; 186 } 187 } 188 189 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, 190 struct intel_cdclk_config *cdclk_config) 191 { 192 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 193 u16 gcfgc = 0; 194 195 pci_read_config_word(pdev, GCFGC, &gcfgc); 196 197 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 198 cdclk_config->cdclk = 133333; 199 return; 200 } 201 202 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 203 case GC_DISPLAY_CLOCK_333_320_MHZ: 204 cdclk_config->cdclk = 333333; 205 break; 206 default: 207 case GC_DISPLAY_CLOCK_190_200_MHZ: 208 cdclk_config->cdclk = 190000; 209 break; 210 } 211 } 212 213 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, 214 struct intel_cdclk_config *cdclk_config) 215 { 216 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 217 u16 gcfgc = 0; 218 219 pci_read_config_word(pdev, GCFGC, &gcfgc); 220 221 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 222 cdclk_config->cdclk = 133333; 223 return; 224 } 225 226 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 227 case GC_DISPLAY_CLOCK_333_320_MHZ: 228 cdclk_config->cdclk = 320000; 229 break; 230 default: 231 case GC_DISPLAY_CLOCK_190_200_MHZ: 232 cdclk_config->cdclk = 200000; 233 break; 234 } 235 } 236 237 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) 238 { 239 static const unsigned int blb_vco[8] = { 240 [0] = 3200000, 241 [1] = 4000000, 242 [2] = 5333333, 243 [3] = 4800000, 244 [4] = 6400000, 245 }; 246 static const unsigned int pnv_vco[8] = { 247 [0] = 3200000, 248 [1] = 4000000, 249 [2] = 5333333, 250 [3] = 4800000, 251 [4] = 2666667, 252 }; 253 static const unsigned int cl_vco[8] = { 254 [0] = 3200000, 255 [1] = 4000000, 256 [2] = 5333333, 257 [3] = 6400000, 258 [4] = 3333333, 259 [5] = 3566667, 260 [6] = 4266667, 261 }; 262 static const unsigned int elk_vco[8] = { 263 [0] = 3200000, 264 [1] = 4000000, 265 [2] = 5333333, 266 [3] = 4800000, 267 }; 268 static const unsigned int ctg_vco[8] = { 269 [0] = 3200000, 270 [1] = 4000000, 271 [2] = 5333333, 272 [3] = 6400000, 273 [4] = 2666667, 274 [5] = 4266667, 275 }; 276 const unsigned int *vco_table; 277 unsigned int vco; 278 u8 tmp = 0; 279 280 /* FIXME other chipsets? */ 281 if (IS_GM45(dev_priv)) 282 vco_table = ctg_vco; 283 else if (IS_G45(dev_priv)) 284 vco_table = elk_vco; 285 else if (IS_I965GM(dev_priv)) 286 vco_table = cl_vco; 287 else if (IS_PINEVIEW(dev_priv)) 288 vco_table = pnv_vco; 289 else if (IS_G33(dev_priv)) 290 vco_table = blb_vco; 291 else 292 return 0; 293 294 tmp = intel_de_read(dev_priv, 295 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); 296 297 vco = vco_table[tmp & 0x7]; 298 if (vco == 0) 299 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", 300 tmp); 301 else 302 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); 303 304 return vco; 305 } 306 307 static void g33_get_cdclk(struct drm_i915_private *dev_priv, 308 struct intel_cdclk_config *cdclk_config) 309 { 310 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 311 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 }; 312 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 }; 313 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 }; 314 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 }; 315 const u8 *div_table; 316 unsigned int cdclk_sel; 317 u16 tmp = 0; 318 319 cdclk_config->vco = intel_hpll_vco(dev_priv); 320 321 pci_read_config_word(pdev, GCFGC, &tmp); 322 323 cdclk_sel = (tmp >> 4) & 0x7; 324 325 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 326 goto fail; 327 328 switch (cdclk_config->vco) { 329 case 3200000: 330 div_table = div_3200; 331 break; 332 case 4000000: 333 div_table = div_4000; 334 break; 335 case 4800000: 336 div_table = div_4800; 337 break; 338 case 5333333: 339 div_table = div_5333; 340 break; 341 default: 342 goto fail; 343 } 344 345 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 346 div_table[cdclk_sel]); 347 return; 348 349 fail: 350 drm_err(&dev_priv->drm, 351 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", 352 cdclk_config->vco, tmp); 353 cdclk_config->cdclk = 190476; 354 } 355 356 static void pnv_get_cdclk(struct drm_i915_private *dev_priv, 357 struct intel_cdclk_config *cdclk_config) 358 { 359 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 360 u16 gcfgc = 0; 361 362 pci_read_config_word(pdev, GCFGC, &gcfgc); 363 364 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 365 case GC_DISPLAY_CLOCK_267_MHZ_PNV: 366 cdclk_config->cdclk = 266667; 367 break; 368 case GC_DISPLAY_CLOCK_333_MHZ_PNV: 369 cdclk_config->cdclk = 333333; 370 break; 371 case GC_DISPLAY_CLOCK_444_MHZ_PNV: 372 cdclk_config->cdclk = 444444; 373 break; 374 case GC_DISPLAY_CLOCK_200_MHZ_PNV: 375 cdclk_config->cdclk = 200000; 376 break; 377 default: 378 drm_err(&dev_priv->drm, 379 "Unknown pnv display core clock 0x%04x\n", gcfgc); 380 fallthrough; 381 case GC_DISPLAY_CLOCK_133_MHZ_PNV: 382 cdclk_config->cdclk = 133333; 383 break; 384 case GC_DISPLAY_CLOCK_167_MHZ_PNV: 385 cdclk_config->cdclk = 166667; 386 break; 387 } 388 } 389 390 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, 391 struct intel_cdclk_config *cdclk_config) 392 { 393 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 394 static const u8 div_3200[] = { 16, 10, 8 }; 395 static const u8 div_4000[] = { 20, 12, 10 }; 396 static const u8 div_5333[] = { 24, 16, 14 }; 397 const u8 *div_table; 398 unsigned int cdclk_sel; 399 u16 tmp = 0; 400 401 cdclk_config->vco = intel_hpll_vco(dev_priv); 402 403 pci_read_config_word(pdev, GCFGC, &tmp); 404 405 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; 406 407 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 408 goto fail; 409 410 switch (cdclk_config->vco) { 411 case 3200000: 412 div_table = div_3200; 413 break; 414 case 4000000: 415 div_table = div_4000; 416 break; 417 case 5333333: 418 div_table = div_5333; 419 break; 420 default: 421 goto fail; 422 } 423 424 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 425 div_table[cdclk_sel]); 426 return; 427 428 fail: 429 drm_err(&dev_priv->drm, 430 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", 431 cdclk_config->vco, tmp); 432 cdclk_config->cdclk = 200000; 433 } 434 435 static void gm45_get_cdclk(struct drm_i915_private *dev_priv, 436 struct intel_cdclk_config *cdclk_config) 437 { 438 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 439 unsigned int cdclk_sel; 440 u16 tmp = 0; 441 442 cdclk_config->vco = intel_hpll_vco(dev_priv); 443 444 pci_read_config_word(pdev, GCFGC, &tmp); 445 446 cdclk_sel = (tmp >> 12) & 0x1; 447 448 switch (cdclk_config->vco) { 449 case 2666667: 450 case 4000000: 451 case 5333333: 452 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; 453 break; 454 case 3200000: 455 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; 456 break; 457 default: 458 drm_err(&dev_priv->drm, 459 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", 460 cdclk_config->vco, tmp); 461 cdclk_config->cdclk = 222222; 462 break; 463 } 464 } 465 466 static void hsw_get_cdclk(struct drm_i915_private *dev_priv, 467 struct intel_cdclk_config *cdclk_config) 468 { 469 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); 470 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 471 472 if (lcpll & LCPLL_CD_SOURCE_FCLK) 473 cdclk_config->cdclk = 800000; 474 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 475 cdclk_config->cdclk = 450000; 476 else if (freq == LCPLL_CLK_FREQ_450) 477 cdclk_config->cdclk = 450000; 478 else if (IS_HSW_ULT(dev_priv)) 479 cdclk_config->cdclk = 337500; 480 else 481 cdclk_config->cdclk = 540000; 482 } 483 484 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) 485 { 486 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 487 333333 : 320000; 488 489 /* 490 * We seem to get an unstable or solid color picture at 200MHz. 491 * Not sure what's wrong. For now use 200MHz only when all pipes 492 * are off. 493 */ 494 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) 495 return 400000; 496 else if (min_cdclk > 266667) 497 return freq_320; 498 else if (min_cdclk > 0) 499 return 266667; 500 else 501 return 200000; 502 } 503 504 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) 505 { 506 if (IS_VALLEYVIEW(dev_priv)) { 507 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ 508 return 2; 509 else if (cdclk >= 266667) 510 return 1; 511 else 512 return 0; 513 } else { 514 /* 515 * Specs are full of misinformation, but testing on actual 516 * hardware has shown that we just need to write the desired 517 * CCK divider into the Punit register. 518 */ 519 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; 520 } 521 } 522 523 static void vlv_get_cdclk(struct drm_i915_private *dev_priv, 524 struct intel_cdclk_config *cdclk_config) 525 { 526 u32 val; 527 528 vlv_iosf_sb_get(dev_priv, 529 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 530 531 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); 532 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", 533 CCK_DISPLAY_CLOCK_CONTROL, 534 cdclk_config->vco); 535 536 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 537 538 vlv_iosf_sb_put(dev_priv, 539 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 540 541 if (IS_VALLEYVIEW(dev_priv)) 542 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> 543 DSPFREQGUAR_SHIFT; 544 else 545 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> 546 DSPFREQGUAR_SHIFT_CHV; 547 } 548 549 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) 550 { 551 unsigned int credits, default_credits; 552 553 if (IS_CHERRYVIEW(dev_priv)) 554 default_credits = PFI_CREDIT(12); 555 else 556 default_credits = PFI_CREDIT(8); 557 558 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) { 559 /* CHV suggested value is 31 or 63 */ 560 if (IS_CHERRYVIEW(dev_priv)) 561 credits = PFI_CREDIT_63; 562 else 563 credits = PFI_CREDIT(15); 564 } else { 565 credits = default_credits; 566 } 567 568 /* 569 * WA - write default credits before re-programming 570 * FIXME: should we also set the resend bit here? 571 */ 572 intel_de_write(dev_priv, GCI_CONTROL, 573 VGA_FAST_MODE_DISABLE | default_credits); 574 575 intel_de_write(dev_priv, GCI_CONTROL, 576 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND); 577 578 /* 579 * FIXME is this guaranteed to clear 580 * immediately or should we poll for it? 581 */ 582 drm_WARN_ON(&dev_priv->drm, 583 intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND); 584 } 585 586 static void vlv_set_cdclk(struct drm_i915_private *dev_priv, 587 const struct intel_cdclk_config *cdclk_config, 588 enum pipe pipe) 589 { 590 int cdclk = cdclk_config->cdclk; 591 u32 val, cmd = cdclk_config->voltage_level; 592 intel_wakeref_t wakeref; 593 594 switch (cdclk) { 595 case 400000: 596 case 333333: 597 case 320000: 598 case 266667: 599 case 200000: 600 break; 601 default: 602 MISSING_CASE(cdclk); 603 return; 604 } 605 606 /* There are cases where we can end up here with power domains 607 * off and a CDCLK frequency other than the minimum, like when 608 * issuing a modeset without actually changing any display after 609 * a system suspend. So grab the display core domain, which covers 610 * the HW blocks needed for the following programming. 611 */ 612 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); 613 614 vlv_iosf_sb_get(dev_priv, 615 BIT(VLV_IOSF_SB_CCK) | 616 BIT(VLV_IOSF_SB_BUNIT) | 617 BIT(VLV_IOSF_SB_PUNIT)); 618 619 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 620 val &= ~DSPFREQGUAR_MASK; 621 val |= (cmd << DSPFREQGUAR_SHIFT); 622 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); 623 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & 624 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 625 50)) { 626 drm_err(&dev_priv->drm, 627 "timed out waiting for CDclk change\n"); 628 } 629 630 if (cdclk == 400000) { 631 u32 divider; 632 633 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, 634 cdclk) - 1; 635 636 /* adjust cdclk divider */ 637 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); 638 val &= ~CCK_FREQUENCY_VALUES; 639 val |= divider; 640 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); 641 642 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & 643 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 644 50)) 645 drm_err(&dev_priv->drm, 646 "timed out waiting for CDclk change\n"); 647 } 648 649 /* adjust self-refresh exit latency value */ 650 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); 651 val &= ~0x7f; 652 653 /* 654 * For high bandwidth configs, we set a higher latency in the bunit 655 * so that the core display fetch happens in time to avoid underruns. 656 */ 657 if (cdclk == 400000) 658 val |= 4500 / 250; /* 4.5 usec */ 659 else 660 val |= 3000 / 250; /* 3.0 usec */ 661 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); 662 663 vlv_iosf_sb_put(dev_priv, 664 BIT(VLV_IOSF_SB_CCK) | 665 BIT(VLV_IOSF_SB_BUNIT) | 666 BIT(VLV_IOSF_SB_PUNIT)); 667 668 intel_update_cdclk(dev_priv); 669 670 vlv_program_pfi_credits(dev_priv); 671 672 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); 673 } 674 675 static void chv_set_cdclk(struct drm_i915_private *dev_priv, 676 const struct intel_cdclk_config *cdclk_config, 677 enum pipe pipe) 678 { 679 int cdclk = cdclk_config->cdclk; 680 u32 val, cmd = cdclk_config->voltage_level; 681 intel_wakeref_t wakeref; 682 683 switch (cdclk) { 684 case 333333: 685 case 320000: 686 case 266667: 687 case 200000: 688 break; 689 default: 690 MISSING_CASE(cdclk); 691 return; 692 } 693 694 /* There are cases where we can end up here with power domains 695 * off and a CDCLK frequency other than the minimum, like when 696 * issuing a modeset without actually changing any display after 697 * a system suspend. So grab the display core domain, which covers 698 * the HW blocks needed for the following programming. 699 */ 700 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); 701 702 vlv_punit_get(dev_priv); 703 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 704 val &= ~DSPFREQGUAR_MASK_CHV; 705 val |= (cmd << DSPFREQGUAR_SHIFT_CHV); 706 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); 707 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & 708 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 709 50)) { 710 drm_err(&dev_priv->drm, 711 "timed out waiting for CDclk change\n"); 712 } 713 714 vlv_punit_put(dev_priv); 715 716 intel_update_cdclk(dev_priv); 717 718 vlv_program_pfi_credits(dev_priv); 719 720 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); 721 } 722 723 static int bdw_calc_cdclk(int min_cdclk) 724 { 725 if (min_cdclk > 540000) 726 return 675000; 727 else if (min_cdclk > 450000) 728 return 540000; 729 else if (min_cdclk > 337500) 730 return 450000; 731 else 732 return 337500; 733 } 734 735 static u8 bdw_calc_voltage_level(int cdclk) 736 { 737 switch (cdclk) { 738 default: 739 case 337500: 740 return 2; 741 case 450000: 742 return 0; 743 case 540000: 744 return 1; 745 case 675000: 746 return 3; 747 } 748 } 749 750 static void bdw_get_cdclk(struct drm_i915_private *dev_priv, 751 struct intel_cdclk_config *cdclk_config) 752 { 753 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); 754 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 755 756 if (lcpll & LCPLL_CD_SOURCE_FCLK) 757 cdclk_config->cdclk = 800000; 758 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 759 cdclk_config->cdclk = 450000; 760 else if (freq == LCPLL_CLK_FREQ_450) 761 cdclk_config->cdclk = 450000; 762 else if (freq == LCPLL_CLK_FREQ_54O_BDW) 763 cdclk_config->cdclk = 540000; 764 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 765 cdclk_config->cdclk = 337500; 766 else 767 cdclk_config->cdclk = 675000; 768 769 /* 770 * Can't read this out :( Let's assume it's 771 * at least what the CDCLK frequency requires. 772 */ 773 cdclk_config->voltage_level = 774 bdw_calc_voltage_level(cdclk_config->cdclk); 775 } 776 777 static u32 bdw_cdclk_freq_sel(int cdclk) 778 { 779 switch (cdclk) { 780 default: 781 MISSING_CASE(cdclk); 782 fallthrough; 783 case 337500: 784 return LCPLL_CLK_FREQ_337_5_BDW; 785 case 450000: 786 return LCPLL_CLK_FREQ_450; 787 case 540000: 788 return LCPLL_CLK_FREQ_54O_BDW; 789 case 675000: 790 return LCPLL_CLK_FREQ_675_BDW; 791 } 792 } 793 794 static void bdw_set_cdclk(struct drm_i915_private *dev_priv, 795 const struct intel_cdclk_config *cdclk_config, 796 enum pipe pipe) 797 { 798 int cdclk = cdclk_config->cdclk; 799 int ret; 800 801 if (drm_WARN(&dev_priv->drm, 802 (intel_de_read(dev_priv, LCPLL_CTL) & 803 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | 804 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | 805 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | 806 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, 807 "trying to change cdclk frequency with cdclk not enabled\n")) 808 return; 809 810 ret = snb_pcode_write(dev_priv, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); 811 if (ret) { 812 drm_err(&dev_priv->drm, 813 "failed to inform pcode about cdclk change\n"); 814 return; 815 } 816 817 intel_de_rmw(dev_priv, LCPLL_CTL, 818 0, LCPLL_CD_SOURCE_FCLK); 819 820 /* 821 * According to the spec, it should be enough to poll for this 1 us. 822 * However, extensive testing shows that this can take longer. 823 */ 824 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) & 825 LCPLL_CD_SOURCE_FCLK_DONE, 100)) 826 drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); 827 828 intel_de_rmw(dev_priv, LCPLL_CTL, 829 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk)); 830 831 intel_de_rmw(dev_priv, LCPLL_CTL, 832 LCPLL_CD_SOURCE_FCLK, 0); 833 834 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) & 835 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 836 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n"); 837 838 snb_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, 839 cdclk_config->voltage_level); 840 841 intel_de_write(dev_priv, CDCLK_FREQ, 842 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); 843 844 intel_update_cdclk(dev_priv); 845 } 846 847 static int skl_calc_cdclk(int min_cdclk, int vco) 848 { 849 if (vco == 8640000) { 850 if (min_cdclk > 540000) 851 return 617143; 852 else if (min_cdclk > 432000) 853 return 540000; 854 else if (min_cdclk > 308571) 855 return 432000; 856 else 857 return 308571; 858 } else { 859 if (min_cdclk > 540000) 860 return 675000; 861 else if (min_cdclk > 450000) 862 return 540000; 863 else if (min_cdclk > 337500) 864 return 450000; 865 else 866 return 337500; 867 } 868 } 869 870 static u8 skl_calc_voltage_level(int cdclk) 871 { 872 if (cdclk > 540000) 873 return 3; 874 else if (cdclk > 450000) 875 return 2; 876 else if (cdclk > 337500) 877 return 1; 878 else 879 return 0; 880 } 881 882 static void skl_dpll0_update(struct drm_i915_private *dev_priv, 883 struct intel_cdclk_config *cdclk_config) 884 { 885 u32 val; 886 887 cdclk_config->ref = 24000; 888 cdclk_config->vco = 0; 889 890 val = intel_de_read(dev_priv, LCPLL1_CTL); 891 if ((val & LCPLL_PLL_ENABLE) == 0) 892 return; 893 894 if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0)) 895 return; 896 897 val = intel_de_read(dev_priv, DPLL_CTRL1); 898 899 if (drm_WARN_ON(&dev_priv->drm, 900 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 901 DPLL_CTRL1_SSC(SKL_DPLL0) | 902 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != 903 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) 904 return; 905 906 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { 907 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): 908 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): 909 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): 910 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): 911 cdclk_config->vco = 8100000; 912 break; 913 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): 914 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): 915 cdclk_config->vco = 8640000; 916 break; 917 default: 918 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 919 break; 920 } 921 } 922 923 static void skl_get_cdclk(struct drm_i915_private *dev_priv, 924 struct intel_cdclk_config *cdclk_config) 925 { 926 u32 cdctl; 927 928 skl_dpll0_update(dev_priv, cdclk_config); 929 930 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; 931 932 if (cdclk_config->vco == 0) 933 goto out; 934 935 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 936 937 if (cdclk_config->vco == 8640000) { 938 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 939 case CDCLK_FREQ_450_432: 940 cdclk_config->cdclk = 432000; 941 break; 942 case CDCLK_FREQ_337_308: 943 cdclk_config->cdclk = 308571; 944 break; 945 case CDCLK_FREQ_540: 946 cdclk_config->cdclk = 540000; 947 break; 948 case CDCLK_FREQ_675_617: 949 cdclk_config->cdclk = 617143; 950 break; 951 default: 952 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 953 break; 954 } 955 } else { 956 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 957 case CDCLK_FREQ_450_432: 958 cdclk_config->cdclk = 450000; 959 break; 960 case CDCLK_FREQ_337_308: 961 cdclk_config->cdclk = 337500; 962 break; 963 case CDCLK_FREQ_540: 964 cdclk_config->cdclk = 540000; 965 break; 966 case CDCLK_FREQ_675_617: 967 cdclk_config->cdclk = 675000; 968 break; 969 default: 970 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 971 break; 972 } 973 } 974 975 out: 976 /* 977 * Can't read this out :( Let's assume it's 978 * at least what the CDCLK frequency requires. 979 */ 980 cdclk_config->voltage_level = 981 skl_calc_voltage_level(cdclk_config->cdclk); 982 } 983 984 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ 985 static int skl_cdclk_decimal(int cdclk) 986 { 987 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); 988 } 989 990 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, 991 int vco) 992 { 993 bool changed = dev_priv->skl_preferred_vco_freq != vco; 994 995 dev_priv->skl_preferred_vco_freq = vco; 996 997 if (changed) 998 intel_update_max_cdclk(dev_priv); 999 } 1000 1001 static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco) 1002 { 1003 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); 1004 1005 /* 1006 * We always enable DPLL0 with the lowest link rate possible, but still 1007 * taking into account the VCO required to operate the eDP panel at the 1008 * desired frequency. The usual DP link rates operate with a VCO of 1009 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. 1010 * The modeset code is responsible for the selection of the exact link 1011 * rate later on, with the constraint of choosing a frequency that 1012 * works with vco. 1013 */ 1014 if (vco == 8640000) 1015 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0); 1016 else 1017 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0); 1018 } 1019 1020 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) 1021 { 1022 intel_de_rmw(dev_priv, DPLL_CTRL1, 1023 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 1024 DPLL_CTRL1_SSC(SKL_DPLL0) | 1025 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0), 1026 DPLL_CTRL1_OVERRIDE(SKL_DPLL0) | 1027 skl_dpll0_link_rate(dev_priv, vco)); 1028 intel_de_posting_read(dev_priv, DPLL_CTRL1); 1029 1030 intel_de_rmw(dev_priv, LCPLL1_CTL, 1031 0, LCPLL_PLL_ENABLE); 1032 1033 if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) 1034 drm_err(&dev_priv->drm, "DPLL0 not locked\n"); 1035 1036 dev_priv->cdclk.hw.vco = vco; 1037 1038 /* We'll want to keep using the current vco from now on. */ 1039 skl_set_preferred_cdclk_vco(dev_priv, vco); 1040 } 1041 1042 static void skl_dpll0_disable(struct drm_i915_private *dev_priv) 1043 { 1044 intel_de_rmw(dev_priv, LCPLL1_CTL, 1045 LCPLL_PLL_ENABLE, 0); 1046 1047 if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) 1048 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n"); 1049 1050 dev_priv->cdclk.hw.vco = 0; 1051 } 1052 1053 static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv, 1054 int cdclk, int vco) 1055 { 1056 switch (cdclk) { 1057 default: 1058 drm_WARN_ON(&dev_priv->drm, 1059 cdclk != dev_priv->cdclk.hw.bypass); 1060 drm_WARN_ON(&dev_priv->drm, vco != 0); 1061 fallthrough; 1062 case 308571: 1063 case 337500: 1064 return CDCLK_FREQ_337_308; 1065 case 450000: 1066 case 432000: 1067 return CDCLK_FREQ_450_432; 1068 case 540000: 1069 return CDCLK_FREQ_540; 1070 case 617143: 1071 case 675000: 1072 return CDCLK_FREQ_675_617; 1073 } 1074 } 1075 1076 static void skl_set_cdclk(struct drm_i915_private *dev_priv, 1077 const struct intel_cdclk_config *cdclk_config, 1078 enum pipe pipe) 1079 { 1080 int cdclk = cdclk_config->cdclk; 1081 int vco = cdclk_config->vco; 1082 u32 freq_select, cdclk_ctl; 1083 int ret; 1084 1085 /* 1086 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are 1087 * unsupported on SKL. In theory this should never happen since only 1088 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not 1089 * supported on SKL either, see the above WA. WARN whenever trying to 1090 * use the corresponding VCO freq as that always leads to using the 1091 * minimum 308MHz CDCLK. 1092 */ 1093 drm_WARN_ON_ONCE(&dev_priv->drm, 1094 IS_SKYLAKE(dev_priv) && vco == 8640000); 1095 1096 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, 1097 SKL_CDCLK_PREPARE_FOR_CHANGE, 1098 SKL_CDCLK_READY_FOR_CHANGE, 1099 SKL_CDCLK_READY_FOR_CHANGE, 3); 1100 if (ret) { 1101 drm_err(&dev_priv->drm, 1102 "Failed to inform PCU about cdclk change (%d)\n", ret); 1103 return; 1104 } 1105 1106 freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco); 1107 1108 if (dev_priv->cdclk.hw.vco != 0 && 1109 dev_priv->cdclk.hw.vco != vco) 1110 skl_dpll0_disable(dev_priv); 1111 1112 cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL); 1113 1114 if (dev_priv->cdclk.hw.vco != vco) { 1115 /* Wa Display #1183: skl,kbl,cfl */ 1116 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1117 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1118 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1119 } 1120 1121 /* Wa Display #1183: skl,kbl,cfl */ 1122 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; 1123 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1124 intel_de_posting_read(dev_priv, CDCLK_CTL); 1125 1126 if (dev_priv->cdclk.hw.vco != vco) 1127 skl_dpll0_enable(dev_priv, vco); 1128 1129 /* Wa Display #1183: skl,kbl,cfl */ 1130 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1131 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1132 1133 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1134 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1135 1136 /* Wa Display #1183: skl,kbl,cfl */ 1137 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; 1138 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1139 intel_de_posting_read(dev_priv, CDCLK_CTL); 1140 1141 /* inform PCU of the change */ 1142 snb_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, 1143 cdclk_config->voltage_level); 1144 1145 intel_update_cdclk(dev_priv); 1146 } 1147 1148 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) 1149 { 1150 u32 cdctl, expected; 1151 1152 /* 1153 * check if the pre-os initialized the display 1154 * There is SWF18 scratchpad register defined which is set by the 1155 * pre-os which can be used by the OS drivers to check the status 1156 */ 1157 if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) 1158 goto sanitize; 1159 1160 intel_update_cdclk(dev_priv); 1161 intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "Current CDCLK"); 1162 1163 /* Is PLL enabled and locked ? */ 1164 if (dev_priv->cdclk.hw.vco == 0 || 1165 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) 1166 goto sanitize; 1167 1168 /* DPLL okay; verify the cdclock 1169 * 1170 * Noticed in some instances that the freq selection is correct but 1171 * decimal part is programmed wrong from BIOS where pre-os does not 1172 * enable display. Verify the same as well. 1173 */ 1174 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 1175 expected = (cdctl & CDCLK_FREQ_SEL_MASK) | 1176 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); 1177 if (cdctl == expected) 1178 /* All well; nothing to sanitize */ 1179 return; 1180 1181 sanitize: 1182 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); 1183 1184 /* force cdclk programming */ 1185 dev_priv->cdclk.hw.cdclk = 0; 1186 /* force full PLL disable + enable */ 1187 dev_priv->cdclk.hw.vco = -1; 1188 } 1189 1190 static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv) 1191 { 1192 struct intel_cdclk_config cdclk_config; 1193 1194 skl_sanitize_cdclk(dev_priv); 1195 1196 if (dev_priv->cdclk.hw.cdclk != 0 && 1197 dev_priv->cdclk.hw.vco != 0) { 1198 /* 1199 * Use the current vco as our initial 1200 * guess as to what the preferred vco is. 1201 */ 1202 if (dev_priv->skl_preferred_vco_freq == 0) 1203 skl_set_preferred_cdclk_vco(dev_priv, 1204 dev_priv->cdclk.hw.vco); 1205 return; 1206 } 1207 1208 cdclk_config = dev_priv->cdclk.hw; 1209 1210 cdclk_config.vco = dev_priv->skl_preferred_vco_freq; 1211 if (cdclk_config.vco == 0) 1212 cdclk_config.vco = 8100000; 1213 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); 1214 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1215 1216 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1217 } 1218 1219 static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv) 1220 { 1221 struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw; 1222 1223 cdclk_config.cdclk = cdclk_config.bypass; 1224 cdclk_config.vco = 0; 1225 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1226 1227 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1228 } 1229 1230 static bool has_cdclk_squasher(struct drm_i915_private *i915) 1231 { 1232 return IS_DG2(i915); 1233 } 1234 1235 struct intel_cdclk_vals { 1236 u32 cdclk; 1237 u16 refclk; 1238 u16 waveform; 1239 u8 divider; /* CD2X divider * 2 */ 1240 u8 ratio; 1241 }; 1242 1243 static const struct intel_cdclk_vals bxt_cdclk_table[] = { 1244 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 }, 1245 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 }, 1246 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 }, 1247 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 }, 1248 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 }, 1249 {} 1250 }; 1251 1252 static const struct intel_cdclk_vals glk_cdclk_table[] = { 1253 { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 }, 1254 { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 }, 1255 { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 }, 1256 {} 1257 }; 1258 1259 static const struct intel_cdclk_vals icl_cdclk_table[] = { 1260 { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 }, 1261 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 }, 1262 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 }, 1263 { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 }, 1264 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 }, 1265 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 }, 1266 1267 { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 }, 1268 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 }, 1269 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 }, 1270 { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 }, 1271 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 }, 1272 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 }, 1273 1274 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 }, 1275 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 }, 1276 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 }, 1277 { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 }, 1278 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 }, 1279 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 }, 1280 {} 1281 }; 1282 1283 static const struct intel_cdclk_vals rkl_cdclk_table[] = { 1284 { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 }, 1285 { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 }, 1286 { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 }, 1287 { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 }, 1288 { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 }, 1289 { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 }, 1290 1291 { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 }, 1292 { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 }, 1293 { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 }, 1294 { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 }, 1295 { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 }, 1296 { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 }, 1297 1298 { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 }, 1299 { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 }, 1300 { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 }, 1301 { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 }, 1302 { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 }, 1303 { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 }, 1304 {} 1305 }; 1306 1307 static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = { 1308 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 }, 1309 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 }, 1310 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 }, 1311 1312 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 }, 1313 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 }, 1314 { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 }, 1315 1316 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 }, 1317 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 }, 1318 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 }, 1319 {} 1320 }; 1321 1322 static const struct intel_cdclk_vals adlp_cdclk_table[] = { 1323 { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 }, 1324 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 }, 1325 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 }, 1326 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 }, 1327 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 }, 1328 1329 { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 }, 1330 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 }, 1331 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 }, 1332 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 }, 1333 { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 }, 1334 1335 { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 }, 1336 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 }, 1337 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 }, 1338 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 }, 1339 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 }, 1340 {} 1341 }; 1342 1343 static const struct intel_cdclk_vals dg2_cdclk_table[] = { 1344 { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 }, 1345 { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 }, 1346 { .refclk = 38400, .cdclk = 244800, .divider = 2, .ratio = 34, .waveform = 0xa4a4 }, 1347 { .refclk = 38400, .cdclk = 285600, .divider = 2, .ratio = 34, .waveform = 0xa54a }, 1348 { .refclk = 38400, .cdclk = 326400, .divider = 2, .ratio = 34, .waveform = 0xaaaa }, 1349 { .refclk = 38400, .cdclk = 367200, .divider = 2, .ratio = 34, .waveform = 0xad5a }, 1350 { .refclk = 38400, .cdclk = 408000, .divider = 2, .ratio = 34, .waveform = 0xb6b6 }, 1351 { .refclk = 38400, .cdclk = 448800, .divider = 2, .ratio = 34, .waveform = 0xdbb6 }, 1352 { .refclk = 38400, .cdclk = 489600, .divider = 2, .ratio = 34, .waveform = 0xeeee }, 1353 { .refclk = 38400, .cdclk = 530400, .divider = 2, .ratio = 34, .waveform = 0xf7de }, 1354 { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe }, 1355 { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe }, 1356 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff }, 1357 {} 1358 }; 1359 1360 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) 1361 { 1362 const struct intel_cdclk_vals *table = dev_priv->cdclk.table; 1363 int i; 1364 1365 for (i = 0; table[i].refclk; i++) 1366 if (table[i].refclk == dev_priv->cdclk.hw.ref && 1367 table[i].cdclk >= min_cdclk) 1368 return table[i].cdclk; 1369 1370 drm_WARN(&dev_priv->drm, 1, 1371 "Cannot satisfy minimum cdclk %d with refclk %u\n", 1372 min_cdclk, dev_priv->cdclk.hw.ref); 1373 return 0; 1374 } 1375 1376 static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) 1377 { 1378 const struct intel_cdclk_vals *table = dev_priv->cdclk.table; 1379 int i; 1380 1381 if (cdclk == dev_priv->cdclk.hw.bypass) 1382 return 0; 1383 1384 for (i = 0; table[i].refclk; i++) 1385 if (table[i].refclk == dev_priv->cdclk.hw.ref && 1386 table[i].cdclk == cdclk) 1387 return dev_priv->cdclk.hw.ref * table[i].ratio; 1388 1389 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", 1390 cdclk, dev_priv->cdclk.hw.ref); 1391 return 0; 1392 } 1393 1394 static u8 bxt_calc_voltage_level(int cdclk) 1395 { 1396 return DIV_ROUND_UP(cdclk, 25000); 1397 } 1398 1399 static u8 icl_calc_voltage_level(int cdclk) 1400 { 1401 if (cdclk > 556800) 1402 return 2; 1403 else if (cdclk > 312000) 1404 return 1; 1405 else 1406 return 0; 1407 } 1408 1409 static u8 ehl_calc_voltage_level(int cdclk) 1410 { 1411 if (cdclk > 326400) 1412 return 3; 1413 else if (cdclk > 312000) 1414 return 2; 1415 else if (cdclk > 180000) 1416 return 1; 1417 else 1418 return 0; 1419 } 1420 1421 static u8 tgl_calc_voltage_level(int cdclk) 1422 { 1423 if (cdclk > 556800) 1424 return 3; 1425 else if (cdclk > 326400) 1426 return 2; 1427 else if (cdclk > 312000) 1428 return 1; 1429 else 1430 return 0; 1431 } 1432 1433 static void icl_readout_refclk(struct drm_i915_private *dev_priv, 1434 struct intel_cdclk_config *cdclk_config) 1435 { 1436 u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; 1437 1438 switch (dssm) { 1439 default: 1440 MISSING_CASE(dssm); 1441 fallthrough; 1442 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz: 1443 cdclk_config->ref = 24000; 1444 break; 1445 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz: 1446 cdclk_config->ref = 19200; 1447 break; 1448 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz: 1449 cdclk_config->ref = 38400; 1450 break; 1451 } 1452 } 1453 1454 static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, 1455 struct intel_cdclk_config *cdclk_config) 1456 { 1457 u32 val, ratio; 1458 1459 if (IS_DG2(dev_priv)) 1460 cdclk_config->ref = 38400; 1461 else if (DISPLAY_VER(dev_priv) >= 11) 1462 icl_readout_refclk(dev_priv, cdclk_config); 1463 else 1464 cdclk_config->ref = 19200; 1465 1466 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE); 1467 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || 1468 (val & BXT_DE_PLL_LOCK) == 0) { 1469 /* 1470 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but 1471 * setting it to zero is a way to signal that. 1472 */ 1473 cdclk_config->vco = 0; 1474 return; 1475 } 1476 1477 /* 1478 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register, 1479 * gen9lp had it in a separate PLL control register. 1480 */ 1481 if (DISPLAY_VER(dev_priv) >= 11) 1482 ratio = val & ICL_CDCLK_PLL_RATIO_MASK; 1483 else 1484 ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; 1485 1486 cdclk_config->vco = ratio * cdclk_config->ref; 1487 } 1488 1489 static void bxt_get_cdclk(struct drm_i915_private *dev_priv, 1490 struct intel_cdclk_config *cdclk_config) 1491 { 1492 u32 squash_ctl = 0; 1493 u32 divider; 1494 int div; 1495 1496 bxt_de_pll_readout(dev_priv, cdclk_config); 1497 1498 if (DISPLAY_VER(dev_priv) >= 12) 1499 cdclk_config->bypass = cdclk_config->ref / 2; 1500 else if (DISPLAY_VER(dev_priv) >= 11) 1501 cdclk_config->bypass = 50000; 1502 else 1503 cdclk_config->bypass = cdclk_config->ref; 1504 1505 if (cdclk_config->vco == 0) { 1506 cdclk_config->cdclk = cdclk_config->bypass; 1507 goto out; 1508 } 1509 1510 divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; 1511 1512 switch (divider) { 1513 case BXT_CDCLK_CD2X_DIV_SEL_1: 1514 div = 2; 1515 break; 1516 case BXT_CDCLK_CD2X_DIV_SEL_1_5: 1517 div = 3; 1518 break; 1519 case BXT_CDCLK_CD2X_DIV_SEL_2: 1520 div = 4; 1521 break; 1522 case BXT_CDCLK_CD2X_DIV_SEL_4: 1523 div = 8; 1524 break; 1525 default: 1526 MISSING_CASE(divider); 1527 return; 1528 } 1529 1530 if (has_cdclk_squasher(dev_priv)) 1531 squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL); 1532 1533 if (squash_ctl & CDCLK_SQUASH_ENABLE) { 1534 u16 waveform; 1535 int size; 1536 1537 size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1; 1538 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size); 1539 1540 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * 1541 cdclk_config->vco, size * div); 1542 } else { 1543 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); 1544 } 1545 1546 out: 1547 /* 1548 * Can't read this out :( Let's assume it's 1549 * at least what the CDCLK frequency requires. 1550 */ 1551 cdclk_config->voltage_level = 1552 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk); 1553 } 1554 1555 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) 1556 { 1557 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0); 1558 1559 /* Timeout 200us */ 1560 if (intel_de_wait_for_clear(dev_priv, 1561 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1562 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n"); 1563 1564 dev_priv->cdclk.hw.vco = 0; 1565 } 1566 1567 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) 1568 { 1569 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); 1570 1571 intel_de_rmw(dev_priv, BXT_DE_PLL_CTL, 1572 BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio)); 1573 1574 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); 1575 1576 /* Timeout 200us */ 1577 if (intel_de_wait_for_set(dev_priv, 1578 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1579 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n"); 1580 1581 dev_priv->cdclk.hw.vco = vco; 1582 } 1583 1584 static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv) 1585 { 1586 intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE, 1587 BXT_DE_PLL_PLL_ENABLE, 0); 1588 1589 /* Timeout 200us */ 1590 if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1591 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n"); 1592 1593 dev_priv->cdclk.hw.vco = 0; 1594 } 1595 1596 static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) 1597 { 1598 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); 1599 u32 val; 1600 1601 val = ICL_CDCLK_PLL_RATIO(ratio); 1602 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1603 1604 val |= BXT_DE_PLL_PLL_ENABLE; 1605 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1606 1607 /* Timeout 200us */ 1608 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1609 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n"); 1610 1611 dev_priv->cdclk.hw.vco = vco; 1612 } 1613 1614 static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco) 1615 { 1616 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); 1617 u32 val; 1618 1619 /* Write PLL ratio without disabling */ 1620 val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE; 1621 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1622 1623 /* Submit freq change request */ 1624 val |= BXT_DE_PLL_FREQ_REQ; 1625 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1626 1627 /* Timeout 200us */ 1628 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, 1629 BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1)) 1630 drm_err(&dev_priv->drm, "timeout waiting for FREQ change request ack\n"); 1631 1632 val &= ~BXT_DE_PLL_FREQ_REQ; 1633 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1634 1635 dev_priv->cdclk.hw.vco = vco; 1636 } 1637 1638 static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 1639 { 1640 if (DISPLAY_VER(dev_priv) >= 12) { 1641 if (pipe == INVALID_PIPE) 1642 return TGL_CDCLK_CD2X_PIPE_NONE; 1643 else 1644 return TGL_CDCLK_CD2X_PIPE(pipe); 1645 } else if (DISPLAY_VER(dev_priv) >= 11) { 1646 if (pipe == INVALID_PIPE) 1647 return ICL_CDCLK_CD2X_PIPE_NONE; 1648 else 1649 return ICL_CDCLK_CD2X_PIPE(pipe); 1650 } else { 1651 if (pipe == INVALID_PIPE) 1652 return BXT_CDCLK_CD2X_PIPE_NONE; 1653 else 1654 return BXT_CDCLK_CD2X_PIPE(pipe); 1655 } 1656 } 1657 1658 static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv, 1659 int cdclk, int vco) 1660 { 1661 /* cdclk = vco / 2 / div{1,1.5,2,4} */ 1662 switch (DIV_ROUND_CLOSEST(vco, cdclk)) { 1663 default: 1664 drm_WARN_ON(&dev_priv->drm, 1665 cdclk != dev_priv->cdclk.hw.bypass); 1666 drm_WARN_ON(&dev_priv->drm, vco != 0); 1667 fallthrough; 1668 case 2: 1669 return BXT_CDCLK_CD2X_DIV_SEL_1; 1670 case 3: 1671 return BXT_CDCLK_CD2X_DIV_SEL_1_5; 1672 case 4: 1673 return BXT_CDCLK_CD2X_DIV_SEL_2; 1674 case 8: 1675 return BXT_CDCLK_CD2X_DIV_SEL_4; 1676 } 1677 } 1678 1679 static u32 cdclk_squash_waveform(struct drm_i915_private *dev_priv, 1680 int cdclk) 1681 { 1682 const struct intel_cdclk_vals *table = dev_priv->cdclk.table; 1683 int i; 1684 1685 if (cdclk == dev_priv->cdclk.hw.bypass) 1686 return 0; 1687 1688 for (i = 0; table[i].refclk; i++) 1689 if (table[i].refclk == dev_priv->cdclk.hw.ref && 1690 table[i].cdclk == cdclk) 1691 return table[i].waveform; 1692 1693 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", 1694 cdclk, dev_priv->cdclk.hw.ref); 1695 1696 return 0xffff; 1697 } 1698 1699 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 1700 const struct intel_cdclk_config *cdclk_config, 1701 enum pipe pipe) 1702 { 1703 int cdclk = cdclk_config->cdclk; 1704 int vco = cdclk_config->vco; 1705 u32 val; 1706 u16 waveform; 1707 int clock; 1708 int ret; 1709 1710 /* Inform power controller of upcoming frequency change. */ 1711 if (DISPLAY_VER(dev_priv) >= 11) 1712 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, 1713 SKL_CDCLK_PREPARE_FOR_CHANGE, 1714 SKL_CDCLK_READY_FOR_CHANGE, 1715 SKL_CDCLK_READY_FOR_CHANGE, 3); 1716 else 1717 /* 1718 * BSpec requires us to wait up to 150usec, but that leads to 1719 * timeouts; the 2ms used here is based on experiment. 1720 */ 1721 ret = snb_pcode_write_timeout(dev_priv, 1722 HSW_PCODE_DE_WRITE_FREQ_REQ, 1723 0x80000000, 150, 2); 1724 if (ret) { 1725 drm_err(&dev_priv->drm, 1726 "Failed to inform PCU about cdclk change (err %d, freq %d)\n", 1727 ret, cdclk); 1728 return; 1729 } 1730 1731 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) { 1732 if (dev_priv->cdclk.hw.vco != vco) 1733 adlp_cdclk_pll_crawl(dev_priv, vco); 1734 } else if (DISPLAY_VER(dev_priv) >= 11) { 1735 if (dev_priv->cdclk.hw.vco != 0 && 1736 dev_priv->cdclk.hw.vco != vco) 1737 icl_cdclk_pll_disable(dev_priv); 1738 1739 if (dev_priv->cdclk.hw.vco != vco) 1740 icl_cdclk_pll_enable(dev_priv, vco); 1741 } else { 1742 if (dev_priv->cdclk.hw.vco != 0 && 1743 dev_priv->cdclk.hw.vco != vco) 1744 bxt_de_pll_disable(dev_priv); 1745 1746 if (dev_priv->cdclk.hw.vco != vco) 1747 bxt_de_pll_enable(dev_priv, vco); 1748 } 1749 1750 waveform = cdclk_squash_waveform(dev_priv, cdclk); 1751 1752 if (waveform) 1753 clock = vco / 2; 1754 else 1755 clock = cdclk; 1756 1757 if (has_cdclk_squasher(dev_priv)) { 1758 u32 squash_ctl = 0; 1759 1760 if (waveform) 1761 squash_ctl = CDCLK_SQUASH_ENABLE | 1762 CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; 1763 1764 intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl); 1765 } 1766 1767 val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) | 1768 bxt_cdclk_cd2x_pipe(dev_priv, pipe) | 1769 skl_cdclk_decimal(cdclk); 1770 1771 /* 1772 * Disable SSA Precharge when CD clock frequency < 500 MHz, 1773 * enable otherwise. 1774 */ 1775 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1776 cdclk >= 500000) 1777 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 1778 intel_de_write(dev_priv, CDCLK_CTL, val); 1779 1780 if (pipe != INVALID_PIPE) 1781 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe)); 1782 1783 if (DISPLAY_VER(dev_priv) >= 11) { 1784 ret = snb_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, 1785 cdclk_config->voltage_level); 1786 } else { 1787 /* 1788 * The timeout isn't specified, the 2ms used here is based on 1789 * experiment. 1790 * FIXME: Waiting for the request completion could be delayed 1791 * until the next PCODE request based on BSpec. 1792 */ 1793 ret = snb_pcode_write_timeout(dev_priv, 1794 HSW_PCODE_DE_WRITE_FREQ_REQ, 1795 cdclk_config->voltage_level, 1796 150, 2); 1797 } 1798 1799 if (ret) { 1800 drm_err(&dev_priv->drm, 1801 "PCode CDCLK freq set failed, (err %d, freq %d)\n", 1802 ret, cdclk); 1803 return; 1804 } 1805 1806 intel_update_cdclk(dev_priv); 1807 1808 if (DISPLAY_VER(dev_priv) >= 11) 1809 /* 1810 * Can't read out the voltage level :( 1811 * Let's just assume everything is as expected. 1812 */ 1813 dev_priv->cdclk.hw.voltage_level = cdclk_config->voltage_level; 1814 } 1815 1816 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) 1817 { 1818 u32 cdctl, expected; 1819 int cdclk, clock, vco; 1820 1821 intel_update_cdclk(dev_priv); 1822 intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "Current CDCLK"); 1823 1824 if (dev_priv->cdclk.hw.vco == 0 || 1825 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) 1826 goto sanitize; 1827 1828 /* DPLL okay; verify the cdclock 1829 * 1830 * Some BIOS versions leave an incorrect decimal frequency value and 1831 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, 1832 * so sanitize this register. 1833 */ 1834 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 1835 /* 1836 * Let's ignore the pipe field, since BIOS could have configured the 1837 * dividers both synching to an active pipe, or asynchronously 1838 * (PIPE_NONE). 1839 */ 1840 cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); 1841 1842 /* Make sure this is a legal cdclk value for the platform */ 1843 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk); 1844 if (cdclk != dev_priv->cdclk.hw.cdclk) 1845 goto sanitize; 1846 1847 /* Make sure the VCO is correct for the cdclk */ 1848 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 1849 if (vco != dev_priv->cdclk.hw.vco) 1850 goto sanitize; 1851 1852 expected = skl_cdclk_decimal(cdclk); 1853 1854 /* Figure out what CD2X divider we should be using for this cdclk */ 1855 if (has_cdclk_squasher(dev_priv)) 1856 clock = dev_priv->cdclk.hw.vco / 2; 1857 else 1858 clock = dev_priv->cdclk.hw.cdclk; 1859 1860 expected |= bxt_cdclk_cd2x_div_sel(dev_priv, clock, 1861 dev_priv->cdclk.hw.vco); 1862 1863 /* 1864 * Disable SSA Precharge when CD clock frequency < 500 MHz, 1865 * enable otherwise. 1866 */ 1867 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1868 dev_priv->cdclk.hw.cdclk >= 500000) 1869 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 1870 1871 if (cdctl == expected) 1872 /* All well; nothing to sanitize */ 1873 return; 1874 1875 sanitize: 1876 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); 1877 1878 /* force cdclk programming */ 1879 dev_priv->cdclk.hw.cdclk = 0; 1880 1881 /* force full PLL disable + enable */ 1882 dev_priv->cdclk.hw.vco = -1; 1883 } 1884 1885 static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv) 1886 { 1887 struct intel_cdclk_config cdclk_config; 1888 1889 bxt_sanitize_cdclk(dev_priv); 1890 1891 if (dev_priv->cdclk.hw.cdclk != 0 && 1892 dev_priv->cdclk.hw.vco != 0) 1893 return; 1894 1895 cdclk_config = dev_priv->cdclk.hw; 1896 1897 /* 1898 * FIXME: 1899 * - The initial CDCLK needs to be read from VBT. 1900 * Need to make this change after VBT has changes for BXT. 1901 */ 1902 cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0); 1903 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); 1904 cdclk_config.voltage_level = 1905 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); 1906 1907 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1908 } 1909 1910 static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv) 1911 { 1912 struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw; 1913 1914 cdclk_config.cdclk = cdclk_config.bypass; 1915 cdclk_config.vco = 0; 1916 cdclk_config.voltage_level = 1917 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); 1918 1919 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1920 } 1921 1922 /** 1923 * intel_cdclk_init_hw - Initialize CDCLK hardware 1924 * @i915: i915 device 1925 * 1926 * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and 1927 * sanitizing the state of the hardware if needed. This is generally done only 1928 * during the display core initialization sequence, after which the DMC will 1929 * take care of turning CDCLK off/on as needed. 1930 */ 1931 void intel_cdclk_init_hw(struct drm_i915_private *i915) 1932 { 1933 if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915)) 1934 bxt_cdclk_init_hw(i915); 1935 else if (DISPLAY_VER(i915) == 9) 1936 skl_cdclk_init_hw(i915); 1937 } 1938 1939 /** 1940 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware 1941 * @i915: i915 device 1942 * 1943 * Uninitialize CDCLK. This is done only during the display core 1944 * uninitialization sequence. 1945 */ 1946 void intel_cdclk_uninit_hw(struct drm_i915_private *i915) 1947 { 1948 if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915)) 1949 bxt_cdclk_uninit_hw(i915); 1950 else if (DISPLAY_VER(i915) == 9) 1951 skl_cdclk_uninit_hw(i915); 1952 } 1953 1954 static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, 1955 const struct intel_cdclk_config *a, 1956 const struct intel_cdclk_config *b) 1957 { 1958 int a_div, b_div; 1959 1960 if (!HAS_CDCLK_CRAWL(dev_priv)) 1961 return false; 1962 1963 /* 1964 * The vco and cd2x divider will change independently 1965 * from each, so we disallow cd2x change when crawling. 1966 */ 1967 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); 1968 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); 1969 1970 return a->vco != 0 && b->vco != 0 && 1971 a->vco != b->vco && 1972 a_div == b_div && 1973 a->ref == b->ref; 1974 } 1975 1976 static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, 1977 const struct intel_cdclk_config *a, 1978 const struct intel_cdclk_config *b) 1979 { 1980 /* 1981 * FIXME should store a bit more state in intel_cdclk_config 1982 * to differentiate squasher vs. cd2x divider properly. For 1983 * the moment all platforms with squasher use a fixed cd2x 1984 * divider. 1985 */ 1986 if (!has_cdclk_squasher(dev_priv)) 1987 return false; 1988 1989 return a->cdclk != b->cdclk && 1990 a->vco != 0 && 1991 a->vco == b->vco && 1992 a->ref == b->ref; 1993 } 1994 1995 /** 1996 * intel_cdclk_needs_modeset - Determine if changong between the CDCLK 1997 * configurations requires a modeset on all pipes 1998 * @a: first CDCLK configuration 1999 * @b: second CDCLK configuration 2000 * 2001 * Returns: 2002 * True if changing between the two CDCLK configurations 2003 * requires all pipes to be off, false if not. 2004 */ 2005 bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a, 2006 const struct intel_cdclk_config *b) 2007 { 2008 return a->cdclk != b->cdclk || 2009 a->vco != b->vco || 2010 a->ref != b->ref; 2011 } 2012 2013 /** 2014 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK 2015 * configurations requires only a cd2x divider update 2016 * @dev_priv: i915 device 2017 * @a: first CDCLK configuration 2018 * @b: second CDCLK configuration 2019 * 2020 * Returns: 2021 * True if changing between the two CDCLK configurations 2022 * can be done with just a cd2x divider update, false if not. 2023 */ 2024 static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, 2025 const struct intel_cdclk_config *a, 2026 const struct intel_cdclk_config *b) 2027 { 2028 /* Older hw doesn't have the capability */ 2029 if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv)) 2030 return false; 2031 2032 /* 2033 * FIXME should store a bit more state in intel_cdclk_config 2034 * to differentiate squasher vs. cd2x divider properly. For 2035 * the moment all platforms with squasher use a fixed cd2x 2036 * divider. 2037 */ 2038 if (has_cdclk_squasher(dev_priv)) 2039 return false; 2040 2041 return a->cdclk != b->cdclk && 2042 a->vco != 0 && 2043 a->vco == b->vco && 2044 a->ref == b->ref; 2045 } 2046 2047 /** 2048 * intel_cdclk_changed - Determine if two CDCLK configurations are different 2049 * @a: first CDCLK configuration 2050 * @b: second CDCLK configuration 2051 * 2052 * Returns: 2053 * True if the CDCLK configurations don't match, false if they do. 2054 */ 2055 static bool intel_cdclk_changed(const struct intel_cdclk_config *a, 2056 const struct intel_cdclk_config *b) 2057 { 2058 return intel_cdclk_needs_modeset(a, b) || 2059 a->voltage_level != b->voltage_level; 2060 } 2061 2062 void intel_cdclk_dump_config(struct drm_i915_private *i915, 2063 const struct intel_cdclk_config *cdclk_config, 2064 const char *context) 2065 { 2066 drm_dbg_kms(&i915->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", 2067 context, cdclk_config->cdclk, cdclk_config->vco, 2068 cdclk_config->ref, cdclk_config->bypass, 2069 cdclk_config->voltage_level); 2070 } 2071 2072 /** 2073 * intel_set_cdclk - Push the CDCLK configuration to the hardware 2074 * @dev_priv: i915 device 2075 * @cdclk_config: new CDCLK configuration 2076 * @pipe: pipe with which to synchronize the update 2077 * 2078 * Program the hardware based on the passed in CDCLK state, 2079 * if necessary. 2080 */ 2081 static void intel_set_cdclk(struct drm_i915_private *dev_priv, 2082 const struct intel_cdclk_config *cdclk_config, 2083 enum pipe pipe) 2084 { 2085 struct intel_encoder *encoder; 2086 2087 if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config)) 2088 return; 2089 2090 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->cdclk_funcs->set_cdclk)) 2091 return; 2092 2093 intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to"); 2094 2095 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2096 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2097 2098 intel_psr_pause(intel_dp); 2099 } 2100 2101 intel_audio_cdclk_change_pre(dev_priv); 2102 2103 /* 2104 * Lock aux/gmbus while we change cdclk in case those 2105 * functions use cdclk. Not all platforms/ports do, 2106 * but we'll lock them all for simplicity. 2107 */ 2108 mutex_lock(&dev_priv->gmbus_mutex); 2109 for_each_intel_dp(&dev_priv->drm, encoder) { 2110 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2111 2112 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, 2113 &dev_priv->gmbus_mutex); 2114 } 2115 2116 intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe); 2117 2118 for_each_intel_dp(&dev_priv->drm, encoder) { 2119 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2120 2121 mutex_unlock(&intel_dp->aux.hw_mutex); 2122 } 2123 mutex_unlock(&dev_priv->gmbus_mutex); 2124 2125 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2126 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2127 2128 intel_psr_resume(intel_dp); 2129 } 2130 2131 intel_audio_cdclk_change_post(dev_priv); 2132 2133 if (drm_WARN(&dev_priv->drm, 2134 intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config), 2135 "cdclk state doesn't match!\n")) { 2136 intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "[hw state]"); 2137 intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]"); 2138 } 2139 } 2140 2141 /** 2142 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware 2143 * @state: intel atomic state 2144 * 2145 * Program the hardware before updating the HW plane state based on the 2146 * new CDCLK state, if necessary. 2147 */ 2148 void 2149 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) 2150 { 2151 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2152 const struct intel_cdclk_state *old_cdclk_state = 2153 intel_atomic_get_old_cdclk_state(state); 2154 const struct intel_cdclk_state *new_cdclk_state = 2155 intel_atomic_get_new_cdclk_state(state); 2156 enum pipe pipe = new_cdclk_state->pipe; 2157 2158 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2159 &new_cdclk_state->actual)) 2160 return; 2161 2162 if (pipe == INVALID_PIPE || 2163 old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) { 2164 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); 2165 2166 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); 2167 } 2168 } 2169 2170 /** 2171 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware 2172 * @state: intel atomic state 2173 * 2174 * Program the hardware after updating the HW plane state based on the 2175 * new CDCLK state, if necessary. 2176 */ 2177 void 2178 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) 2179 { 2180 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2181 const struct intel_cdclk_state *old_cdclk_state = 2182 intel_atomic_get_old_cdclk_state(state); 2183 const struct intel_cdclk_state *new_cdclk_state = 2184 intel_atomic_get_new_cdclk_state(state); 2185 enum pipe pipe = new_cdclk_state->pipe; 2186 2187 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2188 &new_cdclk_state->actual)) 2189 return; 2190 2191 if (pipe != INVALID_PIPE && 2192 old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) { 2193 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); 2194 2195 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); 2196 } 2197 } 2198 2199 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) 2200 { 2201 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2202 int pixel_rate = crtc_state->pixel_rate; 2203 2204 if (DISPLAY_VER(dev_priv) >= 10) 2205 return DIV_ROUND_UP(pixel_rate, 2); 2206 else if (DISPLAY_VER(dev_priv) == 9 || 2207 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2208 return pixel_rate; 2209 else if (IS_CHERRYVIEW(dev_priv)) 2210 return DIV_ROUND_UP(pixel_rate * 100, 95); 2211 else if (crtc_state->double_wide) 2212 return DIV_ROUND_UP(pixel_rate * 100, 90 * 2); 2213 else 2214 return DIV_ROUND_UP(pixel_rate * 100, 90); 2215 } 2216 2217 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) 2218 { 2219 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2220 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2221 struct intel_plane *plane; 2222 int min_cdclk = 0; 2223 2224 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 2225 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk); 2226 2227 return min_cdclk; 2228 } 2229 2230 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) 2231 { 2232 struct drm_i915_private *dev_priv = 2233 to_i915(crtc_state->uapi.crtc->dev); 2234 int min_cdclk; 2235 2236 if (!crtc_state->hw.enable) 2237 return 0; 2238 2239 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state); 2240 2241 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ 2242 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state)) 2243 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95); 2244 2245 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, 2246 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else 2247 * there may be audio corruption or screen corruption." This cdclk 2248 * restriction for GLK is 316.8 MHz. 2249 */ 2250 if (intel_crtc_has_dp_encoder(crtc_state) && 2251 crtc_state->has_audio && 2252 crtc_state->port_clock >= 540000 && 2253 crtc_state->lane_count == 4) { 2254 if (DISPLAY_VER(dev_priv) == 10) { 2255 /* Display WA #1145: glk */ 2256 min_cdclk = max(316800, min_cdclk); 2257 } else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) { 2258 /* Display WA #1144: skl,bxt */ 2259 min_cdclk = max(432000, min_cdclk); 2260 } 2261 } 2262 2263 /* 2264 * According to BSpec, "The CD clock frequency must be at least twice 2265 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. 2266 */ 2267 if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9) 2268 min_cdclk = max(2 * 96000, min_cdclk); 2269 2270 /* 2271 * "For DP audio configuration, cdclk frequency shall be set to 2272 * meet the following requirements: 2273 * DP Link Frequency(MHz) | Cdclk frequency(MHz) 2274 * 270 | 320 or higher 2275 * 162 | 200 or higher" 2276 */ 2277 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2278 intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio) 2279 min_cdclk = max(crtc_state->port_clock, min_cdclk); 2280 2281 /* 2282 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower 2283 * than 320000KHz. 2284 */ 2285 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 2286 IS_VALLEYVIEW(dev_priv)) 2287 min_cdclk = max(320000, min_cdclk); 2288 2289 /* 2290 * On Geminilake once the CDCLK gets as low as 79200 2291 * picture gets unstable, despite that values are 2292 * correct for DSI PLL and DE PLL. 2293 */ 2294 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 2295 IS_GEMINILAKE(dev_priv)) 2296 min_cdclk = max(158400, min_cdclk); 2297 2298 /* Account for additional needs from the planes */ 2299 min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); 2300 2301 /* 2302 * When we decide to use only one VDSC engine, since 2303 * each VDSC operates with 1 ppc throughput, pixel clock 2304 * cannot be higher than the VDSC clock (cdclk) 2305 */ 2306 if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split) 2307 min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); 2308 2309 /* 2310 * HACK. Currently for TGL platforms we calculate 2311 * min_cdclk initially based on pixel_rate divided 2312 * by 2, accounting for also plane requirements, 2313 * however in some cases the lowest possible CDCLK 2314 * doesn't work and causing the underruns. 2315 * Explicitly stating here that this seems to be currently 2316 * rather a Hack, than final solution. 2317 */ 2318 if (IS_TIGERLAKE(dev_priv)) { 2319 /* 2320 * Clamp to max_cdclk_freq in case pixel rate is higher, 2321 * in order not to break an 8K, but still leave W/A at place. 2322 */ 2323 min_cdclk = max_t(int, min_cdclk, 2324 min_t(int, crtc_state->pixel_rate, 2325 dev_priv->max_cdclk_freq)); 2326 } 2327 2328 if (min_cdclk > dev_priv->max_cdclk_freq) { 2329 drm_dbg_kms(&dev_priv->drm, 2330 "required cdclk (%d kHz) exceeds max (%d kHz)\n", 2331 min_cdclk, dev_priv->max_cdclk_freq); 2332 return -EINVAL; 2333 } 2334 2335 return min_cdclk; 2336 } 2337 2338 static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) 2339 { 2340 struct intel_atomic_state *state = cdclk_state->base.state; 2341 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2342 struct intel_bw_state *bw_state = NULL; 2343 struct intel_crtc *crtc; 2344 struct intel_crtc_state *crtc_state; 2345 int min_cdclk, i; 2346 enum pipe pipe; 2347 2348 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2349 int ret; 2350 2351 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 2352 if (min_cdclk < 0) 2353 return min_cdclk; 2354 2355 bw_state = intel_atomic_get_bw_state(state); 2356 if (IS_ERR(bw_state)) 2357 return PTR_ERR(bw_state); 2358 2359 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk) 2360 continue; 2361 2362 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 2363 2364 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2365 if (ret) 2366 return ret; 2367 } 2368 2369 min_cdclk = cdclk_state->force_min_cdclk; 2370 for_each_pipe(dev_priv, pipe) { 2371 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); 2372 2373 if (!bw_state) 2374 continue; 2375 2376 min_cdclk = max(bw_state->min_cdclk, min_cdclk); 2377 } 2378 2379 return min_cdclk; 2380 } 2381 2382 /* 2383 * Account for port clock min voltage level requirements. 2384 * This only really does something on DISPLA_VER >= 11 but can be 2385 * called on earlier platforms as well. 2386 * 2387 * Note that this functions assumes that 0 is 2388 * the lowest voltage value, and higher values 2389 * correspond to increasingly higher voltages. 2390 * 2391 * Should that relationship no longer hold on 2392 * future platforms this code will need to be 2393 * adjusted. 2394 */ 2395 static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state) 2396 { 2397 struct intel_atomic_state *state = cdclk_state->base.state; 2398 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2399 struct intel_crtc *crtc; 2400 struct intel_crtc_state *crtc_state; 2401 u8 min_voltage_level; 2402 int i; 2403 enum pipe pipe; 2404 2405 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2406 int ret; 2407 2408 if (crtc_state->hw.enable) 2409 min_voltage_level = crtc_state->min_voltage_level; 2410 else 2411 min_voltage_level = 0; 2412 2413 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level) 2414 continue; 2415 2416 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level; 2417 2418 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2419 if (ret) 2420 return ret; 2421 } 2422 2423 min_voltage_level = 0; 2424 for_each_pipe(dev_priv, pipe) 2425 min_voltage_level = max(cdclk_state->min_voltage_level[pipe], 2426 min_voltage_level); 2427 2428 return min_voltage_level; 2429 } 2430 2431 static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2432 { 2433 struct intel_atomic_state *state = cdclk_state->base.state; 2434 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2435 int min_cdclk, cdclk; 2436 2437 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2438 if (min_cdclk < 0) 2439 return min_cdclk; 2440 2441 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); 2442 2443 cdclk_state->logical.cdclk = cdclk; 2444 cdclk_state->logical.voltage_level = 2445 vlv_calc_voltage_level(dev_priv, cdclk); 2446 2447 if (!cdclk_state->active_pipes) { 2448 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); 2449 2450 cdclk_state->actual.cdclk = cdclk; 2451 cdclk_state->actual.voltage_level = 2452 vlv_calc_voltage_level(dev_priv, cdclk); 2453 } else { 2454 cdclk_state->actual = cdclk_state->logical; 2455 } 2456 2457 return 0; 2458 } 2459 2460 static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2461 { 2462 int min_cdclk, cdclk; 2463 2464 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2465 if (min_cdclk < 0) 2466 return min_cdclk; 2467 2468 /* 2469 * FIXME should also account for plane ratio 2470 * once 64bpp pixel formats are supported. 2471 */ 2472 cdclk = bdw_calc_cdclk(min_cdclk); 2473 2474 cdclk_state->logical.cdclk = cdclk; 2475 cdclk_state->logical.voltage_level = 2476 bdw_calc_voltage_level(cdclk); 2477 2478 if (!cdclk_state->active_pipes) { 2479 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); 2480 2481 cdclk_state->actual.cdclk = cdclk; 2482 cdclk_state->actual.voltage_level = 2483 bdw_calc_voltage_level(cdclk); 2484 } else { 2485 cdclk_state->actual = cdclk_state->logical; 2486 } 2487 2488 return 0; 2489 } 2490 2491 static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state) 2492 { 2493 struct intel_atomic_state *state = cdclk_state->base.state; 2494 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2495 struct intel_crtc *crtc; 2496 struct intel_crtc_state *crtc_state; 2497 int vco, i; 2498 2499 vco = cdclk_state->logical.vco; 2500 if (!vco) 2501 vco = dev_priv->skl_preferred_vco_freq; 2502 2503 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2504 if (!crtc_state->hw.enable) 2505 continue; 2506 2507 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 2508 continue; 2509 2510 /* 2511 * DPLL0 VCO may need to be adjusted to get the correct 2512 * clock for eDP. This will affect cdclk as well. 2513 */ 2514 switch (crtc_state->port_clock / 2) { 2515 case 108000: 2516 case 216000: 2517 vco = 8640000; 2518 break; 2519 default: 2520 vco = 8100000; 2521 break; 2522 } 2523 } 2524 2525 return vco; 2526 } 2527 2528 static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2529 { 2530 int min_cdclk, cdclk, vco; 2531 2532 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2533 if (min_cdclk < 0) 2534 return min_cdclk; 2535 2536 vco = skl_dpll0_vco(cdclk_state); 2537 2538 /* 2539 * FIXME should also account for plane ratio 2540 * once 64bpp pixel formats are supported. 2541 */ 2542 cdclk = skl_calc_cdclk(min_cdclk, vco); 2543 2544 cdclk_state->logical.vco = vco; 2545 cdclk_state->logical.cdclk = cdclk; 2546 cdclk_state->logical.voltage_level = 2547 skl_calc_voltage_level(cdclk); 2548 2549 if (!cdclk_state->active_pipes) { 2550 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); 2551 2552 cdclk_state->actual.vco = vco; 2553 cdclk_state->actual.cdclk = cdclk; 2554 cdclk_state->actual.voltage_level = 2555 skl_calc_voltage_level(cdclk); 2556 } else { 2557 cdclk_state->actual = cdclk_state->logical; 2558 } 2559 2560 return 0; 2561 } 2562 2563 static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2564 { 2565 struct intel_atomic_state *state = cdclk_state->base.state; 2566 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2567 int min_cdclk, min_voltage_level, cdclk, vco; 2568 2569 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2570 if (min_cdclk < 0) 2571 return min_cdclk; 2572 2573 min_voltage_level = bxt_compute_min_voltage_level(cdclk_state); 2574 if (min_voltage_level < 0) 2575 return min_voltage_level; 2576 2577 cdclk = bxt_calc_cdclk(dev_priv, min_cdclk); 2578 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 2579 2580 cdclk_state->logical.vco = vco; 2581 cdclk_state->logical.cdclk = cdclk; 2582 cdclk_state->logical.voltage_level = 2583 max_t(int, min_voltage_level, 2584 intel_cdclk_calc_voltage_level(dev_priv, cdclk)); 2585 2586 if (!cdclk_state->active_pipes) { 2587 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); 2588 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 2589 2590 cdclk_state->actual.vco = vco; 2591 cdclk_state->actual.cdclk = cdclk; 2592 cdclk_state->actual.voltage_level = 2593 intel_cdclk_calc_voltage_level(dev_priv, cdclk); 2594 } else { 2595 cdclk_state->actual = cdclk_state->logical; 2596 } 2597 2598 return 0; 2599 } 2600 2601 static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2602 { 2603 int min_cdclk; 2604 2605 /* 2606 * We can't change the cdclk frequency, but we still want to 2607 * check that the required minimum frequency doesn't exceed 2608 * the actual cdclk frequency. 2609 */ 2610 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2611 if (min_cdclk < 0) 2612 return min_cdclk; 2613 2614 return 0; 2615 } 2616 2617 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj) 2618 { 2619 struct intel_cdclk_state *cdclk_state; 2620 2621 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); 2622 if (!cdclk_state) 2623 return NULL; 2624 2625 cdclk_state->pipe = INVALID_PIPE; 2626 2627 return &cdclk_state->base; 2628 } 2629 2630 static void intel_cdclk_destroy_state(struct intel_global_obj *obj, 2631 struct intel_global_state *state) 2632 { 2633 kfree(state); 2634 } 2635 2636 static const struct intel_global_state_funcs intel_cdclk_funcs = { 2637 .atomic_duplicate_state = intel_cdclk_duplicate_state, 2638 .atomic_destroy_state = intel_cdclk_destroy_state, 2639 }; 2640 2641 struct intel_cdclk_state * 2642 intel_atomic_get_cdclk_state(struct intel_atomic_state *state) 2643 { 2644 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2645 struct intel_global_state *cdclk_state; 2646 2647 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->cdclk.obj); 2648 if (IS_ERR(cdclk_state)) 2649 return ERR_CAST(cdclk_state); 2650 2651 return to_intel_cdclk_state(cdclk_state); 2652 } 2653 2654 int intel_cdclk_atomic_check(struct intel_atomic_state *state, 2655 bool *need_cdclk_calc) 2656 { 2657 struct drm_i915_private *i915 = to_i915(state->base.dev); 2658 const struct intel_cdclk_state *old_cdclk_state; 2659 const struct intel_cdclk_state *new_cdclk_state; 2660 struct intel_plane_state *plane_state; 2661 struct intel_bw_state *new_bw_state; 2662 struct intel_plane *plane; 2663 int min_cdclk = 0; 2664 enum pipe pipe; 2665 int ret; 2666 int i; 2667 2668 /* 2669 * active_planes bitmask has been updated, and potentially affected 2670 * planes are part of the state. We can now compute the minimum cdclk 2671 * for each plane. 2672 */ 2673 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 2674 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc); 2675 if (ret) 2676 return ret; 2677 } 2678 2679 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 2680 new_cdclk_state = intel_atomic_get_new_cdclk_state(state); 2681 2682 if (new_cdclk_state && 2683 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) 2684 *need_cdclk_calc = true; 2685 2686 ret = intel_cdclk_bw_calc_min_cdclk(state); 2687 if (ret) 2688 return ret; 2689 2690 new_bw_state = intel_atomic_get_new_bw_state(state); 2691 2692 if (!new_cdclk_state || !new_bw_state) 2693 return 0; 2694 2695 for_each_pipe(i915, pipe) { 2696 min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk); 2697 2698 /* Currently do this change only if we need to increase */ 2699 if (new_bw_state->min_cdclk > min_cdclk) 2700 *need_cdclk_calc = true; 2701 } 2702 2703 return 0; 2704 } 2705 2706 int intel_cdclk_init(struct drm_i915_private *dev_priv) 2707 { 2708 struct intel_cdclk_state *cdclk_state; 2709 2710 cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL); 2711 if (!cdclk_state) 2712 return -ENOMEM; 2713 2714 intel_atomic_global_obj_init(dev_priv, &dev_priv->cdclk.obj, 2715 &cdclk_state->base, &intel_cdclk_funcs); 2716 2717 return 0; 2718 } 2719 2720 int intel_modeset_calc_cdclk(struct intel_atomic_state *state) 2721 { 2722 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2723 const struct intel_cdclk_state *old_cdclk_state; 2724 struct intel_cdclk_state *new_cdclk_state; 2725 enum pipe pipe = INVALID_PIPE; 2726 int ret; 2727 2728 new_cdclk_state = intel_atomic_get_cdclk_state(state); 2729 if (IS_ERR(new_cdclk_state)) 2730 return PTR_ERR(new_cdclk_state); 2731 2732 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 2733 2734 new_cdclk_state->active_pipes = 2735 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); 2736 2737 ret = intel_cdclk_modeset_calc_cdclk(dev_priv, new_cdclk_state); 2738 if (ret) 2739 return ret; 2740 2741 if (intel_cdclk_changed(&old_cdclk_state->actual, 2742 &new_cdclk_state->actual)) { 2743 /* 2744 * Also serialize commits across all crtcs 2745 * if the actual hw needs to be poked. 2746 */ 2747 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); 2748 if (ret) 2749 return ret; 2750 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes || 2751 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk || 2752 intel_cdclk_changed(&old_cdclk_state->logical, 2753 &new_cdclk_state->logical)) { 2754 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 2755 if (ret) 2756 return ret; 2757 } else { 2758 return 0; 2759 } 2760 2761 if (is_power_of_2(new_cdclk_state->active_pipes) && 2762 intel_cdclk_can_cd2x_update(dev_priv, 2763 &old_cdclk_state->actual, 2764 &new_cdclk_state->actual)) { 2765 struct intel_crtc *crtc; 2766 struct intel_crtc_state *crtc_state; 2767 2768 pipe = ilog2(new_cdclk_state->active_pipes); 2769 crtc = intel_crtc_for_pipe(dev_priv, pipe); 2770 2771 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 2772 if (IS_ERR(crtc_state)) 2773 return PTR_ERR(crtc_state); 2774 2775 if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) 2776 pipe = INVALID_PIPE; 2777 } 2778 2779 if (intel_cdclk_can_squash(dev_priv, 2780 &old_cdclk_state->actual, 2781 &new_cdclk_state->actual)) { 2782 drm_dbg_kms(&dev_priv->drm, 2783 "Can change cdclk via squasher\n"); 2784 } else if (intel_cdclk_can_crawl(dev_priv, 2785 &old_cdclk_state->actual, 2786 &new_cdclk_state->actual)) { 2787 drm_dbg_kms(&dev_priv->drm, 2788 "Can change cdclk via crawl\n"); 2789 } else if (pipe != INVALID_PIPE) { 2790 new_cdclk_state->pipe = pipe; 2791 2792 drm_dbg_kms(&dev_priv->drm, 2793 "Can change cdclk cd2x divider with pipe %c active\n", 2794 pipe_name(pipe)); 2795 } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual, 2796 &new_cdclk_state->actual)) { 2797 /* All pipes must be switched off while we change the cdclk. */ 2798 ret = intel_modeset_all_pipes(state); 2799 if (ret) 2800 return ret; 2801 2802 drm_dbg_kms(&dev_priv->drm, 2803 "Modeset required for cdclk change\n"); 2804 } 2805 2806 drm_dbg_kms(&dev_priv->drm, 2807 "New cdclk calculated to be logical %u kHz, actual %u kHz\n", 2808 new_cdclk_state->logical.cdclk, 2809 new_cdclk_state->actual.cdclk); 2810 drm_dbg_kms(&dev_priv->drm, 2811 "New voltage level calculated to be logical %u, actual %u\n", 2812 new_cdclk_state->logical.voltage_level, 2813 new_cdclk_state->actual.voltage_level); 2814 2815 return 0; 2816 } 2817 2818 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) 2819 { 2820 int max_cdclk_freq = dev_priv->max_cdclk_freq; 2821 2822 if (DISPLAY_VER(dev_priv) >= 10) 2823 return 2 * max_cdclk_freq; 2824 else if (DISPLAY_VER(dev_priv) == 9 || 2825 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2826 return max_cdclk_freq; 2827 else if (IS_CHERRYVIEW(dev_priv)) 2828 return max_cdclk_freq*95/100; 2829 else if (DISPLAY_VER(dev_priv) < 4) 2830 return 2*max_cdclk_freq*90/100; 2831 else 2832 return max_cdclk_freq*90/100; 2833 } 2834 2835 /** 2836 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency 2837 * @dev_priv: i915 device 2838 * 2839 * Determine the maximum CDCLK frequency the platform supports, and also 2840 * derive the maximum dot clock frequency the maximum CDCLK frequency 2841 * allows. 2842 */ 2843 void intel_update_max_cdclk(struct drm_i915_private *dev_priv) 2844 { 2845 if (IS_JSL_EHL(dev_priv)) { 2846 if (dev_priv->cdclk.hw.ref == 24000) 2847 dev_priv->max_cdclk_freq = 552000; 2848 else 2849 dev_priv->max_cdclk_freq = 556800; 2850 } else if (DISPLAY_VER(dev_priv) >= 11) { 2851 if (dev_priv->cdclk.hw.ref == 24000) 2852 dev_priv->max_cdclk_freq = 648000; 2853 else 2854 dev_priv->max_cdclk_freq = 652800; 2855 } else if (IS_GEMINILAKE(dev_priv)) { 2856 dev_priv->max_cdclk_freq = 316800; 2857 } else if (IS_BROXTON(dev_priv)) { 2858 dev_priv->max_cdclk_freq = 624000; 2859 } else if (DISPLAY_VER(dev_priv) == 9) { 2860 u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; 2861 int max_cdclk, vco; 2862 2863 vco = dev_priv->skl_preferred_vco_freq; 2864 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); 2865 2866 /* 2867 * Use the lower (vco 8640) cdclk values as a 2868 * first guess. skl_calc_cdclk() will correct it 2869 * if the preferred vco is 8100 instead. 2870 */ 2871 if (limit == SKL_DFSM_CDCLK_LIMIT_675) 2872 max_cdclk = 617143; 2873 else if (limit == SKL_DFSM_CDCLK_LIMIT_540) 2874 max_cdclk = 540000; 2875 else if (limit == SKL_DFSM_CDCLK_LIMIT_450) 2876 max_cdclk = 432000; 2877 else 2878 max_cdclk = 308571; 2879 2880 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); 2881 } else if (IS_BROADWELL(dev_priv)) { 2882 /* 2883 * FIXME with extra cooling we can allow 2884 * 540 MHz for ULX and 675 Mhz for ULT. 2885 * How can we know if extra cooling is 2886 * available? PCI ID, VTB, something else? 2887 */ 2888 if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 2889 dev_priv->max_cdclk_freq = 450000; 2890 else if (IS_BDW_ULX(dev_priv)) 2891 dev_priv->max_cdclk_freq = 450000; 2892 else if (IS_BDW_ULT(dev_priv)) 2893 dev_priv->max_cdclk_freq = 540000; 2894 else 2895 dev_priv->max_cdclk_freq = 675000; 2896 } else if (IS_CHERRYVIEW(dev_priv)) { 2897 dev_priv->max_cdclk_freq = 320000; 2898 } else if (IS_VALLEYVIEW(dev_priv)) { 2899 dev_priv->max_cdclk_freq = 400000; 2900 } else { 2901 /* otherwise assume cdclk is fixed */ 2902 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk; 2903 } 2904 2905 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); 2906 2907 drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n", 2908 dev_priv->max_cdclk_freq); 2909 2910 drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n", 2911 dev_priv->max_dotclk_freq); 2912 } 2913 2914 /** 2915 * intel_update_cdclk - Determine the current CDCLK frequency 2916 * @dev_priv: i915 device 2917 * 2918 * Determine the current CDCLK frequency. 2919 */ 2920 void intel_update_cdclk(struct drm_i915_private *dev_priv) 2921 { 2922 intel_cdclk_get_cdclk(dev_priv, &dev_priv->cdclk.hw); 2923 2924 /* 2925 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): 2926 * Programmng [sic] note: bit[9:2] should be programmed to the number 2927 * of cdclk that generates 4MHz reference clock freq which is used to 2928 * generate GMBus clock. This will vary with the cdclk freq. 2929 */ 2930 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 2931 intel_de_write(dev_priv, GMBUSFREQ_VLV, 2932 DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000)); 2933 } 2934 2935 static int dg1_rawclk(struct drm_i915_private *dev_priv) 2936 { 2937 /* 2938 * DG1 always uses a 38.4 MHz rawclk. The bspec tells us 2939 * "Program Numerator=2, Denominator=4, Divider=37 decimal." 2940 */ 2941 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, 2942 CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2)); 2943 2944 return 38400; 2945 } 2946 2947 static int cnp_rawclk(struct drm_i915_private *dev_priv) 2948 { 2949 u32 rawclk; 2950 int divider, fraction; 2951 2952 if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { 2953 /* 24 MHz */ 2954 divider = 24000; 2955 fraction = 0; 2956 } else { 2957 /* 19.2 MHz */ 2958 divider = 19000; 2959 fraction = 200; 2960 } 2961 2962 rawclk = CNP_RAWCLK_DIV(divider / 1000); 2963 if (fraction) { 2964 int numerator = 1; 2965 2966 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000, 2967 fraction) - 1); 2968 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 2969 rawclk |= ICP_RAWCLK_NUM(numerator); 2970 } 2971 2972 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk); 2973 return divider + fraction; 2974 } 2975 2976 static int pch_rawclk(struct drm_i915_private *dev_priv) 2977 { 2978 return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; 2979 } 2980 2981 static int vlv_hrawclk(struct drm_i915_private *dev_priv) 2982 { 2983 /* RAWCLK_FREQ_VLV register updated from power well code */ 2984 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", 2985 CCK_DISPLAY_REF_CLOCK_CONTROL); 2986 } 2987 2988 static int i9xx_hrawclk(struct drm_i915_private *dev_priv) 2989 { 2990 u32 clkcfg; 2991 2992 /* 2993 * hrawclock is 1/4 the FSB frequency 2994 * 2995 * Note that this only reads the state of the FSB 2996 * straps, not the actual FSB frequency. Some BIOSen 2997 * let you configure each independently. Ideally we'd 2998 * read out the actual FSB frequency but sadly we 2999 * don't know which registers have that information, 3000 * and all the relevant docs have gone to bit heaven :( 3001 */ 3002 clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK; 3003 3004 if (IS_MOBILE(dev_priv)) { 3005 switch (clkcfg) { 3006 case CLKCFG_FSB_400: 3007 return 100000; 3008 case CLKCFG_FSB_533: 3009 return 133333; 3010 case CLKCFG_FSB_667: 3011 return 166667; 3012 case CLKCFG_FSB_800: 3013 return 200000; 3014 case CLKCFG_FSB_1067: 3015 return 266667; 3016 case CLKCFG_FSB_1333: 3017 return 333333; 3018 default: 3019 MISSING_CASE(clkcfg); 3020 return 133333; 3021 } 3022 } else { 3023 switch (clkcfg) { 3024 case CLKCFG_FSB_400_ALT: 3025 return 100000; 3026 case CLKCFG_FSB_533: 3027 return 133333; 3028 case CLKCFG_FSB_667: 3029 return 166667; 3030 case CLKCFG_FSB_800: 3031 return 200000; 3032 case CLKCFG_FSB_1067_ALT: 3033 return 266667; 3034 case CLKCFG_FSB_1333_ALT: 3035 return 333333; 3036 case CLKCFG_FSB_1600_ALT: 3037 return 400000; 3038 default: 3039 return 133333; 3040 } 3041 } 3042 } 3043 3044 /** 3045 * intel_read_rawclk - Determine the current RAWCLK frequency 3046 * @dev_priv: i915 device 3047 * 3048 * Determine the current RAWCLK frequency. RAWCLK is a fixed 3049 * frequency clock so this needs to done only once. 3050 */ 3051 u32 intel_read_rawclk(struct drm_i915_private *dev_priv) 3052 { 3053 u32 freq; 3054 3055 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 3056 freq = dg1_rawclk(dev_priv); 3057 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) 3058 freq = cnp_rawclk(dev_priv); 3059 else if (HAS_PCH_SPLIT(dev_priv)) 3060 freq = pch_rawclk(dev_priv); 3061 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 3062 freq = vlv_hrawclk(dev_priv); 3063 else if (DISPLAY_VER(dev_priv) >= 3) 3064 freq = i9xx_hrawclk(dev_priv); 3065 else 3066 /* no rawclk on other platforms, or no need to know it */ 3067 return 0; 3068 3069 return freq; 3070 } 3071 3072 static const struct intel_cdclk_funcs tgl_cdclk_funcs = { 3073 .get_cdclk = bxt_get_cdclk, 3074 .set_cdclk = bxt_set_cdclk, 3075 .bw_calc_min_cdclk = skl_bw_calc_min_cdclk, 3076 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3077 .calc_voltage_level = tgl_calc_voltage_level, 3078 }; 3079 3080 static const struct intel_cdclk_funcs ehl_cdclk_funcs = { 3081 .get_cdclk = bxt_get_cdclk, 3082 .set_cdclk = bxt_set_cdclk, 3083 .bw_calc_min_cdclk = skl_bw_calc_min_cdclk, 3084 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3085 .calc_voltage_level = ehl_calc_voltage_level, 3086 }; 3087 3088 static const struct intel_cdclk_funcs icl_cdclk_funcs = { 3089 .get_cdclk = bxt_get_cdclk, 3090 .set_cdclk = bxt_set_cdclk, 3091 .bw_calc_min_cdclk = skl_bw_calc_min_cdclk, 3092 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3093 .calc_voltage_level = icl_calc_voltage_level, 3094 }; 3095 3096 static const struct intel_cdclk_funcs bxt_cdclk_funcs = { 3097 .get_cdclk = bxt_get_cdclk, 3098 .set_cdclk = bxt_set_cdclk, 3099 .bw_calc_min_cdclk = skl_bw_calc_min_cdclk, 3100 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3101 .calc_voltage_level = bxt_calc_voltage_level, 3102 }; 3103 3104 static const struct intel_cdclk_funcs skl_cdclk_funcs = { 3105 .get_cdclk = skl_get_cdclk, 3106 .set_cdclk = skl_set_cdclk, 3107 .bw_calc_min_cdclk = skl_bw_calc_min_cdclk, 3108 .modeset_calc_cdclk = skl_modeset_calc_cdclk, 3109 }; 3110 3111 static const struct intel_cdclk_funcs bdw_cdclk_funcs = { 3112 .get_cdclk = bdw_get_cdclk, 3113 .set_cdclk = bdw_set_cdclk, 3114 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3115 .modeset_calc_cdclk = bdw_modeset_calc_cdclk, 3116 }; 3117 3118 static const struct intel_cdclk_funcs chv_cdclk_funcs = { 3119 .get_cdclk = vlv_get_cdclk, 3120 .set_cdclk = chv_set_cdclk, 3121 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3122 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3123 }; 3124 3125 static const struct intel_cdclk_funcs vlv_cdclk_funcs = { 3126 .get_cdclk = vlv_get_cdclk, 3127 .set_cdclk = vlv_set_cdclk, 3128 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3129 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3130 }; 3131 3132 static const struct intel_cdclk_funcs hsw_cdclk_funcs = { 3133 .get_cdclk = hsw_get_cdclk, 3134 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3135 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3136 }; 3137 3138 /* SNB, IVB, 965G, 945G */ 3139 static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = { 3140 .get_cdclk = fixed_400mhz_get_cdclk, 3141 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3142 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3143 }; 3144 3145 static const struct intel_cdclk_funcs ilk_cdclk_funcs = { 3146 .get_cdclk = fixed_450mhz_get_cdclk, 3147 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3148 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3149 }; 3150 3151 static const struct intel_cdclk_funcs gm45_cdclk_funcs = { 3152 .get_cdclk = gm45_get_cdclk, 3153 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3154 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3155 }; 3156 3157 /* G45 uses G33 */ 3158 3159 static const struct intel_cdclk_funcs i965gm_cdclk_funcs = { 3160 .get_cdclk = i965gm_get_cdclk, 3161 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3162 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3163 }; 3164 3165 /* i965G uses fixed 400 */ 3166 3167 static const struct intel_cdclk_funcs pnv_cdclk_funcs = { 3168 .get_cdclk = pnv_get_cdclk, 3169 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3170 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3171 }; 3172 3173 static const struct intel_cdclk_funcs g33_cdclk_funcs = { 3174 .get_cdclk = g33_get_cdclk, 3175 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3176 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3177 }; 3178 3179 static const struct intel_cdclk_funcs i945gm_cdclk_funcs = { 3180 .get_cdclk = i945gm_get_cdclk, 3181 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3182 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3183 }; 3184 3185 /* i945G uses fixed 400 */ 3186 3187 static const struct intel_cdclk_funcs i915gm_cdclk_funcs = { 3188 .get_cdclk = i915gm_get_cdclk, 3189 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3190 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3191 }; 3192 3193 static const struct intel_cdclk_funcs i915g_cdclk_funcs = { 3194 .get_cdclk = fixed_333mhz_get_cdclk, 3195 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3196 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3197 }; 3198 3199 static const struct intel_cdclk_funcs i865g_cdclk_funcs = { 3200 .get_cdclk = fixed_266mhz_get_cdclk, 3201 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3202 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3203 }; 3204 3205 static const struct intel_cdclk_funcs i85x_cdclk_funcs = { 3206 .get_cdclk = i85x_get_cdclk, 3207 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3208 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3209 }; 3210 3211 static const struct intel_cdclk_funcs i845g_cdclk_funcs = { 3212 .get_cdclk = fixed_200mhz_get_cdclk, 3213 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3214 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3215 }; 3216 3217 static const struct intel_cdclk_funcs i830_cdclk_funcs = { 3218 .get_cdclk = fixed_133mhz_get_cdclk, 3219 .bw_calc_min_cdclk = intel_bw_calc_min_cdclk, 3220 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3221 }; 3222 3223 /** 3224 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks 3225 * @dev_priv: i915 device 3226 */ 3227 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) 3228 { 3229 if (IS_DG2(dev_priv)) { 3230 dev_priv->cdclk_funcs = &tgl_cdclk_funcs; 3231 dev_priv->cdclk.table = dg2_cdclk_table; 3232 } else if (IS_ALDERLAKE_P(dev_priv)) { 3233 dev_priv->cdclk_funcs = &tgl_cdclk_funcs; 3234 /* Wa_22011320316:adl-p[a0] */ 3235 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 3236 dev_priv->cdclk.table = adlp_a_step_cdclk_table; 3237 else 3238 dev_priv->cdclk.table = adlp_cdclk_table; 3239 } else if (IS_ROCKETLAKE(dev_priv)) { 3240 dev_priv->cdclk_funcs = &tgl_cdclk_funcs; 3241 dev_priv->cdclk.table = rkl_cdclk_table; 3242 } else if (DISPLAY_VER(dev_priv) >= 12) { 3243 dev_priv->cdclk_funcs = &tgl_cdclk_funcs; 3244 dev_priv->cdclk.table = icl_cdclk_table; 3245 } else if (IS_JSL_EHL(dev_priv)) { 3246 dev_priv->cdclk_funcs = &ehl_cdclk_funcs; 3247 dev_priv->cdclk.table = icl_cdclk_table; 3248 } else if (DISPLAY_VER(dev_priv) >= 11) { 3249 dev_priv->cdclk_funcs = &icl_cdclk_funcs; 3250 dev_priv->cdclk.table = icl_cdclk_table; 3251 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 3252 dev_priv->cdclk_funcs = &bxt_cdclk_funcs; 3253 if (IS_GEMINILAKE(dev_priv)) 3254 dev_priv->cdclk.table = glk_cdclk_table; 3255 else 3256 dev_priv->cdclk.table = bxt_cdclk_table; 3257 } else if (DISPLAY_VER(dev_priv) == 9) { 3258 dev_priv->cdclk_funcs = &skl_cdclk_funcs; 3259 } else if (IS_BROADWELL(dev_priv)) { 3260 dev_priv->cdclk_funcs = &bdw_cdclk_funcs; 3261 } else if (IS_HASWELL(dev_priv)) { 3262 dev_priv->cdclk_funcs = &hsw_cdclk_funcs; 3263 } else if (IS_CHERRYVIEW(dev_priv)) { 3264 dev_priv->cdclk_funcs = &chv_cdclk_funcs; 3265 } else if (IS_VALLEYVIEW(dev_priv)) { 3266 dev_priv->cdclk_funcs = &vlv_cdclk_funcs; 3267 } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) { 3268 dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs; 3269 } else if (IS_IRONLAKE(dev_priv)) { 3270 dev_priv->cdclk_funcs = &ilk_cdclk_funcs; 3271 } else if (IS_GM45(dev_priv)) { 3272 dev_priv->cdclk_funcs = &gm45_cdclk_funcs; 3273 } else if (IS_G45(dev_priv)) { 3274 dev_priv->cdclk_funcs = &g33_cdclk_funcs; 3275 } else if (IS_I965GM(dev_priv)) { 3276 dev_priv->cdclk_funcs = &i965gm_cdclk_funcs; 3277 } else if (IS_I965G(dev_priv)) { 3278 dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs; 3279 } else if (IS_PINEVIEW(dev_priv)) { 3280 dev_priv->cdclk_funcs = &pnv_cdclk_funcs; 3281 } else if (IS_G33(dev_priv)) { 3282 dev_priv->cdclk_funcs = &g33_cdclk_funcs; 3283 } else if (IS_I945GM(dev_priv)) { 3284 dev_priv->cdclk_funcs = &i945gm_cdclk_funcs; 3285 } else if (IS_I945G(dev_priv)) { 3286 dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs; 3287 } else if (IS_I915GM(dev_priv)) { 3288 dev_priv->cdclk_funcs = &i915gm_cdclk_funcs; 3289 } else if (IS_I915G(dev_priv)) { 3290 dev_priv->cdclk_funcs = &i915g_cdclk_funcs; 3291 } else if (IS_I865G(dev_priv)) { 3292 dev_priv->cdclk_funcs = &i865g_cdclk_funcs; 3293 } else if (IS_I85X(dev_priv)) { 3294 dev_priv->cdclk_funcs = &i85x_cdclk_funcs; 3295 } else if (IS_I845G(dev_priv)) { 3296 dev_priv->cdclk_funcs = &i845g_cdclk_funcs; 3297 } else if (IS_I830(dev_priv)) { 3298 dev_priv->cdclk_funcs = &i830_cdclk_funcs; 3299 } 3300 3301 if (drm_WARN(&dev_priv->drm, !dev_priv->cdclk_funcs, 3302 "Unknown platform. Assuming i830\n")) 3303 dev_priv->cdclk_funcs = &i830_cdclk_funcs; 3304 } 3305