1 /* 2 * Copyright © 2006-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "intel_atomic.h" 25 #include "intel_cdclk.h" 26 #include "intel_display_types.h" 27 #include "intel_sideband.h" 28 29 /** 30 * DOC: CDCLK / RAWCLK 31 * 32 * The display engine uses several different clocks to do its work. There 33 * are two main clocks involved that aren't directly related to the actual 34 * pixel clock or any symbol/bit clock of the actual output port. These 35 * are the core display clock (CDCLK) and RAWCLK. 36 * 37 * CDCLK clocks most of the display pipe logic, and thus its frequency 38 * must be high enough to support the rate at which pixels are flowing 39 * through the pipes. Downscaling must also be accounted as that increases 40 * the effective pixel rate. 41 * 42 * On several platforms the CDCLK frequency can be changed dynamically 43 * to minimize power consumption for a given display configuration. 44 * Typically changes to the CDCLK frequency require all the display pipes 45 * to be shut down while the frequency is being changed. 46 * 47 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. 48 * DMC will not change the active CDCLK frequency however, so that part 49 * will still be performed by the driver directly. 50 * 51 * RAWCLK is a fixed frequency clock, often used by various auxiliary 52 * blocks such as AUX CH or backlight PWM. Hence the only thing we 53 * really need to know about RAWCLK is its frequency so that various 54 * dividers can be programmed correctly. 55 */ 56 57 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, 58 struct intel_cdclk_config *cdclk_config) 59 { 60 cdclk_config->cdclk = 133333; 61 } 62 63 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, 64 struct intel_cdclk_config *cdclk_config) 65 { 66 cdclk_config->cdclk = 200000; 67 } 68 69 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, 70 struct intel_cdclk_config *cdclk_config) 71 { 72 cdclk_config->cdclk = 266667; 73 } 74 75 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, 76 struct intel_cdclk_config *cdclk_config) 77 { 78 cdclk_config->cdclk = 333333; 79 } 80 81 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, 82 struct intel_cdclk_config *cdclk_config) 83 { 84 cdclk_config->cdclk = 400000; 85 } 86 87 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, 88 struct intel_cdclk_config *cdclk_config) 89 { 90 cdclk_config->cdclk = 450000; 91 } 92 93 static void i85x_get_cdclk(struct drm_i915_private *dev_priv, 94 struct intel_cdclk_config *cdclk_config) 95 { 96 struct pci_dev *pdev = dev_priv->drm.pdev; 97 u16 hpllcc = 0; 98 99 /* 100 * 852GM/852GMV only supports 133 MHz and the HPLLCC 101 * encoding is different :( 102 * FIXME is this the right way to detect 852GM/852GMV? 103 */ 104 if (pdev->revision == 0x1) { 105 cdclk_config->cdclk = 133333; 106 return; 107 } 108 109 pci_bus_read_config_word(pdev->bus, 110 PCI_DEVFN(0, 3), HPLLCC, &hpllcc); 111 112 /* Assume that the hardware is in the high speed state. This 113 * should be the default. 114 */ 115 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 116 case GC_CLOCK_133_200: 117 case GC_CLOCK_133_200_2: 118 case GC_CLOCK_100_200: 119 cdclk_config->cdclk = 200000; 120 break; 121 case GC_CLOCK_166_250: 122 cdclk_config->cdclk = 250000; 123 break; 124 case GC_CLOCK_100_133: 125 cdclk_config->cdclk = 133333; 126 break; 127 case GC_CLOCK_133_266: 128 case GC_CLOCK_133_266_2: 129 case GC_CLOCK_166_266: 130 cdclk_config->cdclk = 266667; 131 break; 132 } 133 } 134 135 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, 136 struct intel_cdclk_config *cdclk_config) 137 { 138 struct pci_dev *pdev = dev_priv->drm.pdev; 139 u16 gcfgc = 0; 140 141 pci_read_config_word(pdev, GCFGC, &gcfgc); 142 143 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 144 cdclk_config->cdclk = 133333; 145 return; 146 } 147 148 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 149 case GC_DISPLAY_CLOCK_333_320_MHZ: 150 cdclk_config->cdclk = 333333; 151 break; 152 default: 153 case GC_DISPLAY_CLOCK_190_200_MHZ: 154 cdclk_config->cdclk = 190000; 155 break; 156 } 157 } 158 159 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, 160 struct intel_cdclk_config *cdclk_config) 161 { 162 struct pci_dev *pdev = dev_priv->drm.pdev; 163 u16 gcfgc = 0; 164 165 pci_read_config_word(pdev, GCFGC, &gcfgc); 166 167 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 168 cdclk_config->cdclk = 133333; 169 return; 170 } 171 172 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 173 case GC_DISPLAY_CLOCK_333_320_MHZ: 174 cdclk_config->cdclk = 320000; 175 break; 176 default: 177 case GC_DISPLAY_CLOCK_190_200_MHZ: 178 cdclk_config->cdclk = 200000; 179 break; 180 } 181 } 182 183 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) 184 { 185 static const unsigned int blb_vco[8] = { 186 [0] = 3200000, 187 [1] = 4000000, 188 [2] = 5333333, 189 [3] = 4800000, 190 [4] = 6400000, 191 }; 192 static const unsigned int pnv_vco[8] = { 193 [0] = 3200000, 194 [1] = 4000000, 195 [2] = 5333333, 196 [3] = 4800000, 197 [4] = 2666667, 198 }; 199 static const unsigned int cl_vco[8] = { 200 [0] = 3200000, 201 [1] = 4000000, 202 [2] = 5333333, 203 [3] = 6400000, 204 [4] = 3333333, 205 [5] = 3566667, 206 [6] = 4266667, 207 }; 208 static const unsigned int elk_vco[8] = { 209 [0] = 3200000, 210 [1] = 4000000, 211 [2] = 5333333, 212 [3] = 4800000, 213 }; 214 static const unsigned int ctg_vco[8] = { 215 [0] = 3200000, 216 [1] = 4000000, 217 [2] = 5333333, 218 [3] = 6400000, 219 [4] = 2666667, 220 [5] = 4266667, 221 }; 222 const unsigned int *vco_table; 223 unsigned int vco; 224 u8 tmp = 0; 225 226 /* FIXME other chipsets? */ 227 if (IS_GM45(dev_priv)) 228 vco_table = ctg_vco; 229 else if (IS_G45(dev_priv)) 230 vco_table = elk_vco; 231 else if (IS_I965GM(dev_priv)) 232 vco_table = cl_vco; 233 else if (IS_PINEVIEW(dev_priv)) 234 vco_table = pnv_vco; 235 else if (IS_G33(dev_priv)) 236 vco_table = blb_vco; 237 else 238 return 0; 239 240 tmp = intel_de_read(dev_priv, 241 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); 242 243 vco = vco_table[tmp & 0x7]; 244 if (vco == 0) 245 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", 246 tmp); 247 else 248 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); 249 250 return vco; 251 } 252 253 static void g33_get_cdclk(struct drm_i915_private *dev_priv, 254 struct intel_cdclk_config *cdclk_config) 255 { 256 struct pci_dev *pdev = dev_priv->drm.pdev; 257 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 }; 258 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 }; 259 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 }; 260 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 }; 261 const u8 *div_table; 262 unsigned int cdclk_sel; 263 u16 tmp = 0; 264 265 cdclk_config->vco = intel_hpll_vco(dev_priv); 266 267 pci_read_config_word(pdev, GCFGC, &tmp); 268 269 cdclk_sel = (tmp >> 4) & 0x7; 270 271 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 272 goto fail; 273 274 switch (cdclk_config->vco) { 275 case 3200000: 276 div_table = div_3200; 277 break; 278 case 4000000: 279 div_table = div_4000; 280 break; 281 case 4800000: 282 div_table = div_4800; 283 break; 284 case 5333333: 285 div_table = div_5333; 286 break; 287 default: 288 goto fail; 289 } 290 291 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 292 div_table[cdclk_sel]); 293 return; 294 295 fail: 296 drm_err(&dev_priv->drm, 297 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", 298 cdclk_config->vco, tmp); 299 cdclk_config->cdclk = 190476; 300 } 301 302 static void pnv_get_cdclk(struct drm_i915_private *dev_priv, 303 struct intel_cdclk_config *cdclk_config) 304 { 305 struct pci_dev *pdev = dev_priv->drm.pdev; 306 u16 gcfgc = 0; 307 308 pci_read_config_word(pdev, GCFGC, &gcfgc); 309 310 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 311 case GC_DISPLAY_CLOCK_267_MHZ_PNV: 312 cdclk_config->cdclk = 266667; 313 break; 314 case GC_DISPLAY_CLOCK_333_MHZ_PNV: 315 cdclk_config->cdclk = 333333; 316 break; 317 case GC_DISPLAY_CLOCK_444_MHZ_PNV: 318 cdclk_config->cdclk = 444444; 319 break; 320 case GC_DISPLAY_CLOCK_200_MHZ_PNV: 321 cdclk_config->cdclk = 200000; 322 break; 323 default: 324 drm_err(&dev_priv->drm, 325 "Unknown pnv display core clock 0x%04x\n", gcfgc); 326 /* fall through */ 327 case GC_DISPLAY_CLOCK_133_MHZ_PNV: 328 cdclk_config->cdclk = 133333; 329 break; 330 case GC_DISPLAY_CLOCK_167_MHZ_PNV: 331 cdclk_config->cdclk = 166667; 332 break; 333 } 334 } 335 336 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, 337 struct intel_cdclk_config *cdclk_config) 338 { 339 struct pci_dev *pdev = dev_priv->drm.pdev; 340 static const u8 div_3200[] = { 16, 10, 8 }; 341 static const u8 div_4000[] = { 20, 12, 10 }; 342 static const u8 div_5333[] = { 24, 16, 14 }; 343 const u8 *div_table; 344 unsigned int cdclk_sel; 345 u16 tmp = 0; 346 347 cdclk_config->vco = intel_hpll_vco(dev_priv); 348 349 pci_read_config_word(pdev, GCFGC, &tmp); 350 351 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; 352 353 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 354 goto fail; 355 356 switch (cdclk_config->vco) { 357 case 3200000: 358 div_table = div_3200; 359 break; 360 case 4000000: 361 div_table = div_4000; 362 break; 363 case 5333333: 364 div_table = div_5333; 365 break; 366 default: 367 goto fail; 368 } 369 370 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 371 div_table[cdclk_sel]); 372 return; 373 374 fail: 375 drm_err(&dev_priv->drm, 376 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", 377 cdclk_config->vco, tmp); 378 cdclk_config->cdclk = 200000; 379 } 380 381 static void gm45_get_cdclk(struct drm_i915_private *dev_priv, 382 struct intel_cdclk_config *cdclk_config) 383 { 384 struct pci_dev *pdev = dev_priv->drm.pdev; 385 unsigned int cdclk_sel; 386 u16 tmp = 0; 387 388 cdclk_config->vco = intel_hpll_vco(dev_priv); 389 390 pci_read_config_word(pdev, GCFGC, &tmp); 391 392 cdclk_sel = (tmp >> 12) & 0x1; 393 394 switch (cdclk_config->vco) { 395 case 2666667: 396 case 4000000: 397 case 5333333: 398 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; 399 break; 400 case 3200000: 401 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; 402 break; 403 default: 404 drm_err(&dev_priv->drm, 405 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", 406 cdclk_config->vco, tmp); 407 cdclk_config->cdclk = 222222; 408 break; 409 } 410 } 411 412 static void hsw_get_cdclk(struct drm_i915_private *dev_priv, 413 struct intel_cdclk_config *cdclk_config) 414 { 415 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); 416 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 417 418 if (lcpll & LCPLL_CD_SOURCE_FCLK) 419 cdclk_config->cdclk = 800000; 420 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 421 cdclk_config->cdclk = 450000; 422 else if (freq == LCPLL_CLK_FREQ_450) 423 cdclk_config->cdclk = 450000; 424 else if (IS_HSW_ULT(dev_priv)) 425 cdclk_config->cdclk = 337500; 426 else 427 cdclk_config->cdclk = 540000; 428 } 429 430 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) 431 { 432 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 433 333333 : 320000; 434 435 /* 436 * We seem to get an unstable or solid color picture at 200MHz. 437 * Not sure what's wrong. For now use 200MHz only when all pipes 438 * are off. 439 */ 440 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) 441 return 400000; 442 else if (min_cdclk > 266667) 443 return freq_320; 444 else if (min_cdclk > 0) 445 return 266667; 446 else 447 return 200000; 448 } 449 450 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) 451 { 452 if (IS_VALLEYVIEW(dev_priv)) { 453 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ 454 return 2; 455 else if (cdclk >= 266667) 456 return 1; 457 else 458 return 0; 459 } else { 460 /* 461 * Specs are full of misinformation, but testing on actual 462 * hardware has shown that we just need to write the desired 463 * CCK divider into the Punit register. 464 */ 465 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; 466 } 467 } 468 469 static void vlv_get_cdclk(struct drm_i915_private *dev_priv, 470 struct intel_cdclk_config *cdclk_config) 471 { 472 u32 val; 473 474 vlv_iosf_sb_get(dev_priv, 475 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 476 477 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); 478 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", 479 CCK_DISPLAY_CLOCK_CONTROL, 480 cdclk_config->vco); 481 482 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 483 484 vlv_iosf_sb_put(dev_priv, 485 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 486 487 if (IS_VALLEYVIEW(dev_priv)) 488 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> 489 DSPFREQGUAR_SHIFT; 490 else 491 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> 492 DSPFREQGUAR_SHIFT_CHV; 493 } 494 495 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) 496 { 497 unsigned int credits, default_credits; 498 499 if (IS_CHERRYVIEW(dev_priv)) 500 default_credits = PFI_CREDIT(12); 501 else 502 default_credits = PFI_CREDIT(8); 503 504 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) { 505 /* CHV suggested value is 31 or 63 */ 506 if (IS_CHERRYVIEW(dev_priv)) 507 credits = PFI_CREDIT_63; 508 else 509 credits = PFI_CREDIT(15); 510 } else { 511 credits = default_credits; 512 } 513 514 /* 515 * WA - write default credits before re-programming 516 * FIXME: should we also set the resend bit here? 517 */ 518 intel_de_write(dev_priv, GCI_CONTROL, 519 VGA_FAST_MODE_DISABLE | default_credits); 520 521 intel_de_write(dev_priv, GCI_CONTROL, 522 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND); 523 524 /* 525 * FIXME is this guaranteed to clear 526 * immediately or should we poll for it? 527 */ 528 drm_WARN_ON(&dev_priv->drm, 529 intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND); 530 } 531 532 static void vlv_set_cdclk(struct drm_i915_private *dev_priv, 533 const struct intel_cdclk_config *cdclk_config, 534 enum pipe pipe) 535 { 536 int cdclk = cdclk_config->cdclk; 537 u32 val, cmd = cdclk_config->voltage_level; 538 intel_wakeref_t wakeref; 539 540 switch (cdclk) { 541 case 400000: 542 case 333333: 543 case 320000: 544 case 266667: 545 case 200000: 546 break; 547 default: 548 MISSING_CASE(cdclk); 549 return; 550 } 551 552 /* There are cases where we can end up here with power domains 553 * off and a CDCLK frequency other than the minimum, like when 554 * issuing a modeset without actually changing any display after 555 * a system suspend. So grab the display core domain, which covers 556 * the HW blocks needed for the following programming. 557 */ 558 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); 559 560 vlv_iosf_sb_get(dev_priv, 561 BIT(VLV_IOSF_SB_CCK) | 562 BIT(VLV_IOSF_SB_BUNIT) | 563 BIT(VLV_IOSF_SB_PUNIT)); 564 565 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 566 val &= ~DSPFREQGUAR_MASK; 567 val |= (cmd << DSPFREQGUAR_SHIFT); 568 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); 569 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & 570 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 571 50)) { 572 drm_err(&dev_priv->drm, 573 "timed out waiting for CDclk change\n"); 574 } 575 576 if (cdclk == 400000) { 577 u32 divider; 578 579 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, 580 cdclk) - 1; 581 582 /* adjust cdclk divider */ 583 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); 584 val &= ~CCK_FREQUENCY_VALUES; 585 val |= divider; 586 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); 587 588 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & 589 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 590 50)) 591 drm_err(&dev_priv->drm, 592 "timed out waiting for CDclk change\n"); 593 } 594 595 /* adjust self-refresh exit latency value */ 596 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); 597 val &= ~0x7f; 598 599 /* 600 * For high bandwidth configs, we set a higher latency in the bunit 601 * so that the core display fetch happens in time to avoid underruns. 602 */ 603 if (cdclk == 400000) 604 val |= 4500 / 250; /* 4.5 usec */ 605 else 606 val |= 3000 / 250; /* 3.0 usec */ 607 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); 608 609 vlv_iosf_sb_put(dev_priv, 610 BIT(VLV_IOSF_SB_CCK) | 611 BIT(VLV_IOSF_SB_BUNIT) | 612 BIT(VLV_IOSF_SB_PUNIT)); 613 614 intel_update_cdclk(dev_priv); 615 616 vlv_program_pfi_credits(dev_priv); 617 618 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); 619 } 620 621 static void chv_set_cdclk(struct drm_i915_private *dev_priv, 622 const struct intel_cdclk_config *cdclk_config, 623 enum pipe pipe) 624 { 625 int cdclk = cdclk_config->cdclk; 626 u32 val, cmd = cdclk_config->voltage_level; 627 intel_wakeref_t wakeref; 628 629 switch (cdclk) { 630 case 333333: 631 case 320000: 632 case 266667: 633 case 200000: 634 break; 635 default: 636 MISSING_CASE(cdclk); 637 return; 638 } 639 640 /* There are cases where we can end up here with power domains 641 * off and a CDCLK frequency other than the minimum, like when 642 * issuing a modeset without actually changing any display after 643 * a system suspend. So grab the display core domain, which covers 644 * the HW blocks needed for the following programming. 645 */ 646 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); 647 648 vlv_punit_get(dev_priv); 649 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 650 val &= ~DSPFREQGUAR_MASK_CHV; 651 val |= (cmd << DSPFREQGUAR_SHIFT_CHV); 652 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); 653 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & 654 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 655 50)) { 656 drm_err(&dev_priv->drm, 657 "timed out waiting for CDclk change\n"); 658 } 659 660 vlv_punit_put(dev_priv); 661 662 intel_update_cdclk(dev_priv); 663 664 vlv_program_pfi_credits(dev_priv); 665 666 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); 667 } 668 669 static int bdw_calc_cdclk(int min_cdclk) 670 { 671 if (min_cdclk > 540000) 672 return 675000; 673 else if (min_cdclk > 450000) 674 return 540000; 675 else if (min_cdclk > 337500) 676 return 450000; 677 else 678 return 337500; 679 } 680 681 static u8 bdw_calc_voltage_level(int cdclk) 682 { 683 switch (cdclk) { 684 default: 685 case 337500: 686 return 2; 687 case 450000: 688 return 0; 689 case 540000: 690 return 1; 691 case 675000: 692 return 3; 693 } 694 } 695 696 static void bdw_get_cdclk(struct drm_i915_private *dev_priv, 697 struct intel_cdclk_config *cdclk_config) 698 { 699 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); 700 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 701 702 if (lcpll & LCPLL_CD_SOURCE_FCLK) 703 cdclk_config->cdclk = 800000; 704 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 705 cdclk_config->cdclk = 450000; 706 else if (freq == LCPLL_CLK_FREQ_450) 707 cdclk_config->cdclk = 450000; 708 else if (freq == LCPLL_CLK_FREQ_54O_BDW) 709 cdclk_config->cdclk = 540000; 710 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 711 cdclk_config->cdclk = 337500; 712 else 713 cdclk_config->cdclk = 675000; 714 715 /* 716 * Can't read this out :( Let's assume it's 717 * at least what the CDCLK frequency requires. 718 */ 719 cdclk_config->voltage_level = 720 bdw_calc_voltage_level(cdclk_config->cdclk); 721 } 722 723 static void bdw_set_cdclk(struct drm_i915_private *dev_priv, 724 const struct intel_cdclk_config *cdclk_config, 725 enum pipe pipe) 726 { 727 int cdclk = cdclk_config->cdclk; 728 u32 val; 729 int ret; 730 731 if (drm_WARN(&dev_priv->drm, 732 (intel_de_read(dev_priv, LCPLL_CTL) & 733 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | 734 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | 735 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | 736 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, 737 "trying to change cdclk frequency with cdclk not enabled\n")) 738 return; 739 740 ret = sandybridge_pcode_write(dev_priv, 741 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); 742 if (ret) { 743 drm_err(&dev_priv->drm, 744 "failed to inform pcode about cdclk change\n"); 745 return; 746 } 747 748 val = intel_de_read(dev_priv, LCPLL_CTL); 749 val |= LCPLL_CD_SOURCE_FCLK; 750 intel_de_write(dev_priv, LCPLL_CTL, val); 751 752 /* 753 * According to the spec, it should be enough to poll for this 1 us. 754 * However, extensive testing shows that this can take longer. 755 */ 756 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) & 757 LCPLL_CD_SOURCE_FCLK_DONE, 100)) 758 drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); 759 760 val = intel_de_read(dev_priv, LCPLL_CTL); 761 val &= ~LCPLL_CLK_FREQ_MASK; 762 763 switch (cdclk) { 764 default: 765 MISSING_CASE(cdclk); 766 /* fall through */ 767 case 337500: 768 val |= LCPLL_CLK_FREQ_337_5_BDW; 769 break; 770 case 450000: 771 val |= LCPLL_CLK_FREQ_450; 772 break; 773 case 540000: 774 val |= LCPLL_CLK_FREQ_54O_BDW; 775 break; 776 case 675000: 777 val |= LCPLL_CLK_FREQ_675_BDW; 778 break; 779 } 780 781 intel_de_write(dev_priv, LCPLL_CTL, val); 782 783 val = intel_de_read(dev_priv, LCPLL_CTL); 784 val &= ~LCPLL_CD_SOURCE_FCLK; 785 intel_de_write(dev_priv, LCPLL_CTL, val); 786 787 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) & 788 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 789 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n"); 790 791 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, 792 cdclk_config->voltage_level); 793 794 intel_de_write(dev_priv, CDCLK_FREQ, 795 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); 796 797 intel_update_cdclk(dev_priv); 798 } 799 800 static int skl_calc_cdclk(int min_cdclk, int vco) 801 { 802 if (vco == 8640000) { 803 if (min_cdclk > 540000) 804 return 617143; 805 else if (min_cdclk > 432000) 806 return 540000; 807 else if (min_cdclk > 308571) 808 return 432000; 809 else 810 return 308571; 811 } else { 812 if (min_cdclk > 540000) 813 return 675000; 814 else if (min_cdclk > 450000) 815 return 540000; 816 else if (min_cdclk > 337500) 817 return 450000; 818 else 819 return 337500; 820 } 821 } 822 823 static u8 skl_calc_voltage_level(int cdclk) 824 { 825 if (cdclk > 540000) 826 return 3; 827 else if (cdclk > 450000) 828 return 2; 829 else if (cdclk > 337500) 830 return 1; 831 else 832 return 0; 833 } 834 835 static void skl_dpll0_update(struct drm_i915_private *dev_priv, 836 struct intel_cdclk_config *cdclk_config) 837 { 838 u32 val; 839 840 cdclk_config->ref = 24000; 841 cdclk_config->vco = 0; 842 843 val = intel_de_read(dev_priv, LCPLL1_CTL); 844 if ((val & LCPLL_PLL_ENABLE) == 0) 845 return; 846 847 if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0)) 848 return; 849 850 val = intel_de_read(dev_priv, DPLL_CTRL1); 851 852 if (drm_WARN_ON(&dev_priv->drm, 853 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 854 DPLL_CTRL1_SSC(SKL_DPLL0) | 855 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != 856 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) 857 return; 858 859 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { 860 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): 861 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): 862 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): 863 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): 864 cdclk_config->vco = 8100000; 865 break; 866 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): 867 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): 868 cdclk_config->vco = 8640000; 869 break; 870 default: 871 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 872 break; 873 } 874 } 875 876 static void skl_get_cdclk(struct drm_i915_private *dev_priv, 877 struct intel_cdclk_config *cdclk_config) 878 { 879 u32 cdctl; 880 881 skl_dpll0_update(dev_priv, cdclk_config); 882 883 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; 884 885 if (cdclk_config->vco == 0) 886 goto out; 887 888 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 889 890 if (cdclk_config->vco == 8640000) { 891 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 892 case CDCLK_FREQ_450_432: 893 cdclk_config->cdclk = 432000; 894 break; 895 case CDCLK_FREQ_337_308: 896 cdclk_config->cdclk = 308571; 897 break; 898 case CDCLK_FREQ_540: 899 cdclk_config->cdclk = 540000; 900 break; 901 case CDCLK_FREQ_675_617: 902 cdclk_config->cdclk = 617143; 903 break; 904 default: 905 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 906 break; 907 } 908 } else { 909 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 910 case CDCLK_FREQ_450_432: 911 cdclk_config->cdclk = 450000; 912 break; 913 case CDCLK_FREQ_337_308: 914 cdclk_config->cdclk = 337500; 915 break; 916 case CDCLK_FREQ_540: 917 cdclk_config->cdclk = 540000; 918 break; 919 case CDCLK_FREQ_675_617: 920 cdclk_config->cdclk = 675000; 921 break; 922 default: 923 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 924 break; 925 } 926 } 927 928 out: 929 /* 930 * Can't read this out :( Let's assume it's 931 * at least what the CDCLK frequency requires. 932 */ 933 cdclk_config->voltage_level = 934 skl_calc_voltage_level(cdclk_config->cdclk); 935 } 936 937 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ 938 static int skl_cdclk_decimal(int cdclk) 939 { 940 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); 941 } 942 943 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, 944 int vco) 945 { 946 bool changed = dev_priv->skl_preferred_vco_freq != vco; 947 948 dev_priv->skl_preferred_vco_freq = vco; 949 950 if (changed) 951 intel_update_max_cdclk(dev_priv); 952 } 953 954 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) 955 { 956 u32 val; 957 958 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); 959 960 /* 961 * We always enable DPLL0 with the lowest link rate possible, but still 962 * taking into account the VCO required to operate the eDP panel at the 963 * desired frequency. The usual DP link rates operate with a VCO of 964 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. 965 * The modeset code is responsible for the selection of the exact link 966 * rate later on, with the constraint of choosing a frequency that 967 * works with vco. 968 */ 969 val = intel_de_read(dev_priv, DPLL_CTRL1); 970 971 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | 972 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 973 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); 974 if (vco == 8640000) 975 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 976 SKL_DPLL0); 977 else 978 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 979 SKL_DPLL0); 980 981 intel_de_write(dev_priv, DPLL_CTRL1, val); 982 intel_de_posting_read(dev_priv, DPLL_CTRL1); 983 984 intel_de_write(dev_priv, LCPLL1_CTL, 985 intel_de_read(dev_priv, LCPLL1_CTL) | LCPLL_PLL_ENABLE); 986 987 if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) 988 drm_err(&dev_priv->drm, "DPLL0 not locked\n"); 989 990 dev_priv->cdclk.hw.vco = vco; 991 992 /* We'll want to keep using the current vco from now on. */ 993 skl_set_preferred_cdclk_vco(dev_priv, vco); 994 } 995 996 static void skl_dpll0_disable(struct drm_i915_private *dev_priv) 997 { 998 intel_de_write(dev_priv, LCPLL1_CTL, 999 intel_de_read(dev_priv, LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); 1000 if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) 1001 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n"); 1002 1003 dev_priv->cdclk.hw.vco = 0; 1004 } 1005 1006 static void skl_set_cdclk(struct drm_i915_private *dev_priv, 1007 const struct intel_cdclk_config *cdclk_config, 1008 enum pipe pipe) 1009 { 1010 int cdclk = cdclk_config->cdclk; 1011 int vco = cdclk_config->vco; 1012 u32 freq_select, cdclk_ctl; 1013 int ret; 1014 1015 /* 1016 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are 1017 * unsupported on SKL. In theory this should never happen since only 1018 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not 1019 * supported on SKL either, see the above WA. WARN whenever trying to 1020 * use the corresponding VCO freq as that always leads to using the 1021 * minimum 308MHz CDCLK. 1022 */ 1023 drm_WARN_ON_ONCE(&dev_priv->drm, 1024 IS_SKYLAKE(dev_priv) && vco == 8640000); 1025 1026 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, 1027 SKL_CDCLK_PREPARE_FOR_CHANGE, 1028 SKL_CDCLK_READY_FOR_CHANGE, 1029 SKL_CDCLK_READY_FOR_CHANGE, 3); 1030 if (ret) { 1031 drm_err(&dev_priv->drm, 1032 "Failed to inform PCU about cdclk change (%d)\n", ret); 1033 return; 1034 } 1035 1036 /* Choose frequency for this cdclk */ 1037 switch (cdclk) { 1038 default: 1039 drm_WARN_ON(&dev_priv->drm, 1040 cdclk != dev_priv->cdclk.hw.bypass); 1041 drm_WARN_ON(&dev_priv->drm, vco != 0); 1042 /* fall through */ 1043 case 308571: 1044 case 337500: 1045 freq_select = CDCLK_FREQ_337_308; 1046 break; 1047 case 450000: 1048 case 432000: 1049 freq_select = CDCLK_FREQ_450_432; 1050 break; 1051 case 540000: 1052 freq_select = CDCLK_FREQ_540; 1053 break; 1054 case 617143: 1055 case 675000: 1056 freq_select = CDCLK_FREQ_675_617; 1057 break; 1058 } 1059 1060 if (dev_priv->cdclk.hw.vco != 0 && 1061 dev_priv->cdclk.hw.vco != vco) 1062 skl_dpll0_disable(dev_priv); 1063 1064 cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL); 1065 1066 if (dev_priv->cdclk.hw.vco != vco) { 1067 /* Wa Display #1183: skl,kbl,cfl */ 1068 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1069 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1070 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1071 } 1072 1073 /* Wa Display #1183: skl,kbl,cfl */ 1074 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; 1075 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1076 intel_de_posting_read(dev_priv, CDCLK_CTL); 1077 1078 if (dev_priv->cdclk.hw.vco != vco) 1079 skl_dpll0_enable(dev_priv, vco); 1080 1081 /* Wa Display #1183: skl,kbl,cfl */ 1082 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1083 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1084 1085 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1086 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1087 1088 /* Wa Display #1183: skl,kbl,cfl */ 1089 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; 1090 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1091 intel_de_posting_read(dev_priv, CDCLK_CTL); 1092 1093 /* inform PCU of the change */ 1094 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, 1095 cdclk_config->voltage_level); 1096 1097 intel_update_cdclk(dev_priv); 1098 } 1099 1100 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) 1101 { 1102 u32 cdctl, expected; 1103 1104 /* 1105 * check if the pre-os initialized the display 1106 * There is SWF18 scratchpad register defined which is set by the 1107 * pre-os which can be used by the OS drivers to check the status 1108 */ 1109 if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) 1110 goto sanitize; 1111 1112 intel_update_cdclk(dev_priv); 1113 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK"); 1114 1115 /* Is PLL enabled and locked ? */ 1116 if (dev_priv->cdclk.hw.vco == 0 || 1117 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) 1118 goto sanitize; 1119 1120 /* DPLL okay; verify the cdclock 1121 * 1122 * Noticed in some instances that the freq selection is correct but 1123 * decimal part is programmed wrong from BIOS where pre-os does not 1124 * enable display. Verify the same as well. 1125 */ 1126 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 1127 expected = (cdctl & CDCLK_FREQ_SEL_MASK) | 1128 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); 1129 if (cdctl == expected) 1130 /* All well; nothing to sanitize */ 1131 return; 1132 1133 sanitize: 1134 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); 1135 1136 /* force cdclk programming */ 1137 dev_priv->cdclk.hw.cdclk = 0; 1138 /* force full PLL disable + enable */ 1139 dev_priv->cdclk.hw.vco = -1; 1140 } 1141 1142 static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv) 1143 { 1144 struct intel_cdclk_config cdclk_config; 1145 1146 skl_sanitize_cdclk(dev_priv); 1147 1148 if (dev_priv->cdclk.hw.cdclk != 0 && 1149 dev_priv->cdclk.hw.vco != 0) { 1150 /* 1151 * Use the current vco as our initial 1152 * guess as to what the preferred vco is. 1153 */ 1154 if (dev_priv->skl_preferred_vco_freq == 0) 1155 skl_set_preferred_cdclk_vco(dev_priv, 1156 dev_priv->cdclk.hw.vco); 1157 return; 1158 } 1159 1160 cdclk_config = dev_priv->cdclk.hw; 1161 1162 cdclk_config.vco = dev_priv->skl_preferred_vco_freq; 1163 if (cdclk_config.vco == 0) 1164 cdclk_config.vco = 8100000; 1165 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); 1166 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1167 1168 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1169 } 1170 1171 static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv) 1172 { 1173 struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw; 1174 1175 cdclk_config.cdclk = cdclk_config.bypass; 1176 cdclk_config.vco = 0; 1177 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1178 1179 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1180 } 1181 1182 static const struct intel_cdclk_vals bxt_cdclk_table[] = { 1183 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 }, 1184 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 }, 1185 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 }, 1186 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 }, 1187 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 }, 1188 {} 1189 }; 1190 1191 static const struct intel_cdclk_vals glk_cdclk_table[] = { 1192 { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 }, 1193 { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 }, 1194 { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 }, 1195 {} 1196 }; 1197 1198 static const struct intel_cdclk_vals cnl_cdclk_table[] = { 1199 { .refclk = 19200, .cdclk = 168000, .divider = 4, .ratio = 35 }, 1200 { .refclk = 19200, .cdclk = 336000, .divider = 2, .ratio = 35 }, 1201 { .refclk = 19200, .cdclk = 528000, .divider = 2, .ratio = 55 }, 1202 1203 { .refclk = 24000, .cdclk = 168000, .divider = 4, .ratio = 28 }, 1204 { .refclk = 24000, .cdclk = 336000, .divider = 2, .ratio = 28 }, 1205 { .refclk = 24000, .cdclk = 528000, .divider = 2, .ratio = 44 }, 1206 {} 1207 }; 1208 1209 static const struct intel_cdclk_vals icl_cdclk_table[] = { 1210 { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 }, 1211 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 }, 1212 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 }, 1213 { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 }, 1214 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 }, 1215 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 }, 1216 1217 { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 }, 1218 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 }, 1219 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 }, 1220 { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 }, 1221 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 }, 1222 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 }, 1223 1224 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 }, 1225 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 }, 1226 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 }, 1227 { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 }, 1228 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 }, 1229 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 }, 1230 {} 1231 }; 1232 1233 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) 1234 { 1235 const struct intel_cdclk_vals *table = dev_priv->cdclk.table; 1236 int i; 1237 1238 for (i = 0; table[i].refclk; i++) 1239 if (table[i].refclk == dev_priv->cdclk.hw.ref && 1240 table[i].cdclk >= min_cdclk) 1241 return table[i].cdclk; 1242 1243 drm_WARN(&dev_priv->drm, 1, 1244 "Cannot satisfy minimum cdclk %d with refclk %u\n", 1245 min_cdclk, dev_priv->cdclk.hw.ref); 1246 return 0; 1247 } 1248 1249 static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) 1250 { 1251 const struct intel_cdclk_vals *table = dev_priv->cdclk.table; 1252 int i; 1253 1254 if (cdclk == dev_priv->cdclk.hw.bypass) 1255 return 0; 1256 1257 for (i = 0; table[i].refclk; i++) 1258 if (table[i].refclk == dev_priv->cdclk.hw.ref && 1259 table[i].cdclk == cdclk) 1260 return dev_priv->cdclk.hw.ref * table[i].ratio; 1261 1262 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", 1263 cdclk, dev_priv->cdclk.hw.ref); 1264 return 0; 1265 } 1266 1267 static u8 bxt_calc_voltage_level(int cdclk) 1268 { 1269 return DIV_ROUND_UP(cdclk, 25000); 1270 } 1271 1272 static u8 cnl_calc_voltage_level(int cdclk) 1273 { 1274 if (cdclk > 336000) 1275 return 2; 1276 else if (cdclk > 168000) 1277 return 1; 1278 else 1279 return 0; 1280 } 1281 1282 static u8 icl_calc_voltage_level(int cdclk) 1283 { 1284 if (cdclk > 556800) 1285 return 2; 1286 else if (cdclk > 312000) 1287 return 1; 1288 else 1289 return 0; 1290 } 1291 1292 static u8 ehl_calc_voltage_level(int cdclk) 1293 { 1294 if (cdclk > 326400) 1295 return 3; 1296 else if (cdclk > 312000) 1297 return 2; 1298 else if (cdclk > 180000) 1299 return 1; 1300 else 1301 return 0; 1302 } 1303 1304 static u8 tgl_calc_voltage_level(int cdclk) 1305 { 1306 if (cdclk > 556800) 1307 return 3; 1308 else if (cdclk > 326400) 1309 return 2; 1310 else if (cdclk > 312000) 1311 return 1; 1312 else 1313 return 0; 1314 } 1315 1316 static void cnl_readout_refclk(struct drm_i915_private *dev_priv, 1317 struct intel_cdclk_config *cdclk_config) 1318 { 1319 if (intel_de_read(dev_priv, SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz) 1320 cdclk_config->ref = 24000; 1321 else 1322 cdclk_config->ref = 19200; 1323 } 1324 1325 static void icl_readout_refclk(struct drm_i915_private *dev_priv, 1326 struct intel_cdclk_config *cdclk_config) 1327 { 1328 u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; 1329 1330 switch (dssm) { 1331 default: 1332 MISSING_CASE(dssm); 1333 /* fall through */ 1334 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz: 1335 cdclk_config->ref = 24000; 1336 break; 1337 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz: 1338 cdclk_config->ref = 19200; 1339 break; 1340 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz: 1341 cdclk_config->ref = 38400; 1342 break; 1343 } 1344 } 1345 1346 static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, 1347 struct intel_cdclk_config *cdclk_config) 1348 { 1349 u32 val, ratio; 1350 1351 if (INTEL_GEN(dev_priv) >= 11) 1352 icl_readout_refclk(dev_priv, cdclk_config); 1353 else if (IS_CANNONLAKE(dev_priv)) 1354 cnl_readout_refclk(dev_priv, cdclk_config); 1355 else 1356 cdclk_config->ref = 19200; 1357 1358 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE); 1359 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || 1360 (val & BXT_DE_PLL_LOCK) == 0) { 1361 /* 1362 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but 1363 * setting it to zero is a way to signal that. 1364 */ 1365 cdclk_config->vco = 0; 1366 return; 1367 } 1368 1369 /* 1370 * CNL+ have the ratio directly in the PLL enable register, gen9lp had 1371 * it in a separate PLL control register. 1372 */ 1373 if (INTEL_GEN(dev_priv) >= 10) 1374 ratio = val & CNL_CDCLK_PLL_RATIO_MASK; 1375 else 1376 ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; 1377 1378 cdclk_config->vco = ratio * cdclk_config->ref; 1379 } 1380 1381 static void bxt_get_cdclk(struct drm_i915_private *dev_priv, 1382 struct intel_cdclk_config *cdclk_config) 1383 { 1384 u32 divider; 1385 int div; 1386 1387 bxt_de_pll_readout(dev_priv, cdclk_config); 1388 1389 if (INTEL_GEN(dev_priv) >= 12) 1390 cdclk_config->bypass = cdclk_config->ref / 2; 1391 else if (INTEL_GEN(dev_priv) >= 11) 1392 cdclk_config->bypass = 50000; 1393 else 1394 cdclk_config->bypass = cdclk_config->ref; 1395 1396 if (cdclk_config->vco == 0) { 1397 cdclk_config->cdclk = cdclk_config->bypass; 1398 goto out; 1399 } 1400 1401 divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; 1402 1403 switch (divider) { 1404 case BXT_CDCLK_CD2X_DIV_SEL_1: 1405 div = 2; 1406 break; 1407 case BXT_CDCLK_CD2X_DIV_SEL_1_5: 1408 drm_WARN(&dev_priv->drm, 1409 IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10, 1410 "Unsupported divider\n"); 1411 div = 3; 1412 break; 1413 case BXT_CDCLK_CD2X_DIV_SEL_2: 1414 div = 4; 1415 break; 1416 case BXT_CDCLK_CD2X_DIV_SEL_4: 1417 drm_WARN(&dev_priv->drm, INTEL_GEN(dev_priv) >= 10, 1418 "Unsupported divider\n"); 1419 div = 8; 1420 break; 1421 default: 1422 MISSING_CASE(divider); 1423 return; 1424 } 1425 1426 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); 1427 1428 out: 1429 /* 1430 * Can't read this out :( Let's assume it's 1431 * at least what the CDCLK frequency requires. 1432 */ 1433 cdclk_config->voltage_level = 1434 dev_priv->display.calc_voltage_level(cdclk_config->cdclk); 1435 } 1436 1437 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) 1438 { 1439 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0); 1440 1441 /* Timeout 200us */ 1442 if (intel_de_wait_for_clear(dev_priv, 1443 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1444 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n"); 1445 1446 dev_priv->cdclk.hw.vco = 0; 1447 } 1448 1449 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) 1450 { 1451 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); 1452 u32 val; 1453 1454 val = intel_de_read(dev_priv, BXT_DE_PLL_CTL); 1455 val &= ~BXT_DE_PLL_RATIO_MASK; 1456 val |= BXT_DE_PLL_RATIO(ratio); 1457 intel_de_write(dev_priv, BXT_DE_PLL_CTL, val); 1458 1459 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); 1460 1461 /* Timeout 200us */ 1462 if (intel_de_wait_for_set(dev_priv, 1463 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1464 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n"); 1465 1466 dev_priv->cdclk.hw.vco = vco; 1467 } 1468 1469 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv) 1470 { 1471 u32 val; 1472 1473 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE); 1474 val &= ~BXT_DE_PLL_PLL_ENABLE; 1475 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1476 1477 /* Timeout 200us */ 1478 if (wait_for((intel_de_read(dev_priv, BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1)) 1479 drm_err(&dev_priv->drm, 1480 "timeout waiting for CDCLK PLL unlock\n"); 1481 1482 dev_priv->cdclk.hw.vco = 0; 1483 } 1484 1485 static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) 1486 { 1487 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); 1488 u32 val; 1489 1490 val = CNL_CDCLK_PLL_RATIO(ratio); 1491 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1492 1493 val |= BXT_DE_PLL_PLL_ENABLE; 1494 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1495 1496 /* Timeout 200us */ 1497 if (wait_for((intel_de_read(dev_priv, BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1)) 1498 drm_err(&dev_priv->drm, 1499 "timeout waiting for CDCLK PLL lock\n"); 1500 1501 dev_priv->cdclk.hw.vco = vco; 1502 } 1503 1504 static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 1505 { 1506 if (INTEL_GEN(dev_priv) >= 12) { 1507 if (pipe == INVALID_PIPE) 1508 return TGL_CDCLK_CD2X_PIPE_NONE; 1509 else 1510 return TGL_CDCLK_CD2X_PIPE(pipe); 1511 } else if (INTEL_GEN(dev_priv) >= 11) { 1512 if (pipe == INVALID_PIPE) 1513 return ICL_CDCLK_CD2X_PIPE_NONE; 1514 else 1515 return ICL_CDCLK_CD2X_PIPE(pipe); 1516 } else { 1517 if (pipe == INVALID_PIPE) 1518 return BXT_CDCLK_CD2X_PIPE_NONE; 1519 else 1520 return BXT_CDCLK_CD2X_PIPE(pipe); 1521 } 1522 } 1523 1524 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 1525 const struct intel_cdclk_config *cdclk_config, 1526 enum pipe pipe) 1527 { 1528 int cdclk = cdclk_config->cdclk; 1529 int vco = cdclk_config->vco; 1530 u32 val, divider; 1531 int ret; 1532 1533 /* Inform power controller of upcoming frequency change. */ 1534 if (INTEL_GEN(dev_priv) >= 10) 1535 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, 1536 SKL_CDCLK_PREPARE_FOR_CHANGE, 1537 SKL_CDCLK_READY_FOR_CHANGE, 1538 SKL_CDCLK_READY_FOR_CHANGE, 3); 1539 else 1540 /* 1541 * BSpec requires us to wait up to 150usec, but that leads to 1542 * timeouts; the 2ms used here is based on experiment. 1543 */ 1544 ret = sandybridge_pcode_write_timeout(dev_priv, 1545 HSW_PCODE_DE_WRITE_FREQ_REQ, 1546 0x80000000, 150, 2); 1547 1548 if (ret) { 1549 drm_err(&dev_priv->drm, 1550 "Failed to inform PCU about cdclk change (err %d, freq %d)\n", 1551 ret, cdclk); 1552 return; 1553 } 1554 1555 /* cdclk = vco / 2 / div{1,1.5,2,4} */ 1556 switch (DIV_ROUND_CLOSEST(vco, cdclk)) { 1557 default: 1558 drm_WARN_ON(&dev_priv->drm, 1559 cdclk != dev_priv->cdclk.hw.bypass); 1560 drm_WARN_ON(&dev_priv->drm, vco != 0); 1561 /* fall through */ 1562 case 2: 1563 divider = BXT_CDCLK_CD2X_DIV_SEL_1; 1564 break; 1565 case 3: 1566 drm_WARN(&dev_priv->drm, 1567 IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10, 1568 "Unsupported divider\n"); 1569 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; 1570 break; 1571 case 4: 1572 divider = BXT_CDCLK_CD2X_DIV_SEL_2; 1573 break; 1574 case 8: 1575 drm_WARN(&dev_priv->drm, INTEL_GEN(dev_priv) >= 10, 1576 "Unsupported divider\n"); 1577 divider = BXT_CDCLK_CD2X_DIV_SEL_4; 1578 break; 1579 } 1580 1581 if (INTEL_GEN(dev_priv) >= 10) { 1582 if (dev_priv->cdclk.hw.vco != 0 && 1583 dev_priv->cdclk.hw.vco != vco) 1584 cnl_cdclk_pll_disable(dev_priv); 1585 1586 if (dev_priv->cdclk.hw.vco != vco) 1587 cnl_cdclk_pll_enable(dev_priv, vco); 1588 1589 } else { 1590 if (dev_priv->cdclk.hw.vco != 0 && 1591 dev_priv->cdclk.hw.vco != vco) 1592 bxt_de_pll_disable(dev_priv); 1593 1594 if (dev_priv->cdclk.hw.vco != vco) 1595 bxt_de_pll_enable(dev_priv, vco); 1596 } 1597 1598 val = divider | skl_cdclk_decimal(cdclk) | 1599 bxt_cdclk_cd2x_pipe(dev_priv, pipe); 1600 1601 /* 1602 * Disable SSA Precharge when CD clock frequency < 500 MHz, 1603 * enable otherwise. 1604 */ 1605 if (IS_GEN9_LP(dev_priv) && cdclk >= 500000) 1606 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 1607 intel_de_write(dev_priv, CDCLK_CTL, val); 1608 1609 if (pipe != INVALID_PIPE) 1610 intel_wait_for_vblank(dev_priv, pipe); 1611 1612 if (INTEL_GEN(dev_priv) >= 10) { 1613 ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, 1614 cdclk_config->voltage_level); 1615 } else { 1616 /* 1617 * The timeout isn't specified, the 2ms used here is based on 1618 * experiment. 1619 * FIXME: Waiting for the request completion could be delayed 1620 * until the next PCODE request based on BSpec. 1621 */ 1622 ret = sandybridge_pcode_write_timeout(dev_priv, 1623 HSW_PCODE_DE_WRITE_FREQ_REQ, 1624 cdclk_config->voltage_level, 1625 150, 2); 1626 } 1627 1628 if (ret) { 1629 drm_err(&dev_priv->drm, 1630 "PCode CDCLK freq set failed, (err %d, freq %d)\n", 1631 ret, cdclk); 1632 return; 1633 } 1634 1635 intel_update_cdclk(dev_priv); 1636 1637 if (INTEL_GEN(dev_priv) >= 10) 1638 /* 1639 * Can't read out the voltage level :( 1640 * Let's just assume everything is as expected. 1641 */ 1642 dev_priv->cdclk.hw.voltage_level = cdclk_config->voltage_level; 1643 } 1644 1645 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) 1646 { 1647 u32 cdctl, expected; 1648 int cdclk, vco; 1649 1650 intel_update_cdclk(dev_priv); 1651 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK"); 1652 1653 if (dev_priv->cdclk.hw.vco == 0 || 1654 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) 1655 goto sanitize; 1656 1657 /* DPLL okay; verify the cdclock 1658 * 1659 * Some BIOS versions leave an incorrect decimal frequency value and 1660 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, 1661 * so sanitize this register. 1662 */ 1663 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 1664 /* 1665 * Let's ignore the pipe field, since BIOS could have configured the 1666 * dividers both synching to an active pipe, or asynchronously 1667 * (PIPE_NONE). 1668 */ 1669 cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); 1670 1671 /* Make sure this is a legal cdclk value for the platform */ 1672 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk); 1673 if (cdclk != dev_priv->cdclk.hw.cdclk) 1674 goto sanitize; 1675 1676 /* Make sure the VCO is correct for the cdclk */ 1677 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 1678 if (vco != dev_priv->cdclk.hw.vco) 1679 goto sanitize; 1680 1681 expected = skl_cdclk_decimal(cdclk); 1682 1683 /* Figure out what CD2X divider we should be using for this cdclk */ 1684 switch (DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.vco, 1685 dev_priv->cdclk.hw.cdclk)) { 1686 case 2: 1687 expected |= BXT_CDCLK_CD2X_DIV_SEL_1; 1688 break; 1689 case 3: 1690 expected |= BXT_CDCLK_CD2X_DIV_SEL_1_5; 1691 break; 1692 case 4: 1693 expected |= BXT_CDCLK_CD2X_DIV_SEL_2; 1694 break; 1695 case 8: 1696 expected |= BXT_CDCLK_CD2X_DIV_SEL_4; 1697 break; 1698 default: 1699 goto sanitize; 1700 } 1701 1702 /* 1703 * Disable SSA Precharge when CD clock frequency < 500 MHz, 1704 * enable otherwise. 1705 */ 1706 if (IS_GEN9_LP(dev_priv) && dev_priv->cdclk.hw.cdclk >= 500000) 1707 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 1708 1709 if (cdctl == expected) 1710 /* All well; nothing to sanitize */ 1711 return; 1712 1713 sanitize: 1714 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); 1715 1716 /* force cdclk programming */ 1717 dev_priv->cdclk.hw.cdclk = 0; 1718 1719 /* force full PLL disable + enable */ 1720 dev_priv->cdclk.hw.vco = -1; 1721 } 1722 1723 static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv) 1724 { 1725 struct intel_cdclk_config cdclk_config; 1726 1727 bxt_sanitize_cdclk(dev_priv); 1728 1729 if (dev_priv->cdclk.hw.cdclk != 0 && 1730 dev_priv->cdclk.hw.vco != 0) 1731 return; 1732 1733 cdclk_config = dev_priv->cdclk.hw; 1734 1735 /* 1736 * FIXME: 1737 * - The initial CDCLK needs to be read from VBT. 1738 * Need to make this change after VBT has changes for BXT. 1739 */ 1740 cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0); 1741 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); 1742 cdclk_config.voltage_level = 1743 dev_priv->display.calc_voltage_level(cdclk_config.cdclk); 1744 1745 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1746 } 1747 1748 static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv) 1749 { 1750 struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw; 1751 1752 cdclk_config.cdclk = cdclk_config.bypass; 1753 cdclk_config.vco = 0; 1754 cdclk_config.voltage_level = 1755 dev_priv->display.calc_voltage_level(cdclk_config.cdclk); 1756 1757 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1758 } 1759 1760 /** 1761 * intel_cdclk_init_hw - Initialize CDCLK hardware 1762 * @i915: i915 device 1763 * 1764 * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and 1765 * sanitizing the state of the hardware if needed. This is generally done only 1766 * during the display core initialization sequence, after which the DMC will 1767 * take care of turning CDCLK off/on as needed. 1768 */ 1769 void intel_cdclk_init_hw(struct drm_i915_private *i915) 1770 { 1771 if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10) 1772 bxt_cdclk_init_hw(i915); 1773 else if (IS_GEN9_BC(i915)) 1774 skl_cdclk_init_hw(i915); 1775 } 1776 1777 /** 1778 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware 1779 * @i915: i915 device 1780 * 1781 * Uninitialize CDCLK. This is done only during the display core 1782 * uninitialization sequence. 1783 */ 1784 void intel_cdclk_uninit_hw(struct drm_i915_private *i915) 1785 { 1786 if (INTEL_GEN(i915) >= 10 || IS_GEN9_LP(i915)) 1787 bxt_cdclk_uninit_hw(i915); 1788 else if (IS_GEN9_BC(i915)) 1789 skl_cdclk_uninit_hw(i915); 1790 } 1791 1792 /** 1793 * intel_cdclk_needs_modeset - Determine if changong between the CDCLK 1794 * configurations requires a modeset on all pipes 1795 * @a: first CDCLK configuration 1796 * @b: second CDCLK configuration 1797 * 1798 * Returns: 1799 * True if changing between the two CDCLK configurations 1800 * requires all pipes to be off, false if not. 1801 */ 1802 bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a, 1803 const struct intel_cdclk_config *b) 1804 { 1805 return a->cdclk != b->cdclk || 1806 a->vco != b->vco || 1807 a->ref != b->ref; 1808 } 1809 1810 /** 1811 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK 1812 * configurations requires only a cd2x divider update 1813 * @dev_priv: i915 device 1814 * @a: first CDCLK configuration 1815 * @b: second CDCLK configuration 1816 * 1817 * Returns: 1818 * True if changing between the two CDCLK configurations 1819 * can be done with just a cd2x divider update, false if not. 1820 */ 1821 static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, 1822 const struct intel_cdclk_config *a, 1823 const struct intel_cdclk_config *b) 1824 { 1825 /* Older hw doesn't have the capability */ 1826 if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv)) 1827 return false; 1828 1829 return a->cdclk != b->cdclk && 1830 a->vco == b->vco && 1831 a->ref == b->ref; 1832 } 1833 1834 /** 1835 * intel_cdclk_changed - Determine if two CDCLK configurations are different 1836 * @a: first CDCLK configuration 1837 * @b: second CDCLK configuration 1838 * 1839 * Returns: 1840 * True if the CDCLK configurations don't match, false if they do. 1841 */ 1842 static bool intel_cdclk_changed(const struct intel_cdclk_config *a, 1843 const struct intel_cdclk_config *b) 1844 { 1845 return intel_cdclk_needs_modeset(a, b) || 1846 a->voltage_level != b->voltage_level; 1847 } 1848 1849 void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config, 1850 const char *context) 1851 { 1852 DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", 1853 context, cdclk_config->cdclk, cdclk_config->vco, 1854 cdclk_config->ref, cdclk_config->bypass, 1855 cdclk_config->voltage_level); 1856 } 1857 1858 /** 1859 * intel_set_cdclk - Push the CDCLK configuration to the hardware 1860 * @dev_priv: i915 device 1861 * @cdclk_config: new CDCLK configuration 1862 * @pipe: pipe with which to synchronize the update 1863 * 1864 * Program the hardware based on the passed in CDCLK state, 1865 * if necessary. 1866 */ 1867 static void intel_set_cdclk(struct drm_i915_private *dev_priv, 1868 const struct intel_cdclk_config *cdclk_config, 1869 enum pipe pipe) 1870 { 1871 if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config)) 1872 return; 1873 1874 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.set_cdclk)) 1875 return; 1876 1877 intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to"); 1878 1879 dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe); 1880 1881 if (drm_WARN(&dev_priv->drm, 1882 intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config), 1883 "cdclk state doesn't match!\n")) { 1884 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "[hw state]"); 1885 intel_dump_cdclk_config(cdclk_config, "[sw state]"); 1886 } 1887 } 1888 1889 /** 1890 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware 1891 * @state: intel atomic state 1892 * 1893 * Program the hardware before updating the HW plane state based on the 1894 * new CDCLK state, if necessary. 1895 */ 1896 void 1897 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) 1898 { 1899 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1900 const struct intel_cdclk_state *old_cdclk_state = 1901 intel_atomic_get_old_cdclk_state(state); 1902 const struct intel_cdclk_state *new_cdclk_state = 1903 intel_atomic_get_new_cdclk_state(state); 1904 enum pipe pipe = new_cdclk_state->pipe; 1905 1906 if (!intel_cdclk_changed(&old_cdclk_state->actual, 1907 &new_cdclk_state->actual)) 1908 return; 1909 1910 if (pipe == INVALID_PIPE || 1911 old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) { 1912 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); 1913 1914 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); 1915 } 1916 } 1917 1918 /** 1919 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware 1920 * @state: intel atomic state 1921 * 1922 * Program the hardware after updating the HW plane state based on the 1923 * new CDCLK state, if necessary. 1924 */ 1925 void 1926 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) 1927 { 1928 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1929 const struct intel_cdclk_state *old_cdclk_state = 1930 intel_atomic_get_old_cdclk_state(state); 1931 const struct intel_cdclk_state *new_cdclk_state = 1932 intel_atomic_get_new_cdclk_state(state); 1933 enum pipe pipe = new_cdclk_state->pipe; 1934 1935 if (!intel_cdclk_changed(&old_cdclk_state->actual, 1936 &new_cdclk_state->actual)) 1937 return; 1938 1939 if (pipe != INVALID_PIPE && 1940 old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) { 1941 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); 1942 1943 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); 1944 } 1945 } 1946 1947 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) 1948 { 1949 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1950 int pixel_rate = crtc_state->pixel_rate; 1951 1952 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 1953 return DIV_ROUND_UP(pixel_rate, 2); 1954 else if (IS_GEN(dev_priv, 9) || 1955 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 1956 return pixel_rate; 1957 else if (IS_CHERRYVIEW(dev_priv)) 1958 return DIV_ROUND_UP(pixel_rate * 100, 95); 1959 else if (crtc_state->double_wide) 1960 return DIV_ROUND_UP(pixel_rate * 100, 90 * 2); 1961 else 1962 return DIV_ROUND_UP(pixel_rate * 100, 90); 1963 } 1964 1965 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) 1966 { 1967 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1968 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1969 struct intel_plane *plane; 1970 int min_cdclk = 0; 1971 1972 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 1973 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk); 1974 1975 return min_cdclk; 1976 } 1977 1978 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) 1979 { 1980 struct drm_i915_private *dev_priv = 1981 to_i915(crtc_state->uapi.crtc->dev); 1982 int min_cdclk; 1983 1984 if (!crtc_state->hw.enable) 1985 return 0; 1986 1987 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state); 1988 1989 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ 1990 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state)) 1991 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95); 1992 1993 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, 1994 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else 1995 * there may be audio corruption or screen corruption." This cdclk 1996 * restriction for GLK is 316.8 MHz. 1997 */ 1998 if (intel_crtc_has_dp_encoder(crtc_state) && 1999 crtc_state->has_audio && 2000 crtc_state->port_clock >= 540000 && 2001 crtc_state->lane_count == 4) { 2002 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { 2003 /* Display WA #1145: glk,cnl */ 2004 min_cdclk = max(316800, min_cdclk); 2005 } else if (IS_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv)) { 2006 /* Display WA #1144: skl,bxt */ 2007 min_cdclk = max(432000, min_cdclk); 2008 } 2009 } 2010 2011 /* 2012 * According to BSpec, "The CD clock frequency must be at least twice 2013 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. 2014 */ 2015 if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) 2016 min_cdclk = max(2 * 96000, min_cdclk); 2017 2018 /* 2019 * "For DP audio configuration, cdclk frequency shall be set to 2020 * meet the following requirements: 2021 * DP Link Frequency(MHz) | Cdclk frequency(MHz) 2022 * 270 | 320 or higher 2023 * 162 | 200 or higher" 2024 */ 2025 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2026 intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio) 2027 min_cdclk = max(crtc_state->port_clock, min_cdclk); 2028 2029 /* 2030 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower 2031 * than 320000KHz. 2032 */ 2033 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 2034 IS_VALLEYVIEW(dev_priv)) 2035 min_cdclk = max(320000, min_cdclk); 2036 2037 /* 2038 * On Geminilake once the CDCLK gets as low as 79200 2039 * picture gets unstable, despite that values are 2040 * correct for DSI PLL and DE PLL. 2041 */ 2042 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 2043 IS_GEMINILAKE(dev_priv)) 2044 min_cdclk = max(158400, min_cdclk); 2045 2046 /* Account for additional needs from the planes */ 2047 min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); 2048 2049 /* 2050 * HACK. Currently for TGL platforms we calculate 2051 * min_cdclk initially based on pixel_rate divided 2052 * by 2, accounting for also plane requirements, 2053 * however in some cases the lowest possible CDCLK 2054 * doesn't work and causing the underruns. 2055 * Explicitly stating here that this seems to be currently 2056 * rather a Hack, than final solution. 2057 */ 2058 if (IS_TIGERLAKE(dev_priv)) 2059 min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); 2060 2061 if (min_cdclk > dev_priv->max_cdclk_freq) { 2062 drm_dbg_kms(&dev_priv->drm, 2063 "required cdclk (%d kHz) exceeds max (%d kHz)\n", 2064 min_cdclk, dev_priv->max_cdclk_freq); 2065 return -EINVAL; 2066 } 2067 2068 return min_cdclk; 2069 } 2070 2071 static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) 2072 { 2073 struct intel_atomic_state *state = cdclk_state->base.state; 2074 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2075 struct intel_crtc *crtc; 2076 struct intel_crtc_state *crtc_state; 2077 int min_cdclk, i; 2078 enum pipe pipe; 2079 2080 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2081 int ret; 2082 2083 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 2084 if (min_cdclk < 0) 2085 return min_cdclk; 2086 2087 if (cdclk_state->min_cdclk[i] == min_cdclk) 2088 continue; 2089 2090 cdclk_state->min_cdclk[i] = min_cdclk; 2091 2092 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2093 if (ret) 2094 return ret; 2095 } 2096 2097 min_cdclk = cdclk_state->force_min_cdclk; 2098 for_each_pipe(dev_priv, pipe) 2099 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); 2100 2101 return min_cdclk; 2102 } 2103 2104 /* 2105 * Account for port clock min voltage level requirements. 2106 * This only really does something on CNL+ but can be 2107 * called on earlier platforms as well. 2108 * 2109 * Note that this functions assumes that 0 is 2110 * the lowest voltage value, and higher values 2111 * correspond to increasingly higher voltages. 2112 * 2113 * Should that relationship no longer hold on 2114 * future platforms this code will need to be 2115 * adjusted. 2116 */ 2117 static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state) 2118 { 2119 struct intel_atomic_state *state = cdclk_state->base.state; 2120 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2121 struct intel_crtc *crtc; 2122 struct intel_crtc_state *crtc_state; 2123 u8 min_voltage_level; 2124 int i; 2125 enum pipe pipe; 2126 2127 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2128 int ret; 2129 2130 if (crtc_state->hw.enable) 2131 min_voltage_level = crtc_state->min_voltage_level; 2132 else 2133 min_voltage_level = 0; 2134 2135 if (cdclk_state->min_voltage_level[i] == min_voltage_level) 2136 continue; 2137 2138 cdclk_state->min_voltage_level[i] = min_voltage_level; 2139 2140 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2141 if (ret) 2142 return ret; 2143 } 2144 2145 min_voltage_level = 0; 2146 for_each_pipe(dev_priv, pipe) 2147 min_voltage_level = max(cdclk_state->min_voltage_level[pipe], 2148 min_voltage_level); 2149 2150 return min_voltage_level; 2151 } 2152 2153 static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2154 { 2155 struct intel_atomic_state *state = cdclk_state->base.state; 2156 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2157 int min_cdclk, cdclk; 2158 2159 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2160 if (min_cdclk < 0) 2161 return min_cdclk; 2162 2163 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); 2164 2165 cdclk_state->logical.cdclk = cdclk; 2166 cdclk_state->logical.voltage_level = 2167 vlv_calc_voltage_level(dev_priv, cdclk); 2168 2169 if (!cdclk_state->active_pipes) { 2170 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); 2171 2172 cdclk_state->actual.cdclk = cdclk; 2173 cdclk_state->actual.voltage_level = 2174 vlv_calc_voltage_level(dev_priv, cdclk); 2175 } else { 2176 cdclk_state->actual = cdclk_state->logical; 2177 } 2178 2179 return 0; 2180 } 2181 2182 static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2183 { 2184 int min_cdclk, cdclk; 2185 2186 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2187 if (min_cdclk < 0) 2188 return min_cdclk; 2189 2190 /* 2191 * FIXME should also account for plane ratio 2192 * once 64bpp pixel formats are supported. 2193 */ 2194 cdclk = bdw_calc_cdclk(min_cdclk); 2195 2196 cdclk_state->logical.cdclk = cdclk; 2197 cdclk_state->logical.voltage_level = 2198 bdw_calc_voltage_level(cdclk); 2199 2200 if (!cdclk_state->active_pipes) { 2201 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); 2202 2203 cdclk_state->actual.cdclk = cdclk; 2204 cdclk_state->actual.voltage_level = 2205 bdw_calc_voltage_level(cdclk); 2206 } else { 2207 cdclk_state->actual = cdclk_state->logical; 2208 } 2209 2210 return 0; 2211 } 2212 2213 static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state) 2214 { 2215 struct intel_atomic_state *state = cdclk_state->base.state; 2216 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2217 struct intel_crtc *crtc; 2218 struct intel_crtc_state *crtc_state; 2219 int vco, i; 2220 2221 vco = cdclk_state->logical.vco; 2222 if (!vco) 2223 vco = dev_priv->skl_preferred_vco_freq; 2224 2225 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2226 if (!crtc_state->hw.enable) 2227 continue; 2228 2229 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 2230 continue; 2231 2232 /* 2233 * DPLL0 VCO may need to be adjusted to get the correct 2234 * clock for eDP. This will affect cdclk as well. 2235 */ 2236 switch (crtc_state->port_clock / 2) { 2237 case 108000: 2238 case 216000: 2239 vco = 8640000; 2240 break; 2241 default: 2242 vco = 8100000; 2243 break; 2244 } 2245 } 2246 2247 return vco; 2248 } 2249 2250 static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2251 { 2252 int min_cdclk, cdclk, vco; 2253 2254 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2255 if (min_cdclk < 0) 2256 return min_cdclk; 2257 2258 vco = skl_dpll0_vco(cdclk_state); 2259 2260 /* 2261 * FIXME should also account for plane ratio 2262 * once 64bpp pixel formats are supported. 2263 */ 2264 cdclk = skl_calc_cdclk(min_cdclk, vco); 2265 2266 cdclk_state->logical.vco = vco; 2267 cdclk_state->logical.cdclk = cdclk; 2268 cdclk_state->logical.voltage_level = 2269 skl_calc_voltage_level(cdclk); 2270 2271 if (!cdclk_state->active_pipes) { 2272 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); 2273 2274 cdclk_state->actual.vco = vco; 2275 cdclk_state->actual.cdclk = cdclk; 2276 cdclk_state->actual.voltage_level = 2277 skl_calc_voltage_level(cdclk); 2278 } else { 2279 cdclk_state->actual = cdclk_state->logical; 2280 } 2281 2282 return 0; 2283 } 2284 2285 static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2286 { 2287 struct intel_atomic_state *state = cdclk_state->base.state; 2288 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2289 int min_cdclk, min_voltage_level, cdclk, vco; 2290 2291 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2292 if (min_cdclk < 0) 2293 return min_cdclk; 2294 2295 min_voltage_level = bxt_compute_min_voltage_level(cdclk_state); 2296 if (min_voltage_level < 0) 2297 return min_voltage_level; 2298 2299 cdclk = bxt_calc_cdclk(dev_priv, min_cdclk); 2300 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 2301 2302 cdclk_state->logical.vco = vco; 2303 cdclk_state->logical.cdclk = cdclk; 2304 cdclk_state->logical.voltage_level = 2305 max_t(int, min_voltage_level, 2306 dev_priv->display.calc_voltage_level(cdclk)); 2307 2308 if (!cdclk_state->active_pipes) { 2309 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); 2310 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 2311 2312 cdclk_state->actual.vco = vco; 2313 cdclk_state->actual.cdclk = cdclk; 2314 cdclk_state->actual.voltage_level = 2315 dev_priv->display.calc_voltage_level(cdclk); 2316 } else { 2317 cdclk_state->actual = cdclk_state->logical; 2318 } 2319 2320 return 0; 2321 } 2322 2323 static int intel_modeset_all_pipes(struct intel_atomic_state *state) 2324 { 2325 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2326 struct intel_crtc *crtc; 2327 2328 /* 2329 * Add all pipes to the state, and force 2330 * a modeset on all the active ones. 2331 */ 2332 for_each_intel_crtc(&dev_priv->drm, crtc) { 2333 struct intel_crtc_state *crtc_state; 2334 int ret; 2335 2336 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 2337 if (IS_ERR(crtc_state)) 2338 return PTR_ERR(crtc_state); 2339 2340 if (!crtc_state->hw.active || 2341 drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) 2342 continue; 2343 2344 crtc_state->uapi.mode_changed = true; 2345 2346 ret = drm_atomic_add_affected_connectors(&state->base, 2347 &crtc->base); 2348 if (ret) 2349 return ret; 2350 2351 ret = drm_atomic_add_affected_planes(&state->base, 2352 &crtc->base); 2353 if (ret) 2354 return ret; 2355 2356 crtc_state->update_planes |= crtc_state->active_planes; 2357 } 2358 2359 return 0; 2360 } 2361 2362 static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2363 { 2364 int min_cdclk; 2365 2366 /* 2367 * We can't change the cdclk frequency, but we still want to 2368 * check that the required minimum frequency doesn't exceed 2369 * the actual cdclk frequency. 2370 */ 2371 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2372 if (min_cdclk < 0) 2373 return min_cdclk; 2374 2375 return 0; 2376 } 2377 2378 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj) 2379 { 2380 struct intel_cdclk_state *cdclk_state; 2381 2382 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); 2383 if (!cdclk_state) 2384 return NULL; 2385 2386 cdclk_state->force_min_cdclk_changed = false; 2387 cdclk_state->pipe = INVALID_PIPE; 2388 2389 return &cdclk_state->base; 2390 } 2391 2392 static void intel_cdclk_destroy_state(struct intel_global_obj *obj, 2393 struct intel_global_state *state) 2394 { 2395 kfree(state); 2396 } 2397 2398 static const struct intel_global_state_funcs intel_cdclk_funcs = { 2399 .atomic_duplicate_state = intel_cdclk_duplicate_state, 2400 .atomic_destroy_state = intel_cdclk_destroy_state, 2401 }; 2402 2403 struct intel_cdclk_state * 2404 intel_atomic_get_cdclk_state(struct intel_atomic_state *state) 2405 { 2406 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2407 struct intel_global_state *cdclk_state; 2408 2409 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->cdclk.obj); 2410 if (IS_ERR(cdclk_state)) 2411 return ERR_CAST(cdclk_state); 2412 2413 return to_intel_cdclk_state(cdclk_state); 2414 } 2415 2416 int intel_cdclk_init(struct drm_i915_private *dev_priv) 2417 { 2418 struct intel_cdclk_state *cdclk_state; 2419 2420 cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL); 2421 if (!cdclk_state) 2422 return -ENOMEM; 2423 2424 intel_atomic_global_obj_init(dev_priv, &dev_priv->cdclk.obj, 2425 &cdclk_state->base, &intel_cdclk_funcs); 2426 2427 return 0; 2428 } 2429 2430 int intel_modeset_calc_cdclk(struct intel_atomic_state *state) 2431 { 2432 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2433 const struct intel_cdclk_state *old_cdclk_state; 2434 struct intel_cdclk_state *new_cdclk_state; 2435 enum pipe pipe; 2436 int ret; 2437 2438 new_cdclk_state = intel_atomic_get_cdclk_state(state); 2439 if (IS_ERR(new_cdclk_state)) 2440 return PTR_ERR(new_cdclk_state); 2441 2442 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 2443 2444 new_cdclk_state->active_pipes = 2445 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); 2446 2447 ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state); 2448 if (ret) 2449 return ret; 2450 2451 if (intel_cdclk_changed(&old_cdclk_state->actual, 2452 &new_cdclk_state->actual)) { 2453 /* 2454 * Also serialize commits across all crtcs 2455 * if the actual hw needs to be poked. 2456 */ 2457 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); 2458 if (ret) 2459 return ret; 2460 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes || 2461 intel_cdclk_changed(&old_cdclk_state->logical, 2462 &new_cdclk_state->logical)) { 2463 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 2464 if (ret) 2465 return ret; 2466 } else { 2467 return 0; 2468 } 2469 2470 if (is_power_of_2(new_cdclk_state->active_pipes) && 2471 intel_cdclk_can_cd2x_update(dev_priv, 2472 &old_cdclk_state->actual, 2473 &new_cdclk_state->actual)) { 2474 struct intel_crtc *crtc; 2475 struct intel_crtc_state *crtc_state; 2476 2477 pipe = ilog2(new_cdclk_state->active_pipes); 2478 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 2479 2480 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 2481 if (IS_ERR(crtc_state)) 2482 return PTR_ERR(crtc_state); 2483 2484 if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) 2485 pipe = INVALID_PIPE; 2486 } else { 2487 pipe = INVALID_PIPE; 2488 } 2489 2490 if (pipe != INVALID_PIPE) { 2491 new_cdclk_state->pipe = pipe; 2492 2493 drm_dbg_kms(&dev_priv->drm, 2494 "Can change cdclk with pipe %c active\n", 2495 pipe_name(pipe)); 2496 } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual, 2497 &new_cdclk_state->actual)) { 2498 /* All pipes must be switched off while we change the cdclk. */ 2499 ret = intel_modeset_all_pipes(state); 2500 if (ret) 2501 return ret; 2502 2503 new_cdclk_state->pipe = INVALID_PIPE; 2504 2505 drm_dbg_kms(&dev_priv->drm, 2506 "Modeset required for cdclk change\n"); 2507 } 2508 2509 drm_dbg_kms(&dev_priv->drm, 2510 "New cdclk calculated to be logical %u kHz, actual %u kHz\n", 2511 new_cdclk_state->logical.cdclk, 2512 new_cdclk_state->actual.cdclk); 2513 drm_dbg_kms(&dev_priv->drm, 2514 "New voltage level calculated to be logical %u, actual %u\n", 2515 new_cdclk_state->logical.voltage_level, 2516 new_cdclk_state->actual.voltage_level); 2517 2518 return 0; 2519 } 2520 2521 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) 2522 { 2523 int max_cdclk_freq = dev_priv->max_cdclk_freq; 2524 2525 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 2526 return 2 * max_cdclk_freq; 2527 else if (IS_GEN(dev_priv, 9) || 2528 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2529 return max_cdclk_freq; 2530 else if (IS_CHERRYVIEW(dev_priv)) 2531 return max_cdclk_freq*95/100; 2532 else if (INTEL_GEN(dev_priv) < 4) 2533 return 2*max_cdclk_freq*90/100; 2534 else 2535 return max_cdclk_freq*90/100; 2536 } 2537 2538 /** 2539 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency 2540 * @dev_priv: i915 device 2541 * 2542 * Determine the maximum CDCLK frequency the platform supports, and also 2543 * derive the maximum dot clock frequency the maximum CDCLK frequency 2544 * allows. 2545 */ 2546 void intel_update_max_cdclk(struct drm_i915_private *dev_priv) 2547 { 2548 if (IS_ELKHARTLAKE(dev_priv)) { 2549 if (dev_priv->cdclk.hw.ref == 24000) 2550 dev_priv->max_cdclk_freq = 552000; 2551 else 2552 dev_priv->max_cdclk_freq = 556800; 2553 } else if (INTEL_GEN(dev_priv) >= 11) { 2554 if (dev_priv->cdclk.hw.ref == 24000) 2555 dev_priv->max_cdclk_freq = 648000; 2556 else 2557 dev_priv->max_cdclk_freq = 652800; 2558 } else if (IS_CANNONLAKE(dev_priv)) { 2559 dev_priv->max_cdclk_freq = 528000; 2560 } else if (IS_GEN9_BC(dev_priv)) { 2561 u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; 2562 int max_cdclk, vco; 2563 2564 vco = dev_priv->skl_preferred_vco_freq; 2565 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); 2566 2567 /* 2568 * Use the lower (vco 8640) cdclk values as a 2569 * first guess. skl_calc_cdclk() will correct it 2570 * if the preferred vco is 8100 instead. 2571 */ 2572 if (limit == SKL_DFSM_CDCLK_LIMIT_675) 2573 max_cdclk = 617143; 2574 else if (limit == SKL_DFSM_CDCLK_LIMIT_540) 2575 max_cdclk = 540000; 2576 else if (limit == SKL_DFSM_CDCLK_LIMIT_450) 2577 max_cdclk = 432000; 2578 else 2579 max_cdclk = 308571; 2580 2581 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); 2582 } else if (IS_GEMINILAKE(dev_priv)) { 2583 dev_priv->max_cdclk_freq = 316800; 2584 } else if (IS_BROXTON(dev_priv)) { 2585 dev_priv->max_cdclk_freq = 624000; 2586 } else if (IS_BROADWELL(dev_priv)) { 2587 /* 2588 * FIXME with extra cooling we can allow 2589 * 540 MHz for ULX and 675 Mhz for ULT. 2590 * How can we know if extra cooling is 2591 * available? PCI ID, VTB, something else? 2592 */ 2593 if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 2594 dev_priv->max_cdclk_freq = 450000; 2595 else if (IS_BDW_ULX(dev_priv)) 2596 dev_priv->max_cdclk_freq = 450000; 2597 else if (IS_BDW_ULT(dev_priv)) 2598 dev_priv->max_cdclk_freq = 540000; 2599 else 2600 dev_priv->max_cdclk_freq = 675000; 2601 } else if (IS_CHERRYVIEW(dev_priv)) { 2602 dev_priv->max_cdclk_freq = 320000; 2603 } else if (IS_VALLEYVIEW(dev_priv)) { 2604 dev_priv->max_cdclk_freq = 400000; 2605 } else { 2606 /* otherwise assume cdclk is fixed */ 2607 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk; 2608 } 2609 2610 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); 2611 2612 drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n", 2613 dev_priv->max_cdclk_freq); 2614 2615 drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n", 2616 dev_priv->max_dotclk_freq); 2617 } 2618 2619 /** 2620 * intel_update_cdclk - Determine the current CDCLK frequency 2621 * @dev_priv: i915 device 2622 * 2623 * Determine the current CDCLK frequency. 2624 */ 2625 void intel_update_cdclk(struct drm_i915_private *dev_priv) 2626 { 2627 dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw); 2628 2629 /* 2630 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): 2631 * Programmng [sic] note: bit[9:2] should be programmed to the number 2632 * of cdclk that generates 4MHz reference clock freq which is used to 2633 * generate GMBus clock. This will vary with the cdclk freq. 2634 */ 2635 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 2636 intel_de_write(dev_priv, GMBUSFREQ_VLV, 2637 DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000)); 2638 } 2639 2640 static int cnp_rawclk(struct drm_i915_private *dev_priv) 2641 { 2642 u32 rawclk; 2643 int divider, fraction; 2644 2645 if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { 2646 /* 24 MHz */ 2647 divider = 24000; 2648 fraction = 0; 2649 } else { 2650 /* 19.2 MHz */ 2651 divider = 19000; 2652 fraction = 200; 2653 } 2654 2655 rawclk = CNP_RAWCLK_DIV(divider / 1000); 2656 if (fraction) { 2657 int numerator = 1; 2658 2659 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000, 2660 fraction) - 1); 2661 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 2662 rawclk |= ICP_RAWCLK_NUM(numerator); 2663 } 2664 2665 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk); 2666 return divider + fraction; 2667 } 2668 2669 static int pch_rawclk(struct drm_i915_private *dev_priv) 2670 { 2671 return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; 2672 } 2673 2674 static int vlv_hrawclk(struct drm_i915_private *dev_priv) 2675 { 2676 /* RAWCLK_FREQ_VLV register updated from power well code */ 2677 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", 2678 CCK_DISPLAY_REF_CLOCK_CONTROL); 2679 } 2680 2681 static int g4x_hrawclk(struct drm_i915_private *dev_priv) 2682 { 2683 u32 clkcfg; 2684 2685 /* hrawclock is 1/4 the FSB frequency */ 2686 clkcfg = intel_de_read(dev_priv, CLKCFG); 2687 switch (clkcfg & CLKCFG_FSB_MASK) { 2688 case CLKCFG_FSB_400: 2689 return 100000; 2690 case CLKCFG_FSB_533: 2691 return 133333; 2692 case CLKCFG_FSB_667: 2693 return 166667; 2694 case CLKCFG_FSB_800: 2695 return 200000; 2696 case CLKCFG_FSB_1067: 2697 case CLKCFG_FSB_1067_ALT: 2698 return 266667; 2699 case CLKCFG_FSB_1333: 2700 case CLKCFG_FSB_1333_ALT: 2701 return 333333; 2702 default: 2703 return 133333; 2704 } 2705 } 2706 2707 /** 2708 * intel_read_rawclk - Determine the current RAWCLK frequency 2709 * @dev_priv: i915 device 2710 * 2711 * Determine the current RAWCLK frequency. RAWCLK is a fixed 2712 * frequency clock so this needs to done only once. 2713 */ 2714 u32 intel_read_rawclk(struct drm_i915_private *dev_priv) 2715 { 2716 u32 freq; 2717 2718 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) 2719 freq = cnp_rawclk(dev_priv); 2720 else if (HAS_PCH_SPLIT(dev_priv)) 2721 freq = pch_rawclk(dev_priv); 2722 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 2723 freq = vlv_hrawclk(dev_priv); 2724 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) 2725 freq = g4x_hrawclk(dev_priv); 2726 else 2727 /* no rawclk on other platforms, or no need to know it */ 2728 return 0; 2729 2730 return freq; 2731 } 2732 2733 /** 2734 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks 2735 * @dev_priv: i915 device 2736 */ 2737 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) 2738 { 2739 if (INTEL_GEN(dev_priv) >= 12) { 2740 dev_priv->display.set_cdclk = bxt_set_cdclk; 2741 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; 2742 dev_priv->display.calc_voltage_level = tgl_calc_voltage_level; 2743 dev_priv->cdclk.table = icl_cdclk_table; 2744 } else if (IS_ELKHARTLAKE(dev_priv)) { 2745 dev_priv->display.set_cdclk = bxt_set_cdclk; 2746 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; 2747 dev_priv->display.calc_voltage_level = ehl_calc_voltage_level; 2748 dev_priv->cdclk.table = icl_cdclk_table; 2749 } else if (INTEL_GEN(dev_priv) >= 11) { 2750 dev_priv->display.set_cdclk = bxt_set_cdclk; 2751 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; 2752 dev_priv->display.calc_voltage_level = icl_calc_voltage_level; 2753 dev_priv->cdclk.table = icl_cdclk_table; 2754 } else if (IS_CANNONLAKE(dev_priv)) { 2755 dev_priv->display.set_cdclk = bxt_set_cdclk; 2756 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; 2757 dev_priv->display.calc_voltage_level = cnl_calc_voltage_level; 2758 dev_priv->cdclk.table = cnl_cdclk_table; 2759 } else if (IS_GEN9_LP(dev_priv)) { 2760 dev_priv->display.set_cdclk = bxt_set_cdclk; 2761 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; 2762 dev_priv->display.calc_voltage_level = bxt_calc_voltage_level; 2763 if (IS_GEMINILAKE(dev_priv)) 2764 dev_priv->cdclk.table = glk_cdclk_table; 2765 else 2766 dev_priv->cdclk.table = bxt_cdclk_table; 2767 } else if (IS_GEN9_BC(dev_priv)) { 2768 dev_priv->display.set_cdclk = skl_set_cdclk; 2769 dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk; 2770 } else if (IS_BROADWELL(dev_priv)) { 2771 dev_priv->display.set_cdclk = bdw_set_cdclk; 2772 dev_priv->display.modeset_calc_cdclk = bdw_modeset_calc_cdclk; 2773 } else if (IS_CHERRYVIEW(dev_priv)) { 2774 dev_priv->display.set_cdclk = chv_set_cdclk; 2775 dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk; 2776 } else if (IS_VALLEYVIEW(dev_priv)) { 2777 dev_priv->display.set_cdclk = vlv_set_cdclk; 2778 dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk; 2779 } else { 2780 dev_priv->display.modeset_calc_cdclk = fixed_modeset_calc_cdclk; 2781 } 2782 2783 if (INTEL_GEN(dev_priv) >= 10 || IS_GEN9_LP(dev_priv)) 2784 dev_priv->display.get_cdclk = bxt_get_cdclk; 2785 else if (IS_GEN9_BC(dev_priv)) 2786 dev_priv->display.get_cdclk = skl_get_cdclk; 2787 else if (IS_BROADWELL(dev_priv)) 2788 dev_priv->display.get_cdclk = bdw_get_cdclk; 2789 else if (IS_HASWELL(dev_priv)) 2790 dev_priv->display.get_cdclk = hsw_get_cdclk; 2791 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 2792 dev_priv->display.get_cdclk = vlv_get_cdclk; 2793 else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) 2794 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; 2795 else if (IS_GEN(dev_priv, 5)) 2796 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk; 2797 else if (IS_GM45(dev_priv)) 2798 dev_priv->display.get_cdclk = gm45_get_cdclk; 2799 else if (IS_G45(dev_priv)) 2800 dev_priv->display.get_cdclk = g33_get_cdclk; 2801 else if (IS_I965GM(dev_priv)) 2802 dev_priv->display.get_cdclk = i965gm_get_cdclk; 2803 else if (IS_I965G(dev_priv)) 2804 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; 2805 else if (IS_PINEVIEW(dev_priv)) 2806 dev_priv->display.get_cdclk = pnv_get_cdclk; 2807 else if (IS_G33(dev_priv)) 2808 dev_priv->display.get_cdclk = g33_get_cdclk; 2809 else if (IS_I945GM(dev_priv)) 2810 dev_priv->display.get_cdclk = i945gm_get_cdclk; 2811 else if (IS_I945G(dev_priv)) 2812 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; 2813 else if (IS_I915GM(dev_priv)) 2814 dev_priv->display.get_cdclk = i915gm_get_cdclk; 2815 else if (IS_I915G(dev_priv)) 2816 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk; 2817 else if (IS_I865G(dev_priv)) 2818 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk; 2819 else if (IS_I85X(dev_priv)) 2820 dev_priv->display.get_cdclk = i85x_get_cdclk; 2821 else if (IS_I845G(dev_priv)) 2822 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk; 2823 else { /* 830 */ 2824 drm_WARN(&dev_priv->drm, !IS_I830(dev_priv), 2825 "Unknown platform. Assuming 133 MHz CDCLK\n"); 2826 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk; 2827 } 2828 } 2829