1 /* 2 * Copyright © 2006-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/time.h> 25 26 #include "hsw_ips.h" 27 #include "i915_reg.h" 28 #include "intel_atomic.h" 29 #include "intel_atomic_plane.h" 30 #include "intel_audio.h" 31 #include "intel_bw.h" 32 #include "intel_cdclk.h" 33 #include "intel_crtc.h" 34 #include "intel_de.h" 35 #include "intel_display_types.h" 36 #include "intel_mchbar_regs.h" 37 #include "intel_pci_config.h" 38 #include "intel_pcode.h" 39 #include "intel_psr.h" 40 #include "vlv_sideband.h" 41 42 /** 43 * DOC: CDCLK / RAWCLK 44 * 45 * The display engine uses several different clocks to do its work. There 46 * are two main clocks involved that aren't directly related to the actual 47 * pixel clock or any symbol/bit clock of the actual output port. These 48 * are the core display clock (CDCLK) and RAWCLK. 49 * 50 * CDCLK clocks most of the display pipe logic, and thus its frequency 51 * must be high enough to support the rate at which pixels are flowing 52 * through the pipes. Downscaling must also be accounted as that increases 53 * the effective pixel rate. 54 * 55 * On several platforms the CDCLK frequency can be changed dynamically 56 * to minimize power consumption for a given display configuration. 57 * Typically changes to the CDCLK frequency require all the display pipes 58 * to be shut down while the frequency is being changed. 59 * 60 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. 61 * DMC will not change the active CDCLK frequency however, so that part 62 * will still be performed by the driver directly. 63 * 64 * RAWCLK is a fixed frequency clock, often used by various auxiliary 65 * blocks such as AUX CH or backlight PWM. Hence the only thing we 66 * really need to know about RAWCLK is its frequency so that various 67 * dividers can be programmed correctly. 68 */ 69 70 struct intel_cdclk_funcs { 71 void (*get_cdclk)(struct drm_i915_private *i915, 72 struct intel_cdclk_config *cdclk_config); 73 void (*set_cdclk)(struct drm_i915_private *i915, 74 const struct intel_cdclk_config *cdclk_config, 75 enum pipe pipe); 76 int (*modeset_calc_cdclk)(struct intel_cdclk_state *state); 77 u8 (*calc_voltage_level)(int cdclk); 78 }; 79 80 void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv, 81 struct intel_cdclk_config *cdclk_config) 82 { 83 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); 84 } 85 86 static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv, 87 const struct intel_cdclk_config *cdclk_config, 88 enum pipe pipe) 89 { 90 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); 91 } 92 93 static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv, 94 struct intel_cdclk_state *cdclk_config) 95 { 96 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config); 97 } 98 99 static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv, 100 int cdclk) 101 { 102 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); 103 } 104 105 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, 106 struct intel_cdclk_config *cdclk_config) 107 { 108 cdclk_config->cdclk = 133333; 109 } 110 111 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, 112 struct intel_cdclk_config *cdclk_config) 113 { 114 cdclk_config->cdclk = 200000; 115 } 116 117 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, 118 struct intel_cdclk_config *cdclk_config) 119 { 120 cdclk_config->cdclk = 266667; 121 } 122 123 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, 124 struct intel_cdclk_config *cdclk_config) 125 { 126 cdclk_config->cdclk = 333333; 127 } 128 129 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, 130 struct intel_cdclk_config *cdclk_config) 131 { 132 cdclk_config->cdclk = 400000; 133 } 134 135 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, 136 struct intel_cdclk_config *cdclk_config) 137 { 138 cdclk_config->cdclk = 450000; 139 } 140 141 static void i85x_get_cdclk(struct drm_i915_private *dev_priv, 142 struct intel_cdclk_config *cdclk_config) 143 { 144 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 145 u16 hpllcc = 0; 146 147 /* 148 * 852GM/852GMV only supports 133 MHz and the HPLLCC 149 * encoding is different :( 150 * FIXME is this the right way to detect 852GM/852GMV? 151 */ 152 if (pdev->revision == 0x1) { 153 cdclk_config->cdclk = 133333; 154 return; 155 } 156 157 pci_bus_read_config_word(pdev->bus, 158 PCI_DEVFN(0, 3), HPLLCC, &hpllcc); 159 160 /* Assume that the hardware is in the high speed state. This 161 * should be the default. 162 */ 163 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 164 case GC_CLOCK_133_200: 165 case GC_CLOCK_133_200_2: 166 case GC_CLOCK_100_200: 167 cdclk_config->cdclk = 200000; 168 break; 169 case GC_CLOCK_166_250: 170 cdclk_config->cdclk = 250000; 171 break; 172 case GC_CLOCK_100_133: 173 cdclk_config->cdclk = 133333; 174 break; 175 case GC_CLOCK_133_266: 176 case GC_CLOCK_133_266_2: 177 case GC_CLOCK_166_266: 178 cdclk_config->cdclk = 266667; 179 break; 180 } 181 } 182 183 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, 184 struct intel_cdclk_config *cdclk_config) 185 { 186 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 187 u16 gcfgc = 0; 188 189 pci_read_config_word(pdev, GCFGC, &gcfgc); 190 191 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 192 cdclk_config->cdclk = 133333; 193 return; 194 } 195 196 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 197 case GC_DISPLAY_CLOCK_333_320_MHZ: 198 cdclk_config->cdclk = 333333; 199 break; 200 default: 201 case GC_DISPLAY_CLOCK_190_200_MHZ: 202 cdclk_config->cdclk = 190000; 203 break; 204 } 205 } 206 207 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, 208 struct intel_cdclk_config *cdclk_config) 209 { 210 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 211 u16 gcfgc = 0; 212 213 pci_read_config_word(pdev, GCFGC, &gcfgc); 214 215 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 216 cdclk_config->cdclk = 133333; 217 return; 218 } 219 220 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 221 case GC_DISPLAY_CLOCK_333_320_MHZ: 222 cdclk_config->cdclk = 320000; 223 break; 224 default: 225 case GC_DISPLAY_CLOCK_190_200_MHZ: 226 cdclk_config->cdclk = 200000; 227 break; 228 } 229 } 230 231 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) 232 { 233 static const unsigned int blb_vco[8] = { 234 [0] = 3200000, 235 [1] = 4000000, 236 [2] = 5333333, 237 [3] = 4800000, 238 [4] = 6400000, 239 }; 240 static const unsigned int pnv_vco[8] = { 241 [0] = 3200000, 242 [1] = 4000000, 243 [2] = 5333333, 244 [3] = 4800000, 245 [4] = 2666667, 246 }; 247 static const unsigned int cl_vco[8] = { 248 [0] = 3200000, 249 [1] = 4000000, 250 [2] = 5333333, 251 [3] = 6400000, 252 [4] = 3333333, 253 [5] = 3566667, 254 [6] = 4266667, 255 }; 256 static const unsigned int elk_vco[8] = { 257 [0] = 3200000, 258 [1] = 4000000, 259 [2] = 5333333, 260 [3] = 4800000, 261 }; 262 static const unsigned int ctg_vco[8] = { 263 [0] = 3200000, 264 [1] = 4000000, 265 [2] = 5333333, 266 [3] = 6400000, 267 [4] = 2666667, 268 [5] = 4266667, 269 }; 270 const unsigned int *vco_table; 271 unsigned int vco; 272 u8 tmp = 0; 273 274 /* FIXME other chipsets? */ 275 if (IS_GM45(dev_priv)) 276 vco_table = ctg_vco; 277 else if (IS_G45(dev_priv)) 278 vco_table = elk_vco; 279 else if (IS_I965GM(dev_priv)) 280 vco_table = cl_vco; 281 else if (IS_PINEVIEW(dev_priv)) 282 vco_table = pnv_vco; 283 else if (IS_G33(dev_priv)) 284 vco_table = blb_vco; 285 else 286 return 0; 287 288 tmp = intel_de_read(dev_priv, 289 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); 290 291 vco = vco_table[tmp & 0x7]; 292 if (vco == 0) 293 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", 294 tmp); 295 else 296 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); 297 298 return vco; 299 } 300 301 static void g33_get_cdclk(struct drm_i915_private *dev_priv, 302 struct intel_cdclk_config *cdclk_config) 303 { 304 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 305 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 }; 306 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 }; 307 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 }; 308 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 }; 309 const u8 *div_table; 310 unsigned int cdclk_sel; 311 u16 tmp = 0; 312 313 cdclk_config->vco = intel_hpll_vco(dev_priv); 314 315 pci_read_config_word(pdev, GCFGC, &tmp); 316 317 cdclk_sel = (tmp >> 4) & 0x7; 318 319 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 320 goto fail; 321 322 switch (cdclk_config->vco) { 323 case 3200000: 324 div_table = div_3200; 325 break; 326 case 4000000: 327 div_table = div_4000; 328 break; 329 case 4800000: 330 div_table = div_4800; 331 break; 332 case 5333333: 333 div_table = div_5333; 334 break; 335 default: 336 goto fail; 337 } 338 339 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 340 div_table[cdclk_sel]); 341 return; 342 343 fail: 344 drm_err(&dev_priv->drm, 345 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", 346 cdclk_config->vco, tmp); 347 cdclk_config->cdclk = 190476; 348 } 349 350 static void pnv_get_cdclk(struct drm_i915_private *dev_priv, 351 struct intel_cdclk_config *cdclk_config) 352 { 353 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 354 u16 gcfgc = 0; 355 356 pci_read_config_word(pdev, GCFGC, &gcfgc); 357 358 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 359 case GC_DISPLAY_CLOCK_267_MHZ_PNV: 360 cdclk_config->cdclk = 266667; 361 break; 362 case GC_DISPLAY_CLOCK_333_MHZ_PNV: 363 cdclk_config->cdclk = 333333; 364 break; 365 case GC_DISPLAY_CLOCK_444_MHZ_PNV: 366 cdclk_config->cdclk = 444444; 367 break; 368 case GC_DISPLAY_CLOCK_200_MHZ_PNV: 369 cdclk_config->cdclk = 200000; 370 break; 371 default: 372 drm_err(&dev_priv->drm, 373 "Unknown pnv display core clock 0x%04x\n", gcfgc); 374 fallthrough; 375 case GC_DISPLAY_CLOCK_133_MHZ_PNV: 376 cdclk_config->cdclk = 133333; 377 break; 378 case GC_DISPLAY_CLOCK_167_MHZ_PNV: 379 cdclk_config->cdclk = 166667; 380 break; 381 } 382 } 383 384 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, 385 struct intel_cdclk_config *cdclk_config) 386 { 387 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 388 static const u8 div_3200[] = { 16, 10, 8 }; 389 static const u8 div_4000[] = { 20, 12, 10 }; 390 static const u8 div_5333[] = { 24, 16, 14 }; 391 const u8 *div_table; 392 unsigned int cdclk_sel; 393 u16 tmp = 0; 394 395 cdclk_config->vco = intel_hpll_vco(dev_priv); 396 397 pci_read_config_word(pdev, GCFGC, &tmp); 398 399 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; 400 401 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 402 goto fail; 403 404 switch (cdclk_config->vco) { 405 case 3200000: 406 div_table = div_3200; 407 break; 408 case 4000000: 409 div_table = div_4000; 410 break; 411 case 5333333: 412 div_table = div_5333; 413 break; 414 default: 415 goto fail; 416 } 417 418 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 419 div_table[cdclk_sel]); 420 return; 421 422 fail: 423 drm_err(&dev_priv->drm, 424 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", 425 cdclk_config->vco, tmp); 426 cdclk_config->cdclk = 200000; 427 } 428 429 static void gm45_get_cdclk(struct drm_i915_private *dev_priv, 430 struct intel_cdclk_config *cdclk_config) 431 { 432 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 433 unsigned int cdclk_sel; 434 u16 tmp = 0; 435 436 cdclk_config->vco = intel_hpll_vco(dev_priv); 437 438 pci_read_config_word(pdev, GCFGC, &tmp); 439 440 cdclk_sel = (tmp >> 12) & 0x1; 441 442 switch (cdclk_config->vco) { 443 case 2666667: 444 case 4000000: 445 case 5333333: 446 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; 447 break; 448 case 3200000: 449 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; 450 break; 451 default: 452 drm_err(&dev_priv->drm, 453 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", 454 cdclk_config->vco, tmp); 455 cdclk_config->cdclk = 222222; 456 break; 457 } 458 } 459 460 static void hsw_get_cdclk(struct drm_i915_private *dev_priv, 461 struct intel_cdclk_config *cdclk_config) 462 { 463 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); 464 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 465 466 if (lcpll & LCPLL_CD_SOURCE_FCLK) 467 cdclk_config->cdclk = 800000; 468 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 469 cdclk_config->cdclk = 450000; 470 else if (freq == LCPLL_CLK_FREQ_450) 471 cdclk_config->cdclk = 450000; 472 else if (IS_HSW_ULT(dev_priv)) 473 cdclk_config->cdclk = 337500; 474 else 475 cdclk_config->cdclk = 540000; 476 } 477 478 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) 479 { 480 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 481 333333 : 320000; 482 483 /* 484 * We seem to get an unstable or solid color picture at 200MHz. 485 * Not sure what's wrong. For now use 200MHz only when all pipes 486 * are off. 487 */ 488 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) 489 return 400000; 490 else if (min_cdclk > 266667) 491 return freq_320; 492 else if (min_cdclk > 0) 493 return 266667; 494 else 495 return 200000; 496 } 497 498 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) 499 { 500 if (IS_VALLEYVIEW(dev_priv)) { 501 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ 502 return 2; 503 else if (cdclk >= 266667) 504 return 1; 505 else 506 return 0; 507 } else { 508 /* 509 * Specs are full of misinformation, but testing on actual 510 * hardware has shown that we just need to write the desired 511 * CCK divider into the Punit register. 512 */ 513 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; 514 } 515 } 516 517 static void vlv_get_cdclk(struct drm_i915_private *dev_priv, 518 struct intel_cdclk_config *cdclk_config) 519 { 520 u32 val; 521 522 vlv_iosf_sb_get(dev_priv, 523 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 524 525 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); 526 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", 527 CCK_DISPLAY_CLOCK_CONTROL, 528 cdclk_config->vco); 529 530 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 531 532 vlv_iosf_sb_put(dev_priv, 533 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 534 535 if (IS_VALLEYVIEW(dev_priv)) 536 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> 537 DSPFREQGUAR_SHIFT; 538 else 539 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> 540 DSPFREQGUAR_SHIFT_CHV; 541 } 542 543 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) 544 { 545 unsigned int credits, default_credits; 546 547 if (IS_CHERRYVIEW(dev_priv)) 548 default_credits = PFI_CREDIT(12); 549 else 550 default_credits = PFI_CREDIT(8); 551 552 if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) { 553 /* CHV suggested value is 31 or 63 */ 554 if (IS_CHERRYVIEW(dev_priv)) 555 credits = PFI_CREDIT_63; 556 else 557 credits = PFI_CREDIT(15); 558 } else { 559 credits = default_credits; 560 } 561 562 /* 563 * WA - write default credits before re-programming 564 * FIXME: should we also set the resend bit here? 565 */ 566 intel_de_write(dev_priv, GCI_CONTROL, 567 VGA_FAST_MODE_DISABLE | default_credits); 568 569 intel_de_write(dev_priv, GCI_CONTROL, 570 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND); 571 572 /* 573 * FIXME is this guaranteed to clear 574 * immediately or should we poll for it? 575 */ 576 drm_WARN_ON(&dev_priv->drm, 577 intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND); 578 } 579 580 static void vlv_set_cdclk(struct drm_i915_private *dev_priv, 581 const struct intel_cdclk_config *cdclk_config, 582 enum pipe pipe) 583 { 584 int cdclk = cdclk_config->cdclk; 585 u32 val, cmd = cdclk_config->voltage_level; 586 intel_wakeref_t wakeref; 587 588 switch (cdclk) { 589 case 400000: 590 case 333333: 591 case 320000: 592 case 266667: 593 case 200000: 594 break; 595 default: 596 MISSING_CASE(cdclk); 597 return; 598 } 599 600 /* There are cases where we can end up here with power domains 601 * off and a CDCLK frequency other than the minimum, like when 602 * issuing a modeset without actually changing any display after 603 * a system suspend. So grab the display core domain, which covers 604 * the HW blocks needed for the following programming. 605 */ 606 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); 607 608 vlv_iosf_sb_get(dev_priv, 609 BIT(VLV_IOSF_SB_CCK) | 610 BIT(VLV_IOSF_SB_BUNIT) | 611 BIT(VLV_IOSF_SB_PUNIT)); 612 613 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 614 val &= ~DSPFREQGUAR_MASK; 615 val |= (cmd << DSPFREQGUAR_SHIFT); 616 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); 617 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & 618 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 619 50)) { 620 drm_err(&dev_priv->drm, 621 "timed out waiting for CDclk change\n"); 622 } 623 624 if (cdclk == 400000) { 625 u32 divider; 626 627 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, 628 cdclk) - 1; 629 630 /* adjust cdclk divider */ 631 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); 632 val &= ~CCK_FREQUENCY_VALUES; 633 val |= divider; 634 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); 635 636 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & 637 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 638 50)) 639 drm_err(&dev_priv->drm, 640 "timed out waiting for CDclk change\n"); 641 } 642 643 /* adjust self-refresh exit latency value */ 644 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); 645 val &= ~0x7f; 646 647 /* 648 * For high bandwidth configs, we set a higher latency in the bunit 649 * so that the core display fetch happens in time to avoid underruns. 650 */ 651 if (cdclk == 400000) 652 val |= 4500 / 250; /* 4.5 usec */ 653 else 654 val |= 3000 / 250; /* 3.0 usec */ 655 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); 656 657 vlv_iosf_sb_put(dev_priv, 658 BIT(VLV_IOSF_SB_CCK) | 659 BIT(VLV_IOSF_SB_BUNIT) | 660 BIT(VLV_IOSF_SB_PUNIT)); 661 662 intel_update_cdclk(dev_priv); 663 664 vlv_program_pfi_credits(dev_priv); 665 666 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); 667 } 668 669 static void chv_set_cdclk(struct drm_i915_private *dev_priv, 670 const struct intel_cdclk_config *cdclk_config, 671 enum pipe pipe) 672 { 673 int cdclk = cdclk_config->cdclk; 674 u32 val, cmd = cdclk_config->voltage_level; 675 intel_wakeref_t wakeref; 676 677 switch (cdclk) { 678 case 333333: 679 case 320000: 680 case 266667: 681 case 200000: 682 break; 683 default: 684 MISSING_CASE(cdclk); 685 return; 686 } 687 688 /* There are cases where we can end up here with power domains 689 * off and a CDCLK frequency other than the minimum, like when 690 * issuing a modeset without actually changing any display after 691 * a system suspend. So grab the display core domain, which covers 692 * the HW blocks needed for the following programming. 693 */ 694 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); 695 696 vlv_punit_get(dev_priv); 697 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 698 val &= ~DSPFREQGUAR_MASK_CHV; 699 val |= (cmd << DSPFREQGUAR_SHIFT_CHV); 700 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); 701 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & 702 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 703 50)) { 704 drm_err(&dev_priv->drm, 705 "timed out waiting for CDclk change\n"); 706 } 707 708 vlv_punit_put(dev_priv); 709 710 intel_update_cdclk(dev_priv); 711 712 vlv_program_pfi_credits(dev_priv); 713 714 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); 715 } 716 717 static int bdw_calc_cdclk(int min_cdclk) 718 { 719 if (min_cdclk > 540000) 720 return 675000; 721 else if (min_cdclk > 450000) 722 return 540000; 723 else if (min_cdclk > 337500) 724 return 450000; 725 else 726 return 337500; 727 } 728 729 static u8 bdw_calc_voltage_level(int cdclk) 730 { 731 switch (cdclk) { 732 default: 733 case 337500: 734 return 2; 735 case 450000: 736 return 0; 737 case 540000: 738 return 1; 739 case 675000: 740 return 3; 741 } 742 } 743 744 static void bdw_get_cdclk(struct drm_i915_private *dev_priv, 745 struct intel_cdclk_config *cdclk_config) 746 { 747 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); 748 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 749 750 if (lcpll & LCPLL_CD_SOURCE_FCLK) 751 cdclk_config->cdclk = 800000; 752 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 753 cdclk_config->cdclk = 450000; 754 else if (freq == LCPLL_CLK_FREQ_450) 755 cdclk_config->cdclk = 450000; 756 else if (freq == LCPLL_CLK_FREQ_54O_BDW) 757 cdclk_config->cdclk = 540000; 758 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 759 cdclk_config->cdclk = 337500; 760 else 761 cdclk_config->cdclk = 675000; 762 763 /* 764 * Can't read this out :( Let's assume it's 765 * at least what the CDCLK frequency requires. 766 */ 767 cdclk_config->voltage_level = 768 bdw_calc_voltage_level(cdclk_config->cdclk); 769 } 770 771 static u32 bdw_cdclk_freq_sel(int cdclk) 772 { 773 switch (cdclk) { 774 default: 775 MISSING_CASE(cdclk); 776 fallthrough; 777 case 337500: 778 return LCPLL_CLK_FREQ_337_5_BDW; 779 case 450000: 780 return LCPLL_CLK_FREQ_450; 781 case 540000: 782 return LCPLL_CLK_FREQ_54O_BDW; 783 case 675000: 784 return LCPLL_CLK_FREQ_675_BDW; 785 } 786 } 787 788 static void bdw_set_cdclk(struct drm_i915_private *dev_priv, 789 const struct intel_cdclk_config *cdclk_config, 790 enum pipe pipe) 791 { 792 int cdclk = cdclk_config->cdclk; 793 int ret; 794 795 if (drm_WARN(&dev_priv->drm, 796 (intel_de_read(dev_priv, LCPLL_CTL) & 797 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | 798 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | 799 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | 800 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, 801 "trying to change cdclk frequency with cdclk not enabled\n")) 802 return; 803 804 ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); 805 if (ret) { 806 drm_err(&dev_priv->drm, 807 "failed to inform pcode about cdclk change\n"); 808 return; 809 } 810 811 intel_de_rmw(dev_priv, LCPLL_CTL, 812 0, LCPLL_CD_SOURCE_FCLK); 813 814 /* 815 * According to the spec, it should be enough to poll for this 1 us. 816 * However, extensive testing shows that this can take longer. 817 */ 818 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) & 819 LCPLL_CD_SOURCE_FCLK_DONE, 100)) 820 drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); 821 822 intel_de_rmw(dev_priv, LCPLL_CTL, 823 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk)); 824 825 intel_de_rmw(dev_priv, LCPLL_CTL, 826 LCPLL_CD_SOURCE_FCLK, 0); 827 828 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) & 829 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 830 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n"); 831 832 snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ, 833 cdclk_config->voltage_level); 834 835 intel_de_write(dev_priv, CDCLK_FREQ, 836 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); 837 838 intel_update_cdclk(dev_priv); 839 } 840 841 static int skl_calc_cdclk(int min_cdclk, int vco) 842 { 843 if (vco == 8640000) { 844 if (min_cdclk > 540000) 845 return 617143; 846 else if (min_cdclk > 432000) 847 return 540000; 848 else if (min_cdclk > 308571) 849 return 432000; 850 else 851 return 308571; 852 } else { 853 if (min_cdclk > 540000) 854 return 675000; 855 else if (min_cdclk > 450000) 856 return 540000; 857 else if (min_cdclk > 337500) 858 return 450000; 859 else 860 return 337500; 861 } 862 } 863 864 static u8 skl_calc_voltage_level(int cdclk) 865 { 866 if (cdclk > 540000) 867 return 3; 868 else if (cdclk > 450000) 869 return 2; 870 else if (cdclk > 337500) 871 return 1; 872 else 873 return 0; 874 } 875 876 static void skl_dpll0_update(struct drm_i915_private *dev_priv, 877 struct intel_cdclk_config *cdclk_config) 878 { 879 u32 val; 880 881 cdclk_config->ref = 24000; 882 cdclk_config->vco = 0; 883 884 val = intel_de_read(dev_priv, LCPLL1_CTL); 885 if ((val & LCPLL_PLL_ENABLE) == 0) 886 return; 887 888 if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0)) 889 return; 890 891 val = intel_de_read(dev_priv, DPLL_CTRL1); 892 893 if (drm_WARN_ON(&dev_priv->drm, 894 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 895 DPLL_CTRL1_SSC(SKL_DPLL0) | 896 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != 897 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) 898 return; 899 900 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { 901 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): 902 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): 903 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): 904 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): 905 cdclk_config->vco = 8100000; 906 break; 907 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): 908 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): 909 cdclk_config->vco = 8640000; 910 break; 911 default: 912 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 913 break; 914 } 915 } 916 917 static void skl_get_cdclk(struct drm_i915_private *dev_priv, 918 struct intel_cdclk_config *cdclk_config) 919 { 920 u32 cdctl; 921 922 skl_dpll0_update(dev_priv, cdclk_config); 923 924 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; 925 926 if (cdclk_config->vco == 0) 927 goto out; 928 929 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 930 931 if (cdclk_config->vco == 8640000) { 932 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 933 case CDCLK_FREQ_450_432: 934 cdclk_config->cdclk = 432000; 935 break; 936 case CDCLK_FREQ_337_308: 937 cdclk_config->cdclk = 308571; 938 break; 939 case CDCLK_FREQ_540: 940 cdclk_config->cdclk = 540000; 941 break; 942 case CDCLK_FREQ_675_617: 943 cdclk_config->cdclk = 617143; 944 break; 945 default: 946 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 947 break; 948 } 949 } else { 950 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 951 case CDCLK_FREQ_450_432: 952 cdclk_config->cdclk = 450000; 953 break; 954 case CDCLK_FREQ_337_308: 955 cdclk_config->cdclk = 337500; 956 break; 957 case CDCLK_FREQ_540: 958 cdclk_config->cdclk = 540000; 959 break; 960 case CDCLK_FREQ_675_617: 961 cdclk_config->cdclk = 675000; 962 break; 963 default: 964 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 965 break; 966 } 967 } 968 969 out: 970 /* 971 * Can't read this out :( Let's assume it's 972 * at least what the CDCLK frequency requires. 973 */ 974 cdclk_config->voltage_level = 975 skl_calc_voltage_level(cdclk_config->cdclk); 976 } 977 978 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ 979 static int skl_cdclk_decimal(int cdclk) 980 { 981 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); 982 } 983 984 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, 985 int vco) 986 { 987 bool changed = dev_priv->skl_preferred_vco_freq != vco; 988 989 dev_priv->skl_preferred_vco_freq = vco; 990 991 if (changed) 992 intel_update_max_cdclk(dev_priv); 993 } 994 995 static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco) 996 { 997 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); 998 999 /* 1000 * We always enable DPLL0 with the lowest link rate possible, but still 1001 * taking into account the VCO required to operate the eDP panel at the 1002 * desired frequency. The usual DP link rates operate with a VCO of 1003 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. 1004 * The modeset code is responsible for the selection of the exact link 1005 * rate later on, with the constraint of choosing a frequency that 1006 * works with vco. 1007 */ 1008 if (vco == 8640000) 1009 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0); 1010 else 1011 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0); 1012 } 1013 1014 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) 1015 { 1016 intel_de_rmw(dev_priv, DPLL_CTRL1, 1017 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 1018 DPLL_CTRL1_SSC(SKL_DPLL0) | 1019 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0), 1020 DPLL_CTRL1_OVERRIDE(SKL_DPLL0) | 1021 skl_dpll0_link_rate(dev_priv, vco)); 1022 intel_de_posting_read(dev_priv, DPLL_CTRL1); 1023 1024 intel_de_rmw(dev_priv, LCPLL1_CTL, 1025 0, LCPLL_PLL_ENABLE); 1026 1027 if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) 1028 drm_err(&dev_priv->drm, "DPLL0 not locked\n"); 1029 1030 dev_priv->display.cdclk.hw.vco = vco; 1031 1032 /* We'll want to keep using the current vco from now on. */ 1033 skl_set_preferred_cdclk_vco(dev_priv, vco); 1034 } 1035 1036 static void skl_dpll0_disable(struct drm_i915_private *dev_priv) 1037 { 1038 intel_de_rmw(dev_priv, LCPLL1_CTL, 1039 LCPLL_PLL_ENABLE, 0); 1040 1041 if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) 1042 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n"); 1043 1044 dev_priv->display.cdclk.hw.vco = 0; 1045 } 1046 1047 static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv, 1048 int cdclk, int vco) 1049 { 1050 switch (cdclk) { 1051 default: 1052 drm_WARN_ON(&dev_priv->drm, 1053 cdclk != dev_priv->display.cdclk.hw.bypass); 1054 drm_WARN_ON(&dev_priv->drm, vco != 0); 1055 fallthrough; 1056 case 308571: 1057 case 337500: 1058 return CDCLK_FREQ_337_308; 1059 case 450000: 1060 case 432000: 1061 return CDCLK_FREQ_450_432; 1062 case 540000: 1063 return CDCLK_FREQ_540; 1064 case 617143: 1065 case 675000: 1066 return CDCLK_FREQ_675_617; 1067 } 1068 } 1069 1070 static void skl_set_cdclk(struct drm_i915_private *dev_priv, 1071 const struct intel_cdclk_config *cdclk_config, 1072 enum pipe pipe) 1073 { 1074 int cdclk = cdclk_config->cdclk; 1075 int vco = cdclk_config->vco; 1076 u32 freq_select, cdclk_ctl; 1077 int ret; 1078 1079 /* 1080 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are 1081 * unsupported on SKL. In theory this should never happen since only 1082 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not 1083 * supported on SKL either, see the above WA. WARN whenever trying to 1084 * use the corresponding VCO freq as that always leads to using the 1085 * minimum 308MHz CDCLK. 1086 */ 1087 drm_WARN_ON_ONCE(&dev_priv->drm, 1088 IS_SKYLAKE(dev_priv) && vco == 8640000); 1089 1090 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 1091 SKL_CDCLK_PREPARE_FOR_CHANGE, 1092 SKL_CDCLK_READY_FOR_CHANGE, 1093 SKL_CDCLK_READY_FOR_CHANGE, 3); 1094 if (ret) { 1095 drm_err(&dev_priv->drm, 1096 "Failed to inform PCU about cdclk change (%d)\n", ret); 1097 return; 1098 } 1099 1100 freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco); 1101 1102 if (dev_priv->display.cdclk.hw.vco != 0 && 1103 dev_priv->display.cdclk.hw.vco != vco) 1104 skl_dpll0_disable(dev_priv); 1105 1106 cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL); 1107 1108 if (dev_priv->display.cdclk.hw.vco != vco) { 1109 /* Wa Display #1183: skl,kbl,cfl */ 1110 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1111 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1112 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1113 } 1114 1115 /* Wa Display #1183: skl,kbl,cfl */ 1116 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; 1117 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1118 intel_de_posting_read(dev_priv, CDCLK_CTL); 1119 1120 if (dev_priv->display.cdclk.hw.vco != vco) 1121 skl_dpll0_enable(dev_priv, vco); 1122 1123 /* Wa Display #1183: skl,kbl,cfl */ 1124 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1125 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1126 1127 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1128 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1129 1130 /* Wa Display #1183: skl,kbl,cfl */ 1131 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; 1132 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1133 intel_de_posting_read(dev_priv, CDCLK_CTL); 1134 1135 /* inform PCU of the change */ 1136 snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 1137 cdclk_config->voltage_level); 1138 1139 intel_update_cdclk(dev_priv); 1140 } 1141 1142 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) 1143 { 1144 u32 cdctl, expected; 1145 1146 /* 1147 * check if the pre-os initialized the display 1148 * There is SWF18 scratchpad register defined which is set by the 1149 * pre-os which can be used by the OS drivers to check the status 1150 */ 1151 if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) 1152 goto sanitize; 1153 1154 intel_update_cdclk(dev_priv); 1155 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); 1156 1157 /* Is PLL enabled and locked ? */ 1158 if (dev_priv->display.cdclk.hw.vco == 0 || 1159 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) 1160 goto sanitize; 1161 1162 /* DPLL okay; verify the cdclock 1163 * 1164 * Noticed in some instances that the freq selection is correct but 1165 * decimal part is programmed wrong from BIOS where pre-os does not 1166 * enable display. Verify the same as well. 1167 */ 1168 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 1169 expected = (cdctl & CDCLK_FREQ_SEL_MASK) | 1170 skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk); 1171 if (cdctl == expected) 1172 /* All well; nothing to sanitize */ 1173 return; 1174 1175 sanitize: 1176 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); 1177 1178 /* force cdclk programming */ 1179 dev_priv->display.cdclk.hw.cdclk = 0; 1180 /* force full PLL disable + enable */ 1181 dev_priv->display.cdclk.hw.vco = -1; 1182 } 1183 1184 static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv) 1185 { 1186 struct intel_cdclk_config cdclk_config; 1187 1188 skl_sanitize_cdclk(dev_priv); 1189 1190 if (dev_priv->display.cdclk.hw.cdclk != 0 && 1191 dev_priv->display.cdclk.hw.vco != 0) { 1192 /* 1193 * Use the current vco as our initial 1194 * guess as to what the preferred vco is. 1195 */ 1196 if (dev_priv->skl_preferred_vco_freq == 0) 1197 skl_set_preferred_cdclk_vco(dev_priv, 1198 dev_priv->display.cdclk.hw.vco); 1199 return; 1200 } 1201 1202 cdclk_config = dev_priv->display.cdclk.hw; 1203 1204 cdclk_config.vco = dev_priv->skl_preferred_vco_freq; 1205 if (cdclk_config.vco == 0) 1206 cdclk_config.vco = 8100000; 1207 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); 1208 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1209 1210 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1211 } 1212 1213 static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv) 1214 { 1215 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; 1216 1217 cdclk_config.cdclk = cdclk_config.bypass; 1218 cdclk_config.vco = 0; 1219 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1220 1221 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1222 } 1223 1224 struct intel_cdclk_vals { 1225 u32 cdclk; 1226 u16 refclk; 1227 u16 waveform; 1228 u8 divider; /* CD2X divider * 2 */ 1229 u8 ratio; 1230 }; 1231 1232 static const struct intel_cdclk_vals bxt_cdclk_table[] = { 1233 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 }, 1234 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 }, 1235 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 }, 1236 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 }, 1237 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 }, 1238 {} 1239 }; 1240 1241 static const struct intel_cdclk_vals glk_cdclk_table[] = { 1242 { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 }, 1243 { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 }, 1244 { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 }, 1245 {} 1246 }; 1247 1248 static const struct intel_cdclk_vals icl_cdclk_table[] = { 1249 { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 }, 1250 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 }, 1251 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 }, 1252 { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 }, 1253 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 }, 1254 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 }, 1255 1256 { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 }, 1257 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 }, 1258 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 }, 1259 { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 }, 1260 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 }, 1261 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 }, 1262 1263 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 }, 1264 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 }, 1265 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 }, 1266 { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 }, 1267 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 }, 1268 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 }, 1269 {} 1270 }; 1271 1272 static const struct intel_cdclk_vals rkl_cdclk_table[] = { 1273 { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 }, 1274 { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 }, 1275 { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 }, 1276 { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 }, 1277 { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 }, 1278 { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 }, 1279 1280 { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 }, 1281 { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 }, 1282 { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 }, 1283 { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 }, 1284 { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 }, 1285 { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 }, 1286 1287 { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 }, 1288 { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 }, 1289 { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 }, 1290 { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 }, 1291 { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 }, 1292 { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 }, 1293 {} 1294 }; 1295 1296 static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = { 1297 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 }, 1298 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 }, 1299 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 }, 1300 1301 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 }, 1302 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 }, 1303 { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 }, 1304 1305 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 }, 1306 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 }, 1307 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 }, 1308 {} 1309 }; 1310 1311 static const struct intel_cdclk_vals adlp_cdclk_table[] = { 1312 { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 }, 1313 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 }, 1314 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 }, 1315 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 }, 1316 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 }, 1317 1318 { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 }, 1319 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 }, 1320 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 }, 1321 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 }, 1322 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 }, 1323 1324 { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 }, 1325 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 }, 1326 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 }, 1327 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 }, 1328 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 }, 1329 {} 1330 }; 1331 1332 static const struct intel_cdclk_vals dg2_cdclk_table[] = { 1333 { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 }, 1334 { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 }, 1335 { .refclk = 38400, .cdclk = 244800, .divider = 2, .ratio = 34, .waveform = 0xa4a4 }, 1336 { .refclk = 38400, .cdclk = 285600, .divider = 2, .ratio = 34, .waveform = 0xa54a }, 1337 { .refclk = 38400, .cdclk = 326400, .divider = 2, .ratio = 34, .waveform = 0xaaaa }, 1338 { .refclk = 38400, .cdclk = 367200, .divider = 2, .ratio = 34, .waveform = 0xad5a }, 1339 { .refclk = 38400, .cdclk = 408000, .divider = 2, .ratio = 34, .waveform = 0xb6b6 }, 1340 { .refclk = 38400, .cdclk = 448800, .divider = 2, .ratio = 34, .waveform = 0xdbb6 }, 1341 { .refclk = 38400, .cdclk = 489600, .divider = 2, .ratio = 34, .waveform = 0xeeee }, 1342 { .refclk = 38400, .cdclk = 530400, .divider = 2, .ratio = 34, .waveform = 0xf7de }, 1343 { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe }, 1344 { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe }, 1345 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff }, 1346 {} 1347 }; 1348 1349 static const struct intel_cdclk_vals mtl_cdclk_table[] = { 1350 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a }, 1351 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 }, 1352 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 }, 1353 { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 }, 1354 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 }, 1355 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 }, 1356 {} 1357 }; 1358 1359 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) 1360 { 1361 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; 1362 int i; 1363 1364 for (i = 0; table[i].refclk; i++) 1365 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && 1366 table[i].cdclk >= min_cdclk) 1367 return table[i].cdclk; 1368 1369 drm_WARN(&dev_priv->drm, 1, 1370 "Cannot satisfy minimum cdclk %d with refclk %u\n", 1371 min_cdclk, dev_priv->display.cdclk.hw.ref); 1372 return 0; 1373 } 1374 1375 static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) 1376 { 1377 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; 1378 int i; 1379 1380 if (cdclk == dev_priv->display.cdclk.hw.bypass) 1381 return 0; 1382 1383 for (i = 0; table[i].refclk; i++) 1384 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && 1385 table[i].cdclk == cdclk) 1386 return dev_priv->display.cdclk.hw.ref * table[i].ratio; 1387 1388 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", 1389 cdclk, dev_priv->display.cdclk.hw.ref); 1390 return 0; 1391 } 1392 1393 static u8 bxt_calc_voltage_level(int cdclk) 1394 { 1395 return DIV_ROUND_UP(cdclk, 25000); 1396 } 1397 1398 static u8 icl_calc_voltage_level(int cdclk) 1399 { 1400 if (cdclk > 556800) 1401 return 2; 1402 else if (cdclk > 312000) 1403 return 1; 1404 else 1405 return 0; 1406 } 1407 1408 static u8 ehl_calc_voltage_level(int cdclk) 1409 { 1410 if (cdclk > 326400) 1411 return 3; 1412 else if (cdclk > 312000) 1413 return 2; 1414 else if (cdclk > 180000) 1415 return 1; 1416 else 1417 return 0; 1418 } 1419 1420 static u8 tgl_calc_voltage_level(int cdclk) 1421 { 1422 if (cdclk > 556800) 1423 return 3; 1424 else if (cdclk > 326400) 1425 return 2; 1426 else if (cdclk > 312000) 1427 return 1; 1428 else 1429 return 0; 1430 } 1431 1432 static void icl_readout_refclk(struct drm_i915_private *dev_priv, 1433 struct intel_cdclk_config *cdclk_config) 1434 { 1435 u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; 1436 1437 switch (dssm) { 1438 default: 1439 MISSING_CASE(dssm); 1440 fallthrough; 1441 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz: 1442 cdclk_config->ref = 24000; 1443 break; 1444 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz: 1445 cdclk_config->ref = 19200; 1446 break; 1447 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz: 1448 cdclk_config->ref = 38400; 1449 break; 1450 } 1451 } 1452 1453 static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, 1454 struct intel_cdclk_config *cdclk_config) 1455 { 1456 u32 val, ratio; 1457 1458 if (IS_DG2(dev_priv)) 1459 cdclk_config->ref = 38400; 1460 else if (DISPLAY_VER(dev_priv) >= 11) 1461 icl_readout_refclk(dev_priv, cdclk_config); 1462 else 1463 cdclk_config->ref = 19200; 1464 1465 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE); 1466 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || 1467 (val & BXT_DE_PLL_LOCK) == 0) { 1468 /* 1469 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but 1470 * setting it to zero is a way to signal that. 1471 */ 1472 cdclk_config->vco = 0; 1473 return; 1474 } 1475 1476 /* 1477 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register, 1478 * gen9lp had it in a separate PLL control register. 1479 */ 1480 if (DISPLAY_VER(dev_priv) >= 11) 1481 ratio = val & ICL_CDCLK_PLL_RATIO_MASK; 1482 else 1483 ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; 1484 1485 cdclk_config->vco = ratio * cdclk_config->ref; 1486 } 1487 1488 static void bxt_get_cdclk(struct drm_i915_private *dev_priv, 1489 struct intel_cdclk_config *cdclk_config) 1490 { 1491 u32 squash_ctl = 0; 1492 u32 divider; 1493 int div; 1494 1495 bxt_de_pll_readout(dev_priv, cdclk_config); 1496 1497 if (DISPLAY_VER(dev_priv) >= 12) 1498 cdclk_config->bypass = cdclk_config->ref / 2; 1499 else if (DISPLAY_VER(dev_priv) >= 11) 1500 cdclk_config->bypass = 50000; 1501 else 1502 cdclk_config->bypass = cdclk_config->ref; 1503 1504 if (cdclk_config->vco == 0) { 1505 cdclk_config->cdclk = cdclk_config->bypass; 1506 goto out; 1507 } 1508 1509 divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; 1510 1511 switch (divider) { 1512 case BXT_CDCLK_CD2X_DIV_SEL_1: 1513 div = 2; 1514 break; 1515 case BXT_CDCLK_CD2X_DIV_SEL_1_5: 1516 div = 3; 1517 break; 1518 case BXT_CDCLK_CD2X_DIV_SEL_2: 1519 div = 4; 1520 break; 1521 case BXT_CDCLK_CD2X_DIV_SEL_4: 1522 div = 8; 1523 break; 1524 default: 1525 MISSING_CASE(divider); 1526 return; 1527 } 1528 1529 if (HAS_CDCLK_SQUASH(dev_priv)) 1530 squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL); 1531 1532 if (squash_ctl & CDCLK_SQUASH_ENABLE) { 1533 u16 waveform; 1534 int size; 1535 1536 size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1; 1537 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size); 1538 1539 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * 1540 cdclk_config->vco, size * div); 1541 } else { 1542 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); 1543 } 1544 1545 out: 1546 /* 1547 * Can't read this out :( Let's assume it's 1548 * at least what the CDCLK frequency requires. 1549 */ 1550 cdclk_config->voltage_level = 1551 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk); 1552 } 1553 1554 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) 1555 { 1556 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0); 1557 1558 /* Timeout 200us */ 1559 if (intel_de_wait_for_clear(dev_priv, 1560 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1561 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n"); 1562 1563 dev_priv->display.cdclk.hw.vco = 0; 1564 } 1565 1566 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) 1567 { 1568 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); 1569 1570 intel_de_rmw(dev_priv, BXT_DE_PLL_CTL, 1571 BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio)); 1572 1573 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); 1574 1575 /* Timeout 200us */ 1576 if (intel_de_wait_for_set(dev_priv, 1577 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1578 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n"); 1579 1580 dev_priv->display.cdclk.hw.vco = vco; 1581 } 1582 1583 static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv) 1584 { 1585 intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE, 1586 BXT_DE_PLL_PLL_ENABLE, 0); 1587 1588 /* Timeout 200us */ 1589 if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1590 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n"); 1591 1592 dev_priv->display.cdclk.hw.vco = 0; 1593 } 1594 1595 static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) 1596 { 1597 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); 1598 u32 val; 1599 1600 val = ICL_CDCLK_PLL_RATIO(ratio); 1601 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1602 1603 val |= BXT_DE_PLL_PLL_ENABLE; 1604 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1605 1606 /* Timeout 200us */ 1607 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1608 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n"); 1609 1610 dev_priv->display.cdclk.hw.vco = vco; 1611 } 1612 1613 static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco) 1614 { 1615 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); 1616 u32 val; 1617 1618 /* Write PLL ratio without disabling */ 1619 val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE; 1620 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1621 1622 /* Submit freq change request */ 1623 val |= BXT_DE_PLL_FREQ_REQ; 1624 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1625 1626 /* Timeout 200us */ 1627 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, 1628 BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1)) 1629 drm_err(&dev_priv->drm, "timeout waiting for FREQ change request ack\n"); 1630 1631 val &= ~BXT_DE_PLL_FREQ_REQ; 1632 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1633 1634 dev_priv->display.cdclk.hw.vco = vco; 1635 } 1636 1637 static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 1638 { 1639 if (DISPLAY_VER(dev_priv) >= 12) { 1640 if (pipe == INVALID_PIPE) 1641 return TGL_CDCLK_CD2X_PIPE_NONE; 1642 else 1643 return TGL_CDCLK_CD2X_PIPE(pipe); 1644 } else if (DISPLAY_VER(dev_priv) >= 11) { 1645 if (pipe == INVALID_PIPE) 1646 return ICL_CDCLK_CD2X_PIPE_NONE; 1647 else 1648 return ICL_CDCLK_CD2X_PIPE(pipe); 1649 } else { 1650 if (pipe == INVALID_PIPE) 1651 return BXT_CDCLK_CD2X_PIPE_NONE; 1652 else 1653 return BXT_CDCLK_CD2X_PIPE(pipe); 1654 } 1655 } 1656 1657 static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv, 1658 int cdclk, int vco) 1659 { 1660 /* cdclk = vco / 2 / div{1,1.5,2,4} */ 1661 switch (DIV_ROUND_CLOSEST(vco, cdclk)) { 1662 default: 1663 drm_WARN_ON(&dev_priv->drm, 1664 cdclk != dev_priv->display.cdclk.hw.bypass); 1665 drm_WARN_ON(&dev_priv->drm, vco != 0); 1666 fallthrough; 1667 case 2: 1668 return BXT_CDCLK_CD2X_DIV_SEL_1; 1669 case 3: 1670 return BXT_CDCLK_CD2X_DIV_SEL_1_5; 1671 case 4: 1672 return BXT_CDCLK_CD2X_DIV_SEL_2; 1673 case 8: 1674 return BXT_CDCLK_CD2X_DIV_SEL_4; 1675 } 1676 } 1677 1678 static u32 cdclk_squash_waveform(struct drm_i915_private *dev_priv, 1679 int cdclk) 1680 { 1681 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; 1682 int i; 1683 1684 if (cdclk == dev_priv->display.cdclk.hw.bypass) 1685 return 0; 1686 1687 for (i = 0; table[i].refclk; i++) 1688 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && 1689 table[i].cdclk == cdclk) 1690 return table[i].waveform; 1691 1692 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", 1693 cdclk, dev_priv->display.cdclk.hw.ref); 1694 1695 return 0xffff; 1696 } 1697 1698 static void icl_cdclk_pll_update(struct drm_i915_private *i915, int vco) 1699 { 1700 if (i915->display.cdclk.hw.vco != 0 && 1701 i915->display.cdclk.hw.vco != vco) 1702 icl_cdclk_pll_disable(i915); 1703 1704 if (i915->display.cdclk.hw.vco != vco) 1705 icl_cdclk_pll_enable(i915, vco); 1706 } 1707 1708 static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco) 1709 { 1710 if (i915->display.cdclk.hw.vco != 0 && 1711 i915->display.cdclk.hw.vco != vco) 1712 bxt_de_pll_disable(i915); 1713 1714 if (i915->display.cdclk.hw.vco != vco) 1715 bxt_de_pll_enable(i915, vco); 1716 } 1717 1718 static void dg2_cdclk_squash_program(struct drm_i915_private *i915, 1719 u16 waveform) 1720 { 1721 u32 squash_ctl = 0; 1722 1723 if (waveform) 1724 squash_ctl = CDCLK_SQUASH_ENABLE | 1725 CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; 1726 1727 intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl); 1728 } 1729 1730 static bool cdclk_pll_is_unknown(unsigned int vco) 1731 { 1732 /* 1733 * Ensure driver does not take the crawl path for the 1734 * case when the vco is set to ~0 in the 1735 * sanitize path. 1736 */ 1737 return vco == ~0; 1738 } 1739 1740 static int cdclk_squash_divider(u16 waveform) 1741 { 1742 return hweight16(waveform ?: 0xffff); 1743 } 1744 1745 static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i915, 1746 const struct intel_cdclk_config *old_cdclk_config, 1747 const struct intel_cdclk_config *new_cdclk_config, 1748 struct intel_cdclk_config *mid_cdclk_config) 1749 { 1750 u16 old_waveform, new_waveform, mid_waveform; 1751 int size = 16; 1752 int div = 2; 1753 1754 /* Return if PLL is in an unknown state, force a complete disable and re-enable. */ 1755 if (cdclk_pll_is_unknown(old_cdclk_config->vco)) 1756 return false; 1757 1758 /* Return if both Squash and Crawl are not present */ 1759 if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915)) 1760 return false; 1761 1762 old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk); 1763 new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk); 1764 1765 /* Return if Squash only or Crawl only is the desired action */ 1766 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 || 1767 old_cdclk_config->vco == new_cdclk_config->vco || 1768 old_waveform == new_waveform) 1769 return false; 1770 1771 *mid_cdclk_config = *new_cdclk_config; 1772 1773 /* 1774 * Populate the mid_cdclk_config accordingly. 1775 * - If moving to a higher cdclk, the desired action is squashing. 1776 * The mid cdclk config should have the new (squash) waveform. 1777 * - If moving to a lower cdclk, the desired action is crawling. 1778 * The mid cdclk config should have the new vco. 1779 */ 1780 1781 if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) { 1782 mid_cdclk_config->vco = old_cdclk_config->vco; 1783 mid_waveform = new_waveform; 1784 } else { 1785 mid_cdclk_config->vco = new_cdclk_config->vco; 1786 mid_waveform = old_waveform; 1787 } 1788 1789 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) * 1790 mid_cdclk_config->vco, size * div); 1791 1792 /* make sure the mid clock came out sane */ 1793 1794 drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk < 1795 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); 1796 drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk > 1797 i915->display.cdclk.max_cdclk_freq); 1798 drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915, mid_cdclk_config->cdclk) != 1799 mid_waveform); 1800 1801 return true; 1802 } 1803 1804 static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, 1805 const struct intel_cdclk_config *cdclk_config, 1806 enum pipe pipe) 1807 { 1808 int cdclk = cdclk_config->cdclk; 1809 int vco = cdclk_config->vco; 1810 u32 val; 1811 u16 waveform; 1812 int clock; 1813 1814 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 && 1815 !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) { 1816 if (dev_priv->display.cdclk.hw.vco != vco) 1817 adlp_cdclk_pll_crawl(dev_priv, vco); 1818 } else if (DISPLAY_VER(dev_priv) >= 11) 1819 icl_cdclk_pll_update(dev_priv, vco); 1820 else 1821 bxt_cdclk_pll_update(dev_priv, vco); 1822 1823 waveform = cdclk_squash_waveform(dev_priv, cdclk); 1824 1825 if (waveform) 1826 clock = vco / 2; 1827 else 1828 clock = cdclk; 1829 1830 if (HAS_CDCLK_SQUASH(dev_priv)) 1831 dg2_cdclk_squash_program(dev_priv, waveform); 1832 1833 val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) | 1834 bxt_cdclk_cd2x_pipe(dev_priv, pipe) | 1835 skl_cdclk_decimal(cdclk); 1836 1837 /* 1838 * Disable SSA Precharge when CD clock frequency < 500 MHz, 1839 * enable otherwise. 1840 */ 1841 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1842 cdclk >= 500000) 1843 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 1844 intel_de_write(dev_priv, CDCLK_CTL, val); 1845 1846 if (pipe != INVALID_PIPE) 1847 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe)); 1848 } 1849 1850 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 1851 const struct intel_cdclk_config *cdclk_config, 1852 enum pipe pipe) 1853 { 1854 struct intel_cdclk_config mid_cdclk_config; 1855 int cdclk = cdclk_config->cdclk; 1856 int ret = 0; 1857 1858 /* 1859 * Inform power controller of upcoming frequency change. 1860 * Display versions 14 and beyond do not follow the PUnit 1861 * mailbox communication, skip 1862 * this step. 1863 */ 1864 if (DISPLAY_VER(dev_priv) >= 14) 1865 /* NOOP */; 1866 else if (DISPLAY_VER(dev_priv) >= 11) 1867 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 1868 SKL_CDCLK_PREPARE_FOR_CHANGE, 1869 SKL_CDCLK_READY_FOR_CHANGE, 1870 SKL_CDCLK_READY_FOR_CHANGE, 3); 1871 else 1872 /* 1873 * BSpec requires us to wait up to 150usec, but that leads to 1874 * timeouts; the 2ms used here is based on experiment. 1875 */ 1876 ret = snb_pcode_write_timeout(&dev_priv->uncore, 1877 HSW_PCODE_DE_WRITE_FREQ_REQ, 1878 0x80000000, 150, 2); 1879 1880 if (ret) { 1881 drm_err(&dev_priv->drm, 1882 "Failed to inform PCU about cdclk change (err %d, freq %d)\n", 1883 ret, cdclk); 1884 return; 1885 } 1886 1887 if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw, 1888 cdclk_config, &mid_cdclk_config)) { 1889 _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe); 1890 _bxt_set_cdclk(dev_priv, cdclk_config, pipe); 1891 } else { 1892 _bxt_set_cdclk(dev_priv, cdclk_config, pipe); 1893 } 1894 1895 if (DISPLAY_VER(dev_priv) >= 14) 1896 /* 1897 * NOOP - No Pcode communication needed for 1898 * Display versions 14 and beyond 1899 */; 1900 else if (DISPLAY_VER(dev_priv) >= 11) 1901 ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 1902 cdclk_config->voltage_level); 1903 else 1904 /* 1905 * The timeout isn't specified, the 2ms used here is based on 1906 * experiment. 1907 * FIXME: Waiting for the request completion could be delayed 1908 * until the next PCODE request based on BSpec. 1909 */ 1910 ret = snb_pcode_write_timeout(&dev_priv->uncore, 1911 HSW_PCODE_DE_WRITE_FREQ_REQ, 1912 cdclk_config->voltage_level, 1913 150, 2); 1914 1915 if (ret) { 1916 drm_err(&dev_priv->drm, 1917 "PCode CDCLK freq set failed, (err %d, freq %d)\n", 1918 ret, cdclk); 1919 return; 1920 } 1921 1922 intel_update_cdclk(dev_priv); 1923 1924 if (DISPLAY_VER(dev_priv) >= 11) 1925 /* 1926 * Can't read out the voltage level :( 1927 * Let's just assume everything is as expected. 1928 */ 1929 dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level; 1930 } 1931 1932 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) 1933 { 1934 u32 cdctl, expected; 1935 int cdclk, clock, vco; 1936 1937 intel_update_cdclk(dev_priv); 1938 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); 1939 1940 if (dev_priv->display.cdclk.hw.vco == 0 || 1941 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) 1942 goto sanitize; 1943 1944 /* DPLL okay; verify the cdclock 1945 * 1946 * Some BIOS versions leave an incorrect decimal frequency value and 1947 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, 1948 * so sanitize this register. 1949 */ 1950 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 1951 /* 1952 * Let's ignore the pipe field, since BIOS could have configured the 1953 * dividers both synching to an active pipe, or asynchronously 1954 * (PIPE_NONE). 1955 */ 1956 cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); 1957 1958 /* Make sure this is a legal cdclk value for the platform */ 1959 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk); 1960 if (cdclk != dev_priv->display.cdclk.hw.cdclk) 1961 goto sanitize; 1962 1963 /* Make sure the VCO is correct for the cdclk */ 1964 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 1965 if (vco != dev_priv->display.cdclk.hw.vco) 1966 goto sanitize; 1967 1968 expected = skl_cdclk_decimal(cdclk); 1969 1970 /* Figure out what CD2X divider we should be using for this cdclk */ 1971 if (HAS_CDCLK_SQUASH(dev_priv)) 1972 clock = dev_priv->display.cdclk.hw.vco / 2; 1973 else 1974 clock = dev_priv->display.cdclk.hw.cdclk; 1975 1976 expected |= bxt_cdclk_cd2x_div_sel(dev_priv, clock, 1977 dev_priv->display.cdclk.hw.vco); 1978 1979 /* 1980 * Disable SSA Precharge when CD clock frequency < 500 MHz, 1981 * enable otherwise. 1982 */ 1983 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1984 dev_priv->display.cdclk.hw.cdclk >= 500000) 1985 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 1986 1987 if (cdctl == expected) 1988 /* All well; nothing to sanitize */ 1989 return; 1990 1991 sanitize: 1992 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); 1993 1994 /* force cdclk programming */ 1995 dev_priv->display.cdclk.hw.cdclk = 0; 1996 1997 /* force full PLL disable + enable */ 1998 dev_priv->display.cdclk.hw.vco = -1; 1999 } 2000 2001 static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv) 2002 { 2003 struct intel_cdclk_config cdclk_config; 2004 2005 bxt_sanitize_cdclk(dev_priv); 2006 2007 if (dev_priv->display.cdclk.hw.cdclk != 0 && 2008 dev_priv->display.cdclk.hw.vco != 0) 2009 return; 2010 2011 cdclk_config = dev_priv->display.cdclk.hw; 2012 2013 /* 2014 * FIXME: 2015 * - The initial CDCLK needs to be read from VBT. 2016 * Need to make this change after VBT has changes for BXT. 2017 */ 2018 cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0); 2019 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); 2020 cdclk_config.voltage_level = 2021 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); 2022 2023 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 2024 } 2025 2026 static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv) 2027 { 2028 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; 2029 2030 cdclk_config.cdclk = cdclk_config.bypass; 2031 cdclk_config.vco = 0; 2032 cdclk_config.voltage_level = 2033 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); 2034 2035 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 2036 } 2037 2038 /** 2039 * intel_cdclk_init_hw - Initialize CDCLK hardware 2040 * @i915: i915 device 2041 * 2042 * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and 2043 * sanitizing the state of the hardware if needed. This is generally done only 2044 * during the display core initialization sequence, after which the DMC will 2045 * take care of turning CDCLK off/on as needed. 2046 */ 2047 void intel_cdclk_init_hw(struct drm_i915_private *i915) 2048 { 2049 if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915)) 2050 bxt_cdclk_init_hw(i915); 2051 else if (DISPLAY_VER(i915) == 9) 2052 skl_cdclk_init_hw(i915); 2053 } 2054 2055 /** 2056 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware 2057 * @i915: i915 device 2058 * 2059 * Uninitialize CDCLK. This is done only during the display core 2060 * uninitialization sequence. 2061 */ 2062 void intel_cdclk_uninit_hw(struct drm_i915_private *i915) 2063 { 2064 if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915)) 2065 bxt_cdclk_uninit_hw(i915); 2066 else if (DISPLAY_VER(i915) == 9) 2067 skl_cdclk_uninit_hw(i915); 2068 } 2069 2070 static bool intel_cdclk_can_crawl_and_squash(struct drm_i915_private *i915, 2071 const struct intel_cdclk_config *a, 2072 const struct intel_cdclk_config *b) 2073 { 2074 u16 old_waveform; 2075 u16 new_waveform; 2076 2077 drm_WARN_ON(&i915->drm, cdclk_pll_is_unknown(a->vco)); 2078 2079 if (a->vco == 0 || b->vco == 0) 2080 return false; 2081 2082 if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915)) 2083 return false; 2084 2085 old_waveform = cdclk_squash_waveform(i915, a->cdclk); 2086 new_waveform = cdclk_squash_waveform(i915, b->cdclk); 2087 2088 return a->vco != b->vco && 2089 old_waveform != new_waveform; 2090 } 2091 2092 static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, 2093 const struct intel_cdclk_config *a, 2094 const struct intel_cdclk_config *b) 2095 { 2096 int a_div, b_div; 2097 2098 if (!HAS_CDCLK_CRAWL(dev_priv)) 2099 return false; 2100 2101 /* 2102 * The vco and cd2x divider will change independently 2103 * from each, so we disallow cd2x change when crawling. 2104 */ 2105 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); 2106 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); 2107 2108 return a->vco != 0 && b->vco != 0 && 2109 a->vco != b->vco && 2110 a_div == b_div && 2111 a->ref == b->ref; 2112 } 2113 2114 static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, 2115 const struct intel_cdclk_config *a, 2116 const struct intel_cdclk_config *b) 2117 { 2118 /* 2119 * FIXME should store a bit more state in intel_cdclk_config 2120 * to differentiate squasher vs. cd2x divider properly. For 2121 * the moment all platforms with squasher use a fixed cd2x 2122 * divider. 2123 */ 2124 if (!HAS_CDCLK_SQUASH(dev_priv)) 2125 return false; 2126 2127 return a->cdclk != b->cdclk && 2128 a->vco != 0 && 2129 a->vco == b->vco && 2130 a->ref == b->ref; 2131 } 2132 2133 /** 2134 * intel_cdclk_needs_modeset - Determine if changong between the CDCLK 2135 * configurations requires a modeset on all pipes 2136 * @a: first CDCLK configuration 2137 * @b: second CDCLK configuration 2138 * 2139 * Returns: 2140 * True if changing between the two CDCLK configurations 2141 * requires all pipes to be off, false if not. 2142 */ 2143 bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a, 2144 const struct intel_cdclk_config *b) 2145 { 2146 return a->cdclk != b->cdclk || 2147 a->vco != b->vco || 2148 a->ref != b->ref; 2149 } 2150 2151 /** 2152 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK 2153 * configurations requires only a cd2x divider update 2154 * @dev_priv: i915 device 2155 * @a: first CDCLK configuration 2156 * @b: second CDCLK configuration 2157 * 2158 * Returns: 2159 * True if changing between the two CDCLK configurations 2160 * can be done with just a cd2x divider update, false if not. 2161 */ 2162 static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, 2163 const struct intel_cdclk_config *a, 2164 const struct intel_cdclk_config *b) 2165 { 2166 /* Older hw doesn't have the capability */ 2167 if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv)) 2168 return false; 2169 2170 /* 2171 * FIXME should store a bit more state in intel_cdclk_config 2172 * to differentiate squasher vs. cd2x divider properly. For 2173 * the moment all platforms with squasher use a fixed cd2x 2174 * divider. 2175 */ 2176 if (HAS_CDCLK_SQUASH(dev_priv)) 2177 return false; 2178 2179 return a->cdclk != b->cdclk && 2180 a->vco != 0 && 2181 a->vco == b->vco && 2182 a->ref == b->ref; 2183 } 2184 2185 /** 2186 * intel_cdclk_changed - Determine if two CDCLK configurations are different 2187 * @a: first CDCLK configuration 2188 * @b: second CDCLK configuration 2189 * 2190 * Returns: 2191 * True if the CDCLK configurations don't match, false if they do. 2192 */ 2193 static bool intel_cdclk_changed(const struct intel_cdclk_config *a, 2194 const struct intel_cdclk_config *b) 2195 { 2196 return intel_cdclk_needs_modeset(a, b) || 2197 a->voltage_level != b->voltage_level; 2198 } 2199 2200 void intel_cdclk_dump_config(struct drm_i915_private *i915, 2201 const struct intel_cdclk_config *cdclk_config, 2202 const char *context) 2203 { 2204 drm_dbg_kms(&i915->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", 2205 context, cdclk_config->cdclk, cdclk_config->vco, 2206 cdclk_config->ref, cdclk_config->bypass, 2207 cdclk_config->voltage_level); 2208 } 2209 2210 /** 2211 * intel_set_cdclk - Push the CDCLK configuration to the hardware 2212 * @dev_priv: i915 device 2213 * @cdclk_config: new CDCLK configuration 2214 * @pipe: pipe with which to synchronize the update 2215 * 2216 * Program the hardware based on the passed in CDCLK state, 2217 * if necessary. 2218 */ 2219 static void intel_set_cdclk(struct drm_i915_private *dev_priv, 2220 const struct intel_cdclk_config *cdclk_config, 2221 enum pipe pipe) 2222 { 2223 struct intel_encoder *encoder; 2224 2225 if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config)) 2226 return; 2227 2228 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk)) 2229 return; 2230 2231 intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to"); 2232 2233 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2234 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2235 2236 intel_psr_pause(intel_dp); 2237 } 2238 2239 intel_audio_cdclk_change_pre(dev_priv); 2240 2241 /* 2242 * Lock aux/gmbus while we change cdclk in case those 2243 * functions use cdclk. Not all platforms/ports do, 2244 * but we'll lock them all for simplicity. 2245 */ 2246 mutex_lock(&dev_priv->display.gmbus.mutex); 2247 for_each_intel_dp(&dev_priv->drm, encoder) { 2248 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2249 2250 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, 2251 &dev_priv->display.gmbus.mutex); 2252 } 2253 2254 intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe); 2255 2256 for_each_intel_dp(&dev_priv->drm, encoder) { 2257 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2258 2259 mutex_unlock(&intel_dp->aux.hw_mutex); 2260 } 2261 mutex_unlock(&dev_priv->display.gmbus.mutex); 2262 2263 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2264 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2265 2266 intel_psr_resume(intel_dp); 2267 } 2268 2269 intel_audio_cdclk_change_post(dev_priv); 2270 2271 if (drm_WARN(&dev_priv->drm, 2272 intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config), 2273 "cdclk state doesn't match!\n")) { 2274 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]"); 2275 intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]"); 2276 } 2277 } 2278 2279 /** 2280 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware 2281 * @state: intel atomic state 2282 * 2283 * Program the hardware before updating the HW plane state based on the 2284 * new CDCLK state, if necessary. 2285 */ 2286 void 2287 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) 2288 { 2289 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2290 const struct intel_cdclk_state *old_cdclk_state = 2291 intel_atomic_get_old_cdclk_state(state); 2292 const struct intel_cdclk_state *new_cdclk_state = 2293 intel_atomic_get_new_cdclk_state(state); 2294 enum pipe pipe = new_cdclk_state->pipe; 2295 2296 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2297 &new_cdclk_state->actual)) 2298 return; 2299 2300 if (pipe == INVALID_PIPE || 2301 old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) { 2302 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); 2303 2304 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); 2305 } 2306 } 2307 2308 /** 2309 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware 2310 * @state: intel atomic state 2311 * 2312 * Program the hardware after updating the HW plane state based on the 2313 * new CDCLK state, if necessary. 2314 */ 2315 void 2316 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) 2317 { 2318 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2319 const struct intel_cdclk_state *old_cdclk_state = 2320 intel_atomic_get_old_cdclk_state(state); 2321 const struct intel_cdclk_state *new_cdclk_state = 2322 intel_atomic_get_new_cdclk_state(state); 2323 enum pipe pipe = new_cdclk_state->pipe; 2324 2325 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2326 &new_cdclk_state->actual)) 2327 return; 2328 2329 if (pipe != INVALID_PIPE && 2330 old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) { 2331 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); 2332 2333 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); 2334 } 2335 } 2336 2337 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) 2338 { 2339 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2340 int pixel_rate = crtc_state->pixel_rate; 2341 2342 if (DISPLAY_VER(dev_priv) >= 10) 2343 return DIV_ROUND_UP(pixel_rate, 2); 2344 else if (DISPLAY_VER(dev_priv) == 9 || 2345 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2346 return pixel_rate; 2347 else if (IS_CHERRYVIEW(dev_priv)) 2348 return DIV_ROUND_UP(pixel_rate * 100, 95); 2349 else if (crtc_state->double_wide) 2350 return DIV_ROUND_UP(pixel_rate * 100, 90 * 2); 2351 else 2352 return DIV_ROUND_UP(pixel_rate * 100, 90); 2353 } 2354 2355 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) 2356 { 2357 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2358 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2359 struct intel_plane *plane; 2360 int min_cdclk = 0; 2361 2362 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 2363 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk); 2364 2365 return min_cdclk; 2366 } 2367 2368 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) 2369 { 2370 struct drm_i915_private *dev_priv = 2371 to_i915(crtc_state->uapi.crtc->dev); 2372 int min_cdclk; 2373 2374 if (!crtc_state->hw.enable) 2375 return 0; 2376 2377 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state); 2378 2379 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ 2380 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state)) 2381 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95); 2382 2383 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, 2384 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else 2385 * there may be audio corruption or screen corruption." This cdclk 2386 * restriction for GLK is 316.8 MHz. 2387 */ 2388 if (intel_crtc_has_dp_encoder(crtc_state) && 2389 crtc_state->has_audio && 2390 crtc_state->port_clock >= 540000 && 2391 crtc_state->lane_count == 4) { 2392 if (DISPLAY_VER(dev_priv) == 10) { 2393 /* Display WA #1145: glk */ 2394 min_cdclk = max(316800, min_cdclk); 2395 } else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) { 2396 /* Display WA #1144: skl,bxt */ 2397 min_cdclk = max(432000, min_cdclk); 2398 } 2399 } 2400 2401 /* 2402 * According to BSpec, "The CD clock frequency must be at least twice 2403 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. 2404 */ 2405 if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9) 2406 min_cdclk = max(2 * 96000, min_cdclk); 2407 2408 /* 2409 * "For DP audio configuration, cdclk frequency shall be set to 2410 * meet the following requirements: 2411 * DP Link Frequency(MHz) | Cdclk frequency(MHz) 2412 * 270 | 320 or higher 2413 * 162 | 200 or higher" 2414 */ 2415 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2416 intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio) 2417 min_cdclk = max(crtc_state->port_clock, min_cdclk); 2418 2419 /* 2420 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower 2421 * than 320000KHz. 2422 */ 2423 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 2424 IS_VALLEYVIEW(dev_priv)) 2425 min_cdclk = max(320000, min_cdclk); 2426 2427 /* 2428 * On Geminilake once the CDCLK gets as low as 79200 2429 * picture gets unstable, despite that values are 2430 * correct for DSI PLL and DE PLL. 2431 */ 2432 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 2433 IS_GEMINILAKE(dev_priv)) 2434 min_cdclk = max(158400, min_cdclk); 2435 2436 /* Account for additional needs from the planes */ 2437 min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); 2438 2439 /* 2440 * When we decide to use only one VDSC engine, since 2441 * each VDSC operates with 1 ppc throughput, pixel clock 2442 * cannot be higher than the VDSC clock (cdclk) 2443 */ 2444 if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split) 2445 min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); 2446 2447 /* 2448 * HACK. Currently for TGL/DG2 platforms we calculate 2449 * min_cdclk initially based on pixel_rate divided 2450 * by 2, accounting for also plane requirements, 2451 * however in some cases the lowest possible CDCLK 2452 * doesn't work and causing the underruns. 2453 * Explicitly stating here that this seems to be currently 2454 * rather a Hack, than final solution. 2455 */ 2456 if (IS_TIGERLAKE(dev_priv) || IS_DG2(dev_priv)) { 2457 /* 2458 * Clamp to max_cdclk_freq in case pixel rate is higher, 2459 * in order not to break an 8K, but still leave W/A at place. 2460 */ 2461 min_cdclk = max_t(int, min_cdclk, 2462 min_t(int, crtc_state->pixel_rate, 2463 dev_priv->display.cdclk.max_cdclk_freq)); 2464 } 2465 2466 return min_cdclk; 2467 } 2468 2469 static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) 2470 { 2471 struct intel_atomic_state *state = cdclk_state->base.state; 2472 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2473 const struct intel_bw_state *bw_state; 2474 struct intel_crtc *crtc; 2475 struct intel_crtc_state *crtc_state; 2476 int min_cdclk, i; 2477 enum pipe pipe; 2478 2479 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2480 int ret; 2481 2482 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 2483 if (min_cdclk < 0) 2484 return min_cdclk; 2485 2486 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk) 2487 continue; 2488 2489 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 2490 2491 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2492 if (ret) 2493 return ret; 2494 } 2495 2496 bw_state = intel_atomic_get_new_bw_state(state); 2497 if (bw_state) { 2498 min_cdclk = intel_bw_min_cdclk(dev_priv, bw_state); 2499 2500 if (cdclk_state->bw_min_cdclk != min_cdclk) { 2501 int ret; 2502 2503 cdclk_state->bw_min_cdclk = min_cdclk; 2504 2505 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2506 if (ret) 2507 return ret; 2508 } 2509 } 2510 2511 min_cdclk = max(cdclk_state->force_min_cdclk, 2512 cdclk_state->bw_min_cdclk); 2513 for_each_pipe(dev_priv, pipe) 2514 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); 2515 2516 if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) { 2517 drm_dbg_kms(&dev_priv->drm, 2518 "required cdclk (%d kHz) exceeds max (%d kHz)\n", 2519 min_cdclk, dev_priv->display.cdclk.max_cdclk_freq); 2520 return -EINVAL; 2521 } 2522 2523 return min_cdclk; 2524 } 2525 2526 /* 2527 * Account for port clock min voltage level requirements. 2528 * This only really does something on DISPLA_VER >= 11 but can be 2529 * called on earlier platforms as well. 2530 * 2531 * Note that this functions assumes that 0 is 2532 * the lowest voltage value, and higher values 2533 * correspond to increasingly higher voltages. 2534 * 2535 * Should that relationship no longer hold on 2536 * future platforms this code will need to be 2537 * adjusted. 2538 */ 2539 static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state) 2540 { 2541 struct intel_atomic_state *state = cdclk_state->base.state; 2542 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2543 struct intel_crtc *crtc; 2544 struct intel_crtc_state *crtc_state; 2545 u8 min_voltage_level; 2546 int i; 2547 enum pipe pipe; 2548 2549 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2550 int ret; 2551 2552 if (crtc_state->hw.enable) 2553 min_voltage_level = crtc_state->min_voltage_level; 2554 else 2555 min_voltage_level = 0; 2556 2557 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level) 2558 continue; 2559 2560 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level; 2561 2562 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2563 if (ret) 2564 return ret; 2565 } 2566 2567 min_voltage_level = 0; 2568 for_each_pipe(dev_priv, pipe) 2569 min_voltage_level = max(cdclk_state->min_voltage_level[pipe], 2570 min_voltage_level); 2571 2572 return min_voltage_level; 2573 } 2574 2575 static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2576 { 2577 struct intel_atomic_state *state = cdclk_state->base.state; 2578 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2579 int min_cdclk, cdclk; 2580 2581 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2582 if (min_cdclk < 0) 2583 return min_cdclk; 2584 2585 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); 2586 2587 cdclk_state->logical.cdclk = cdclk; 2588 cdclk_state->logical.voltage_level = 2589 vlv_calc_voltage_level(dev_priv, cdclk); 2590 2591 if (!cdclk_state->active_pipes) { 2592 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); 2593 2594 cdclk_state->actual.cdclk = cdclk; 2595 cdclk_state->actual.voltage_level = 2596 vlv_calc_voltage_level(dev_priv, cdclk); 2597 } else { 2598 cdclk_state->actual = cdclk_state->logical; 2599 } 2600 2601 return 0; 2602 } 2603 2604 static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2605 { 2606 int min_cdclk, cdclk; 2607 2608 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2609 if (min_cdclk < 0) 2610 return min_cdclk; 2611 2612 cdclk = bdw_calc_cdclk(min_cdclk); 2613 2614 cdclk_state->logical.cdclk = cdclk; 2615 cdclk_state->logical.voltage_level = 2616 bdw_calc_voltage_level(cdclk); 2617 2618 if (!cdclk_state->active_pipes) { 2619 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); 2620 2621 cdclk_state->actual.cdclk = cdclk; 2622 cdclk_state->actual.voltage_level = 2623 bdw_calc_voltage_level(cdclk); 2624 } else { 2625 cdclk_state->actual = cdclk_state->logical; 2626 } 2627 2628 return 0; 2629 } 2630 2631 static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state) 2632 { 2633 struct intel_atomic_state *state = cdclk_state->base.state; 2634 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2635 struct intel_crtc *crtc; 2636 struct intel_crtc_state *crtc_state; 2637 int vco, i; 2638 2639 vco = cdclk_state->logical.vco; 2640 if (!vco) 2641 vco = dev_priv->skl_preferred_vco_freq; 2642 2643 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2644 if (!crtc_state->hw.enable) 2645 continue; 2646 2647 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 2648 continue; 2649 2650 /* 2651 * DPLL0 VCO may need to be adjusted to get the correct 2652 * clock for eDP. This will affect cdclk as well. 2653 */ 2654 switch (crtc_state->port_clock / 2) { 2655 case 108000: 2656 case 216000: 2657 vco = 8640000; 2658 break; 2659 default: 2660 vco = 8100000; 2661 break; 2662 } 2663 } 2664 2665 return vco; 2666 } 2667 2668 static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2669 { 2670 int min_cdclk, cdclk, vco; 2671 2672 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2673 if (min_cdclk < 0) 2674 return min_cdclk; 2675 2676 vco = skl_dpll0_vco(cdclk_state); 2677 2678 cdclk = skl_calc_cdclk(min_cdclk, vco); 2679 2680 cdclk_state->logical.vco = vco; 2681 cdclk_state->logical.cdclk = cdclk; 2682 cdclk_state->logical.voltage_level = 2683 skl_calc_voltage_level(cdclk); 2684 2685 if (!cdclk_state->active_pipes) { 2686 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); 2687 2688 cdclk_state->actual.vco = vco; 2689 cdclk_state->actual.cdclk = cdclk; 2690 cdclk_state->actual.voltage_level = 2691 skl_calc_voltage_level(cdclk); 2692 } else { 2693 cdclk_state->actual = cdclk_state->logical; 2694 } 2695 2696 return 0; 2697 } 2698 2699 static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2700 { 2701 struct intel_atomic_state *state = cdclk_state->base.state; 2702 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2703 int min_cdclk, min_voltage_level, cdclk, vco; 2704 2705 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2706 if (min_cdclk < 0) 2707 return min_cdclk; 2708 2709 min_voltage_level = bxt_compute_min_voltage_level(cdclk_state); 2710 if (min_voltage_level < 0) 2711 return min_voltage_level; 2712 2713 cdclk = bxt_calc_cdclk(dev_priv, min_cdclk); 2714 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 2715 2716 cdclk_state->logical.vco = vco; 2717 cdclk_state->logical.cdclk = cdclk; 2718 cdclk_state->logical.voltage_level = 2719 max_t(int, min_voltage_level, 2720 intel_cdclk_calc_voltage_level(dev_priv, cdclk)); 2721 2722 if (!cdclk_state->active_pipes) { 2723 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); 2724 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 2725 2726 cdclk_state->actual.vco = vco; 2727 cdclk_state->actual.cdclk = cdclk; 2728 cdclk_state->actual.voltage_level = 2729 intel_cdclk_calc_voltage_level(dev_priv, cdclk); 2730 } else { 2731 cdclk_state->actual = cdclk_state->logical; 2732 } 2733 2734 return 0; 2735 } 2736 2737 static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2738 { 2739 int min_cdclk; 2740 2741 /* 2742 * We can't change the cdclk frequency, but we still want to 2743 * check that the required minimum frequency doesn't exceed 2744 * the actual cdclk frequency. 2745 */ 2746 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2747 if (min_cdclk < 0) 2748 return min_cdclk; 2749 2750 return 0; 2751 } 2752 2753 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj) 2754 { 2755 struct intel_cdclk_state *cdclk_state; 2756 2757 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); 2758 if (!cdclk_state) 2759 return NULL; 2760 2761 cdclk_state->pipe = INVALID_PIPE; 2762 2763 return &cdclk_state->base; 2764 } 2765 2766 static void intel_cdclk_destroy_state(struct intel_global_obj *obj, 2767 struct intel_global_state *state) 2768 { 2769 kfree(state); 2770 } 2771 2772 static const struct intel_global_state_funcs intel_cdclk_funcs = { 2773 .atomic_duplicate_state = intel_cdclk_duplicate_state, 2774 .atomic_destroy_state = intel_cdclk_destroy_state, 2775 }; 2776 2777 struct intel_cdclk_state * 2778 intel_atomic_get_cdclk_state(struct intel_atomic_state *state) 2779 { 2780 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2781 struct intel_global_state *cdclk_state; 2782 2783 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj); 2784 if (IS_ERR(cdclk_state)) 2785 return ERR_CAST(cdclk_state); 2786 2787 return to_intel_cdclk_state(cdclk_state); 2788 } 2789 2790 int intel_cdclk_atomic_check(struct intel_atomic_state *state, 2791 bool *need_cdclk_calc) 2792 { 2793 const struct intel_cdclk_state *old_cdclk_state; 2794 const struct intel_cdclk_state *new_cdclk_state; 2795 struct intel_plane_state *plane_state; 2796 struct intel_plane *plane; 2797 int ret; 2798 int i; 2799 2800 /* 2801 * active_planes bitmask has been updated, and potentially affected 2802 * planes are part of the state. We can now compute the minimum cdclk 2803 * for each plane. 2804 */ 2805 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 2806 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc); 2807 if (ret) 2808 return ret; 2809 } 2810 2811 ret = intel_bw_calc_min_cdclk(state, need_cdclk_calc); 2812 if (ret) 2813 return ret; 2814 2815 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 2816 new_cdclk_state = intel_atomic_get_new_cdclk_state(state); 2817 2818 if (new_cdclk_state && 2819 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) 2820 *need_cdclk_calc = true; 2821 2822 return 0; 2823 } 2824 2825 int intel_cdclk_init(struct drm_i915_private *dev_priv) 2826 { 2827 struct intel_cdclk_state *cdclk_state; 2828 2829 cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL); 2830 if (!cdclk_state) 2831 return -ENOMEM; 2832 2833 intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj, 2834 &cdclk_state->base, &intel_cdclk_funcs); 2835 2836 return 0; 2837 } 2838 2839 int intel_modeset_calc_cdclk(struct intel_atomic_state *state) 2840 { 2841 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2842 const struct intel_cdclk_state *old_cdclk_state; 2843 struct intel_cdclk_state *new_cdclk_state; 2844 enum pipe pipe = INVALID_PIPE; 2845 int ret; 2846 2847 new_cdclk_state = intel_atomic_get_cdclk_state(state); 2848 if (IS_ERR(new_cdclk_state)) 2849 return PTR_ERR(new_cdclk_state); 2850 2851 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 2852 2853 new_cdclk_state->active_pipes = 2854 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); 2855 2856 ret = intel_cdclk_modeset_calc_cdclk(dev_priv, new_cdclk_state); 2857 if (ret) 2858 return ret; 2859 2860 if (intel_cdclk_changed(&old_cdclk_state->actual, 2861 &new_cdclk_state->actual)) { 2862 /* 2863 * Also serialize commits across all crtcs 2864 * if the actual hw needs to be poked. 2865 */ 2866 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); 2867 if (ret) 2868 return ret; 2869 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes || 2870 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk || 2871 intel_cdclk_changed(&old_cdclk_state->logical, 2872 &new_cdclk_state->logical)) { 2873 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 2874 if (ret) 2875 return ret; 2876 } else { 2877 return 0; 2878 } 2879 2880 if (is_power_of_2(new_cdclk_state->active_pipes) && 2881 intel_cdclk_can_cd2x_update(dev_priv, 2882 &old_cdclk_state->actual, 2883 &new_cdclk_state->actual)) { 2884 struct intel_crtc *crtc; 2885 struct intel_crtc_state *crtc_state; 2886 2887 pipe = ilog2(new_cdclk_state->active_pipes); 2888 crtc = intel_crtc_for_pipe(dev_priv, pipe); 2889 2890 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 2891 if (IS_ERR(crtc_state)) 2892 return PTR_ERR(crtc_state); 2893 2894 if (intel_crtc_needs_modeset(crtc_state)) 2895 pipe = INVALID_PIPE; 2896 } 2897 2898 if (intel_cdclk_can_crawl_and_squash(dev_priv, 2899 &old_cdclk_state->actual, 2900 &new_cdclk_state->actual)) { 2901 drm_dbg_kms(&dev_priv->drm, 2902 "Can change cdclk via crawling and squashing\n"); 2903 } else if (intel_cdclk_can_squash(dev_priv, 2904 &old_cdclk_state->actual, 2905 &new_cdclk_state->actual)) { 2906 drm_dbg_kms(&dev_priv->drm, 2907 "Can change cdclk via squashing\n"); 2908 } else if (intel_cdclk_can_crawl(dev_priv, 2909 &old_cdclk_state->actual, 2910 &new_cdclk_state->actual)) { 2911 drm_dbg_kms(&dev_priv->drm, 2912 "Can change cdclk via crawling\n"); 2913 } else if (pipe != INVALID_PIPE) { 2914 new_cdclk_state->pipe = pipe; 2915 2916 drm_dbg_kms(&dev_priv->drm, 2917 "Can change cdclk cd2x divider with pipe %c active\n", 2918 pipe_name(pipe)); 2919 } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual, 2920 &new_cdclk_state->actual)) { 2921 /* All pipes must be switched off while we change the cdclk. */ 2922 ret = intel_modeset_all_pipes(state, "CDCLK change"); 2923 if (ret) 2924 return ret; 2925 2926 drm_dbg_kms(&dev_priv->drm, 2927 "Modeset required for cdclk change\n"); 2928 } 2929 2930 drm_dbg_kms(&dev_priv->drm, 2931 "New cdclk calculated to be logical %u kHz, actual %u kHz\n", 2932 new_cdclk_state->logical.cdclk, 2933 new_cdclk_state->actual.cdclk); 2934 drm_dbg_kms(&dev_priv->drm, 2935 "New voltage level calculated to be logical %u, actual %u\n", 2936 new_cdclk_state->logical.voltage_level, 2937 new_cdclk_state->actual.voltage_level); 2938 2939 return 0; 2940 } 2941 2942 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) 2943 { 2944 int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq; 2945 2946 if (DISPLAY_VER(dev_priv) >= 10) 2947 return 2 * max_cdclk_freq; 2948 else if (DISPLAY_VER(dev_priv) == 9 || 2949 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2950 return max_cdclk_freq; 2951 else if (IS_CHERRYVIEW(dev_priv)) 2952 return max_cdclk_freq*95/100; 2953 else if (DISPLAY_VER(dev_priv) < 4) 2954 return 2*max_cdclk_freq*90/100; 2955 else 2956 return max_cdclk_freq*90/100; 2957 } 2958 2959 /** 2960 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency 2961 * @dev_priv: i915 device 2962 * 2963 * Determine the maximum CDCLK frequency the platform supports, and also 2964 * derive the maximum dot clock frequency the maximum CDCLK frequency 2965 * allows. 2966 */ 2967 void intel_update_max_cdclk(struct drm_i915_private *dev_priv) 2968 { 2969 if (IS_JSL_EHL(dev_priv)) { 2970 if (dev_priv->display.cdclk.hw.ref == 24000) 2971 dev_priv->display.cdclk.max_cdclk_freq = 552000; 2972 else 2973 dev_priv->display.cdclk.max_cdclk_freq = 556800; 2974 } else if (DISPLAY_VER(dev_priv) >= 11) { 2975 if (dev_priv->display.cdclk.hw.ref == 24000) 2976 dev_priv->display.cdclk.max_cdclk_freq = 648000; 2977 else 2978 dev_priv->display.cdclk.max_cdclk_freq = 652800; 2979 } else if (IS_GEMINILAKE(dev_priv)) { 2980 dev_priv->display.cdclk.max_cdclk_freq = 316800; 2981 } else if (IS_BROXTON(dev_priv)) { 2982 dev_priv->display.cdclk.max_cdclk_freq = 624000; 2983 } else if (DISPLAY_VER(dev_priv) == 9) { 2984 u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; 2985 int max_cdclk, vco; 2986 2987 vco = dev_priv->skl_preferred_vco_freq; 2988 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); 2989 2990 /* 2991 * Use the lower (vco 8640) cdclk values as a 2992 * first guess. skl_calc_cdclk() will correct it 2993 * if the preferred vco is 8100 instead. 2994 */ 2995 if (limit == SKL_DFSM_CDCLK_LIMIT_675) 2996 max_cdclk = 617143; 2997 else if (limit == SKL_DFSM_CDCLK_LIMIT_540) 2998 max_cdclk = 540000; 2999 else if (limit == SKL_DFSM_CDCLK_LIMIT_450) 3000 max_cdclk = 432000; 3001 else 3002 max_cdclk = 308571; 3003 3004 dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); 3005 } else if (IS_BROADWELL(dev_priv)) { 3006 /* 3007 * FIXME with extra cooling we can allow 3008 * 540 MHz for ULX and 675 Mhz for ULT. 3009 * How can we know if extra cooling is 3010 * available? PCI ID, VTB, something else? 3011 */ 3012 if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 3013 dev_priv->display.cdclk.max_cdclk_freq = 450000; 3014 else if (IS_BDW_ULX(dev_priv)) 3015 dev_priv->display.cdclk.max_cdclk_freq = 450000; 3016 else if (IS_BDW_ULT(dev_priv)) 3017 dev_priv->display.cdclk.max_cdclk_freq = 540000; 3018 else 3019 dev_priv->display.cdclk.max_cdclk_freq = 675000; 3020 } else if (IS_CHERRYVIEW(dev_priv)) { 3021 dev_priv->display.cdclk.max_cdclk_freq = 320000; 3022 } else if (IS_VALLEYVIEW(dev_priv)) { 3023 dev_priv->display.cdclk.max_cdclk_freq = 400000; 3024 } else { 3025 /* otherwise assume cdclk is fixed */ 3026 dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk; 3027 } 3028 3029 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); 3030 3031 drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n", 3032 dev_priv->display.cdclk.max_cdclk_freq); 3033 3034 drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n", 3035 dev_priv->max_dotclk_freq); 3036 } 3037 3038 /** 3039 * intel_update_cdclk - Determine the current CDCLK frequency 3040 * @dev_priv: i915 device 3041 * 3042 * Determine the current CDCLK frequency. 3043 */ 3044 void intel_update_cdclk(struct drm_i915_private *dev_priv) 3045 { 3046 intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw); 3047 3048 /* 3049 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): 3050 * Programmng [sic] note: bit[9:2] should be programmed to the number 3051 * of cdclk that generates 4MHz reference clock freq which is used to 3052 * generate GMBus clock. This will vary with the cdclk freq. 3053 */ 3054 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 3055 intel_de_write(dev_priv, GMBUSFREQ_VLV, 3056 DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000)); 3057 } 3058 3059 static int dg1_rawclk(struct drm_i915_private *dev_priv) 3060 { 3061 /* 3062 * DG1 always uses a 38.4 MHz rawclk. The bspec tells us 3063 * "Program Numerator=2, Denominator=4, Divider=37 decimal." 3064 */ 3065 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, 3066 CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2)); 3067 3068 return 38400; 3069 } 3070 3071 static int cnp_rawclk(struct drm_i915_private *dev_priv) 3072 { 3073 u32 rawclk; 3074 int divider, fraction; 3075 3076 if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { 3077 /* 24 MHz */ 3078 divider = 24000; 3079 fraction = 0; 3080 } else { 3081 /* 19.2 MHz */ 3082 divider = 19000; 3083 fraction = 200; 3084 } 3085 3086 rawclk = CNP_RAWCLK_DIV(divider / 1000); 3087 if (fraction) { 3088 int numerator = 1; 3089 3090 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000, 3091 fraction) - 1); 3092 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 3093 rawclk |= ICP_RAWCLK_NUM(numerator); 3094 } 3095 3096 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk); 3097 return divider + fraction; 3098 } 3099 3100 static int pch_rawclk(struct drm_i915_private *dev_priv) 3101 { 3102 return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; 3103 } 3104 3105 static int vlv_hrawclk(struct drm_i915_private *dev_priv) 3106 { 3107 /* RAWCLK_FREQ_VLV register updated from power well code */ 3108 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", 3109 CCK_DISPLAY_REF_CLOCK_CONTROL); 3110 } 3111 3112 static int i9xx_hrawclk(struct drm_i915_private *dev_priv) 3113 { 3114 u32 clkcfg; 3115 3116 /* 3117 * hrawclock is 1/4 the FSB frequency 3118 * 3119 * Note that this only reads the state of the FSB 3120 * straps, not the actual FSB frequency. Some BIOSen 3121 * let you configure each independently. Ideally we'd 3122 * read out the actual FSB frequency but sadly we 3123 * don't know which registers have that information, 3124 * and all the relevant docs have gone to bit heaven :( 3125 */ 3126 clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK; 3127 3128 if (IS_MOBILE(dev_priv)) { 3129 switch (clkcfg) { 3130 case CLKCFG_FSB_400: 3131 return 100000; 3132 case CLKCFG_FSB_533: 3133 return 133333; 3134 case CLKCFG_FSB_667: 3135 return 166667; 3136 case CLKCFG_FSB_800: 3137 return 200000; 3138 case CLKCFG_FSB_1067: 3139 return 266667; 3140 case CLKCFG_FSB_1333: 3141 return 333333; 3142 default: 3143 MISSING_CASE(clkcfg); 3144 return 133333; 3145 } 3146 } else { 3147 switch (clkcfg) { 3148 case CLKCFG_FSB_400_ALT: 3149 return 100000; 3150 case CLKCFG_FSB_533: 3151 return 133333; 3152 case CLKCFG_FSB_667: 3153 return 166667; 3154 case CLKCFG_FSB_800: 3155 return 200000; 3156 case CLKCFG_FSB_1067_ALT: 3157 return 266667; 3158 case CLKCFG_FSB_1333_ALT: 3159 return 333333; 3160 case CLKCFG_FSB_1600_ALT: 3161 return 400000; 3162 default: 3163 return 133333; 3164 } 3165 } 3166 } 3167 3168 /** 3169 * intel_read_rawclk - Determine the current RAWCLK frequency 3170 * @dev_priv: i915 device 3171 * 3172 * Determine the current RAWCLK frequency. RAWCLK is a fixed 3173 * frequency clock so this needs to done only once. 3174 */ 3175 u32 intel_read_rawclk(struct drm_i915_private *dev_priv) 3176 { 3177 u32 freq; 3178 3179 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 3180 freq = dg1_rawclk(dev_priv); 3181 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP) 3182 /* 3183 * MTL always uses a 38.4 MHz rawclk. The bspec tells us 3184 * "RAWCLK_FREQ defaults to the values for 38.4 and does 3185 * not need to be programmed." 3186 */ 3187 freq = 38400; 3188 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) 3189 freq = cnp_rawclk(dev_priv); 3190 else if (HAS_PCH_SPLIT(dev_priv)) 3191 freq = pch_rawclk(dev_priv); 3192 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 3193 freq = vlv_hrawclk(dev_priv); 3194 else if (DISPLAY_VER(dev_priv) >= 3) 3195 freq = i9xx_hrawclk(dev_priv); 3196 else 3197 /* no rawclk on other platforms, or no need to know it */ 3198 return 0; 3199 3200 return freq; 3201 } 3202 3203 static const struct intel_cdclk_funcs mtl_cdclk_funcs = { 3204 .get_cdclk = bxt_get_cdclk, 3205 .set_cdclk = bxt_set_cdclk, 3206 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3207 .calc_voltage_level = tgl_calc_voltage_level, 3208 }; 3209 3210 static const struct intel_cdclk_funcs tgl_cdclk_funcs = { 3211 .get_cdclk = bxt_get_cdclk, 3212 .set_cdclk = bxt_set_cdclk, 3213 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3214 .calc_voltage_level = tgl_calc_voltage_level, 3215 }; 3216 3217 static const struct intel_cdclk_funcs ehl_cdclk_funcs = { 3218 .get_cdclk = bxt_get_cdclk, 3219 .set_cdclk = bxt_set_cdclk, 3220 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3221 .calc_voltage_level = ehl_calc_voltage_level, 3222 }; 3223 3224 static const struct intel_cdclk_funcs icl_cdclk_funcs = { 3225 .get_cdclk = bxt_get_cdclk, 3226 .set_cdclk = bxt_set_cdclk, 3227 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3228 .calc_voltage_level = icl_calc_voltage_level, 3229 }; 3230 3231 static const struct intel_cdclk_funcs bxt_cdclk_funcs = { 3232 .get_cdclk = bxt_get_cdclk, 3233 .set_cdclk = bxt_set_cdclk, 3234 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3235 .calc_voltage_level = bxt_calc_voltage_level, 3236 }; 3237 3238 static const struct intel_cdclk_funcs skl_cdclk_funcs = { 3239 .get_cdclk = skl_get_cdclk, 3240 .set_cdclk = skl_set_cdclk, 3241 .modeset_calc_cdclk = skl_modeset_calc_cdclk, 3242 }; 3243 3244 static const struct intel_cdclk_funcs bdw_cdclk_funcs = { 3245 .get_cdclk = bdw_get_cdclk, 3246 .set_cdclk = bdw_set_cdclk, 3247 .modeset_calc_cdclk = bdw_modeset_calc_cdclk, 3248 }; 3249 3250 static const struct intel_cdclk_funcs chv_cdclk_funcs = { 3251 .get_cdclk = vlv_get_cdclk, 3252 .set_cdclk = chv_set_cdclk, 3253 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3254 }; 3255 3256 static const struct intel_cdclk_funcs vlv_cdclk_funcs = { 3257 .get_cdclk = vlv_get_cdclk, 3258 .set_cdclk = vlv_set_cdclk, 3259 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3260 }; 3261 3262 static const struct intel_cdclk_funcs hsw_cdclk_funcs = { 3263 .get_cdclk = hsw_get_cdclk, 3264 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3265 }; 3266 3267 /* SNB, IVB, 965G, 945G */ 3268 static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = { 3269 .get_cdclk = fixed_400mhz_get_cdclk, 3270 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3271 }; 3272 3273 static const struct intel_cdclk_funcs ilk_cdclk_funcs = { 3274 .get_cdclk = fixed_450mhz_get_cdclk, 3275 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3276 }; 3277 3278 static const struct intel_cdclk_funcs gm45_cdclk_funcs = { 3279 .get_cdclk = gm45_get_cdclk, 3280 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3281 }; 3282 3283 /* G45 uses G33 */ 3284 3285 static const struct intel_cdclk_funcs i965gm_cdclk_funcs = { 3286 .get_cdclk = i965gm_get_cdclk, 3287 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3288 }; 3289 3290 /* i965G uses fixed 400 */ 3291 3292 static const struct intel_cdclk_funcs pnv_cdclk_funcs = { 3293 .get_cdclk = pnv_get_cdclk, 3294 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3295 }; 3296 3297 static const struct intel_cdclk_funcs g33_cdclk_funcs = { 3298 .get_cdclk = g33_get_cdclk, 3299 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3300 }; 3301 3302 static const struct intel_cdclk_funcs i945gm_cdclk_funcs = { 3303 .get_cdclk = i945gm_get_cdclk, 3304 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3305 }; 3306 3307 /* i945G uses fixed 400 */ 3308 3309 static const struct intel_cdclk_funcs i915gm_cdclk_funcs = { 3310 .get_cdclk = i915gm_get_cdclk, 3311 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3312 }; 3313 3314 static const struct intel_cdclk_funcs i915g_cdclk_funcs = { 3315 .get_cdclk = fixed_333mhz_get_cdclk, 3316 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3317 }; 3318 3319 static const struct intel_cdclk_funcs i865g_cdclk_funcs = { 3320 .get_cdclk = fixed_266mhz_get_cdclk, 3321 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3322 }; 3323 3324 static const struct intel_cdclk_funcs i85x_cdclk_funcs = { 3325 .get_cdclk = i85x_get_cdclk, 3326 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3327 }; 3328 3329 static const struct intel_cdclk_funcs i845g_cdclk_funcs = { 3330 .get_cdclk = fixed_200mhz_get_cdclk, 3331 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3332 }; 3333 3334 static const struct intel_cdclk_funcs i830_cdclk_funcs = { 3335 .get_cdclk = fixed_133mhz_get_cdclk, 3336 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3337 }; 3338 3339 /** 3340 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks 3341 * @dev_priv: i915 device 3342 */ 3343 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) 3344 { 3345 if (IS_METEORLAKE(dev_priv)) { 3346 dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs; 3347 dev_priv->display.cdclk.table = mtl_cdclk_table; 3348 } else if (IS_DG2(dev_priv)) { 3349 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3350 dev_priv->display.cdclk.table = dg2_cdclk_table; 3351 } else if (IS_ALDERLAKE_P(dev_priv)) { 3352 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3353 /* Wa_22011320316:adl-p[a0] */ 3354 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 3355 dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; 3356 else 3357 dev_priv->display.cdclk.table = adlp_cdclk_table; 3358 } else if (IS_ROCKETLAKE(dev_priv)) { 3359 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3360 dev_priv->display.cdclk.table = rkl_cdclk_table; 3361 } else if (DISPLAY_VER(dev_priv) >= 12) { 3362 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3363 dev_priv->display.cdclk.table = icl_cdclk_table; 3364 } else if (IS_JSL_EHL(dev_priv)) { 3365 dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs; 3366 dev_priv->display.cdclk.table = icl_cdclk_table; 3367 } else if (DISPLAY_VER(dev_priv) >= 11) { 3368 dev_priv->display.funcs.cdclk = &icl_cdclk_funcs; 3369 dev_priv->display.cdclk.table = icl_cdclk_table; 3370 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 3371 dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs; 3372 if (IS_GEMINILAKE(dev_priv)) 3373 dev_priv->display.cdclk.table = glk_cdclk_table; 3374 else 3375 dev_priv->display.cdclk.table = bxt_cdclk_table; 3376 } else if (DISPLAY_VER(dev_priv) == 9) { 3377 dev_priv->display.funcs.cdclk = &skl_cdclk_funcs; 3378 } else if (IS_BROADWELL(dev_priv)) { 3379 dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs; 3380 } else if (IS_HASWELL(dev_priv)) { 3381 dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs; 3382 } else if (IS_CHERRYVIEW(dev_priv)) { 3383 dev_priv->display.funcs.cdclk = &chv_cdclk_funcs; 3384 } else if (IS_VALLEYVIEW(dev_priv)) { 3385 dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs; 3386 } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) { 3387 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3388 } else if (IS_IRONLAKE(dev_priv)) { 3389 dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs; 3390 } else if (IS_GM45(dev_priv)) { 3391 dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs; 3392 } else if (IS_G45(dev_priv)) { 3393 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; 3394 } else if (IS_I965GM(dev_priv)) { 3395 dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs; 3396 } else if (IS_I965G(dev_priv)) { 3397 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3398 } else if (IS_PINEVIEW(dev_priv)) { 3399 dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs; 3400 } else if (IS_G33(dev_priv)) { 3401 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; 3402 } else if (IS_I945GM(dev_priv)) { 3403 dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs; 3404 } else if (IS_I945G(dev_priv)) { 3405 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3406 } else if (IS_I915GM(dev_priv)) { 3407 dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs; 3408 } else if (IS_I915G(dev_priv)) { 3409 dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs; 3410 } else if (IS_I865G(dev_priv)) { 3411 dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs; 3412 } else if (IS_I85X(dev_priv)) { 3413 dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs; 3414 } else if (IS_I845G(dev_priv)) { 3415 dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs; 3416 } else if (IS_I830(dev_priv)) { 3417 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; 3418 } 3419 3420 if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk, 3421 "Unknown platform. Assuming i830\n")) 3422 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; 3423 } 3424