1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2019 Intel Corporation
4  */
5 
6 #ifndef __INTEL_BW_H__
7 #define __INTEL_BW_H__
8 
9 #include <drm/drm_atomic.h>
10 
11 #include "intel_display.h"
12 #include "intel_display_power.h"
13 #include "intel_global_state.h"
14 
15 struct drm_i915_private;
16 struct intel_atomic_state;
17 struct intel_crtc_state;
18 
19 struct intel_dbuf_bw {
20 	int used_bw[I915_MAX_DBUF_SLICES];
21 };
22 
23 struct intel_bw_state {
24 	struct intel_global_state base;
25 	struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES];
26 
27 	/*
28 	 * Contains a bit mask, used to determine, whether correspondent
29 	 * pipe allows SAGV or not.
30 	 */
31 	u8 pipe_sagv_reject;
32 
33 	/*
34 	 * Current QGV points mask, which restricts
35 	 * some particular SAGV states, not to confuse
36 	 * with pipe_sagv_mask.
37 	 */
38 	u8 qgv_points_mask;
39 
40 	unsigned int data_rate[I915_MAX_PIPES];
41 	u8 num_active_planes[I915_MAX_PIPES];
42 
43 	/* bitmask of active pipes */
44 	u8 active_pipes;
45 
46 	int min_cdclk;
47 };
48 
49 #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
50 
51 struct intel_bw_state *
52 intel_atomic_get_old_bw_state(struct intel_atomic_state *state);
53 
54 struct intel_bw_state *
55 intel_atomic_get_new_bw_state(struct intel_atomic_state *state);
56 
57 struct intel_bw_state *
58 intel_atomic_get_bw_state(struct intel_atomic_state *state);
59 
60 void intel_bw_init_hw(struct drm_i915_private *dev_priv);
61 int intel_bw_init(struct drm_i915_private *dev_priv);
62 int intel_bw_atomic_check(struct intel_atomic_state *state);
63 void intel_bw_crtc_update(struct intel_bw_state *bw_state,
64 			  const struct intel_crtc_state *crtc_state);
65 int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
66 				  u32 points_mask);
67 int intel_bw_calc_min_cdclk(struct intel_atomic_state *state);
68 int skl_bw_calc_min_cdclk(struct intel_atomic_state *state);
69 
70 #endif /* __INTEL_BW_H__ */
71