1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_BW_H__ 7 #define __INTEL_BW_H__ 8 9 #include <drm/drm_atomic.h> 10 11 #include "intel_display.h" 12 #include "intel_global_state.h" 13 14 struct drm_i915_private; 15 struct intel_atomic_state; 16 struct intel_crtc_state; 17 18 struct intel_bw_state { 19 struct intel_global_state base; 20 21 /* 22 * Contains a bit mask, used to determine, whether correspondent 23 * pipe allows SAGV or not. 24 */ 25 u8 pipe_sagv_reject; 26 27 /* 28 * Current QGV points mask, which restricts 29 * some particular SAGV states, not to confuse 30 * with pipe_sagv_mask. 31 */ 32 u8 qgv_points_mask; 33 34 unsigned int data_rate[I915_MAX_PIPES]; 35 u8 num_active_planes[I915_MAX_PIPES]; 36 37 /* bitmask of active pipes */ 38 u8 active_pipes; 39 }; 40 41 #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base) 42 43 struct intel_bw_state * 44 intel_atomic_get_old_bw_state(struct intel_atomic_state *state); 45 46 struct intel_bw_state * 47 intel_atomic_get_new_bw_state(struct intel_atomic_state *state); 48 49 struct intel_bw_state * 50 intel_atomic_get_bw_state(struct intel_atomic_state *state); 51 52 void intel_bw_init_hw(struct drm_i915_private *dev_priv); 53 int intel_bw_init(struct drm_i915_private *dev_priv); 54 int intel_bw_atomic_check(struct intel_atomic_state *state); 55 void intel_bw_crtc_update(struct intel_bw_state *bw_state, 56 const struct intel_crtc_state *crtc_state); 57 int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv, 58 u32 points_mask); 59 60 #endif /* __INTEL_BW_H__ */ 61