1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <drm/drm_atomic_state_helper.h> 7 8 #include "intel_bw.h" 9 #include "intel_display_types.h" 10 #include "intel_sideband.h" 11 12 /* Parameters for Qclk Geyserville (QGV) */ 13 struct intel_qgv_point { 14 u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd; 15 }; 16 17 struct intel_qgv_info { 18 struct intel_qgv_point points[3]; 19 u8 num_points; 20 u8 num_channels; 21 u8 t_bl; 22 enum intel_dram_type dram_type; 23 }; 24 25 static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv, 26 struct intel_qgv_info *qi) 27 { 28 u32 val = 0; 29 int ret; 30 31 ret = sandybridge_pcode_read(dev_priv, 32 ICL_PCODE_MEM_SUBSYSYSTEM_INFO | 33 ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, 34 &val, NULL); 35 if (ret) 36 return ret; 37 38 if (IS_GEN(dev_priv, 12)) { 39 switch (val & 0xf) { 40 case 0: 41 qi->dram_type = INTEL_DRAM_DDR4; 42 break; 43 case 3: 44 qi->dram_type = INTEL_DRAM_LPDDR4; 45 break; 46 case 4: 47 qi->dram_type = INTEL_DRAM_DDR3; 48 break; 49 case 5: 50 qi->dram_type = INTEL_DRAM_LPDDR3; 51 break; 52 default: 53 MISSING_CASE(val & 0xf); 54 break; 55 } 56 } else if (IS_GEN(dev_priv, 11)) { 57 switch (val & 0xf) { 58 case 0: 59 qi->dram_type = INTEL_DRAM_DDR4; 60 break; 61 case 1: 62 qi->dram_type = INTEL_DRAM_DDR3; 63 break; 64 case 2: 65 qi->dram_type = INTEL_DRAM_LPDDR3; 66 break; 67 case 3: 68 qi->dram_type = INTEL_DRAM_LPDDR4; 69 break; 70 default: 71 MISSING_CASE(val & 0xf); 72 break; 73 } 74 } else { 75 MISSING_CASE(INTEL_GEN(dev_priv)); 76 qi->dram_type = INTEL_DRAM_LPDDR3; /* Conservative default */ 77 } 78 79 qi->num_channels = (val & 0xf0) >> 4; 80 qi->num_points = (val & 0xf00) >> 8; 81 82 if (IS_GEN(dev_priv, 12)) 83 qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 16; 84 else if (IS_GEN(dev_priv, 11)) 85 qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8; 86 87 return 0; 88 } 89 90 static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv, 91 struct intel_qgv_point *sp, 92 int point) 93 { 94 u32 val = 0, val2 = 0; 95 int ret; 96 97 ret = sandybridge_pcode_read(dev_priv, 98 ICL_PCODE_MEM_SUBSYSYSTEM_INFO | 99 ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point), 100 &val, &val2); 101 if (ret) 102 return ret; 103 104 sp->dclk = val & 0xffff; 105 sp->t_rp = (val & 0xff0000) >> 16; 106 sp->t_rcd = (val & 0xff000000) >> 24; 107 108 sp->t_rdpre = val2 & 0xff; 109 sp->t_ras = (val2 & 0xff00) >> 8; 110 111 sp->t_rc = sp->t_rp + sp->t_ras; 112 113 return 0; 114 } 115 116 static int icl_get_qgv_points(struct drm_i915_private *dev_priv, 117 struct intel_qgv_info *qi) 118 { 119 int i, ret; 120 121 ret = icl_pcode_read_mem_global_info(dev_priv, qi); 122 if (ret) 123 return ret; 124 125 if (WARN_ON(qi->num_points > ARRAY_SIZE(qi->points))) 126 qi->num_points = ARRAY_SIZE(qi->points); 127 128 for (i = 0; i < qi->num_points; i++) { 129 struct intel_qgv_point *sp = &qi->points[i]; 130 131 ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i); 132 if (ret) 133 return ret; 134 135 DRM_DEBUG_KMS("QGV %d: DCLK=%d tRP=%d tRDPRE=%d tRAS=%d tRCD=%d tRC=%d\n", 136 i, sp->dclk, sp->t_rp, sp->t_rdpre, sp->t_ras, 137 sp->t_rcd, sp->t_rc); 138 } 139 140 return 0; 141 } 142 143 static int icl_calc_bw(int dclk, int num, int den) 144 { 145 /* multiples of 16.666MHz (100/6) */ 146 return DIV_ROUND_CLOSEST(num * dclk * 100, den * 6); 147 } 148 149 static int icl_sagv_max_dclk(const struct intel_qgv_info *qi) 150 { 151 u16 dclk = 0; 152 int i; 153 154 for (i = 0; i < qi->num_points; i++) 155 dclk = max(dclk, qi->points[i].dclk); 156 157 return dclk; 158 } 159 160 struct intel_sa_info { 161 u16 displayrtids; 162 u8 deburst, deprogbwlimit; 163 }; 164 165 static const struct intel_sa_info icl_sa_info = { 166 .deburst = 8, 167 .deprogbwlimit = 25, /* GB/s */ 168 .displayrtids = 128, 169 }; 170 171 static const struct intel_sa_info tgl_sa_info = { 172 .deburst = 16, 173 .deprogbwlimit = 34, /* GB/s */ 174 .displayrtids = 256, 175 }; 176 177 static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa) 178 { 179 struct intel_qgv_info qi = {}; 180 bool is_y_tile = true; /* assume y tile may be used */ 181 int num_channels; 182 int deinterleave; 183 int ipqdepth, ipqdepthpch; 184 int dclk_max; 185 int maxdebw; 186 int i, ret; 187 188 ret = icl_get_qgv_points(dev_priv, &qi); 189 if (ret) { 190 DRM_DEBUG_KMS("Failed to get memory subsystem information, ignoring bandwidth limits"); 191 return ret; 192 } 193 num_channels = qi.num_channels; 194 195 deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2); 196 dclk_max = icl_sagv_max_dclk(&qi); 197 198 ipqdepthpch = 16; 199 200 maxdebw = min(sa->deprogbwlimit * 1000, 201 icl_calc_bw(dclk_max, 16, 1) * 6 / 10); /* 60% */ 202 ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels); 203 204 for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) { 205 struct intel_bw_info *bi = &dev_priv->max_bw[i]; 206 int clpchgroup; 207 int j; 208 209 clpchgroup = (sa->deburst * deinterleave / num_channels) << i; 210 bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1; 211 212 bi->num_qgv_points = qi.num_points; 213 214 for (j = 0; j < qi.num_points; j++) { 215 const struct intel_qgv_point *sp = &qi.points[j]; 216 int ct, bw; 217 218 /* 219 * Max row cycle time 220 * 221 * FIXME what is the logic behind the 222 * assumed burst length? 223 */ 224 ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd + 225 (clpchgroup - 1) * qi.t_bl + sp->t_rdpre); 226 bw = icl_calc_bw(sp->dclk, clpchgroup * 32 * num_channels, ct); 227 228 bi->deratedbw[j] = min(maxdebw, 229 bw * 9 / 10); /* 90% */ 230 231 DRM_DEBUG_KMS("BW%d / QGV %d: num_planes=%d deratedbw=%u\n", 232 i, j, bi->num_planes, bi->deratedbw[j]); 233 } 234 235 if (bi->num_planes == 1) 236 break; 237 } 238 239 return 0; 240 } 241 242 static unsigned int icl_max_bw(struct drm_i915_private *dev_priv, 243 int num_planes, int qgv_point) 244 { 245 int i; 246 247 for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) { 248 const struct intel_bw_info *bi = 249 &dev_priv->max_bw[i]; 250 251 /* 252 * Pcode will not expose all QGV points when 253 * SAGV is forced to off/min/med/max. 254 */ 255 if (qgv_point >= bi->num_qgv_points) 256 return UINT_MAX; 257 258 if (num_planes >= bi->num_planes) 259 return bi->deratedbw[qgv_point]; 260 } 261 262 return 0; 263 } 264 265 void intel_bw_init_hw(struct drm_i915_private *dev_priv) 266 { 267 if (IS_GEN(dev_priv, 12)) 268 icl_get_bw_info(dev_priv, &tgl_sa_info); 269 else if (IS_GEN(dev_priv, 11)) 270 icl_get_bw_info(dev_priv, &icl_sa_info); 271 } 272 273 static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv, 274 int num_planes) 275 { 276 if (INTEL_GEN(dev_priv) >= 11) 277 /* 278 * FIXME with SAGV disabled maybe we can assume 279 * point 1 will always be used? Seems to match 280 * the behaviour observed in the wild. 281 */ 282 return min3(icl_max_bw(dev_priv, num_planes, 0), 283 icl_max_bw(dev_priv, num_planes, 1), 284 icl_max_bw(dev_priv, num_planes, 2)); 285 else 286 return UINT_MAX; 287 } 288 289 static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state) 290 { 291 /* 292 * We assume cursors are small enough 293 * to not not cause bandwidth problems. 294 */ 295 return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR)); 296 } 297 298 static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_state) 299 { 300 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 301 unsigned int data_rate = 0; 302 enum plane_id plane_id; 303 304 for_each_plane_id_on_crtc(crtc, plane_id) { 305 /* 306 * We assume cursors are small enough 307 * to not not cause bandwidth problems. 308 */ 309 if (plane_id == PLANE_CURSOR) 310 continue; 311 312 data_rate += crtc_state->data_rate[plane_id]; 313 } 314 315 return data_rate; 316 } 317 318 void intel_bw_crtc_update(struct intel_bw_state *bw_state, 319 const struct intel_crtc_state *crtc_state) 320 { 321 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 322 323 bw_state->data_rate[crtc->pipe] = 324 intel_bw_crtc_data_rate(crtc_state); 325 bw_state->num_active_planes[crtc->pipe] = 326 intel_bw_crtc_num_active_planes(crtc_state); 327 328 DRM_DEBUG_KMS("pipe %c data rate %u num active planes %u\n", 329 pipe_name(crtc->pipe), 330 bw_state->data_rate[crtc->pipe], 331 bw_state->num_active_planes[crtc->pipe]); 332 } 333 334 static unsigned int intel_bw_num_active_planes(struct drm_i915_private *dev_priv, 335 const struct intel_bw_state *bw_state) 336 { 337 unsigned int num_active_planes = 0; 338 enum pipe pipe; 339 340 for_each_pipe(dev_priv, pipe) 341 num_active_planes += bw_state->num_active_planes[pipe]; 342 343 return num_active_planes; 344 } 345 346 static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv, 347 const struct intel_bw_state *bw_state) 348 { 349 unsigned int data_rate = 0; 350 enum pipe pipe; 351 352 for_each_pipe(dev_priv, pipe) 353 data_rate += bw_state->data_rate[pipe]; 354 355 return data_rate; 356 } 357 358 static struct intel_bw_state * 359 intel_atomic_get_bw_state(struct intel_atomic_state *state) 360 { 361 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 362 struct drm_private_state *bw_state; 363 364 bw_state = drm_atomic_get_private_obj_state(&state->base, 365 &dev_priv->bw_obj); 366 if (IS_ERR(bw_state)) 367 return ERR_CAST(bw_state); 368 369 return to_intel_bw_state(bw_state); 370 } 371 372 int intel_bw_atomic_check(struct intel_atomic_state *state) 373 { 374 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 375 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 376 struct intel_bw_state *bw_state = NULL; 377 unsigned int data_rate, max_data_rate; 378 unsigned int num_active_planes; 379 struct intel_crtc *crtc; 380 int i; 381 382 /* FIXME earlier gens need some checks too */ 383 if (INTEL_GEN(dev_priv) < 11) 384 return 0; 385 386 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 387 new_crtc_state, i) { 388 unsigned int old_data_rate = 389 intel_bw_crtc_data_rate(old_crtc_state); 390 unsigned int new_data_rate = 391 intel_bw_crtc_data_rate(new_crtc_state); 392 unsigned int old_active_planes = 393 intel_bw_crtc_num_active_planes(old_crtc_state); 394 unsigned int new_active_planes = 395 intel_bw_crtc_num_active_planes(new_crtc_state); 396 397 /* 398 * Avoid locking the bw state when 399 * nothing significant has changed. 400 */ 401 if (old_data_rate == new_data_rate && 402 old_active_planes == new_active_planes) 403 continue; 404 405 bw_state = intel_atomic_get_bw_state(state); 406 if (IS_ERR(bw_state)) 407 return PTR_ERR(bw_state); 408 409 bw_state->data_rate[crtc->pipe] = new_data_rate; 410 bw_state->num_active_planes[crtc->pipe] = new_active_planes; 411 412 DRM_DEBUG_KMS("pipe %c data rate %u num active planes %u\n", 413 pipe_name(crtc->pipe), 414 bw_state->data_rate[crtc->pipe], 415 bw_state->num_active_planes[crtc->pipe]); 416 } 417 418 if (!bw_state) 419 return 0; 420 421 data_rate = intel_bw_data_rate(dev_priv, bw_state); 422 num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state); 423 424 max_data_rate = intel_max_data_rate(dev_priv, num_active_planes); 425 426 data_rate = DIV_ROUND_UP(data_rate, 1000); 427 428 if (data_rate > max_data_rate) { 429 DRM_DEBUG_KMS("Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n", 430 data_rate, max_data_rate, num_active_planes); 431 return -EINVAL; 432 } 433 434 return 0; 435 } 436 437 static struct drm_private_state *intel_bw_duplicate_state(struct drm_private_obj *obj) 438 { 439 struct intel_bw_state *state; 440 441 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); 442 if (!state) 443 return NULL; 444 445 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); 446 447 return &state->base; 448 } 449 450 static void intel_bw_destroy_state(struct drm_private_obj *obj, 451 struct drm_private_state *state) 452 { 453 kfree(state); 454 } 455 456 static const struct drm_private_state_funcs intel_bw_funcs = { 457 .atomic_duplicate_state = intel_bw_duplicate_state, 458 .atomic_destroy_state = intel_bw_destroy_state, 459 }; 460 461 int intel_bw_init(struct drm_i915_private *dev_priv) 462 { 463 struct intel_bw_state *state; 464 465 state = kzalloc(sizeof(*state), GFP_KERNEL); 466 if (!state) 467 return -ENOMEM; 468 469 drm_atomic_private_obj_init(&dev_priv->drm, &dev_priv->bw_obj, 470 &state->base, &intel_bw_funcs); 471 472 return 0; 473 } 474