1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 */ 23 24 /* 25 * Please use intel_vbt_defs.h for VBT private data, to hide and abstract away 26 * the VBT from the rest of the driver. Add the parsed, clean data to struct 27 * intel_vbt_data within struct drm_i915_private. 28 */ 29 30 #ifndef _INTEL_BIOS_H_ 31 #define _INTEL_BIOS_H_ 32 33 #include <linux/types.h> 34 35 #include <drm/i915_drm.h> 36 37 struct drm_i915_private; 38 39 enum intel_backlight_type { 40 INTEL_BACKLIGHT_PMIC, 41 INTEL_BACKLIGHT_LPSS, 42 INTEL_BACKLIGHT_DISPLAY_DDI, 43 INTEL_BACKLIGHT_DSI_DCS, 44 INTEL_BACKLIGHT_PANEL_DRIVER_INTERFACE, 45 }; 46 47 struct edp_power_seq { 48 u16 t1_t3; 49 u16 t8; 50 u16 t9; 51 u16 t10; 52 u16 t11_t12; 53 } __packed; 54 55 /* 56 * MIPI Sequence Block definitions 57 * 58 * Note the VBT spec has AssertReset / DeassertReset swapped from their 59 * usual naming, we use the proper names here to avoid confusion when 60 * reading the code. 61 */ 62 enum mipi_seq { 63 MIPI_SEQ_END = 0, 64 MIPI_SEQ_DEASSERT_RESET, /* Spec says MipiAssertResetPin */ 65 MIPI_SEQ_INIT_OTP, 66 MIPI_SEQ_DISPLAY_ON, 67 MIPI_SEQ_DISPLAY_OFF, 68 MIPI_SEQ_ASSERT_RESET, /* Spec says MipiDeassertResetPin */ 69 MIPI_SEQ_BACKLIGHT_ON, /* sequence block v2+ */ 70 MIPI_SEQ_BACKLIGHT_OFF, /* sequence block v2+ */ 71 MIPI_SEQ_TEAR_ON, /* sequence block v2+ */ 72 MIPI_SEQ_TEAR_OFF, /* sequence block v3+ */ 73 MIPI_SEQ_POWER_ON, /* sequence block v3+ */ 74 MIPI_SEQ_POWER_OFF, /* sequence block v3+ */ 75 MIPI_SEQ_MAX 76 }; 77 78 enum mipi_seq_element { 79 MIPI_SEQ_ELEM_END = 0, 80 MIPI_SEQ_ELEM_SEND_PKT, 81 MIPI_SEQ_ELEM_DELAY, 82 MIPI_SEQ_ELEM_GPIO, 83 MIPI_SEQ_ELEM_I2C, /* sequence block v2+ */ 84 MIPI_SEQ_ELEM_SPI, /* sequence block v3+ */ 85 MIPI_SEQ_ELEM_PMIC, /* sequence block v3+ */ 86 MIPI_SEQ_ELEM_MAX 87 }; 88 89 #define MIPI_DSI_UNDEFINED_PANEL_ID 0 90 #define MIPI_DSI_GENERIC_PANEL_ID 1 91 92 struct mipi_config { 93 u16 panel_id; 94 95 /* General Params */ 96 u32 enable_dithering:1; 97 u32 rsvd1:1; 98 u32 is_bridge:1; 99 100 u32 panel_arch_type:2; 101 u32 is_cmd_mode:1; 102 103 #define NON_BURST_SYNC_PULSE 0x1 104 #define NON_BURST_SYNC_EVENTS 0x2 105 #define BURST_MODE 0x3 106 u32 video_transfer_mode:2; 107 108 u32 cabc_supported:1; 109 #define PPS_BLC_PMIC 0 110 #define PPS_BLC_SOC 1 111 u32 pwm_blc:1; 112 113 /* Bit 13:10 */ 114 #define PIXEL_FORMAT_RGB565 0x1 115 #define PIXEL_FORMAT_RGB666 0x2 116 #define PIXEL_FORMAT_RGB666_LOOSELY_PACKED 0x3 117 #define PIXEL_FORMAT_RGB888 0x4 118 u32 videomode_color_format:4; 119 120 /* Bit 15:14 */ 121 #define ENABLE_ROTATION_0 0x0 122 #define ENABLE_ROTATION_90 0x1 123 #define ENABLE_ROTATION_180 0x2 124 #define ENABLE_ROTATION_270 0x3 125 u32 rotation:2; 126 u32 bta_enabled:1; 127 u32 rsvd2:15; 128 129 /* 2 byte Port Description */ 130 #define DUAL_LINK_NOT_SUPPORTED 0 131 #define DUAL_LINK_FRONT_BACK 1 132 #define DUAL_LINK_PIXEL_ALT 2 133 u16 dual_link:2; 134 u16 lane_cnt:2; 135 u16 pixel_overlap:3; 136 u16 rgb_flip:1; 137 #define DL_DCS_PORT_A 0x00 138 #define DL_DCS_PORT_C 0x01 139 #define DL_DCS_PORT_A_AND_C 0x02 140 u16 dl_dcs_cabc_ports:2; 141 u16 dl_dcs_backlight_ports:2; 142 u16 rsvd3:4; 143 144 u16 rsvd4; 145 146 u8 rsvd5; 147 u32 target_burst_mode_freq; 148 u32 dsi_ddr_clk; 149 u32 bridge_ref_clk; 150 151 #define BYTE_CLK_SEL_20MHZ 0 152 #define BYTE_CLK_SEL_10MHZ 1 153 #define BYTE_CLK_SEL_5MHZ 2 154 u8 byte_clk_sel:2; 155 156 u8 rsvd6:6; 157 158 /* DPHY Flags */ 159 u16 dphy_param_valid:1; 160 u16 eot_pkt_disabled:1; 161 u16 enable_clk_stop:1; 162 u16 rsvd7:13; 163 164 u32 hs_tx_timeout; 165 u32 lp_rx_timeout; 166 u32 turn_around_timeout; 167 u32 device_reset_timer; 168 u32 master_init_timer; 169 u32 dbi_bw_timer; 170 u32 lp_byte_clk_val; 171 172 /* 4 byte Dphy Params */ 173 u32 prepare_cnt:6; 174 u32 rsvd8:2; 175 u32 clk_zero_cnt:8; 176 u32 trail_cnt:5; 177 u32 rsvd9:3; 178 u32 exit_zero_cnt:6; 179 u32 rsvd10:2; 180 181 u32 clk_lane_switch_cnt; 182 u32 hl_switch_cnt; 183 184 u32 rsvd11[6]; 185 186 /* timings based on dphy spec */ 187 u8 tclk_miss; 188 u8 tclk_post; 189 u8 rsvd12; 190 u8 tclk_pre; 191 u8 tclk_prepare; 192 u8 tclk_settle; 193 u8 tclk_term_enable; 194 u8 tclk_trail; 195 u16 tclk_prepare_clkzero; 196 u8 rsvd13; 197 u8 td_term_enable; 198 u8 teot; 199 u8 ths_exit; 200 u8 ths_prepare; 201 u16 ths_prepare_hszero; 202 u8 rsvd14; 203 u8 ths_settle; 204 u8 ths_skip; 205 u8 ths_trail; 206 u8 tinit; 207 u8 tlpx; 208 u8 rsvd15[3]; 209 210 /* GPIOs */ 211 u8 panel_enable; 212 u8 bl_enable; 213 u8 pwm_enable; 214 u8 reset_r_n; 215 u8 pwr_down_r; 216 u8 stdby_r_n; 217 218 } __packed; 219 220 /* all delays have a unit of 100us */ 221 struct mipi_pps_data { 222 u16 panel_on_delay; 223 u16 bl_enable_delay; 224 u16 bl_disable_delay; 225 u16 panel_off_delay; 226 u16 panel_power_cycle_delay; 227 } __packed; 228 229 void intel_bios_init(struct drm_i915_private *dev_priv); 230 void intel_bios_cleanup(struct drm_i915_private *dev_priv); 231 bool intel_bios_is_valid_vbt(const void *buf, size_t size); 232 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv); 233 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin); 234 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port); 235 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port); 236 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port); 237 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port); 238 bool intel_bios_is_port_hpd_inverted(const struct drm_i915_private *i915, 239 enum port port); 240 bool intel_bios_is_lspcon_present(const struct drm_i915_private *i915, 241 enum port port); 242 enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, enum port port); 243 244 #endif /* _INTEL_BIOS_H_ */ 245