1 /*
2  * Copyright © 2016-2019 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  */
23 
24 /*
25  * Please use intel_vbt_defs.h for VBT private data, to hide and abstract away
26  * the VBT from the rest of the driver. Add the parsed, clean data to struct
27  * intel_vbt_data within struct drm_i915_private.
28  */
29 
30 #ifndef _INTEL_BIOS_H_
31 #define _INTEL_BIOS_H_
32 
33 #include <linux/types.h>
34 
35 #include <drm/i915_drm.h>
36 
37 struct drm_i915_private;
38 struct intel_crtc_state;
39 struct intel_encoder;
40 enum port;
41 
42 enum intel_backlight_type {
43 	INTEL_BACKLIGHT_PMIC,
44 	INTEL_BACKLIGHT_LPSS,
45 	INTEL_BACKLIGHT_DISPLAY_DDI,
46 	INTEL_BACKLIGHT_DSI_DCS,
47 	INTEL_BACKLIGHT_PANEL_DRIVER_INTERFACE,
48 	INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE,
49 };
50 
51 struct edp_power_seq {
52 	u16 t1_t3;
53 	u16 t8;
54 	u16 t9;
55 	u16 t10;
56 	u16 t11_t12;
57 } __packed;
58 
59 /*
60  * MIPI Sequence Block definitions
61  *
62  * Note the VBT spec has AssertReset / DeassertReset swapped from their
63  * usual naming, we use the proper names here to avoid confusion when
64  * reading the code.
65  */
66 enum mipi_seq {
67 	MIPI_SEQ_END = 0,
68 	MIPI_SEQ_DEASSERT_RESET,	/* Spec says MipiAssertResetPin */
69 	MIPI_SEQ_INIT_OTP,
70 	MIPI_SEQ_DISPLAY_ON,
71 	MIPI_SEQ_DISPLAY_OFF,
72 	MIPI_SEQ_ASSERT_RESET,		/* Spec says MipiDeassertResetPin */
73 	MIPI_SEQ_BACKLIGHT_ON,		/* sequence block v2+ */
74 	MIPI_SEQ_BACKLIGHT_OFF,		/* sequence block v2+ */
75 	MIPI_SEQ_TEAR_ON,		/* sequence block v2+ */
76 	MIPI_SEQ_TEAR_OFF,		/* sequence block v3+ */
77 	MIPI_SEQ_POWER_ON,		/* sequence block v3+ */
78 	MIPI_SEQ_POWER_OFF,		/* sequence block v3+ */
79 	MIPI_SEQ_MAX
80 };
81 
82 enum mipi_seq_element {
83 	MIPI_SEQ_ELEM_END = 0,
84 	MIPI_SEQ_ELEM_SEND_PKT,
85 	MIPI_SEQ_ELEM_DELAY,
86 	MIPI_SEQ_ELEM_GPIO,
87 	MIPI_SEQ_ELEM_I2C,		/* sequence block v2+ */
88 	MIPI_SEQ_ELEM_SPI,		/* sequence block v3+ */
89 	MIPI_SEQ_ELEM_PMIC,		/* sequence block v3+ */
90 	MIPI_SEQ_ELEM_MAX
91 };
92 
93 #define MIPI_DSI_UNDEFINED_PANEL_ID	0
94 #define MIPI_DSI_GENERIC_PANEL_ID	1
95 
96 struct mipi_config {
97 	u16 panel_id;
98 
99 	/* General Params */
100 	u32 enable_dithering:1;
101 	u32 rsvd1:1;
102 	u32 is_bridge:1;
103 
104 	u32 panel_arch_type:2;
105 	u32 is_cmd_mode:1;
106 
107 #define NON_BURST_SYNC_PULSE	0x1
108 #define NON_BURST_SYNC_EVENTS	0x2
109 #define BURST_MODE		0x3
110 	u32 video_transfer_mode:2;
111 
112 	u32 cabc_supported:1;
113 #define PPS_BLC_PMIC   0
114 #define PPS_BLC_SOC    1
115 	u32 pwm_blc:1;
116 
117 	/* Bit 13:10 */
118 #define PIXEL_FORMAT_RGB565			0x1
119 #define PIXEL_FORMAT_RGB666			0x2
120 #define PIXEL_FORMAT_RGB666_LOOSELY_PACKED	0x3
121 #define PIXEL_FORMAT_RGB888			0x4
122 	u32 videomode_color_format:4;
123 
124 	/* Bit 15:14 */
125 #define ENABLE_ROTATION_0	0x0
126 #define ENABLE_ROTATION_90	0x1
127 #define ENABLE_ROTATION_180	0x2
128 #define ENABLE_ROTATION_270	0x3
129 	u32 rotation:2;
130 	u32 bta_enabled:1;
131 	u32 rsvd2:15;
132 
133 	/* 2 byte Port Description */
134 #define DUAL_LINK_NOT_SUPPORTED	0
135 #define DUAL_LINK_FRONT_BACK	1
136 #define DUAL_LINK_PIXEL_ALT	2
137 	u16 dual_link:2;
138 	u16 lane_cnt:2;
139 	u16 pixel_overlap:3;
140 	u16 rgb_flip:1;
141 #define DL_DCS_PORT_A			0x00
142 #define DL_DCS_PORT_C			0x01
143 #define DL_DCS_PORT_A_AND_C		0x02
144 	u16 dl_dcs_cabc_ports:2;
145 	u16 dl_dcs_backlight_ports:2;
146 	u16 rsvd3:4;
147 
148 	u16 rsvd4;
149 
150 	u8 rsvd5;
151 	u32 target_burst_mode_freq;
152 	u32 dsi_ddr_clk;
153 	u32 bridge_ref_clk;
154 
155 #define  BYTE_CLK_SEL_20MHZ		0
156 #define  BYTE_CLK_SEL_10MHZ		1
157 #define  BYTE_CLK_SEL_5MHZ		2
158 	u8 byte_clk_sel:2;
159 
160 	u8 rsvd6:6;
161 
162 	/* DPHY Flags */
163 	u16 dphy_param_valid:1;
164 	u16 eot_pkt_disabled:1;
165 	u16 enable_clk_stop:1;
166 	u16 rsvd7:13;
167 
168 	u32 hs_tx_timeout;
169 	u32 lp_rx_timeout;
170 	u32 turn_around_timeout;
171 	u32 device_reset_timer;
172 	u32 master_init_timer;
173 	u32 dbi_bw_timer;
174 	u32 lp_byte_clk_val;
175 
176 	/*  4 byte Dphy Params */
177 	u32 prepare_cnt:6;
178 	u32 rsvd8:2;
179 	u32 clk_zero_cnt:8;
180 	u32 trail_cnt:5;
181 	u32 rsvd9:3;
182 	u32 exit_zero_cnt:6;
183 	u32 rsvd10:2;
184 
185 	u32 clk_lane_switch_cnt;
186 	u32 hl_switch_cnt;
187 
188 	u32 rsvd11[6];
189 
190 	/* timings based on dphy spec */
191 	u8 tclk_miss;
192 	u8 tclk_post;
193 	u8 rsvd12;
194 	u8 tclk_pre;
195 	u8 tclk_prepare;
196 	u8 tclk_settle;
197 	u8 tclk_term_enable;
198 	u8 tclk_trail;
199 	u16 tclk_prepare_clkzero;
200 	u8 rsvd13;
201 	u8 td_term_enable;
202 	u8 teot;
203 	u8 ths_exit;
204 	u8 ths_prepare;
205 	u16 ths_prepare_hszero;
206 	u8 rsvd14;
207 	u8 ths_settle;
208 	u8 ths_skip;
209 	u8 ths_trail;
210 	u8 tinit;
211 	u8 tlpx;
212 	u8 rsvd15[3];
213 
214 	/* GPIOs */
215 	u8 panel_enable;
216 	u8 bl_enable;
217 	u8 pwm_enable;
218 	u8 reset_r_n;
219 	u8 pwr_down_r;
220 	u8 stdby_r_n;
221 
222 } __packed;
223 
224 /* all delays have a unit of 100us */
225 struct mipi_pps_data {
226 	u16 panel_on_delay;
227 	u16 bl_enable_delay;
228 	u16 bl_disable_delay;
229 	u16 panel_off_delay;
230 	u16 panel_power_cycle_delay;
231 } __packed;
232 
233 void intel_bios_init(struct drm_i915_private *dev_priv);
234 void intel_bios_driver_remove(struct drm_i915_private *dev_priv);
235 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
236 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
237 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
238 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
239 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
240 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
241 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
242 bool intel_bios_is_port_hpd_inverted(const struct drm_i915_private *i915,
243 				     enum port port);
244 bool intel_bios_is_lspcon_present(const struct drm_i915_private *i915,
245 				  enum port port);
246 enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, enum port port);
247 bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
248 			       struct intel_crtc_state *crtc_state,
249 			       int dsc_max_bpc);
250 
251 #endif /* _INTEL_BIOS_H_ */
252