1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2022 Intel Corporation
4  */
5 
6 #ifndef __INTEL_AUDIO_REGS_H__
7 #define __INTEL_AUDIO_REGS_H__
8 
9 #include "i915_reg_defs.h"
10 
11 #define G4X_AUD_VID_DID			_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)
12 #define   INTEL_AUDIO_DEVCL		0x808629FB
13 #define   INTEL_AUDIO_DEVBLC		0x80862801
14 #define   INTEL_AUDIO_DEVCTG		0x80862802
15 
16 #define G4X_AUD_CNTL_ST			_MMIO(0x620B4)
17 #define   G4X_ELDV_DEVCL_DEVBLC		(1 << 13)
18 #define   G4X_ELDV_DEVCTG		(1 << 14)
19 #define   G4X_ELD_ADDR_MASK		(0xf << 5)
20 #define   G4X_ELD_ACK			(1 << 4)
21 #define G4X_HDMIW_HDMIEDID		_MMIO(0x6210C)
22 
23 #define _IBX_HDMIW_HDMIEDID_A		0xE2050
24 #define _IBX_HDMIW_HDMIEDID_B		0xE2150
25 #define IBX_HDMIW_HDMIEDID(pipe)	_MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
26 						  _IBX_HDMIW_HDMIEDID_B)
27 #define _IBX_AUD_CNTL_ST_A		0xE20B4
28 #define _IBX_AUD_CNTL_ST_B		0xE21B4
29 #define IBX_AUD_CNTL_ST(pipe)		_MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
30 						  _IBX_AUD_CNTL_ST_B)
31 #define   IBX_ELD_BUFFER_SIZE_MASK	(0x1f << 10)
32 #define   IBX_ELD_ADDRESS_MASK		(0x1f << 5)
33 #define   IBX_ELD_ACK			(1 << 4)
34 #define IBX_AUD_CNTL_ST2		_MMIO(0xE20C0)
35 #define   IBX_CP_READY(port)		((1 << 1) << (((port) - 1) * 4))
36 #define   IBX_ELD_VALID(port)		((1 << 0) << (((port) - 1) * 4))
37 
38 #define _CPT_HDMIW_HDMIEDID_A		0xE5050
39 #define _CPT_HDMIW_HDMIEDID_B		0xE5150
40 #define CPT_HDMIW_HDMIEDID(pipe)	_MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
41 #define _CPT_AUD_CNTL_ST_A		0xE50B4
42 #define _CPT_AUD_CNTL_ST_B		0xE51B4
43 #define CPT_AUD_CNTL_ST(pipe)		_MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
44 #define CPT_AUD_CNTRL_ST2		_MMIO(0xE50C0)
45 
46 #define _VLV_HDMIW_HDMIEDID_A		(VLV_DISPLAY_BASE + 0x62050)
47 #define _VLV_HDMIW_HDMIEDID_B		(VLV_DISPLAY_BASE + 0x62150)
48 #define VLV_HDMIW_HDMIEDID(pipe)	_MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
49 #define _VLV_AUD_CNTL_ST_A		(VLV_DISPLAY_BASE + 0x620B4)
50 #define _VLV_AUD_CNTL_ST_B		(VLV_DISPLAY_BASE + 0x621B4)
51 #define VLV_AUD_CNTL_ST(pipe)		_MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
52 #define VLV_AUD_CNTL_ST2		_MMIO(VLV_DISPLAY_BASE + 0x620C0)
53 
54 #define _IBX_AUD_CONFIG_A		0xe2000
55 #define _IBX_AUD_CONFIG_B		0xe2100
56 #define IBX_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
57 #define _CPT_AUD_CONFIG_A		0xe5000
58 #define _CPT_AUD_CONFIG_B		0xe5100
59 #define CPT_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
60 #define _VLV_AUD_CONFIG_A		(VLV_DISPLAY_BASE + 0x62000)
61 #define _VLV_AUD_CONFIG_B		(VLV_DISPLAY_BASE + 0x62100)
62 #define VLV_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
63 
64 #define   AUD_CONFIG_N_VALUE_INDEX		(1 << 29)
65 #define   AUD_CONFIG_N_PROG_ENABLE		(1 << 28)
66 #define   AUD_CONFIG_UPPER_N_SHIFT		20
67 #define   AUD_CONFIG_UPPER_N_MASK		(0xff << 20)
68 #define   AUD_CONFIG_LOWER_N_SHIFT		4
69 #define   AUD_CONFIG_LOWER_N_MASK		(0xfff << 4)
70 #define   AUD_CONFIG_N_MASK			(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK)
71 #define   AUD_CONFIG_N(n) \
72 	(((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) |	\
73 	 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))
74 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT	16
75 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK	(0xf << 16)
76 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25175	(0 << 16)
77 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25200	(1 << 16)
78 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27000	(2 << 16)
79 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27027	(3 << 16)
80 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54000	(4 << 16)
81 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54054	(5 << 16)
82 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74176	(6 << 16)
83 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74250	(7 << 16)
84 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148352	(8 << 16)
85 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148500	(9 << 16)
86 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_296703	(10 << 16)
87 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_297000	(11 << 16)
88 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_593407	(12 << 16)
89 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_594000	(13 << 16)
90 #define   AUD_CONFIG_DISABLE_NCTS		(1 << 3)
91 
92 #define _HSW_AUD_CONFIG_A		0x65000
93 #define _HSW_AUD_CONFIG_B		0x65100
94 #define HSW_AUD_CFG(trans)		_MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
95 
96 #define _HSW_AUD_MISC_CTRL_A		0x65010
97 #define _HSW_AUD_MISC_CTRL_B		0x65110
98 #define HSW_AUD_MISC_CTRL(trans)	_MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
99 
100 #define _HSW_AUD_M_CTS_ENABLE_A		0x65028
101 #define _HSW_AUD_M_CTS_ENABLE_B		0x65128
102 #define HSW_AUD_M_CTS_ENABLE(trans)	_MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
103 #define   AUD_M_CTS_M_VALUE_INDEX	(1 << 21)
104 #define   AUD_M_CTS_M_PROG_ENABLE	(1 << 20)
105 #define   AUD_CONFIG_M_MASK		0xfffff
106 
107 #define _HSW_AUD_DIP_ELD_CTRL_ST_A	0x650b4
108 #define _HSW_AUD_DIP_ELD_CTRL_ST_B	0x651b4
109 #define HSW_AUD_DIP_ELD_CTRL(trans)	_MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
110 
111 /* Audio Digital Converter */
112 #define _HSW_AUD_DIG_CNVT_1		0x65080
113 #define _HSW_AUD_DIG_CNVT_2		0x65180
114 #define AUD_DIG_CNVT(trans)		_MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
115 #define DIP_PORT_SEL_MASK		0x3
116 
117 #define _HSW_AUD_EDID_DATA_A		0x65050
118 #define _HSW_AUD_EDID_DATA_B		0x65150
119 #define HSW_AUD_EDID_DATA(trans)	_MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
120 
121 #define HSW_AUD_PIPE_CONV_CFG		_MMIO(0x6507c)
122 #define HSW_AUD_PIN_ELD_CP_VLD		_MMIO(0x650c0)
123 #define   AUDIO_INACTIVE(trans)		((1 << 3) << ((trans) * 4))
124 #define   AUDIO_OUTPUT_ENABLE(trans)	((1 << 2) << ((trans) * 4))
125 #define   AUDIO_CP_READY(trans)		((1 << 1) << ((trans) * 4))
126 #define   AUDIO_ELD_VALID(trans)	((1 << 0) << ((trans) * 4))
127 
128 #define _AUD_TCA_DP_2DOT0_CTRL		0x650bc
129 #define _AUD_TCB_DP_2DOT0_CTRL		0x651bc
130 #define AUD_DP_2DOT0_CTRL(trans)	_MMIO_TRANS(trans, _AUD_TCA_DP_2DOT0_CTRL, _AUD_TCB_DP_2DOT0_CTRL)
131 #define  AUD_ENABLE_SDP_SPLIT		REG_BIT(31)
132 
133 #define HSW_AUD_CHICKENBIT			_MMIO(0x65f10)
134 #define   SKL_AUD_CODEC_WAKE_SIGNAL		(1 << 15)
135 
136 #define AUD_FREQ_CNTRL			_MMIO(0x65900)
137 #define AUD_PIN_BUF_CTL		_MMIO(0x48414)
138 #define   AUD_PIN_BUF_ENABLE		REG_BIT(31)
139 
140 #define AUD_TS_CDCLK_M			_MMIO(0x65ea0)
141 #define   AUD_TS_CDCLK_M_EN		REG_BIT(31)
142 #define AUD_TS_CDCLK_N			_MMIO(0x65ea4)
143 
144 /* Display Audio Config Reg */
145 #define AUD_CONFIG_BE			_MMIO(0x65ef0)
146 #define HBLANK_EARLY_ENABLE_ICL(pipe)		(0x1 << (20 - (pipe)))
147 #define HBLANK_EARLY_ENABLE_TGL(pipe)		(0x1 << (24 + (pipe)))
148 #define HBLANK_START_COUNT_MASK(pipe)		(0x7 << (3 + ((pipe) * 6)))
149 #define HBLANK_START_COUNT(pipe, val)		(((val) & 0x7) << (3 + ((pipe)) * 6))
150 #define NUMBER_SAMPLES_PER_LINE_MASK(pipe)	(0x3 << ((pipe) * 6))
151 #define NUMBER_SAMPLES_PER_LINE(pipe, val)	(((val) & 0x3) << ((pipe) * 6))
152 
153 #define HBLANK_START_COUNT_8	0
154 #define HBLANK_START_COUNT_16	1
155 #define HBLANK_START_COUNT_32	2
156 #define HBLANK_START_COUNT_64	3
157 #define HBLANK_START_COUNT_96	4
158 #define HBLANK_START_COUNT_128	5
159 
160 #endif /* __INTEL_AUDIO_REGS_H__ */
161