1*b43edc50SJani Nikula /* SPDX-License-Identifier: MIT */ 2*b43edc50SJani Nikula /* 3*b43edc50SJani Nikula * Copyright © 2022 Intel Corporation 4*b43edc50SJani Nikula */ 5*b43edc50SJani Nikula 6*b43edc50SJani Nikula #ifndef __INTEL_AUDIO_REGS_H__ 7*b43edc50SJani Nikula #define __INTEL_AUDIO_REGS_H__ 8*b43edc50SJani Nikula 9*b43edc50SJani Nikula #include "i915_reg_defs.h" 10*b43edc50SJani Nikula 11*b43edc50SJani Nikula #define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020) 12*b43edc50SJani Nikula #define INTEL_AUDIO_DEVCL 0x808629FB 13*b43edc50SJani Nikula #define INTEL_AUDIO_DEVBLC 0x80862801 14*b43edc50SJani Nikula #define INTEL_AUDIO_DEVCTG 0x80862802 15*b43edc50SJani Nikula 16*b43edc50SJani Nikula #define G4X_AUD_CNTL_ST _MMIO(0x620B4) 17*b43edc50SJani Nikula #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) 18*b43edc50SJani Nikula #define G4X_ELDV_DEVCTG (1 << 14) 19*b43edc50SJani Nikula #define G4X_ELD_ADDR_MASK (0xf << 5) 20*b43edc50SJani Nikula #define G4X_ELD_ACK (1 << 4) 21*b43edc50SJani Nikula #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C) 22*b43edc50SJani Nikula 23*b43edc50SJani Nikula #define _IBX_HDMIW_HDMIEDID_A 0xE2050 24*b43edc50SJani Nikula #define _IBX_HDMIW_HDMIEDID_B 0xE2150 25*b43edc50SJani Nikula #define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \ 26*b43edc50SJani Nikula _IBX_HDMIW_HDMIEDID_B) 27*b43edc50SJani Nikula #define _IBX_AUD_CNTL_ST_A 0xE20B4 28*b43edc50SJani Nikula #define _IBX_AUD_CNTL_ST_B 0xE21B4 29*b43edc50SJani Nikula #define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \ 30*b43edc50SJani Nikula _IBX_AUD_CNTL_ST_B) 31*b43edc50SJani Nikula #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10) 32*b43edc50SJani Nikula #define IBX_ELD_ADDRESS_MASK (0x1f << 5) 33*b43edc50SJani Nikula #define IBX_ELD_ACK (1 << 4) 34*b43edc50SJani Nikula #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0) 35*b43edc50SJani Nikula #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4)) 36*b43edc50SJani Nikula #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4)) 37*b43edc50SJani Nikula 38*b43edc50SJani Nikula #define _CPT_HDMIW_HDMIEDID_A 0xE5050 39*b43edc50SJani Nikula #define _CPT_HDMIW_HDMIEDID_B 0xE5150 40*b43edc50SJani Nikula #define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B) 41*b43edc50SJani Nikula #define _CPT_AUD_CNTL_ST_A 0xE50B4 42*b43edc50SJani Nikula #define _CPT_AUD_CNTL_ST_B 0xE51B4 43*b43edc50SJani Nikula #define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B) 44*b43edc50SJani Nikula #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0) 45*b43edc50SJani Nikula 46*b43edc50SJani Nikula #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) 47*b43edc50SJani Nikula #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) 48*b43edc50SJani Nikula #define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B) 49*b43edc50SJani Nikula #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) 50*b43edc50SJani Nikula #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) 51*b43edc50SJani Nikula #define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B) 52*b43edc50SJani Nikula #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0) 53*b43edc50SJani Nikula 54*b43edc50SJani Nikula #define _IBX_AUD_CONFIG_A 0xe2000 55*b43edc50SJani Nikula #define _IBX_AUD_CONFIG_B 0xe2100 56*b43edc50SJani Nikula #define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B) 57*b43edc50SJani Nikula #define _CPT_AUD_CONFIG_A 0xe5000 58*b43edc50SJani Nikula #define _CPT_AUD_CONFIG_B 0xe5100 59*b43edc50SJani Nikula #define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B) 60*b43edc50SJani Nikula #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) 61*b43edc50SJani Nikula #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) 62*b43edc50SJani Nikula #define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B) 63*b43edc50SJani Nikula 64*b43edc50SJani Nikula #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) 65*b43edc50SJani Nikula #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) 66*b43edc50SJani Nikula #define AUD_CONFIG_UPPER_N_SHIFT 20 67*b43edc50SJani Nikula #define AUD_CONFIG_UPPER_N_MASK (0xff << 20) 68*b43edc50SJani Nikula #define AUD_CONFIG_LOWER_N_SHIFT 4 69*b43edc50SJani Nikula #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4) 70*b43edc50SJani Nikula #define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK) 71*b43edc50SJani Nikula #define AUD_CONFIG_N(n) \ 72*b43edc50SJani Nikula (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \ 73*b43edc50SJani Nikula (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT)) 74*b43edc50SJani Nikula #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 75*b43edc50SJani Nikula #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) 76*b43edc50SJani Nikula #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) 77*b43edc50SJani Nikula #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) 78*b43edc50SJani Nikula #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) 79*b43edc50SJani Nikula #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) 80*b43edc50SJani Nikula #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) 81*b43edc50SJani Nikula #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) 82*b43edc50SJani Nikula #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) 83*b43edc50SJani Nikula #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) 84*b43edc50SJani Nikula #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) 85*b43edc50SJani Nikula #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) 86*b43edc50SJani Nikula #define AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 (10 << 16) 87*b43edc50SJani Nikula #define AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 (11 << 16) 88*b43edc50SJani Nikula #define AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 (12 << 16) 89*b43edc50SJani Nikula #define AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 (13 << 16) 90*b43edc50SJani Nikula #define AUD_CONFIG_DISABLE_NCTS (1 << 3) 91*b43edc50SJani Nikula 92*b43edc50SJani Nikula #define _HSW_AUD_CONFIG_A 0x65000 93*b43edc50SJani Nikula #define _HSW_AUD_CONFIG_B 0x65100 94*b43edc50SJani Nikula #define HSW_AUD_CFG(trans) _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B) 95*b43edc50SJani Nikula 96*b43edc50SJani Nikula #define _HSW_AUD_MISC_CTRL_A 0x65010 97*b43edc50SJani Nikula #define _HSW_AUD_MISC_CTRL_B 0x65110 98*b43edc50SJani Nikula #define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B) 99*b43edc50SJani Nikula 100*b43edc50SJani Nikula #define _HSW_AUD_M_CTS_ENABLE_A 0x65028 101*b43edc50SJani Nikula #define _HSW_AUD_M_CTS_ENABLE_B 0x65128 102*b43edc50SJani Nikula #define HSW_AUD_M_CTS_ENABLE(trans) _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B) 103*b43edc50SJani Nikula #define AUD_M_CTS_M_VALUE_INDEX (1 << 21) 104*b43edc50SJani Nikula #define AUD_M_CTS_M_PROG_ENABLE (1 << 20) 105*b43edc50SJani Nikula #define AUD_CONFIG_M_MASK 0xfffff 106*b43edc50SJani Nikula 107*b43edc50SJani Nikula #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 108*b43edc50SJani Nikula #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 109*b43edc50SJani Nikula #define HSW_AUD_DIP_ELD_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B) 110*b43edc50SJani Nikula 111*b43edc50SJani Nikula /* Audio Digital Converter */ 112*b43edc50SJani Nikula #define _HSW_AUD_DIG_CNVT_1 0x65080 113*b43edc50SJani Nikula #define _HSW_AUD_DIG_CNVT_2 0x65180 114*b43edc50SJani Nikula #define AUD_DIG_CNVT(trans) _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2) 115*b43edc50SJani Nikula #define DIP_PORT_SEL_MASK 0x3 116*b43edc50SJani Nikula 117*b43edc50SJani Nikula #define _HSW_AUD_EDID_DATA_A 0x65050 118*b43edc50SJani Nikula #define _HSW_AUD_EDID_DATA_B 0x65150 119*b43edc50SJani Nikula #define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B) 120*b43edc50SJani Nikula 121*b43edc50SJani Nikula #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c) 122*b43edc50SJani Nikula #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0) 123*b43edc50SJani Nikula #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) 124*b43edc50SJani Nikula #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) 125*b43edc50SJani Nikula #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) 126*b43edc50SJani Nikula #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) 127*b43edc50SJani Nikula 128*b43edc50SJani Nikula #define _AUD_TCA_DP_2DOT0_CTRL 0x650bc 129*b43edc50SJani Nikula #define _AUD_TCB_DP_2DOT0_CTRL 0x651bc 130*b43edc50SJani Nikula #define AUD_DP_2DOT0_CTRL(trans) _MMIO_TRANS(trans, _AUD_TCA_DP_2DOT0_CTRL, _AUD_TCB_DP_2DOT0_CTRL) 131*b43edc50SJani Nikula #define AUD_ENABLE_SDP_SPLIT REG_BIT(31) 132*b43edc50SJani Nikula 133*b43edc50SJani Nikula #define HSW_AUD_CHICKENBIT _MMIO(0x65f10) 134*b43edc50SJani Nikula #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15) 135*b43edc50SJani Nikula 136*b43edc50SJani Nikula #define AUD_FREQ_CNTRL _MMIO(0x65900) 137*b43edc50SJani Nikula #define AUD_PIN_BUF_CTL _MMIO(0x48414) 138*b43edc50SJani Nikula #define AUD_PIN_BUF_ENABLE REG_BIT(31) 139*b43edc50SJani Nikula 140*b43edc50SJani Nikula #define AUD_TS_CDCLK_M _MMIO(0x65ea0) 141*b43edc50SJani Nikula #define AUD_TS_CDCLK_M_EN REG_BIT(31) 142*b43edc50SJani Nikula #define AUD_TS_CDCLK_N _MMIO(0x65ea4) 143*b43edc50SJani Nikula 144*b43edc50SJani Nikula /* Display Audio Config Reg */ 145*b43edc50SJani Nikula #define AUD_CONFIG_BE _MMIO(0x65ef0) 146*b43edc50SJani Nikula #define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe))) 147*b43edc50SJani Nikula #define HBLANK_EARLY_ENABLE_TGL(pipe) (0x1 << (24 + (pipe))) 148*b43edc50SJani Nikula #define HBLANK_START_COUNT_MASK(pipe) (0x7 << (3 + ((pipe) * 6))) 149*b43edc50SJani Nikula #define HBLANK_START_COUNT(pipe, val) (((val) & 0x7) << (3 + ((pipe)) * 6)) 150*b43edc50SJani Nikula #define NUMBER_SAMPLES_PER_LINE_MASK(pipe) (0x3 << ((pipe) * 6)) 151*b43edc50SJani Nikula #define NUMBER_SAMPLES_PER_LINE(pipe, val) (((val) & 0x3) << ((pipe) * 6)) 152*b43edc50SJani Nikula 153*b43edc50SJani Nikula #define HBLANK_START_COUNT_8 0 154*b43edc50SJani Nikula #define HBLANK_START_COUNT_16 1 155*b43edc50SJani Nikula #define HBLANK_START_COUNT_32 2 156*b43edc50SJani Nikula #define HBLANK_START_COUNT_64 3 157*b43edc50SJani Nikula #define HBLANK_START_COUNT_96 4 158*b43edc50SJani Nikula #define HBLANK_START_COUNT_128 5 159*b43edc50SJani Nikula 160*b43edc50SJani Nikula #endif /* __INTEL_AUDIO_REGS_H__ */ 161