1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/component.h> 25 #include <linux/kernel.h> 26 27 #include <drm/drm_edid.h> 28 #include <drm/i915_component.h> 29 30 #include "i915_drv.h" 31 #include "intel_atomic.h" 32 #include "intel_audio.h" 33 #include "intel_audio_regs.h" 34 #include "intel_cdclk.h" 35 #include "intel_crtc.h" 36 #include "intel_de.h" 37 #include "intel_display_types.h" 38 #include "intel_lpe_audio.h" 39 40 /** 41 * DOC: High Definition Audio over HDMI and Display Port 42 * 43 * The graphics and audio drivers together support High Definition Audio over 44 * HDMI and Display Port. The audio programming sequences are divided into audio 45 * codec and controller enable and disable sequences. The graphics driver 46 * handles the audio codec sequences, while the audio driver handles the audio 47 * controller sequences. 48 * 49 * The disable sequences must be performed before disabling the transcoder or 50 * port. The enable sequences may only be performed after enabling the 51 * transcoder and port, and after completed link training. Therefore the audio 52 * enable/disable sequences are part of the modeset sequence. 53 * 54 * The codec and controller sequences could be done either parallel or serial, 55 * but generally the ELDV/PD change in the codec sequence indicates to the audio 56 * driver that the controller sequence should start. Indeed, most of the 57 * co-operation between the graphics and audio drivers is handled via audio 58 * related registers. (The notable exception is the power management, not 59 * covered here.) 60 * 61 * The struct &i915_audio_component is used to interact between the graphics 62 * and audio drivers. The struct &i915_audio_component_ops @ops in it is 63 * defined in graphics driver and called in audio driver. The 64 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver. 65 */ 66 67 struct intel_audio_funcs { 68 void (*audio_codec_enable)(struct intel_encoder *encoder, 69 const struct intel_crtc_state *crtc_state, 70 const struct drm_connector_state *conn_state); 71 void (*audio_codec_disable)(struct intel_encoder *encoder, 72 const struct intel_crtc_state *old_crtc_state, 73 const struct drm_connector_state *old_conn_state); 74 void (*audio_codec_get_config)(struct intel_encoder *encoder, 75 struct intel_crtc_state *crtc_state); 76 }; 77 78 struct hdmi_aud_ncts { 79 int sample_rate; 80 int clock; 81 int n; 82 int cts; 83 }; 84 85 static const struct { 86 int clock; 87 u32 config; 88 } hdmi_audio_clock[] = { 89 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, 90 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ 91 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, 92 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, 93 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, 94 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, 95 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, 96 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, 97 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, 98 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, 99 { 296703, AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 }, 100 { 297000, AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 }, 101 { 593407, AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 }, 102 { 594000, AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 }, 103 }; 104 105 /* HDMI N/CTS table */ 106 #define TMDS_297M 297000 107 #define TMDS_296M 296703 108 #define TMDS_594M 594000 109 #define TMDS_593M 593407 110 111 static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = { 112 { 32000, TMDS_296M, 5824, 421875 }, 113 { 32000, TMDS_297M, 3072, 222750 }, 114 { 32000, TMDS_593M, 5824, 843750 }, 115 { 32000, TMDS_594M, 3072, 445500 }, 116 { 44100, TMDS_296M, 4459, 234375 }, 117 { 44100, TMDS_297M, 4704, 247500 }, 118 { 44100, TMDS_593M, 8918, 937500 }, 119 { 44100, TMDS_594M, 9408, 990000 }, 120 { 88200, TMDS_296M, 8918, 234375 }, 121 { 88200, TMDS_297M, 9408, 247500 }, 122 { 88200, TMDS_593M, 17836, 937500 }, 123 { 88200, TMDS_594M, 18816, 990000 }, 124 { 176400, TMDS_296M, 17836, 234375 }, 125 { 176400, TMDS_297M, 18816, 247500 }, 126 { 176400, TMDS_593M, 35672, 937500 }, 127 { 176400, TMDS_594M, 37632, 990000 }, 128 { 48000, TMDS_296M, 5824, 281250 }, 129 { 48000, TMDS_297M, 5120, 247500 }, 130 { 48000, TMDS_593M, 5824, 562500 }, 131 { 48000, TMDS_594M, 6144, 594000 }, 132 { 96000, TMDS_296M, 11648, 281250 }, 133 { 96000, TMDS_297M, 10240, 247500 }, 134 { 96000, TMDS_593M, 11648, 562500 }, 135 { 96000, TMDS_594M, 12288, 594000 }, 136 { 192000, TMDS_296M, 23296, 281250 }, 137 { 192000, TMDS_297M, 20480, 247500 }, 138 { 192000, TMDS_593M, 23296, 562500 }, 139 { 192000, TMDS_594M, 24576, 594000 }, 140 }; 141 142 /* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/ 143 /* HDMI N/CTS table for 10 bit deep color(30 bpp)*/ 144 #define TMDS_371M 371250 145 #define TMDS_370M 370878 146 147 static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = { 148 { 32000, TMDS_370M, 5824, 527344 }, 149 { 32000, TMDS_371M, 6144, 556875 }, 150 { 44100, TMDS_370M, 8918, 585938 }, 151 { 44100, TMDS_371M, 4704, 309375 }, 152 { 88200, TMDS_370M, 17836, 585938 }, 153 { 88200, TMDS_371M, 9408, 309375 }, 154 { 176400, TMDS_370M, 35672, 585938 }, 155 { 176400, TMDS_371M, 18816, 309375 }, 156 { 48000, TMDS_370M, 11648, 703125 }, 157 { 48000, TMDS_371M, 5120, 309375 }, 158 { 96000, TMDS_370M, 23296, 703125 }, 159 { 96000, TMDS_371M, 10240, 309375 }, 160 { 192000, TMDS_370M, 46592, 703125 }, 161 { 192000, TMDS_371M, 20480, 309375 }, 162 }; 163 164 /* HDMI N/CTS table for 12 bit deep color(36 bpp)*/ 165 #define TMDS_445_5M 445500 166 #define TMDS_445M 445054 167 168 static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = { 169 { 32000, TMDS_445M, 5824, 632813 }, 170 { 32000, TMDS_445_5M, 4096, 445500 }, 171 { 44100, TMDS_445M, 8918, 703125 }, 172 { 44100, TMDS_445_5M, 4704, 371250 }, 173 { 88200, TMDS_445M, 17836, 703125 }, 174 { 88200, TMDS_445_5M, 9408, 371250 }, 175 { 176400, TMDS_445M, 35672, 703125 }, 176 { 176400, TMDS_445_5M, 18816, 371250 }, 177 { 48000, TMDS_445M, 5824, 421875 }, 178 { 48000, TMDS_445_5M, 5120, 371250 }, 179 { 96000, TMDS_445M, 11648, 421875 }, 180 { 96000, TMDS_445_5M, 10240, 371250 }, 181 { 192000, TMDS_445M, 23296, 421875 }, 182 { 192000, TMDS_445_5M, 20480, 371250 }, 183 }; 184 185 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ 186 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state) 187 { 188 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 189 const struct drm_display_mode *adjusted_mode = 190 &crtc_state->hw.adjusted_mode; 191 int i; 192 193 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { 194 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) 195 break; 196 } 197 198 if (DISPLAY_VER(i915) < 12 && adjusted_mode->crtc_clock > 148500) 199 i = ARRAY_SIZE(hdmi_audio_clock); 200 201 if (i == ARRAY_SIZE(hdmi_audio_clock)) { 202 drm_dbg_kms(&i915->drm, 203 "HDMI audio pixel clock setting for %d not found, falling back to defaults\n", 204 adjusted_mode->crtc_clock); 205 i = 1; 206 } 207 208 drm_dbg_kms(&i915->drm, 209 "Configuring HDMI audio for pixel clock %d (0x%08x)\n", 210 hdmi_audio_clock[i].clock, 211 hdmi_audio_clock[i].config); 212 213 return hdmi_audio_clock[i].config; 214 } 215 216 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state, 217 int rate) 218 { 219 const struct hdmi_aud_ncts *hdmi_ncts_table; 220 int i, size; 221 222 if (crtc_state->pipe_bpp == 36) { 223 hdmi_ncts_table = hdmi_aud_ncts_36bpp; 224 size = ARRAY_SIZE(hdmi_aud_ncts_36bpp); 225 } else if (crtc_state->pipe_bpp == 30) { 226 hdmi_ncts_table = hdmi_aud_ncts_30bpp; 227 size = ARRAY_SIZE(hdmi_aud_ncts_30bpp); 228 } else { 229 hdmi_ncts_table = hdmi_aud_ncts_24bpp; 230 size = ARRAY_SIZE(hdmi_aud_ncts_24bpp); 231 } 232 233 for (i = 0; i < size; i++) { 234 if (rate == hdmi_ncts_table[i].sample_rate && 235 crtc_state->port_clock == hdmi_ncts_table[i].clock) { 236 return hdmi_ncts_table[i].n; 237 } 238 } 239 return 0; 240 } 241 242 /* ELD buffer size in dwords */ 243 static int g4x_eld_buffer_size(struct drm_i915_private *i915) 244 { 245 u32 tmp; 246 247 tmp = intel_de_read(i915, G4X_AUD_CNTL_ST); 248 249 return REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp); 250 } 251 252 static void g4x_audio_codec_get_config(struct intel_encoder *encoder, 253 struct intel_crtc_state *crtc_state) 254 { 255 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 256 u32 *eld = (u32 *)crtc_state->eld; 257 int eld_buffer_size, len, i; 258 u32 tmp; 259 260 tmp = intel_de_read(i915, G4X_AUD_CNTL_ST); 261 if ((tmp & G4X_ELD_VALID) == 0) 262 return; 263 264 intel_de_rmw(i915, G4X_AUD_CNTL_ST, G4X_ELD_ADDRESS_MASK, 0); 265 266 eld_buffer_size = g4x_eld_buffer_size(i915); 267 len = min_t(int, sizeof(crtc_state->eld) / 4, eld_buffer_size); 268 269 for (i = 0; i < len; i++) 270 eld[i] = intel_de_read(i915, G4X_HDMIW_HDMIEDID); 271 } 272 273 static void g4x_audio_codec_disable(struct intel_encoder *encoder, 274 const struct intel_crtc_state *old_crtc_state, 275 const struct drm_connector_state *old_conn_state) 276 { 277 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 278 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 279 280 /* Invalidate ELD */ 281 intel_de_rmw(i915, G4X_AUD_CNTL_ST, 282 G4X_ELD_VALID, 0); 283 284 intel_crtc_wait_for_next_vblank(crtc); 285 intel_crtc_wait_for_next_vblank(crtc); 286 } 287 288 static void g4x_audio_codec_enable(struct intel_encoder *encoder, 289 const struct intel_crtc_state *crtc_state, 290 const struct drm_connector_state *conn_state) 291 { 292 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 293 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 294 const u32 *eld = (const u32 *)crtc_state->eld; 295 int eld_buffer_size, len, i; 296 297 intel_crtc_wait_for_next_vblank(crtc); 298 299 intel_de_rmw(i915, G4X_AUD_CNTL_ST, 300 G4X_ELD_VALID | G4X_ELD_ADDRESS_MASK, 0); 301 302 eld_buffer_size = g4x_eld_buffer_size(i915); 303 len = min(drm_eld_size(crtc_state->eld) / 4, eld_buffer_size); 304 305 for (i = 0; i < len; i++) 306 intel_de_write(i915, G4X_HDMIW_HDMIEDID, eld[i]); 307 for (; i < eld_buffer_size; i++) 308 intel_de_write(i915, G4X_HDMIW_HDMIEDID, 0); 309 310 drm_WARN_ON(&i915->drm, 311 (intel_de_read(i915, G4X_AUD_CNTL_ST) & G4X_ELD_ADDRESS_MASK) != 0); 312 313 intel_de_rmw(i915, G4X_AUD_CNTL_ST, 314 0, G4X_ELD_VALID); 315 } 316 317 static void 318 hsw_dp_audio_config_update(struct intel_encoder *encoder, 319 const struct intel_crtc_state *crtc_state) 320 { 321 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 322 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 323 324 /* Enable time stamps. Let HW calculate Maud/Naud values */ 325 intel_de_rmw(i915, HSW_AUD_CFG(cpu_transcoder), 326 AUD_CONFIG_N_VALUE_INDEX | 327 AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK | 328 AUD_CONFIG_UPPER_N_MASK | 329 AUD_CONFIG_LOWER_N_MASK | 330 AUD_CONFIG_N_PROG_ENABLE, 331 AUD_CONFIG_N_VALUE_INDEX); 332 333 } 334 335 static void 336 hsw_hdmi_audio_config_update(struct intel_encoder *encoder, 337 const struct intel_crtc_state *crtc_state) 338 { 339 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 340 struct i915_audio_component *acomp = i915->display.audio.component; 341 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 342 enum port port = encoder->port; 343 int n, rate; 344 u32 tmp; 345 346 rate = acomp ? acomp->aud_sample_rate[port] : 0; 347 348 tmp = intel_de_read(i915, HSW_AUD_CFG(cpu_transcoder)); 349 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 350 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 351 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 352 tmp |= audio_config_hdmi_pixel_clock(crtc_state); 353 354 n = audio_config_hdmi_get_n(crtc_state, rate); 355 if (n != 0) { 356 drm_dbg_kms(&i915->drm, "using N %d\n", n); 357 358 tmp &= ~AUD_CONFIG_N_MASK; 359 tmp |= AUD_CONFIG_N(n); 360 tmp |= AUD_CONFIG_N_PROG_ENABLE; 361 } else { 362 drm_dbg_kms(&i915->drm, "using automatic N\n"); 363 } 364 365 intel_de_write(i915, HSW_AUD_CFG(cpu_transcoder), tmp); 366 367 /* 368 * Let's disable "Enable CTS or M Prog bit" 369 * and let HW calculate the value 370 */ 371 tmp = intel_de_read(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); 372 tmp &= ~AUD_M_CTS_M_PROG_ENABLE; 373 tmp &= ~AUD_M_CTS_M_VALUE_INDEX; 374 intel_de_write(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 375 } 376 377 static void 378 hsw_audio_config_update(struct intel_encoder *encoder, 379 const struct intel_crtc_state *crtc_state) 380 { 381 if (intel_crtc_has_dp_encoder(crtc_state)) 382 hsw_dp_audio_config_update(encoder, crtc_state); 383 else 384 hsw_hdmi_audio_config_update(encoder, crtc_state); 385 } 386 387 static void hsw_audio_codec_disable(struct intel_encoder *encoder, 388 const struct intel_crtc_state *old_crtc_state, 389 const struct drm_connector_state *old_conn_state) 390 { 391 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 392 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 393 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 394 395 mutex_lock(&i915->display.audio.mutex); 396 397 /* Disable timestamps */ 398 intel_de_rmw(i915, HSW_AUD_CFG(cpu_transcoder), 399 AUD_CONFIG_N_VALUE_INDEX | 400 AUD_CONFIG_UPPER_N_MASK | 401 AUD_CONFIG_LOWER_N_MASK, 402 AUD_CONFIG_N_PROG_ENABLE | 403 (intel_crtc_has_dp_encoder(old_crtc_state) ? 404 AUD_CONFIG_N_VALUE_INDEX : 0)); 405 406 /* Invalidate ELD */ 407 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, 408 AUDIO_ELD_VALID(cpu_transcoder), 0); 409 410 intel_crtc_wait_for_next_vblank(crtc); 411 intel_crtc_wait_for_next_vblank(crtc); 412 413 /* Disable audio presence detect */ 414 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, 415 AUDIO_OUTPUT_ENABLE(cpu_transcoder), 0); 416 417 mutex_unlock(&i915->display.audio.mutex); 418 } 419 420 static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, 421 const struct intel_crtc_state *crtc_state) 422 { 423 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 424 unsigned int link_clks_available, link_clks_required; 425 unsigned int tu_data, tu_line, link_clks_active; 426 unsigned int h_active, h_total, hblank_delta, pixel_clk; 427 unsigned int fec_coeff, cdclk, vdsc_bpp; 428 unsigned int link_clk, lanes; 429 unsigned int hblank_rise; 430 431 h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay; 432 h_total = crtc_state->hw.adjusted_mode.crtc_htotal; 433 pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock; 434 vdsc_bpp = crtc_state->dsc.compressed_bpp; 435 cdclk = i915->display.cdclk.hw.cdclk; 436 /* fec= 0.972261, using rounding multiplier of 1000000 */ 437 fec_coeff = 972261; 438 link_clk = crtc_state->port_clock; 439 lanes = crtc_state->lane_count; 440 441 drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :" 442 "lanes = %u vdsc_bpp = %u cdclk = %u\n", 443 h_active, link_clk, lanes, vdsc_bpp, cdclk); 444 445 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk)) 446 return 0; 447 448 link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28; 449 link_clks_required = DIV_ROUND_UP(192000 * h_total, 1000 * pixel_clk) * (48 / lanes + 2); 450 451 if (link_clks_available > link_clks_required) 452 hblank_delta = 32; 453 else 454 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), 455 mul_u32_u32(link_clk, cdclk)); 456 457 tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bpp * 8, 1000000), 458 mul_u32_u32(link_clk * lanes, fec_coeff)); 459 tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff), 460 mul_u32_u32(64 * pixel_clk, 1000000)); 461 link_clks_active = (tu_line - 1) * 64 + tu_data; 462 463 hblank_rise = (link_clks_active + 6 * DIV_ROUND_UP(link_clks_active, 250) + 4) * pixel_clk / link_clk; 464 465 return h_active - hblank_rise + hblank_delta; 466 } 467 468 static unsigned int calc_samples_room(const struct intel_crtc_state *crtc_state) 469 { 470 unsigned int h_active, h_total, pixel_clk; 471 unsigned int link_clk, lanes; 472 473 h_active = crtc_state->hw.adjusted_mode.hdisplay; 474 h_total = crtc_state->hw.adjusted_mode.htotal; 475 pixel_clk = crtc_state->hw.adjusted_mode.clock; 476 link_clk = crtc_state->port_clock; 477 lanes = crtc_state->lane_count; 478 479 return ((h_total - h_active) * link_clk - 12 * pixel_clk) / 480 (pixel_clk * (48 / lanes + 2)); 481 } 482 483 static void enable_audio_dsc_wa(struct intel_encoder *encoder, 484 const struct intel_crtc_state *crtc_state) 485 { 486 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 487 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 488 unsigned int hblank_early_prog, samples_room; 489 unsigned int val; 490 491 if (DISPLAY_VER(i915) < 11) 492 return; 493 494 val = intel_de_read(i915, AUD_CONFIG_BE); 495 496 if (DISPLAY_VER(i915) == 11) 497 val |= HBLANK_EARLY_ENABLE_ICL(cpu_transcoder); 498 else if (DISPLAY_VER(i915) >= 12) 499 val |= HBLANK_EARLY_ENABLE_TGL(cpu_transcoder); 500 501 if (crtc_state->dsc.compression_enable && 502 crtc_state->hw.adjusted_mode.hdisplay >= 3840 && 503 crtc_state->hw.adjusted_mode.vdisplay >= 2160) { 504 /* Get hblank early enable value required */ 505 val &= ~HBLANK_START_COUNT_MASK(cpu_transcoder); 506 hblank_early_prog = calc_hblank_early_prog(encoder, crtc_state); 507 if (hblank_early_prog < 32) 508 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_32); 509 else if (hblank_early_prog < 64) 510 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_64); 511 else if (hblank_early_prog < 96) 512 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_96); 513 else 514 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_128); 515 516 /* Get samples room value required */ 517 val &= ~NUMBER_SAMPLES_PER_LINE_MASK(cpu_transcoder); 518 samples_room = calc_samples_room(crtc_state); 519 if (samples_room < 3) 520 val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, samples_room); 521 else /* Program 0 i.e "All Samples available in buffer" */ 522 val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, 0x0); 523 } 524 525 intel_de_write(i915, AUD_CONFIG_BE, val); 526 } 527 528 static void hsw_audio_codec_enable(struct intel_encoder *encoder, 529 const struct intel_crtc_state *crtc_state, 530 const struct drm_connector_state *conn_state) 531 { 532 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 533 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 534 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 535 536 mutex_lock(&i915->display.audio.mutex); 537 538 /* Enable Audio WA for 4k DSC usecases */ 539 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP)) 540 enable_audio_dsc_wa(encoder, crtc_state); 541 542 /* Enable audio presence detect */ 543 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, 544 0, AUDIO_OUTPUT_ENABLE(cpu_transcoder)); 545 546 intel_crtc_wait_for_next_vblank(crtc); 547 548 /* Invalidate ELD */ 549 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, 550 AUDIO_ELD_VALID(cpu_transcoder), 0); 551 552 /* 553 * The audio componenent is used to convey the ELD 554 * instead using of the hardware ELD buffer. 555 */ 556 557 /* Enable timestamps */ 558 hsw_audio_config_update(encoder, crtc_state); 559 560 mutex_unlock(&i915->display.audio.mutex); 561 } 562 563 struct ibx_audio_regs { 564 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; 565 }; 566 567 static void ibx_audio_regs_init(struct drm_i915_private *i915, 568 enum pipe pipe, 569 struct ibx_audio_regs *regs) 570 { 571 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 572 regs->hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); 573 regs->aud_config = VLV_AUD_CFG(pipe); 574 regs->aud_cntl_st = VLV_AUD_CNTL_ST(pipe); 575 regs->aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 576 } else if (HAS_PCH_CPT(i915)) { 577 regs->hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); 578 regs->aud_config = CPT_AUD_CFG(pipe); 579 regs->aud_cntl_st = CPT_AUD_CNTL_ST(pipe); 580 regs->aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 581 } else if (HAS_PCH_IBX(i915)) { 582 regs->hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); 583 regs->aud_config = IBX_AUD_CFG(pipe); 584 regs->aud_cntl_st = IBX_AUD_CNTL_ST(pipe); 585 regs->aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 586 } 587 } 588 589 static void ibx_audio_codec_disable(struct intel_encoder *encoder, 590 const struct intel_crtc_state *old_crtc_state, 591 const struct drm_connector_state *old_conn_state) 592 { 593 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 594 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 595 enum port port = encoder->port; 596 enum pipe pipe = crtc->pipe; 597 struct ibx_audio_regs regs; 598 599 if (drm_WARN_ON(&i915->drm, port == PORT_A)) 600 return; 601 602 ibx_audio_regs_init(i915, pipe, ®s); 603 604 mutex_lock(&i915->display.audio.mutex); 605 606 /* Disable timestamps */ 607 intel_de_rmw(i915, regs.aud_config, 608 AUD_CONFIG_N_VALUE_INDEX | 609 AUD_CONFIG_UPPER_N_MASK | 610 AUD_CONFIG_LOWER_N_MASK, 611 AUD_CONFIG_N_PROG_ENABLE | 612 (intel_crtc_has_dp_encoder(old_crtc_state) ? 613 AUD_CONFIG_N_VALUE_INDEX : 0)); 614 615 /* Invalidate ELD */ 616 intel_de_rmw(i915, regs.aud_cntrl_st2, 617 IBX_ELD_VALID(port), 0); 618 619 mutex_unlock(&i915->display.audio.mutex); 620 621 intel_crtc_wait_for_next_vblank(crtc); 622 intel_crtc_wait_for_next_vblank(crtc); 623 } 624 625 static void ibx_audio_codec_enable(struct intel_encoder *encoder, 626 const struct intel_crtc_state *crtc_state, 627 const struct drm_connector_state *conn_state) 628 { 629 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 630 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 631 enum port port = encoder->port; 632 enum pipe pipe = crtc->pipe; 633 struct ibx_audio_regs regs; 634 635 if (drm_WARN_ON(&i915->drm, port == PORT_A)) 636 return; 637 638 intel_crtc_wait_for_next_vblank(crtc); 639 640 ibx_audio_regs_init(i915, pipe, ®s); 641 642 mutex_lock(&i915->display.audio.mutex); 643 644 /* Invalidate ELD */ 645 intel_de_rmw(i915, regs.aud_cntrl_st2, 646 IBX_ELD_VALID(port), 0); 647 648 /* 649 * The audio componenent is used to convey the ELD 650 * instead using of the hardware ELD buffer. 651 */ 652 653 /* Enable timestamps */ 654 intel_de_rmw(i915, regs.aud_config, 655 AUD_CONFIG_N_VALUE_INDEX | 656 AUD_CONFIG_N_PROG_ENABLE | 657 AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 658 (intel_crtc_has_dp_encoder(crtc_state) ? 659 AUD_CONFIG_N_VALUE_INDEX : 660 audio_config_hdmi_pixel_clock(crtc_state))); 661 662 mutex_unlock(&i915->display.audio.mutex); 663 } 664 665 void intel_audio_sdp_split_update(struct intel_encoder *encoder, 666 const struct intel_crtc_state *crtc_state) 667 { 668 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 669 enum transcoder trans = crtc_state->cpu_transcoder; 670 671 if (HAS_DP20(i915)) 672 intel_de_rmw(i915, AUD_DP_2DOT0_CTRL(trans), AUD_ENABLE_SDP_SPLIT, 673 crtc_state->sdp_split_enable ? AUD_ENABLE_SDP_SPLIT : 0); 674 } 675 676 bool intel_audio_compute_config(struct intel_encoder *encoder, 677 struct intel_crtc_state *crtc_state, 678 struct drm_connector_state *conn_state) 679 { 680 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 681 struct drm_connector *connector = conn_state->connector; 682 const struct drm_display_mode *adjusted_mode = 683 &crtc_state->hw.adjusted_mode; 684 685 if (!connector->eld[0]) { 686 drm_dbg_kms(&i915->drm, 687 "Bogus ELD on [CONNECTOR:%d:%s]\n", 688 connector->base.id, connector->name); 689 return false; 690 } 691 692 BUILD_BUG_ON(sizeof(crtc_state->eld) != sizeof(connector->eld)); 693 memcpy(crtc_state->eld, connector->eld, sizeof(crtc_state->eld)); 694 695 crtc_state->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; 696 697 return true; 698 } 699 700 /** 701 * intel_audio_codec_enable - Enable the audio codec for HD audio 702 * @encoder: encoder on which to enable audio 703 * @crtc_state: pointer to the current crtc state. 704 * @conn_state: pointer to the current connector state. 705 * 706 * The enable sequences may only be performed after enabling the transcoder and 707 * port, and after completed link training. 708 */ 709 void intel_audio_codec_enable(struct intel_encoder *encoder, 710 const struct intel_crtc_state *crtc_state, 711 const struct drm_connector_state *conn_state) 712 { 713 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 714 struct i915_audio_component *acomp = i915->display.audio.component; 715 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 716 struct intel_connector *connector = to_intel_connector(conn_state->connector); 717 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 718 struct intel_audio_state *audio_state; 719 enum port port = encoder->port; 720 721 if (!crtc_state->has_audio) 722 return; 723 724 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Enable audio codec on [CRTC:%d:%s], %u bytes ELD\n", 725 connector->base.base.id, connector->base.name, 726 encoder->base.base.id, encoder->base.name, 727 crtc->base.base.id, crtc->base.name, 728 drm_eld_size(crtc_state->eld)); 729 730 if (i915->display.funcs.audio) 731 i915->display.funcs.audio->audio_codec_enable(encoder, 732 crtc_state, 733 conn_state); 734 735 mutex_lock(&i915->display.audio.mutex); 736 737 audio_state = &i915->display.audio.state[cpu_transcoder]; 738 739 audio_state->encoder = encoder; 740 BUILD_BUG_ON(sizeof(audio_state->eld) != sizeof(crtc_state->eld)); 741 memcpy(audio_state->eld, crtc_state->eld, sizeof(audio_state->eld)); 742 743 mutex_unlock(&i915->display.audio.mutex); 744 745 if (acomp && acomp->base.audio_ops && 746 acomp->base.audio_ops->pin_eld_notify) { 747 /* audio drivers expect cpu_transcoder = -1 to indicate Non-MST cases */ 748 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 749 cpu_transcoder = -1; 750 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 751 (int)port, (int)cpu_transcoder); 752 } 753 754 intel_lpe_audio_notify(i915, cpu_transcoder, port, crtc_state->eld, 755 crtc_state->port_clock, 756 intel_crtc_has_dp_encoder(crtc_state)); 757 } 758 759 /** 760 * intel_audio_codec_disable - Disable the audio codec for HD audio 761 * @encoder: encoder on which to disable audio 762 * @old_crtc_state: pointer to the old crtc state. 763 * @old_conn_state: pointer to the old connector state. 764 * 765 * The disable sequences must be performed before disabling the transcoder or 766 * port. 767 */ 768 void intel_audio_codec_disable(struct intel_encoder *encoder, 769 const struct intel_crtc_state *old_crtc_state, 770 const struct drm_connector_state *old_conn_state) 771 { 772 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 773 struct i915_audio_component *acomp = i915->display.audio.component; 774 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 775 struct intel_connector *connector = to_intel_connector(old_conn_state->connector); 776 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 777 struct intel_audio_state *audio_state; 778 enum port port = encoder->port; 779 780 if (!old_crtc_state->has_audio) 781 return; 782 783 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Disable audio codec on [CRTC:%d:%s]\n", 784 connector->base.base.id, connector->base.name, 785 encoder->base.base.id, encoder->base.name, 786 crtc->base.base.id, crtc->base.name); 787 788 if (i915->display.funcs.audio) 789 i915->display.funcs.audio->audio_codec_disable(encoder, 790 old_crtc_state, 791 old_conn_state); 792 793 mutex_lock(&i915->display.audio.mutex); 794 795 audio_state = &i915->display.audio.state[cpu_transcoder]; 796 797 audio_state->encoder = NULL; 798 memset(audio_state->eld, 0, sizeof(audio_state->eld)); 799 800 mutex_unlock(&i915->display.audio.mutex); 801 802 if (acomp && acomp->base.audio_ops && 803 acomp->base.audio_ops->pin_eld_notify) { 804 /* audio drivers expect cpu_transcoder = -1 to indicate Non-MST cases */ 805 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 806 cpu_transcoder = -1; 807 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 808 (int)port, (int)cpu_transcoder); 809 } 810 811 intel_lpe_audio_notify(i915, cpu_transcoder, port, NULL, 0, false); 812 } 813 814 static void intel_acomp_get_config(struct intel_encoder *encoder, 815 struct intel_crtc_state *crtc_state) 816 { 817 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 818 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 819 struct intel_audio_state *audio_state; 820 821 mutex_lock(&i915->display.audio.mutex); 822 823 audio_state = &i915->display.audio.state[cpu_transcoder]; 824 825 if (audio_state->encoder) 826 memcpy(crtc_state->eld, audio_state->eld, sizeof(audio_state->eld)); 827 828 mutex_unlock(&i915->display.audio.mutex); 829 } 830 831 void intel_audio_codec_get_config(struct intel_encoder *encoder, 832 struct intel_crtc_state *crtc_state) 833 { 834 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 835 836 if (!crtc_state->has_audio) 837 return; 838 839 if (i915->display.funcs.audio) 840 i915->display.funcs.audio->audio_codec_get_config(encoder, crtc_state); 841 } 842 843 static const struct intel_audio_funcs g4x_audio_funcs = { 844 .audio_codec_enable = g4x_audio_codec_enable, 845 .audio_codec_disable = g4x_audio_codec_disable, 846 .audio_codec_get_config = g4x_audio_codec_get_config, 847 }; 848 849 static const struct intel_audio_funcs ibx_audio_funcs = { 850 .audio_codec_enable = ibx_audio_codec_enable, 851 .audio_codec_disable = ibx_audio_codec_disable, 852 .audio_codec_get_config = intel_acomp_get_config, 853 }; 854 855 static const struct intel_audio_funcs hsw_audio_funcs = { 856 .audio_codec_enable = hsw_audio_codec_enable, 857 .audio_codec_disable = hsw_audio_codec_disable, 858 .audio_codec_get_config = intel_acomp_get_config, 859 }; 860 861 /** 862 * intel_audio_hooks_init - Set up chip specific audio hooks 863 * @i915: device private 864 */ 865 void intel_audio_hooks_init(struct drm_i915_private *i915) 866 { 867 if (IS_G4X(i915)) 868 i915->display.funcs.audio = &g4x_audio_funcs; 869 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915) || 870 HAS_PCH_CPT(i915) || HAS_PCH_IBX(i915)) 871 i915->display.funcs.audio = &ibx_audio_funcs; 872 else if (IS_HASWELL(i915) || DISPLAY_VER(i915) >= 8) 873 i915->display.funcs.audio = &hsw_audio_funcs; 874 } 875 876 struct aud_ts_cdclk_m_n { 877 u8 m; 878 u16 n; 879 }; 880 881 void intel_audio_cdclk_change_pre(struct drm_i915_private *i915) 882 { 883 if (DISPLAY_VER(i915) >= 13) 884 intel_de_rmw(i915, AUD_TS_CDCLK_M, AUD_TS_CDCLK_M_EN, 0); 885 } 886 887 static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts) 888 { 889 aud_ts->m = 60; 890 aud_ts->n = cdclk * aud_ts->m / 24000; 891 } 892 893 void intel_audio_cdclk_change_post(struct drm_i915_private *i915) 894 { 895 struct aud_ts_cdclk_m_n aud_ts; 896 897 if (DISPLAY_VER(i915) >= 13) { 898 get_aud_ts_cdclk_m_n(i915->display.cdclk.hw.ref, i915->display.cdclk.hw.cdclk, &aud_ts); 899 900 intel_de_write(i915, AUD_TS_CDCLK_N, aud_ts.n); 901 intel_de_write(i915, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN); 902 drm_dbg_kms(&i915->drm, "aud_ts_cdclk set to M=%u, N=%u\n", aud_ts.m, aud_ts.n); 903 } 904 } 905 906 static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state, 907 struct intel_crtc *crtc, 908 bool enable) 909 { 910 struct intel_cdclk_state *cdclk_state; 911 int ret; 912 913 /* need to hold at least one crtc lock for the global state */ 914 ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx); 915 if (ret) 916 return ret; 917 918 cdclk_state = intel_atomic_get_cdclk_state(state); 919 if (IS_ERR(cdclk_state)) 920 return PTR_ERR(cdclk_state); 921 922 cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0; 923 924 return drm_atomic_commit(&state->base); 925 } 926 927 static void glk_force_audio_cdclk(struct drm_i915_private *i915, 928 bool enable) 929 { 930 struct drm_modeset_acquire_ctx ctx; 931 struct drm_atomic_state *state; 932 struct intel_crtc *crtc; 933 int ret; 934 935 crtc = intel_first_crtc(i915); 936 if (!crtc) 937 return; 938 939 drm_modeset_acquire_init(&ctx, 0); 940 state = drm_atomic_state_alloc(&i915->drm); 941 if (drm_WARN_ON(&i915->drm, !state)) 942 return; 943 944 state->acquire_ctx = &ctx; 945 to_intel_atomic_state(state)->internal = true; 946 947 retry: 948 ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), crtc, 949 enable); 950 if (ret == -EDEADLK) { 951 drm_atomic_state_clear(state); 952 drm_modeset_backoff(&ctx); 953 goto retry; 954 } 955 956 drm_WARN_ON(&i915->drm, ret); 957 958 drm_atomic_state_put(state); 959 960 drm_modeset_drop_locks(&ctx); 961 drm_modeset_acquire_fini(&ctx); 962 } 963 964 static unsigned long i915_audio_component_get_power(struct device *kdev) 965 { 966 struct drm_i915_private *i915 = kdev_to_i915(kdev); 967 intel_wakeref_t ret; 968 969 /* Catch potential impedance mismatches before they occur! */ 970 BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long)); 971 972 ret = intel_display_power_get(i915, POWER_DOMAIN_AUDIO_PLAYBACK); 973 974 if (i915->display.audio.power_refcount++ == 0) { 975 if (DISPLAY_VER(i915) >= 9) { 976 intel_de_write(i915, AUD_FREQ_CNTRL, 977 i915->display.audio.freq_cntrl); 978 drm_dbg_kms(&i915->drm, 979 "restored AUD_FREQ_CNTRL to 0x%x\n", 980 i915->display.audio.freq_cntrl); 981 } 982 983 /* Force CDCLK to 2*BCLK as long as we need audio powered. */ 984 if (IS_GEMINILAKE(i915)) 985 glk_force_audio_cdclk(i915, true); 986 987 if (DISPLAY_VER(i915) >= 10) 988 intel_de_rmw(i915, AUD_PIN_BUF_CTL, 989 0, AUD_PIN_BUF_ENABLE); 990 } 991 992 return ret; 993 } 994 995 static void i915_audio_component_put_power(struct device *kdev, 996 unsigned long cookie) 997 { 998 struct drm_i915_private *i915 = kdev_to_i915(kdev); 999 1000 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */ 1001 if (--i915->display.audio.power_refcount == 0) 1002 if (IS_GEMINILAKE(i915)) 1003 glk_force_audio_cdclk(i915, false); 1004 1005 intel_display_power_put(i915, POWER_DOMAIN_AUDIO_PLAYBACK, cookie); 1006 } 1007 1008 static void i915_audio_component_codec_wake_override(struct device *kdev, 1009 bool enable) 1010 { 1011 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1012 unsigned long cookie; 1013 1014 if (DISPLAY_VER(i915) < 9) 1015 return; 1016 1017 cookie = i915_audio_component_get_power(kdev); 1018 1019 /* 1020 * Enable/disable generating the codec wake signal, overriding the 1021 * internal logic to generate the codec wake to controller. 1022 */ 1023 intel_de_rmw(i915, HSW_AUD_CHICKENBIT, 1024 SKL_AUD_CODEC_WAKE_SIGNAL, 0); 1025 usleep_range(1000, 1500); 1026 1027 if (enable) { 1028 intel_de_rmw(i915, HSW_AUD_CHICKENBIT, 1029 0, SKL_AUD_CODEC_WAKE_SIGNAL); 1030 usleep_range(1000, 1500); 1031 } 1032 1033 i915_audio_component_put_power(kdev, cookie); 1034 } 1035 1036 /* Get CDCLK in kHz */ 1037 static int i915_audio_component_get_cdclk_freq(struct device *kdev) 1038 { 1039 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1040 1041 if (drm_WARN_ON_ONCE(&i915->drm, !HAS_DDI(i915))) 1042 return -ENODEV; 1043 1044 return i915->display.cdclk.hw.cdclk; 1045 } 1046 1047 /* 1048 * get the intel audio state according to the parameter port and cpu_transcoder 1049 * MST & (cpu_transcoder >= 0): return the audio.state[cpu_transcoder].encoder], 1050 * when port is matched 1051 * MST & (cpu_transcoder < 0): this is invalid 1052 * Non-MST & (cpu_transcoder >= 0): only cpu_transcoder = 0 (the first device entry) 1053 * will get the right intel_encoder with port matched 1054 * Non-MST & (cpu_transcoder < 0): get the right intel_encoder with port matched 1055 */ 1056 static struct intel_audio_state *find_audio_state(struct drm_i915_private *i915, 1057 int port, int cpu_transcoder) 1058 { 1059 /* MST */ 1060 if (cpu_transcoder >= 0) { 1061 struct intel_audio_state *audio_state; 1062 struct intel_encoder *encoder; 1063 1064 if (drm_WARN_ON(&i915->drm, 1065 cpu_transcoder >= ARRAY_SIZE(i915->display.audio.state))) 1066 return NULL; 1067 1068 audio_state = &i915->display.audio.state[cpu_transcoder]; 1069 encoder = audio_state->encoder; 1070 1071 if (encoder && encoder->port == port && 1072 encoder->type == INTEL_OUTPUT_DP_MST) 1073 return audio_state; 1074 } 1075 1076 /* Non-MST */ 1077 if (cpu_transcoder > 0) 1078 return NULL; 1079 1080 for_each_cpu_transcoder(i915, cpu_transcoder) { 1081 struct intel_audio_state *audio_state; 1082 struct intel_encoder *encoder; 1083 1084 audio_state = &i915->display.audio.state[cpu_transcoder]; 1085 encoder = audio_state->encoder; 1086 1087 if (encoder && encoder->port == port && 1088 encoder->type != INTEL_OUTPUT_DP_MST) 1089 return audio_state; 1090 } 1091 1092 return NULL; 1093 } 1094 1095 static int i915_audio_component_sync_audio_rate(struct device *kdev, int port, 1096 int cpu_transcoder, int rate) 1097 { 1098 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1099 struct i915_audio_component *acomp = i915->display.audio.component; 1100 const struct intel_audio_state *audio_state; 1101 struct intel_encoder *encoder; 1102 struct intel_crtc *crtc; 1103 unsigned long cookie; 1104 int err = 0; 1105 1106 if (!HAS_DDI(i915)) 1107 return 0; 1108 1109 cookie = i915_audio_component_get_power(kdev); 1110 mutex_lock(&i915->display.audio.mutex); 1111 1112 audio_state = find_audio_state(i915, port, cpu_transcoder); 1113 if (!audio_state) { 1114 drm_dbg_kms(&i915->drm, "Not valid for port %c\n", port_name(port)); 1115 err = -ENODEV; 1116 goto unlock; 1117 } 1118 1119 encoder = audio_state->encoder; 1120 1121 /* FIXME stop using the legacy crtc pointer */ 1122 crtc = to_intel_crtc(encoder->base.crtc); 1123 1124 /* port must be valid now, otherwise the cpu_transcoder will be invalid */ 1125 acomp->aud_sample_rate[port] = rate; 1126 1127 /* FIXME get rid of the crtc->config stuff */ 1128 hsw_audio_config_update(encoder, crtc->config); 1129 1130 unlock: 1131 mutex_unlock(&i915->display.audio.mutex); 1132 i915_audio_component_put_power(kdev, cookie); 1133 return err; 1134 } 1135 1136 static int i915_audio_component_get_eld(struct device *kdev, int port, 1137 int cpu_transcoder, bool *enabled, 1138 unsigned char *buf, int max_bytes) 1139 { 1140 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1141 const struct intel_audio_state *audio_state; 1142 int ret = 0; 1143 1144 mutex_lock(&i915->display.audio.mutex); 1145 1146 audio_state = find_audio_state(i915, port, cpu_transcoder); 1147 if (!audio_state) { 1148 drm_dbg_kms(&i915->drm, "Not valid for port %c\n", port_name(port)); 1149 mutex_unlock(&i915->display.audio.mutex); 1150 return -EINVAL; 1151 } 1152 1153 *enabled = audio_state->encoder != NULL; 1154 if (*enabled) { 1155 const u8 *eld = audio_state->eld; 1156 1157 ret = drm_eld_size(eld); 1158 memcpy(buf, eld, min(max_bytes, ret)); 1159 } 1160 1161 mutex_unlock(&i915->display.audio.mutex); 1162 return ret; 1163 } 1164 1165 static const struct drm_audio_component_ops i915_audio_component_ops = { 1166 .owner = THIS_MODULE, 1167 .get_power = i915_audio_component_get_power, 1168 .put_power = i915_audio_component_put_power, 1169 .codec_wake_override = i915_audio_component_codec_wake_override, 1170 .get_cdclk_freq = i915_audio_component_get_cdclk_freq, 1171 .sync_audio_rate = i915_audio_component_sync_audio_rate, 1172 .get_eld = i915_audio_component_get_eld, 1173 }; 1174 1175 static int i915_audio_component_bind(struct device *i915_kdev, 1176 struct device *hda_kdev, void *data) 1177 { 1178 struct i915_audio_component *acomp = data; 1179 struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); 1180 int i; 1181 1182 if (drm_WARN_ON(&i915->drm, acomp->base.ops || acomp->base.dev)) 1183 return -EEXIST; 1184 1185 if (drm_WARN_ON(&i915->drm, 1186 !device_link_add(hda_kdev, i915_kdev, 1187 DL_FLAG_STATELESS))) 1188 return -ENOMEM; 1189 1190 drm_modeset_lock_all(&i915->drm); 1191 acomp->base.ops = &i915_audio_component_ops; 1192 acomp->base.dev = i915_kdev; 1193 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); 1194 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) 1195 acomp->aud_sample_rate[i] = 0; 1196 i915->display.audio.component = acomp; 1197 drm_modeset_unlock_all(&i915->drm); 1198 1199 return 0; 1200 } 1201 1202 static void i915_audio_component_unbind(struct device *i915_kdev, 1203 struct device *hda_kdev, void *data) 1204 { 1205 struct i915_audio_component *acomp = data; 1206 struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); 1207 1208 drm_modeset_lock_all(&i915->drm); 1209 acomp->base.ops = NULL; 1210 acomp->base.dev = NULL; 1211 i915->display.audio.component = NULL; 1212 drm_modeset_unlock_all(&i915->drm); 1213 1214 device_link_remove(hda_kdev, i915_kdev); 1215 1216 if (i915->display.audio.power_refcount) 1217 drm_err(&i915->drm, "audio power refcount %d after unbind\n", 1218 i915->display.audio.power_refcount); 1219 } 1220 1221 static const struct component_ops i915_audio_component_bind_ops = { 1222 .bind = i915_audio_component_bind, 1223 .unbind = i915_audio_component_unbind, 1224 }; 1225 1226 #define AUD_FREQ_TMODE_SHIFT 14 1227 #define AUD_FREQ_4T 0 1228 #define AUD_FREQ_8T (2 << AUD_FREQ_TMODE_SHIFT) 1229 #define AUD_FREQ_PULLCLKS(x) (((x) & 0x3) << 11) 1230 #define AUD_FREQ_BCLK_96M BIT(4) 1231 1232 #define AUD_FREQ_GEN12 (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(0) | AUD_FREQ_BCLK_96M) 1233 #define AUD_FREQ_TGL_BROKEN (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(2) | AUD_FREQ_BCLK_96M) 1234 1235 /** 1236 * i915_audio_component_init - initialize and register the audio component 1237 * @i915: i915 device instance 1238 * 1239 * This will register with the component framework a child component which 1240 * will bind dynamically to the snd_hda_intel driver's corresponding master 1241 * component when the latter is registered. During binding the child 1242 * initializes an instance of struct i915_audio_component which it receives 1243 * from the master. The master can then start to use the interface defined by 1244 * this struct. Each side can break the binding at any point by deregistering 1245 * its own component after which each side's component unbind callback is 1246 * called. 1247 * 1248 * We ignore any error during registration and continue with reduced 1249 * functionality (i.e. without HDMI audio). 1250 */ 1251 static void i915_audio_component_init(struct drm_i915_private *i915) 1252 { 1253 u32 aud_freq, aud_freq_init; 1254 int ret; 1255 1256 ret = component_add_typed(i915->drm.dev, 1257 &i915_audio_component_bind_ops, 1258 I915_COMPONENT_AUDIO); 1259 if (ret < 0) { 1260 drm_err(&i915->drm, 1261 "failed to add audio component (%d)\n", ret); 1262 /* continue with reduced functionality */ 1263 return; 1264 } 1265 1266 if (DISPLAY_VER(i915) >= 9) { 1267 aud_freq_init = intel_de_read(i915, AUD_FREQ_CNTRL); 1268 1269 if (DISPLAY_VER(i915) >= 12) 1270 aud_freq = AUD_FREQ_GEN12; 1271 else 1272 aud_freq = aud_freq_init; 1273 1274 /* use BIOS provided value for TGL and RKL unless it is a known bad value */ 1275 if ((IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915)) && 1276 aud_freq_init != AUD_FREQ_TGL_BROKEN) 1277 aud_freq = aud_freq_init; 1278 1279 drm_dbg_kms(&i915->drm, "use AUD_FREQ_CNTRL of 0x%x (init value 0x%x)\n", 1280 aud_freq, aud_freq_init); 1281 1282 i915->display.audio.freq_cntrl = aud_freq; 1283 } 1284 1285 /* init with current cdclk */ 1286 intel_audio_cdclk_change_post(i915); 1287 1288 i915->display.audio.component_registered = true; 1289 } 1290 1291 /** 1292 * i915_audio_component_cleanup - deregister the audio component 1293 * @i915: i915 device instance 1294 * 1295 * Deregisters the audio component, breaking any existing binding to the 1296 * corresponding snd_hda_intel driver's master component. 1297 */ 1298 static void i915_audio_component_cleanup(struct drm_i915_private *i915) 1299 { 1300 if (!i915->display.audio.component_registered) 1301 return; 1302 1303 component_del(i915->drm.dev, &i915_audio_component_bind_ops); 1304 i915->display.audio.component_registered = false; 1305 } 1306 1307 /** 1308 * intel_audio_init() - Initialize the audio driver either using 1309 * component framework or using lpe audio bridge 1310 * @i915: the i915 drm device private data 1311 * 1312 */ 1313 void intel_audio_init(struct drm_i915_private *i915) 1314 { 1315 if (intel_lpe_audio_init(i915) < 0) 1316 i915_audio_component_init(i915); 1317 } 1318 1319 /** 1320 * intel_audio_deinit() - deinitialize the audio driver 1321 * @i915: the i915 drm device private data 1322 * 1323 */ 1324 void intel_audio_deinit(struct drm_i915_private *i915) 1325 { 1326 if (i915->display.audio.lpe.platdev != NULL) 1327 intel_lpe_audio_teardown(i915); 1328 else 1329 i915_audio_component_cleanup(i915); 1330 } 1331