1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/component.h> 25 #include <linux/kernel.h> 26 27 #include <drm/drm_edid.h> 28 #include <drm/i915_component.h> 29 30 #include "i915_drv.h" 31 #include "intel_audio.h" 32 #include "intel_display_types.h" 33 #include "intel_lpe_audio.h" 34 35 /** 36 * DOC: High Definition Audio over HDMI and Display Port 37 * 38 * The graphics and audio drivers together support High Definition Audio over 39 * HDMI and Display Port. The audio programming sequences are divided into audio 40 * codec and controller enable and disable sequences. The graphics driver 41 * handles the audio codec sequences, while the audio driver handles the audio 42 * controller sequences. 43 * 44 * The disable sequences must be performed before disabling the transcoder or 45 * port. The enable sequences may only be performed after enabling the 46 * transcoder and port, and after completed link training. Therefore the audio 47 * enable/disable sequences are part of the modeset sequence. 48 * 49 * The codec and controller sequences could be done either parallel or serial, 50 * but generally the ELDV/PD change in the codec sequence indicates to the audio 51 * driver that the controller sequence should start. Indeed, most of the 52 * co-operation between the graphics and audio drivers is handled via audio 53 * related registers. (The notable exception is the power management, not 54 * covered here.) 55 * 56 * The struct &i915_audio_component is used to interact between the graphics 57 * and audio drivers. The struct &i915_audio_component_ops @ops in it is 58 * defined in graphics driver and called in audio driver. The 59 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver. 60 */ 61 62 /* DP N/M table */ 63 #define LC_810M 810000 64 #define LC_540M 540000 65 #define LC_270M 270000 66 #define LC_162M 162000 67 68 struct dp_aud_n_m { 69 int sample_rate; 70 int clock; 71 u16 m; 72 u16 n; 73 }; 74 75 struct hdmi_aud_ncts { 76 int sample_rate; 77 int clock; 78 int n; 79 int cts; 80 }; 81 82 /* Values according to DP 1.4 Table 2-104 */ 83 static const struct dp_aud_n_m dp_aud_n_m[] = { 84 { 32000, LC_162M, 1024, 10125 }, 85 { 44100, LC_162M, 784, 5625 }, 86 { 48000, LC_162M, 512, 3375 }, 87 { 64000, LC_162M, 2048, 10125 }, 88 { 88200, LC_162M, 1568, 5625 }, 89 { 96000, LC_162M, 1024, 3375 }, 90 { 128000, LC_162M, 4096, 10125 }, 91 { 176400, LC_162M, 3136, 5625 }, 92 { 192000, LC_162M, 2048, 3375 }, 93 { 32000, LC_270M, 1024, 16875 }, 94 { 44100, LC_270M, 784, 9375 }, 95 { 48000, LC_270M, 512, 5625 }, 96 { 64000, LC_270M, 2048, 16875 }, 97 { 88200, LC_270M, 1568, 9375 }, 98 { 96000, LC_270M, 1024, 5625 }, 99 { 128000, LC_270M, 4096, 16875 }, 100 { 176400, LC_270M, 3136, 9375 }, 101 { 192000, LC_270M, 2048, 5625 }, 102 { 32000, LC_540M, 1024, 33750 }, 103 { 44100, LC_540M, 784, 18750 }, 104 { 48000, LC_540M, 512, 11250 }, 105 { 64000, LC_540M, 2048, 33750 }, 106 { 88200, LC_540M, 1568, 18750 }, 107 { 96000, LC_540M, 1024, 11250 }, 108 { 128000, LC_540M, 4096, 33750 }, 109 { 176400, LC_540M, 3136, 18750 }, 110 { 192000, LC_540M, 2048, 11250 }, 111 { 32000, LC_810M, 1024, 50625 }, 112 { 44100, LC_810M, 784, 28125 }, 113 { 48000, LC_810M, 512, 16875 }, 114 { 64000, LC_810M, 2048, 50625 }, 115 { 88200, LC_810M, 1568, 28125 }, 116 { 96000, LC_810M, 1024, 16875 }, 117 { 128000, LC_810M, 4096, 50625 }, 118 { 176400, LC_810M, 3136, 28125 }, 119 { 192000, LC_810M, 2048, 16875 }, 120 }; 121 122 static const struct dp_aud_n_m * 123 audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate) 124 { 125 int i; 126 127 for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) { 128 if (rate == dp_aud_n_m[i].sample_rate && 129 crtc_state->port_clock == dp_aud_n_m[i].clock) 130 return &dp_aud_n_m[i]; 131 } 132 133 return NULL; 134 } 135 136 static const struct { 137 int clock; 138 u32 config; 139 } hdmi_audio_clock[] = { 140 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, 141 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ 142 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, 143 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, 144 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, 145 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, 146 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, 147 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, 148 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, 149 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, 150 }; 151 152 /* HDMI N/CTS table */ 153 #define TMDS_297M 297000 154 #define TMDS_296M 296703 155 #define TMDS_594M 594000 156 #define TMDS_593M 593407 157 158 static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = { 159 { 32000, TMDS_296M, 5824, 421875 }, 160 { 32000, TMDS_297M, 3072, 222750 }, 161 { 32000, TMDS_593M, 5824, 843750 }, 162 { 32000, TMDS_594M, 3072, 445500 }, 163 { 44100, TMDS_296M, 4459, 234375 }, 164 { 44100, TMDS_297M, 4704, 247500 }, 165 { 44100, TMDS_593M, 8918, 937500 }, 166 { 44100, TMDS_594M, 9408, 990000 }, 167 { 88200, TMDS_296M, 8918, 234375 }, 168 { 88200, TMDS_297M, 9408, 247500 }, 169 { 88200, TMDS_593M, 17836, 937500 }, 170 { 88200, TMDS_594M, 18816, 990000 }, 171 { 176400, TMDS_296M, 17836, 234375 }, 172 { 176400, TMDS_297M, 18816, 247500 }, 173 { 176400, TMDS_593M, 35672, 937500 }, 174 { 176400, TMDS_594M, 37632, 990000 }, 175 { 48000, TMDS_296M, 5824, 281250 }, 176 { 48000, TMDS_297M, 5120, 247500 }, 177 { 48000, TMDS_593M, 5824, 562500 }, 178 { 48000, TMDS_594M, 6144, 594000 }, 179 { 96000, TMDS_296M, 11648, 281250 }, 180 { 96000, TMDS_297M, 10240, 247500 }, 181 { 96000, TMDS_593M, 11648, 562500 }, 182 { 96000, TMDS_594M, 12288, 594000 }, 183 { 192000, TMDS_296M, 23296, 281250 }, 184 { 192000, TMDS_297M, 20480, 247500 }, 185 { 192000, TMDS_593M, 23296, 562500 }, 186 { 192000, TMDS_594M, 24576, 594000 }, 187 }; 188 189 /* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/ 190 /* HDMI N/CTS table for 10 bit deep color(30 bpp)*/ 191 #define TMDS_371M 371250 192 #define TMDS_370M 370878 193 194 static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = { 195 { 32000, TMDS_370M, 5824, 527344 }, 196 { 32000, TMDS_371M, 6144, 556875 }, 197 { 44100, TMDS_370M, 8918, 585938 }, 198 { 44100, TMDS_371M, 4704, 309375 }, 199 { 88200, TMDS_370M, 17836, 585938 }, 200 { 88200, TMDS_371M, 9408, 309375 }, 201 { 176400, TMDS_370M, 35672, 585938 }, 202 { 176400, TMDS_371M, 18816, 309375 }, 203 { 48000, TMDS_370M, 11648, 703125 }, 204 { 48000, TMDS_371M, 5120, 309375 }, 205 { 96000, TMDS_370M, 23296, 703125 }, 206 { 96000, TMDS_371M, 10240, 309375 }, 207 { 192000, TMDS_370M, 46592, 703125 }, 208 { 192000, TMDS_371M, 20480, 309375 }, 209 }; 210 211 /* HDMI N/CTS table for 12 bit deep color(36 bpp)*/ 212 #define TMDS_445_5M 445500 213 #define TMDS_445M 445054 214 215 static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = { 216 { 32000, TMDS_445M, 5824, 632813 }, 217 { 32000, TMDS_445_5M, 4096, 445500 }, 218 { 44100, TMDS_445M, 8918, 703125 }, 219 { 44100, TMDS_445_5M, 4704, 371250 }, 220 { 88200, TMDS_445M, 17836, 703125 }, 221 { 88200, TMDS_445_5M, 9408, 371250 }, 222 { 176400, TMDS_445M, 35672, 703125 }, 223 { 176400, TMDS_445_5M, 18816, 371250 }, 224 { 48000, TMDS_445M, 5824, 421875 }, 225 { 48000, TMDS_445_5M, 5120, 371250 }, 226 { 96000, TMDS_445M, 11648, 421875 }, 227 { 96000, TMDS_445_5M, 10240, 371250 }, 228 { 192000, TMDS_445M, 23296, 421875 }, 229 { 192000, TMDS_445_5M, 20480, 371250 }, 230 }; 231 232 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ 233 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state) 234 { 235 const struct drm_display_mode *adjusted_mode = 236 &crtc_state->base.adjusted_mode; 237 int i; 238 239 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { 240 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) 241 break; 242 } 243 244 if (i == ARRAY_SIZE(hdmi_audio_clock)) { 245 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", 246 adjusted_mode->crtc_clock); 247 i = 1; 248 } 249 250 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", 251 hdmi_audio_clock[i].clock, 252 hdmi_audio_clock[i].config); 253 254 return hdmi_audio_clock[i].config; 255 } 256 257 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state, 258 int rate) 259 { 260 const struct hdmi_aud_ncts *hdmi_ncts_table; 261 int i, size; 262 263 if (crtc_state->pipe_bpp == 36) { 264 hdmi_ncts_table = hdmi_aud_ncts_36bpp; 265 size = ARRAY_SIZE(hdmi_aud_ncts_36bpp); 266 } else if (crtc_state->pipe_bpp == 30) { 267 hdmi_ncts_table = hdmi_aud_ncts_30bpp; 268 size = ARRAY_SIZE(hdmi_aud_ncts_30bpp); 269 } else { 270 hdmi_ncts_table = hdmi_aud_ncts_24bpp; 271 size = ARRAY_SIZE(hdmi_aud_ncts_24bpp); 272 } 273 274 for (i = 0; i < size; i++) { 275 if (rate == hdmi_ncts_table[i].sample_rate && 276 crtc_state->port_clock == hdmi_ncts_table[i].clock) { 277 return hdmi_ncts_table[i].n; 278 } 279 } 280 return 0; 281 } 282 283 static bool intel_eld_uptodate(struct drm_connector *connector, 284 i915_reg_t reg_eldv, u32 bits_eldv, 285 i915_reg_t reg_elda, u32 bits_elda, 286 i915_reg_t reg_edid) 287 { 288 struct drm_i915_private *dev_priv = to_i915(connector->dev); 289 const u8 *eld = connector->eld; 290 u32 tmp; 291 int i; 292 293 tmp = I915_READ(reg_eldv); 294 tmp &= bits_eldv; 295 296 if (!tmp) 297 return false; 298 299 tmp = I915_READ(reg_elda); 300 tmp &= ~bits_elda; 301 I915_WRITE(reg_elda, tmp); 302 303 for (i = 0; i < drm_eld_size(eld) / 4; i++) 304 if (I915_READ(reg_edid) != *((const u32 *)eld + i)) 305 return false; 306 307 return true; 308 } 309 310 static void g4x_audio_codec_disable(struct intel_encoder *encoder, 311 const struct intel_crtc_state *old_crtc_state, 312 const struct drm_connector_state *old_conn_state) 313 { 314 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 315 u32 eldv, tmp; 316 317 DRM_DEBUG_KMS("Disable audio codec\n"); 318 319 tmp = I915_READ(G4X_AUD_VID_DID); 320 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) 321 eldv = G4X_ELDV_DEVCL_DEVBLC; 322 else 323 eldv = G4X_ELDV_DEVCTG; 324 325 /* Invalidate ELD */ 326 tmp = I915_READ(G4X_AUD_CNTL_ST); 327 tmp &= ~eldv; 328 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 329 } 330 331 static void g4x_audio_codec_enable(struct intel_encoder *encoder, 332 const struct intel_crtc_state *crtc_state, 333 const struct drm_connector_state *conn_state) 334 { 335 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 336 struct drm_connector *connector = conn_state->connector; 337 const u8 *eld = connector->eld; 338 u32 eldv; 339 u32 tmp; 340 int len, i; 341 342 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", drm_eld_size(eld)); 343 344 tmp = I915_READ(G4X_AUD_VID_DID); 345 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) 346 eldv = G4X_ELDV_DEVCL_DEVBLC; 347 else 348 eldv = G4X_ELDV_DEVCTG; 349 350 if (intel_eld_uptodate(connector, 351 G4X_AUD_CNTL_ST, eldv, 352 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK, 353 G4X_HDMIW_HDMIEDID)) 354 return; 355 356 tmp = I915_READ(G4X_AUD_CNTL_ST); 357 tmp &= ~(eldv | G4X_ELD_ADDR_MASK); 358 len = (tmp >> 9) & 0x1f; /* ELD buffer size */ 359 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 360 361 len = min(drm_eld_size(eld) / 4, len); 362 DRM_DEBUG_DRIVER("ELD size %d\n", len); 363 for (i = 0; i < len; i++) 364 I915_WRITE(G4X_HDMIW_HDMIEDID, *((const u32 *)eld + i)); 365 366 tmp = I915_READ(G4X_AUD_CNTL_ST); 367 tmp |= eldv; 368 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 369 } 370 371 static void 372 hsw_dp_audio_config_update(struct intel_encoder *encoder, 373 const struct intel_crtc_state *crtc_state) 374 { 375 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 376 struct i915_audio_component *acomp = dev_priv->audio_component; 377 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 378 enum port port = encoder->port; 379 const struct dp_aud_n_m *nm; 380 int rate; 381 u32 tmp; 382 383 rate = acomp ? acomp->aud_sample_rate[port] : 0; 384 nm = audio_config_dp_get_n_m(crtc_state, rate); 385 if (nm) 386 DRM_DEBUG_KMS("using Maud %u, Naud %u\n", nm->m, nm->n); 387 else 388 DRM_DEBUG_KMS("using automatic Maud, Naud\n"); 389 390 tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder)); 391 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 392 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 393 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 394 tmp |= AUD_CONFIG_N_VALUE_INDEX; 395 396 if (nm) { 397 tmp &= ~AUD_CONFIG_N_MASK; 398 tmp |= AUD_CONFIG_N(nm->n); 399 tmp |= AUD_CONFIG_N_PROG_ENABLE; 400 } 401 402 I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp); 403 404 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); 405 tmp &= ~AUD_CONFIG_M_MASK; 406 tmp &= ~AUD_M_CTS_M_VALUE_INDEX; 407 tmp &= ~AUD_M_CTS_M_PROG_ENABLE; 408 409 if (nm) { 410 tmp |= nm->m; 411 tmp |= AUD_M_CTS_M_VALUE_INDEX; 412 tmp |= AUD_M_CTS_M_PROG_ENABLE; 413 } 414 415 I915_WRITE(HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 416 } 417 418 static void 419 hsw_hdmi_audio_config_update(struct intel_encoder *encoder, 420 const struct intel_crtc_state *crtc_state) 421 { 422 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 423 struct i915_audio_component *acomp = dev_priv->audio_component; 424 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 425 enum port port = encoder->port; 426 int n, rate; 427 u32 tmp; 428 429 rate = acomp ? acomp->aud_sample_rate[port] : 0; 430 431 tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder)); 432 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 433 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 434 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 435 tmp |= audio_config_hdmi_pixel_clock(crtc_state); 436 437 n = audio_config_hdmi_get_n(crtc_state, rate); 438 if (n != 0) { 439 DRM_DEBUG_KMS("using N %d\n", n); 440 441 tmp &= ~AUD_CONFIG_N_MASK; 442 tmp |= AUD_CONFIG_N(n); 443 tmp |= AUD_CONFIG_N_PROG_ENABLE; 444 } else { 445 DRM_DEBUG_KMS("using automatic N\n"); 446 } 447 448 I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp); 449 450 /* 451 * Let's disable "Enable CTS or M Prog bit" 452 * and let HW calculate the value 453 */ 454 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); 455 tmp &= ~AUD_M_CTS_M_PROG_ENABLE; 456 tmp &= ~AUD_M_CTS_M_VALUE_INDEX; 457 I915_WRITE(HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 458 } 459 460 static void 461 hsw_audio_config_update(struct intel_encoder *encoder, 462 const struct intel_crtc_state *crtc_state) 463 { 464 if (intel_crtc_has_dp_encoder(crtc_state)) 465 hsw_dp_audio_config_update(encoder, crtc_state); 466 else 467 hsw_hdmi_audio_config_update(encoder, crtc_state); 468 } 469 470 static void hsw_audio_codec_disable(struct intel_encoder *encoder, 471 const struct intel_crtc_state *old_crtc_state, 472 const struct drm_connector_state *old_conn_state) 473 { 474 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 475 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 476 u32 tmp; 477 478 DRM_DEBUG_KMS("Disable audio codec on transcoder %s\n", 479 transcoder_name(cpu_transcoder)); 480 481 mutex_lock(&dev_priv->av_mutex); 482 483 /* Disable timestamps */ 484 tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder)); 485 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 486 tmp |= AUD_CONFIG_N_PROG_ENABLE; 487 tmp &= ~AUD_CONFIG_UPPER_N_MASK; 488 tmp &= ~AUD_CONFIG_LOWER_N_MASK; 489 if (intel_crtc_has_dp_encoder(old_crtc_state)) 490 tmp |= AUD_CONFIG_N_VALUE_INDEX; 491 I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp); 492 493 /* Invalidate ELD */ 494 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 495 tmp &= ~AUDIO_ELD_VALID(cpu_transcoder); 496 tmp &= ~AUDIO_OUTPUT_ENABLE(cpu_transcoder); 497 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 498 499 mutex_unlock(&dev_priv->av_mutex); 500 } 501 502 static void hsw_audio_codec_enable(struct intel_encoder *encoder, 503 const struct intel_crtc_state *crtc_state, 504 const struct drm_connector_state *conn_state) 505 { 506 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 507 struct drm_connector *connector = conn_state->connector; 508 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 509 const u8 *eld = connector->eld; 510 u32 tmp; 511 int len, i; 512 513 DRM_DEBUG_KMS("Enable audio codec on transcoder %s, %u bytes ELD\n", 514 transcoder_name(cpu_transcoder), drm_eld_size(eld)); 515 516 mutex_lock(&dev_priv->av_mutex); 517 518 /* Enable audio presence detect, invalidate ELD */ 519 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 520 tmp |= AUDIO_OUTPUT_ENABLE(cpu_transcoder); 521 tmp &= ~AUDIO_ELD_VALID(cpu_transcoder); 522 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 523 524 /* 525 * FIXME: We're supposed to wait for vblank here, but we have vblanks 526 * disabled during the mode set. The proper fix would be to push the 527 * rest of the setup into a vblank work item, queued here, but the 528 * infrastructure is not there yet. 529 */ 530 531 /* Reset ELD write address */ 532 tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(cpu_transcoder)); 533 tmp &= ~IBX_ELD_ADDRESS_MASK; 534 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(cpu_transcoder), tmp); 535 536 /* Up to 84 bytes of hw ELD buffer */ 537 len = min(drm_eld_size(eld), 84); 538 for (i = 0; i < len / 4; i++) 539 I915_WRITE(HSW_AUD_EDID_DATA(cpu_transcoder), *((const u32 *)eld + i)); 540 541 /* ELD valid */ 542 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 543 tmp |= AUDIO_ELD_VALID(cpu_transcoder); 544 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 545 546 /* Enable timestamps */ 547 hsw_audio_config_update(encoder, crtc_state); 548 549 mutex_unlock(&dev_priv->av_mutex); 550 } 551 552 static void ilk_audio_codec_disable(struct intel_encoder *encoder, 553 const struct intel_crtc_state *old_crtc_state, 554 const struct drm_connector_state *old_conn_state) 555 { 556 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 557 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); 558 enum pipe pipe = crtc->pipe; 559 enum port port = encoder->port; 560 u32 tmp, eldv; 561 i915_reg_t aud_config, aud_cntrl_st2; 562 563 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n", 564 port_name(port), pipe_name(pipe)); 565 566 if (WARN_ON(port == PORT_A)) 567 return; 568 569 if (HAS_PCH_IBX(dev_priv)) { 570 aud_config = IBX_AUD_CFG(pipe); 571 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 572 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 573 aud_config = VLV_AUD_CFG(pipe); 574 aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 575 } else { 576 aud_config = CPT_AUD_CFG(pipe); 577 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 578 } 579 580 /* Disable timestamps */ 581 tmp = I915_READ(aud_config); 582 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 583 tmp |= AUD_CONFIG_N_PROG_ENABLE; 584 tmp &= ~AUD_CONFIG_UPPER_N_MASK; 585 tmp &= ~AUD_CONFIG_LOWER_N_MASK; 586 if (intel_crtc_has_dp_encoder(old_crtc_state)) 587 tmp |= AUD_CONFIG_N_VALUE_INDEX; 588 I915_WRITE(aud_config, tmp); 589 590 eldv = IBX_ELD_VALID(port); 591 592 /* Invalidate ELD */ 593 tmp = I915_READ(aud_cntrl_st2); 594 tmp &= ~eldv; 595 I915_WRITE(aud_cntrl_st2, tmp); 596 } 597 598 static void ilk_audio_codec_enable(struct intel_encoder *encoder, 599 const struct intel_crtc_state *crtc_state, 600 const struct drm_connector_state *conn_state) 601 { 602 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 603 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 604 struct drm_connector *connector = conn_state->connector; 605 enum pipe pipe = crtc->pipe; 606 enum port port = encoder->port; 607 const u8 *eld = connector->eld; 608 u32 tmp, eldv; 609 int len, i; 610 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; 611 612 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n", 613 port_name(port), pipe_name(pipe), drm_eld_size(eld)); 614 615 if (WARN_ON(port == PORT_A)) 616 return; 617 618 /* 619 * FIXME: We're supposed to wait for vblank here, but we have vblanks 620 * disabled during the mode set. The proper fix would be to push the 621 * rest of the setup into a vblank work item, queued here, but the 622 * infrastructure is not there yet. 623 */ 624 625 if (HAS_PCH_IBX(dev_priv)) { 626 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); 627 aud_config = IBX_AUD_CFG(pipe); 628 aud_cntl_st = IBX_AUD_CNTL_ST(pipe); 629 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 630 } else if (IS_VALLEYVIEW(dev_priv) || 631 IS_CHERRYVIEW(dev_priv)) { 632 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); 633 aud_config = VLV_AUD_CFG(pipe); 634 aud_cntl_st = VLV_AUD_CNTL_ST(pipe); 635 aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 636 } else { 637 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); 638 aud_config = CPT_AUD_CFG(pipe); 639 aud_cntl_st = CPT_AUD_CNTL_ST(pipe); 640 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 641 } 642 643 eldv = IBX_ELD_VALID(port); 644 645 /* Invalidate ELD */ 646 tmp = I915_READ(aud_cntrl_st2); 647 tmp &= ~eldv; 648 I915_WRITE(aud_cntrl_st2, tmp); 649 650 /* Reset ELD write address */ 651 tmp = I915_READ(aud_cntl_st); 652 tmp &= ~IBX_ELD_ADDRESS_MASK; 653 I915_WRITE(aud_cntl_st, tmp); 654 655 /* Up to 84 bytes of hw ELD buffer */ 656 len = min(drm_eld_size(eld), 84); 657 for (i = 0; i < len / 4; i++) 658 I915_WRITE(hdmiw_hdmiedid, *((const u32 *)eld + i)); 659 660 /* ELD valid */ 661 tmp = I915_READ(aud_cntrl_st2); 662 tmp |= eldv; 663 I915_WRITE(aud_cntrl_st2, tmp); 664 665 /* Enable timestamps */ 666 tmp = I915_READ(aud_config); 667 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 668 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 669 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 670 if (intel_crtc_has_dp_encoder(crtc_state)) 671 tmp |= AUD_CONFIG_N_VALUE_INDEX; 672 else 673 tmp |= audio_config_hdmi_pixel_clock(crtc_state); 674 I915_WRITE(aud_config, tmp); 675 } 676 677 /** 678 * intel_audio_codec_enable - Enable the audio codec for HD audio 679 * @encoder: encoder on which to enable audio 680 * @crtc_state: pointer to the current crtc state. 681 * @conn_state: pointer to the current connector state. 682 * 683 * The enable sequences may only be performed after enabling the transcoder and 684 * port, and after completed link training. 685 */ 686 void intel_audio_codec_enable(struct intel_encoder *encoder, 687 const struct intel_crtc_state *crtc_state, 688 const struct drm_connector_state *conn_state) 689 { 690 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 691 struct i915_audio_component *acomp = dev_priv->audio_component; 692 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 693 struct drm_connector *connector = conn_state->connector; 694 const struct drm_display_mode *adjusted_mode = 695 &crtc_state->base.adjusted_mode; 696 enum port port = encoder->port; 697 enum pipe pipe = crtc->pipe; 698 699 /* FIXME precompute the ELD in .compute_config() */ 700 if (!connector->eld[0]) 701 DRM_DEBUG_KMS("Bogus ELD on [CONNECTOR:%d:%s]\n", 702 connector->base.id, connector->name); 703 704 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 705 connector->base.id, 706 connector->name, 707 connector->encoder->base.id, 708 connector->encoder->name); 709 710 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; 711 712 if (dev_priv->display.audio_codec_enable) 713 dev_priv->display.audio_codec_enable(encoder, 714 crtc_state, 715 conn_state); 716 717 mutex_lock(&dev_priv->av_mutex); 718 encoder->audio_connector = connector; 719 720 /* referred in audio callbacks */ 721 dev_priv->av_enc_map[pipe] = encoder; 722 mutex_unlock(&dev_priv->av_mutex); 723 724 if (acomp && acomp->base.audio_ops && 725 acomp->base.audio_ops->pin_eld_notify) { 726 /* audio drivers expect pipe = -1 to indicate Non-MST cases */ 727 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 728 pipe = -1; 729 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 730 (int) port, (int) pipe); 731 } 732 733 intel_lpe_audio_notify(dev_priv, pipe, port, connector->eld, 734 crtc_state->port_clock, 735 intel_crtc_has_dp_encoder(crtc_state)); 736 } 737 738 /** 739 * intel_audio_codec_disable - Disable the audio codec for HD audio 740 * @encoder: encoder on which to disable audio 741 * @old_crtc_state: pointer to the old crtc state. 742 * @old_conn_state: pointer to the old connector state. 743 * 744 * The disable sequences must be performed before disabling the transcoder or 745 * port. 746 */ 747 void intel_audio_codec_disable(struct intel_encoder *encoder, 748 const struct intel_crtc_state *old_crtc_state, 749 const struct drm_connector_state *old_conn_state) 750 { 751 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 752 struct i915_audio_component *acomp = dev_priv->audio_component; 753 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); 754 enum port port = encoder->port; 755 enum pipe pipe = crtc->pipe; 756 757 if (dev_priv->display.audio_codec_disable) 758 dev_priv->display.audio_codec_disable(encoder, 759 old_crtc_state, 760 old_conn_state); 761 762 mutex_lock(&dev_priv->av_mutex); 763 encoder->audio_connector = NULL; 764 dev_priv->av_enc_map[pipe] = NULL; 765 mutex_unlock(&dev_priv->av_mutex); 766 767 if (acomp && acomp->base.audio_ops && 768 acomp->base.audio_ops->pin_eld_notify) { 769 /* audio drivers expect pipe = -1 to indicate Non-MST cases */ 770 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 771 pipe = -1; 772 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 773 (int) port, (int) pipe); 774 } 775 776 intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false); 777 } 778 779 /** 780 * intel_init_audio_hooks - Set up chip specific audio hooks 781 * @dev_priv: device private 782 */ 783 void intel_init_audio_hooks(struct drm_i915_private *dev_priv) 784 { 785 if (IS_G4X(dev_priv)) { 786 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable; 787 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable; 788 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 789 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; 790 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; 791 } else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) { 792 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable; 793 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable; 794 } else if (HAS_PCH_SPLIT(dev_priv)) { 795 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; 796 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; 797 } 798 } 799 800 static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv, 801 bool enable) 802 { 803 struct drm_modeset_acquire_ctx ctx; 804 struct drm_atomic_state *state; 805 int ret; 806 807 drm_modeset_acquire_init(&ctx, 0); 808 state = drm_atomic_state_alloc(&dev_priv->drm); 809 if (WARN_ON(!state)) 810 return; 811 812 state->acquire_ctx = &ctx; 813 814 retry: 815 to_intel_atomic_state(state)->cdclk.force_min_cdclk_changed = true; 816 to_intel_atomic_state(state)->cdclk.force_min_cdclk = 817 enable ? 2 * 96000 : 0; 818 819 /* 820 * Protects dev_priv->cdclk.force_min_cdclk 821 * Need to lock this here in case we have no active pipes 822 * and thus wouldn't lock it during the commit otherwise. 823 */ 824 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 825 &ctx); 826 if (!ret) 827 ret = drm_atomic_commit(state); 828 829 if (ret == -EDEADLK) { 830 drm_atomic_state_clear(state); 831 drm_modeset_backoff(&ctx); 832 goto retry; 833 } 834 835 WARN_ON(ret); 836 837 drm_atomic_state_put(state); 838 839 drm_modeset_drop_locks(&ctx); 840 drm_modeset_acquire_fini(&ctx); 841 } 842 843 static unsigned long i915_audio_component_get_power(struct device *kdev) 844 { 845 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 846 intel_wakeref_t ret; 847 848 /* Catch potential impedance mismatches before they occur! */ 849 BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long)); 850 851 ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); 852 853 /* Force CDCLK to 2*BCLK as long as we need audio to be powered. */ 854 if (dev_priv->audio_power_refcount++ == 0) 855 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) 856 glk_force_audio_cdclk(dev_priv, true); 857 858 return ret; 859 } 860 861 static void i915_audio_component_put_power(struct device *kdev, 862 unsigned long cookie) 863 { 864 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 865 866 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */ 867 if (--dev_priv->audio_power_refcount == 0) 868 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) 869 glk_force_audio_cdclk(dev_priv, false); 870 871 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie); 872 } 873 874 static void i915_audio_component_codec_wake_override(struct device *kdev, 875 bool enable) 876 { 877 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 878 unsigned long cookie; 879 u32 tmp; 880 881 if (!IS_GEN(dev_priv, 9)) 882 return; 883 884 cookie = i915_audio_component_get_power(kdev); 885 886 /* 887 * Enable/disable generating the codec wake signal, overriding the 888 * internal logic to generate the codec wake to controller. 889 */ 890 tmp = I915_READ(HSW_AUD_CHICKENBIT); 891 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL; 892 I915_WRITE(HSW_AUD_CHICKENBIT, tmp); 893 usleep_range(1000, 1500); 894 895 if (enable) { 896 tmp = I915_READ(HSW_AUD_CHICKENBIT); 897 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL; 898 I915_WRITE(HSW_AUD_CHICKENBIT, tmp); 899 usleep_range(1000, 1500); 900 } 901 902 i915_audio_component_put_power(kdev, cookie); 903 } 904 905 /* Get CDCLK in kHz */ 906 static int i915_audio_component_get_cdclk_freq(struct device *kdev) 907 { 908 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 909 910 if (WARN_ON_ONCE(!HAS_DDI(dev_priv))) 911 return -ENODEV; 912 913 return dev_priv->cdclk.hw.cdclk; 914 } 915 916 /* 917 * get the intel_encoder according to the parameter port and pipe 918 * intel_encoder is saved by the index of pipe 919 * MST & (pipe >= 0): return the av_enc_map[pipe], 920 * when port is matched 921 * MST & (pipe < 0): this is invalid 922 * Non-MST & (pipe >= 0): only pipe = 0 (the first device entry) 923 * will get the right intel_encoder with port matched 924 * Non-MST & (pipe < 0): get the right intel_encoder with port matched 925 */ 926 static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv, 927 int port, int pipe) 928 { 929 struct intel_encoder *encoder; 930 931 /* MST */ 932 if (pipe >= 0) { 933 if (WARN_ON(pipe >= ARRAY_SIZE(dev_priv->av_enc_map))) 934 return NULL; 935 936 encoder = dev_priv->av_enc_map[pipe]; 937 /* 938 * when bootup, audio driver may not know it is 939 * MST or not. So it will poll all the port & pipe 940 * combinations 941 */ 942 if (encoder != NULL && encoder->port == port && 943 encoder->type == INTEL_OUTPUT_DP_MST) 944 return encoder; 945 } 946 947 /* Non-MST */ 948 if (pipe > 0) 949 return NULL; 950 951 for_each_pipe(dev_priv, pipe) { 952 encoder = dev_priv->av_enc_map[pipe]; 953 if (encoder == NULL) 954 continue; 955 956 if (encoder->type == INTEL_OUTPUT_DP_MST) 957 continue; 958 959 if (port == encoder->port) 960 return encoder; 961 } 962 963 return NULL; 964 } 965 966 static int i915_audio_component_sync_audio_rate(struct device *kdev, int port, 967 int pipe, int rate) 968 { 969 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 970 struct i915_audio_component *acomp = dev_priv->audio_component; 971 struct intel_encoder *encoder; 972 struct intel_crtc *crtc; 973 unsigned long cookie; 974 int err = 0; 975 976 if (!HAS_DDI(dev_priv)) 977 return 0; 978 979 cookie = i915_audio_component_get_power(kdev); 980 mutex_lock(&dev_priv->av_mutex); 981 982 /* 1. get the pipe */ 983 encoder = get_saved_enc(dev_priv, port, pipe); 984 if (!encoder || !encoder->base.crtc) { 985 DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port)); 986 err = -ENODEV; 987 goto unlock; 988 } 989 990 crtc = to_intel_crtc(encoder->base.crtc); 991 992 /* port must be valid now, otherwise the pipe will be invalid */ 993 acomp->aud_sample_rate[port] = rate; 994 995 hsw_audio_config_update(encoder, crtc->config); 996 997 unlock: 998 mutex_unlock(&dev_priv->av_mutex); 999 i915_audio_component_put_power(kdev, cookie); 1000 return err; 1001 } 1002 1003 static int i915_audio_component_get_eld(struct device *kdev, int port, 1004 int pipe, bool *enabled, 1005 unsigned char *buf, int max_bytes) 1006 { 1007 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1008 struct intel_encoder *intel_encoder; 1009 const u8 *eld; 1010 int ret = -EINVAL; 1011 1012 mutex_lock(&dev_priv->av_mutex); 1013 1014 intel_encoder = get_saved_enc(dev_priv, port, pipe); 1015 if (!intel_encoder) { 1016 DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port)); 1017 mutex_unlock(&dev_priv->av_mutex); 1018 return ret; 1019 } 1020 1021 ret = 0; 1022 *enabled = intel_encoder->audio_connector != NULL; 1023 if (*enabled) { 1024 eld = intel_encoder->audio_connector->eld; 1025 ret = drm_eld_size(eld); 1026 memcpy(buf, eld, min(max_bytes, ret)); 1027 } 1028 1029 mutex_unlock(&dev_priv->av_mutex); 1030 return ret; 1031 } 1032 1033 static const struct drm_audio_component_ops i915_audio_component_ops = { 1034 .owner = THIS_MODULE, 1035 .get_power = i915_audio_component_get_power, 1036 .put_power = i915_audio_component_put_power, 1037 .codec_wake_override = i915_audio_component_codec_wake_override, 1038 .get_cdclk_freq = i915_audio_component_get_cdclk_freq, 1039 .sync_audio_rate = i915_audio_component_sync_audio_rate, 1040 .get_eld = i915_audio_component_get_eld, 1041 }; 1042 1043 static int i915_audio_component_bind(struct device *i915_kdev, 1044 struct device *hda_kdev, void *data) 1045 { 1046 struct i915_audio_component *acomp = data; 1047 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); 1048 int i; 1049 1050 if (WARN_ON(acomp->base.ops || acomp->base.dev)) 1051 return -EEXIST; 1052 1053 if (WARN_ON(!device_link_add(hda_kdev, i915_kdev, DL_FLAG_STATELESS))) 1054 return -ENOMEM; 1055 1056 drm_modeset_lock_all(&dev_priv->drm); 1057 acomp->base.ops = &i915_audio_component_ops; 1058 acomp->base.dev = i915_kdev; 1059 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); 1060 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) 1061 acomp->aud_sample_rate[i] = 0; 1062 dev_priv->audio_component = acomp; 1063 drm_modeset_unlock_all(&dev_priv->drm); 1064 1065 return 0; 1066 } 1067 1068 static void i915_audio_component_unbind(struct device *i915_kdev, 1069 struct device *hda_kdev, void *data) 1070 { 1071 struct i915_audio_component *acomp = data; 1072 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); 1073 1074 drm_modeset_lock_all(&dev_priv->drm); 1075 acomp->base.ops = NULL; 1076 acomp->base.dev = NULL; 1077 dev_priv->audio_component = NULL; 1078 drm_modeset_unlock_all(&dev_priv->drm); 1079 1080 device_link_remove(hda_kdev, i915_kdev); 1081 } 1082 1083 static const struct component_ops i915_audio_component_bind_ops = { 1084 .bind = i915_audio_component_bind, 1085 .unbind = i915_audio_component_unbind, 1086 }; 1087 1088 /** 1089 * i915_audio_component_init - initialize and register the audio component 1090 * @dev_priv: i915 device instance 1091 * 1092 * This will register with the component framework a child component which 1093 * will bind dynamically to the snd_hda_intel driver's corresponding master 1094 * component when the latter is registered. During binding the child 1095 * initializes an instance of struct i915_audio_component which it receives 1096 * from the master. The master can then start to use the interface defined by 1097 * this struct. Each side can break the binding at any point by deregistering 1098 * its own component after which each side's component unbind callback is 1099 * called. 1100 * 1101 * We ignore any error during registration and continue with reduced 1102 * functionality (i.e. without HDMI audio). 1103 */ 1104 static void i915_audio_component_init(struct drm_i915_private *dev_priv) 1105 { 1106 int ret; 1107 1108 ret = component_add_typed(dev_priv->drm.dev, 1109 &i915_audio_component_bind_ops, 1110 I915_COMPONENT_AUDIO); 1111 if (ret < 0) { 1112 DRM_ERROR("failed to add audio component (%d)\n", ret); 1113 /* continue with reduced functionality */ 1114 return; 1115 } 1116 1117 dev_priv->audio_component_registered = true; 1118 } 1119 1120 /** 1121 * i915_audio_component_cleanup - deregister the audio component 1122 * @dev_priv: i915 device instance 1123 * 1124 * Deregisters the audio component, breaking any existing binding to the 1125 * corresponding snd_hda_intel driver's master component. 1126 */ 1127 static void i915_audio_component_cleanup(struct drm_i915_private *dev_priv) 1128 { 1129 if (!dev_priv->audio_component_registered) 1130 return; 1131 1132 component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops); 1133 dev_priv->audio_component_registered = false; 1134 } 1135 1136 /** 1137 * intel_audio_init() - Initialize the audio driver either using 1138 * component framework or using lpe audio bridge 1139 * @dev_priv: the i915 drm device private data 1140 * 1141 */ 1142 void intel_audio_init(struct drm_i915_private *dev_priv) 1143 { 1144 if (intel_lpe_audio_init(dev_priv) < 0) 1145 i915_audio_component_init(dev_priv); 1146 } 1147 1148 /** 1149 * intel_audio_deinit() - deinitialize the audio driver 1150 * @dev_priv: the i915 drm device private data 1151 * 1152 */ 1153 void intel_audio_deinit(struct drm_i915_private *dev_priv) 1154 { 1155 if ((dev_priv)->lpe_audio.platdev != NULL) 1156 intel_lpe_audio_teardown(dev_priv); 1157 else 1158 i915_audio_component_cleanup(dev_priv); 1159 } 1160