1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/component.h> 25 #include <linux/kernel.h> 26 27 #include <drm/drm_edid.h> 28 #include <drm/i915_component.h> 29 30 #include "i915_drv.h" 31 #include "intel_audio.h" 32 #include "intel_drv.h" 33 #include "intel_lpe_audio.h" 34 35 /** 36 * DOC: High Definition Audio over HDMI and Display Port 37 * 38 * The graphics and audio drivers together support High Definition Audio over 39 * HDMI and Display Port. The audio programming sequences are divided into audio 40 * codec and controller enable and disable sequences. The graphics driver 41 * handles the audio codec sequences, while the audio driver handles the audio 42 * controller sequences. 43 * 44 * The disable sequences must be performed before disabling the transcoder or 45 * port. The enable sequences may only be performed after enabling the 46 * transcoder and port, and after completed link training. Therefore the audio 47 * enable/disable sequences are part of the modeset sequence. 48 * 49 * The codec and controller sequences could be done either parallel or serial, 50 * but generally the ELDV/PD change in the codec sequence indicates to the audio 51 * driver that the controller sequence should start. Indeed, most of the 52 * co-operation between the graphics and audio drivers is handled via audio 53 * related registers. (The notable exception is the power management, not 54 * covered here.) 55 * 56 * The struct &i915_audio_component is used to interact between the graphics 57 * and audio drivers. The struct &i915_audio_component_ops @ops in it is 58 * defined in graphics driver and called in audio driver. The 59 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver. 60 */ 61 62 /* DP N/M table */ 63 #define LC_810M 810000 64 #define LC_540M 540000 65 #define LC_270M 270000 66 #define LC_162M 162000 67 68 struct dp_aud_n_m { 69 int sample_rate; 70 int clock; 71 u16 m; 72 u16 n; 73 }; 74 75 /* Values according to DP 1.4 Table 2-104 */ 76 static const struct dp_aud_n_m dp_aud_n_m[] = { 77 { 32000, LC_162M, 1024, 10125 }, 78 { 44100, LC_162M, 784, 5625 }, 79 { 48000, LC_162M, 512, 3375 }, 80 { 64000, LC_162M, 2048, 10125 }, 81 { 88200, LC_162M, 1568, 5625 }, 82 { 96000, LC_162M, 1024, 3375 }, 83 { 128000, LC_162M, 4096, 10125 }, 84 { 176400, LC_162M, 3136, 5625 }, 85 { 192000, LC_162M, 2048, 3375 }, 86 { 32000, LC_270M, 1024, 16875 }, 87 { 44100, LC_270M, 784, 9375 }, 88 { 48000, LC_270M, 512, 5625 }, 89 { 64000, LC_270M, 2048, 16875 }, 90 { 88200, LC_270M, 1568, 9375 }, 91 { 96000, LC_270M, 1024, 5625 }, 92 { 128000, LC_270M, 4096, 16875 }, 93 { 176400, LC_270M, 3136, 9375 }, 94 { 192000, LC_270M, 2048, 5625 }, 95 { 32000, LC_540M, 1024, 33750 }, 96 { 44100, LC_540M, 784, 18750 }, 97 { 48000, LC_540M, 512, 11250 }, 98 { 64000, LC_540M, 2048, 33750 }, 99 { 88200, LC_540M, 1568, 18750 }, 100 { 96000, LC_540M, 1024, 11250 }, 101 { 128000, LC_540M, 4096, 33750 }, 102 { 176400, LC_540M, 3136, 18750 }, 103 { 192000, LC_540M, 2048, 11250 }, 104 { 32000, LC_810M, 1024, 50625 }, 105 { 44100, LC_810M, 784, 28125 }, 106 { 48000, LC_810M, 512, 16875 }, 107 { 64000, LC_810M, 2048, 50625 }, 108 { 88200, LC_810M, 1568, 28125 }, 109 { 96000, LC_810M, 1024, 16875 }, 110 { 128000, LC_810M, 4096, 50625 }, 111 { 176400, LC_810M, 3136, 28125 }, 112 { 192000, LC_810M, 2048, 16875 }, 113 }; 114 115 static const struct dp_aud_n_m * 116 audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate) 117 { 118 int i; 119 120 for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) { 121 if (rate == dp_aud_n_m[i].sample_rate && 122 crtc_state->port_clock == dp_aud_n_m[i].clock) 123 return &dp_aud_n_m[i]; 124 } 125 126 return NULL; 127 } 128 129 static const struct { 130 int clock; 131 u32 config; 132 } hdmi_audio_clock[] = { 133 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, 134 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ 135 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, 136 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, 137 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, 138 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, 139 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, 140 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, 141 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, 142 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, 143 }; 144 145 /* HDMI N/CTS table */ 146 #define TMDS_297M 297000 147 #define TMDS_296M 296703 148 #define TMDS_594M 594000 149 #define TMDS_593M 593407 150 151 static const struct { 152 int sample_rate; 153 int clock; 154 int n; 155 int cts; 156 } hdmi_aud_ncts[] = { 157 { 32000, TMDS_296M, 5824, 421875 }, 158 { 32000, TMDS_297M, 3072, 222750 }, 159 { 32000, TMDS_593M, 5824, 843750 }, 160 { 32000, TMDS_594M, 3072, 445500 }, 161 { 44100, TMDS_296M, 4459, 234375 }, 162 { 44100, TMDS_297M, 4704, 247500 }, 163 { 44100, TMDS_593M, 8918, 937500 }, 164 { 44100, TMDS_594M, 9408, 990000 }, 165 { 88200, TMDS_296M, 8918, 234375 }, 166 { 88200, TMDS_297M, 9408, 247500 }, 167 { 88200, TMDS_593M, 17836, 937500 }, 168 { 88200, TMDS_594M, 18816, 990000 }, 169 { 176400, TMDS_296M, 17836, 234375 }, 170 { 176400, TMDS_297M, 18816, 247500 }, 171 { 176400, TMDS_593M, 35672, 937500 }, 172 { 176400, TMDS_594M, 37632, 990000 }, 173 { 48000, TMDS_296M, 5824, 281250 }, 174 { 48000, TMDS_297M, 5120, 247500 }, 175 { 48000, TMDS_593M, 5824, 562500 }, 176 { 48000, TMDS_594M, 6144, 594000 }, 177 { 96000, TMDS_296M, 11648, 281250 }, 178 { 96000, TMDS_297M, 10240, 247500 }, 179 { 96000, TMDS_593M, 11648, 562500 }, 180 { 96000, TMDS_594M, 12288, 594000 }, 181 { 192000, TMDS_296M, 23296, 281250 }, 182 { 192000, TMDS_297M, 20480, 247500 }, 183 { 192000, TMDS_593M, 23296, 562500 }, 184 { 192000, TMDS_594M, 24576, 594000 }, 185 }; 186 187 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ 188 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state) 189 { 190 const struct drm_display_mode *adjusted_mode = 191 &crtc_state->base.adjusted_mode; 192 int i; 193 194 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { 195 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) 196 break; 197 } 198 199 if (i == ARRAY_SIZE(hdmi_audio_clock)) { 200 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", 201 adjusted_mode->crtc_clock); 202 i = 1; 203 } 204 205 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", 206 hdmi_audio_clock[i].clock, 207 hdmi_audio_clock[i].config); 208 209 return hdmi_audio_clock[i].config; 210 } 211 212 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state, 213 int rate) 214 { 215 const struct drm_display_mode *adjusted_mode = 216 &crtc_state->base.adjusted_mode; 217 int i; 218 219 for (i = 0; i < ARRAY_SIZE(hdmi_aud_ncts); i++) { 220 if (rate == hdmi_aud_ncts[i].sample_rate && 221 adjusted_mode->crtc_clock == hdmi_aud_ncts[i].clock) { 222 return hdmi_aud_ncts[i].n; 223 } 224 } 225 return 0; 226 } 227 228 static bool intel_eld_uptodate(struct drm_connector *connector, 229 i915_reg_t reg_eldv, u32 bits_eldv, 230 i915_reg_t reg_elda, u32 bits_elda, 231 i915_reg_t reg_edid) 232 { 233 struct drm_i915_private *dev_priv = to_i915(connector->dev); 234 const u8 *eld = connector->eld; 235 u32 tmp; 236 int i; 237 238 tmp = I915_READ(reg_eldv); 239 tmp &= bits_eldv; 240 241 if (!tmp) 242 return false; 243 244 tmp = I915_READ(reg_elda); 245 tmp &= ~bits_elda; 246 I915_WRITE(reg_elda, tmp); 247 248 for (i = 0; i < drm_eld_size(eld) / 4; i++) 249 if (I915_READ(reg_edid) != *((const u32 *)eld + i)) 250 return false; 251 252 return true; 253 } 254 255 static void g4x_audio_codec_disable(struct intel_encoder *encoder, 256 const struct intel_crtc_state *old_crtc_state, 257 const struct drm_connector_state *old_conn_state) 258 { 259 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 260 u32 eldv, tmp; 261 262 DRM_DEBUG_KMS("Disable audio codec\n"); 263 264 tmp = I915_READ(G4X_AUD_VID_DID); 265 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) 266 eldv = G4X_ELDV_DEVCL_DEVBLC; 267 else 268 eldv = G4X_ELDV_DEVCTG; 269 270 /* Invalidate ELD */ 271 tmp = I915_READ(G4X_AUD_CNTL_ST); 272 tmp &= ~eldv; 273 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 274 } 275 276 static void g4x_audio_codec_enable(struct intel_encoder *encoder, 277 const struct intel_crtc_state *crtc_state, 278 const struct drm_connector_state *conn_state) 279 { 280 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 281 struct drm_connector *connector = conn_state->connector; 282 const u8 *eld = connector->eld; 283 u32 eldv; 284 u32 tmp; 285 int len, i; 286 287 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", drm_eld_size(eld)); 288 289 tmp = I915_READ(G4X_AUD_VID_DID); 290 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) 291 eldv = G4X_ELDV_DEVCL_DEVBLC; 292 else 293 eldv = G4X_ELDV_DEVCTG; 294 295 if (intel_eld_uptodate(connector, 296 G4X_AUD_CNTL_ST, eldv, 297 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK, 298 G4X_HDMIW_HDMIEDID)) 299 return; 300 301 tmp = I915_READ(G4X_AUD_CNTL_ST); 302 tmp &= ~(eldv | G4X_ELD_ADDR_MASK); 303 len = (tmp >> 9) & 0x1f; /* ELD buffer size */ 304 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 305 306 len = min(drm_eld_size(eld) / 4, len); 307 DRM_DEBUG_DRIVER("ELD size %d\n", len); 308 for (i = 0; i < len; i++) 309 I915_WRITE(G4X_HDMIW_HDMIEDID, *((const u32 *)eld + i)); 310 311 tmp = I915_READ(G4X_AUD_CNTL_ST); 312 tmp |= eldv; 313 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 314 } 315 316 static void 317 hsw_dp_audio_config_update(struct intel_encoder *encoder, 318 const struct intel_crtc_state *crtc_state) 319 { 320 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 321 struct i915_audio_component *acomp = dev_priv->audio_component; 322 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 323 enum port port = encoder->port; 324 const struct dp_aud_n_m *nm; 325 int rate; 326 u32 tmp; 327 328 rate = acomp ? acomp->aud_sample_rate[port] : 0; 329 nm = audio_config_dp_get_n_m(crtc_state, rate); 330 if (nm) 331 DRM_DEBUG_KMS("using Maud %u, Naud %u\n", nm->m, nm->n); 332 else 333 DRM_DEBUG_KMS("using automatic Maud, Naud\n"); 334 335 tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder)); 336 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 337 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 338 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 339 tmp |= AUD_CONFIG_N_VALUE_INDEX; 340 341 if (nm) { 342 tmp &= ~AUD_CONFIG_N_MASK; 343 tmp |= AUD_CONFIG_N(nm->n); 344 tmp |= AUD_CONFIG_N_PROG_ENABLE; 345 } 346 347 I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp); 348 349 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); 350 tmp &= ~AUD_CONFIG_M_MASK; 351 tmp &= ~AUD_M_CTS_M_VALUE_INDEX; 352 tmp &= ~AUD_M_CTS_M_PROG_ENABLE; 353 354 if (nm) { 355 tmp |= nm->m; 356 tmp |= AUD_M_CTS_M_VALUE_INDEX; 357 tmp |= AUD_M_CTS_M_PROG_ENABLE; 358 } 359 360 I915_WRITE(HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 361 } 362 363 static void 364 hsw_hdmi_audio_config_update(struct intel_encoder *encoder, 365 const struct intel_crtc_state *crtc_state) 366 { 367 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 368 struct i915_audio_component *acomp = dev_priv->audio_component; 369 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 370 enum port port = encoder->port; 371 int n, rate; 372 u32 tmp; 373 374 rate = acomp ? acomp->aud_sample_rate[port] : 0; 375 376 tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder)); 377 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 378 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 379 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 380 tmp |= audio_config_hdmi_pixel_clock(crtc_state); 381 382 n = audio_config_hdmi_get_n(crtc_state, rate); 383 if (n != 0) { 384 DRM_DEBUG_KMS("using N %d\n", n); 385 386 tmp &= ~AUD_CONFIG_N_MASK; 387 tmp |= AUD_CONFIG_N(n); 388 tmp |= AUD_CONFIG_N_PROG_ENABLE; 389 } else { 390 DRM_DEBUG_KMS("using automatic N\n"); 391 } 392 393 I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp); 394 395 /* 396 * Let's disable "Enable CTS or M Prog bit" 397 * and let HW calculate the value 398 */ 399 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); 400 tmp &= ~AUD_M_CTS_M_PROG_ENABLE; 401 tmp &= ~AUD_M_CTS_M_VALUE_INDEX; 402 I915_WRITE(HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 403 } 404 405 static void 406 hsw_audio_config_update(struct intel_encoder *encoder, 407 const struct intel_crtc_state *crtc_state) 408 { 409 if (intel_crtc_has_dp_encoder(crtc_state)) 410 hsw_dp_audio_config_update(encoder, crtc_state); 411 else 412 hsw_hdmi_audio_config_update(encoder, crtc_state); 413 } 414 415 static void hsw_audio_codec_disable(struct intel_encoder *encoder, 416 const struct intel_crtc_state *old_crtc_state, 417 const struct drm_connector_state *old_conn_state) 418 { 419 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 420 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 421 u32 tmp; 422 423 DRM_DEBUG_KMS("Disable audio codec on transcoder %s\n", 424 transcoder_name(cpu_transcoder)); 425 426 mutex_lock(&dev_priv->av_mutex); 427 428 /* Disable timestamps */ 429 tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder)); 430 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 431 tmp |= AUD_CONFIG_N_PROG_ENABLE; 432 tmp &= ~AUD_CONFIG_UPPER_N_MASK; 433 tmp &= ~AUD_CONFIG_LOWER_N_MASK; 434 if (intel_crtc_has_dp_encoder(old_crtc_state)) 435 tmp |= AUD_CONFIG_N_VALUE_INDEX; 436 I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp); 437 438 /* Invalidate ELD */ 439 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 440 tmp &= ~AUDIO_ELD_VALID(cpu_transcoder); 441 tmp &= ~AUDIO_OUTPUT_ENABLE(cpu_transcoder); 442 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 443 444 mutex_unlock(&dev_priv->av_mutex); 445 } 446 447 static void hsw_audio_codec_enable(struct intel_encoder *encoder, 448 const struct intel_crtc_state *crtc_state, 449 const struct drm_connector_state *conn_state) 450 { 451 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 452 struct drm_connector *connector = conn_state->connector; 453 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 454 const u8 *eld = connector->eld; 455 u32 tmp; 456 int len, i; 457 458 DRM_DEBUG_KMS("Enable audio codec on transcoder %s, %u bytes ELD\n", 459 transcoder_name(cpu_transcoder), drm_eld_size(eld)); 460 461 mutex_lock(&dev_priv->av_mutex); 462 463 /* Enable audio presence detect, invalidate ELD */ 464 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 465 tmp |= AUDIO_OUTPUT_ENABLE(cpu_transcoder); 466 tmp &= ~AUDIO_ELD_VALID(cpu_transcoder); 467 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 468 469 /* 470 * FIXME: We're supposed to wait for vblank here, but we have vblanks 471 * disabled during the mode set. The proper fix would be to push the 472 * rest of the setup into a vblank work item, queued here, but the 473 * infrastructure is not there yet. 474 */ 475 476 /* Reset ELD write address */ 477 tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(cpu_transcoder)); 478 tmp &= ~IBX_ELD_ADDRESS_MASK; 479 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(cpu_transcoder), tmp); 480 481 /* Up to 84 bytes of hw ELD buffer */ 482 len = min(drm_eld_size(eld), 84); 483 for (i = 0; i < len / 4; i++) 484 I915_WRITE(HSW_AUD_EDID_DATA(cpu_transcoder), *((const u32 *)eld + i)); 485 486 /* ELD valid */ 487 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 488 tmp |= AUDIO_ELD_VALID(cpu_transcoder); 489 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 490 491 /* Enable timestamps */ 492 hsw_audio_config_update(encoder, crtc_state); 493 494 mutex_unlock(&dev_priv->av_mutex); 495 } 496 497 static void ilk_audio_codec_disable(struct intel_encoder *encoder, 498 const struct intel_crtc_state *old_crtc_state, 499 const struct drm_connector_state *old_conn_state) 500 { 501 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 502 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); 503 enum pipe pipe = crtc->pipe; 504 enum port port = encoder->port; 505 u32 tmp, eldv; 506 i915_reg_t aud_config, aud_cntrl_st2; 507 508 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n", 509 port_name(port), pipe_name(pipe)); 510 511 if (WARN_ON(port == PORT_A)) 512 return; 513 514 if (HAS_PCH_IBX(dev_priv)) { 515 aud_config = IBX_AUD_CFG(pipe); 516 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 517 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 518 aud_config = VLV_AUD_CFG(pipe); 519 aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 520 } else { 521 aud_config = CPT_AUD_CFG(pipe); 522 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 523 } 524 525 /* Disable timestamps */ 526 tmp = I915_READ(aud_config); 527 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 528 tmp |= AUD_CONFIG_N_PROG_ENABLE; 529 tmp &= ~AUD_CONFIG_UPPER_N_MASK; 530 tmp &= ~AUD_CONFIG_LOWER_N_MASK; 531 if (intel_crtc_has_dp_encoder(old_crtc_state)) 532 tmp |= AUD_CONFIG_N_VALUE_INDEX; 533 I915_WRITE(aud_config, tmp); 534 535 eldv = IBX_ELD_VALID(port); 536 537 /* Invalidate ELD */ 538 tmp = I915_READ(aud_cntrl_st2); 539 tmp &= ~eldv; 540 I915_WRITE(aud_cntrl_st2, tmp); 541 } 542 543 static void ilk_audio_codec_enable(struct intel_encoder *encoder, 544 const struct intel_crtc_state *crtc_state, 545 const struct drm_connector_state *conn_state) 546 { 547 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 548 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 549 struct drm_connector *connector = conn_state->connector; 550 enum pipe pipe = crtc->pipe; 551 enum port port = encoder->port; 552 const u8 *eld = connector->eld; 553 u32 tmp, eldv; 554 int len, i; 555 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; 556 557 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n", 558 port_name(port), pipe_name(pipe), drm_eld_size(eld)); 559 560 if (WARN_ON(port == PORT_A)) 561 return; 562 563 /* 564 * FIXME: We're supposed to wait for vblank here, but we have vblanks 565 * disabled during the mode set. The proper fix would be to push the 566 * rest of the setup into a vblank work item, queued here, but the 567 * infrastructure is not there yet. 568 */ 569 570 if (HAS_PCH_IBX(dev_priv)) { 571 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); 572 aud_config = IBX_AUD_CFG(pipe); 573 aud_cntl_st = IBX_AUD_CNTL_ST(pipe); 574 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 575 } else if (IS_VALLEYVIEW(dev_priv) || 576 IS_CHERRYVIEW(dev_priv)) { 577 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); 578 aud_config = VLV_AUD_CFG(pipe); 579 aud_cntl_st = VLV_AUD_CNTL_ST(pipe); 580 aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 581 } else { 582 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); 583 aud_config = CPT_AUD_CFG(pipe); 584 aud_cntl_st = CPT_AUD_CNTL_ST(pipe); 585 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 586 } 587 588 eldv = IBX_ELD_VALID(port); 589 590 /* Invalidate ELD */ 591 tmp = I915_READ(aud_cntrl_st2); 592 tmp &= ~eldv; 593 I915_WRITE(aud_cntrl_st2, tmp); 594 595 /* Reset ELD write address */ 596 tmp = I915_READ(aud_cntl_st); 597 tmp &= ~IBX_ELD_ADDRESS_MASK; 598 I915_WRITE(aud_cntl_st, tmp); 599 600 /* Up to 84 bytes of hw ELD buffer */ 601 len = min(drm_eld_size(eld), 84); 602 for (i = 0; i < len / 4; i++) 603 I915_WRITE(hdmiw_hdmiedid, *((const u32 *)eld + i)); 604 605 /* ELD valid */ 606 tmp = I915_READ(aud_cntrl_st2); 607 tmp |= eldv; 608 I915_WRITE(aud_cntrl_st2, tmp); 609 610 /* Enable timestamps */ 611 tmp = I915_READ(aud_config); 612 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 613 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 614 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 615 if (intel_crtc_has_dp_encoder(crtc_state)) 616 tmp |= AUD_CONFIG_N_VALUE_INDEX; 617 else 618 tmp |= audio_config_hdmi_pixel_clock(crtc_state); 619 I915_WRITE(aud_config, tmp); 620 } 621 622 /** 623 * intel_audio_codec_enable - Enable the audio codec for HD audio 624 * @encoder: encoder on which to enable audio 625 * @crtc_state: pointer to the current crtc state. 626 * @conn_state: pointer to the current connector state. 627 * 628 * The enable sequences may only be performed after enabling the transcoder and 629 * port, and after completed link training. 630 */ 631 void intel_audio_codec_enable(struct intel_encoder *encoder, 632 const struct intel_crtc_state *crtc_state, 633 const struct drm_connector_state *conn_state) 634 { 635 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 636 struct i915_audio_component *acomp = dev_priv->audio_component; 637 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 638 struct drm_connector *connector = conn_state->connector; 639 const struct drm_display_mode *adjusted_mode = 640 &crtc_state->base.adjusted_mode; 641 enum port port = encoder->port; 642 enum pipe pipe = crtc->pipe; 643 644 /* FIXME precompute the ELD in .compute_config() */ 645 if (!connector->eld[0]) 646 DRM_DEBUG_KMS("Bogus ELD on [CONNECTOR:%d:%s]\n", 647 connector->base.id, connector->name); 648 649 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 650 connector->base.id, 651 connector->name, 652 connector->encoder->base.id, 653 connector->encoder->name); 654 655 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; 656 657 if (dev_priv->display.audio_codec_enable) 658 dev_priv->display.audio_codec_enable(encoder, 659 crtc_state, 660 conn_state); 661 662 mutex_lock(&dev_priv->av_mutex); 663 encoder->audio_connector = connector; 664 665 /* referred in audio callbacks */ 666 dev_priv->av_enc_map[pipe] = encoder; 667 mutex_unlock(&dev_priv->av_mutex); 668 669 if (acomp && acomp->base.audio_ops && 670 acomp->base.audio_ops->pin_eld_notify) { 671 /* audio drivers expect pipe = -1 to indicate Non-MST cases */ 672 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 673 pipe = -1; 674 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 675 (int) port, (int) pipe); 676 } 677 678 intel_lpe_audio_notify(dev_priv, pipe, port, connector->eld, 679 crtc_state->port_clock, 680 intel_crtc_has_dp_encoder(crtc_state)); 681 } 682 683 /** 684 * intel_audio_codec_disable - Disable the audio codec for HD audio 685 * @encoder: encoder on which to disable audio 686 * @old_crtc_state: pointer to the old crtc state. 687 * @old_conn_state: pointer to the old connector state. 688 * 689 * The disable sequences must be performed before disabling the transcoder or 690 * port. 691 */ 692 void intel_audio_codec_disable(struct intel_encoder *encoder, 693 const struct intel_crtc_state *old_crtc_state, 694 const struct drm_connector_state *old_conn_state) 695 { 696 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 697 struct i915_audio_component *acomp = dev_priv->audio_component; 698 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); 699 enum port port = encoder->port; 700 enum pipe pipe = crtc->pipe; 701 702 if (dev_priv->display.audio_codec_disable) 703 dev_priv->display.audio_codec_disable(encoder, 704 old_crtc_state, 705 old_conn_state); 706 707 mutex_lock(&dev_priv->av_mutex); 708 encoder->audio_connector = NULL; 709 dev_priv->av_enc_map[pipe] = NULL; 710 mutex_unlock(&dev_priv->av_mutex); 711 712 if (acomp && acomp->base.audio_ops && 713 acomp->base.audio_ops->pin_eld_notify) { 714 /* audio drivers expect pipe = -1 to indicate Non-MST cases */ 715 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 716 pipe = -1; 717 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 718 (int) port, (int) pipe); 719 } 720 721 intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false); 722 } 723 724 /** 725 * intel_init_audio_hooks - Set up chip specific audio hooks 726 * @dev_priv: device private 727 */ 728 void intel_init_audio_hooks(struct drm_i915_private *dev_priv) 729 { 730 if (IS_G4X(dev_priv)) { 731 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable; 732 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable; 733 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 734 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; 735 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; 736 } else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) { 737 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable; 738 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable; 739 } else if (HAS_PCH_SPLIT(dev_priv)) { 740 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; 741 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; 742 } 743 } 744 745 static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv, 746 bool enable) 747 { 748 struct drm_modeset_acquire_ctx ctx; 749 struct drm_atomic_state *state; 750 int ret; 751 752 drm_modeset_acquire_init(&ctx, 0); 753 state = drm_atomic_state_alloc(&dev_priv->drm); 754 if (WARN_ON(!state)) 755 return; 756 757 state->acquire_ctx = &ctx; 758 759 retry: 760 to_intel_atomic_state(state)->cdclk.force_min_cdclk_changed = true; 761 to_intel_atomic_state(state)->cdclk.force_min_cdclk = 762 enable ? 2 * 96000 : 0; 763 764 /* 765 * Protects dev_priv->cdclk.force_min_cdclk 766 * Need to lock this here in case we have no active pipes 767 * and thus wouldn't lock it during the commit otherwise. 768 */ 769 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 770 &ctx); 771 if (!ret) 772 ret = drm_atomic_commit(state); 773 774 if (ret == -EDEADLK) { 775 drm_atomic_state_clear(state); 776 drm_modeset_backoff(&ctx); 777 goto retry; 778 } 779 780 WARN_ON(ret); 781 782 drm_atomic_state_put(state); 783 784 drm_modeset_drop_locks(&ctx); 785 drm_modeset_acquire_fini(&ctx); 786 } 787 788 static unsigned long i915_audio_component_get_power(struct device *kdev) 789 { 790 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 791 intel_wakeref_t ret; 792 793 /* Catch potential impedance mismatches before they occur! */ 794 BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long)); 795 796 ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); 797 798 /* Force CDCLK to 2*BCLK as long as we need audio to be powered. */ 799 if (dev_priv->audio_power_refcount++ == 0) 800 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) 801 glk_force_audio_cdclk(dev_priv, true); 802 803 return ret; 804 } 805 806 static void i915_audio_component_put_power(struct device *kdev, 807 unsigned long cookie) 808 { 809 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 810 811 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */ 812 if (--dev_priv->audio_power_refcount == 0) 813 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) 814 glk_force_audio_cdclk(dev_priv, false); 815 816 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie); 817 } 818 819 static void i915_audio_component_codec_wake_override(struct device *kdev, 820 bool enable) 821 { 822 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 823 unsigned long cookie; 824 u32 tmp; 825 826 if (!IS_GEN(dev_priv, 9)) 827 return; 828 829 cookie = i915_audio_component_get_power(kdev); 830 831 /* 832 * Enable/disable generating the codec wake signal, overriding the 833 * internal logic to generate the codec wake to controller. 834 */ 835 tmp = I915_READ(HSW_AUD_CHICKENBIT); 836 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL; 837 I915_WRITE(HSW_AUD_CHICKENBIT, tmp); 838 usleep_range(1000, 1500); 839 840 if (enable) { 841 tmp = I915_READ(HSW_AUD_CHICKENBIT); 842 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL; 843 I915_WRITE(HSW_AUD_CHICKENBIT, tmp); 844 usleep_range(1000, 1500); 845 } 846 847 i915_audio_component_put_power(kdev, cookie); 848 } 849 850 /* Get CDCLK in kHz */ 851 static int i915_audio_component_get_cdclk_freq(struct device *kdev) 852 { 853 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 854 855 if (WARN_ON_ONCE(!HAS_DDI(dev_priv))) 856 return -ENODEV; 857 858 return dev_priv->cdclk.hw.cdclk; 859 } 860 861 /* 862 * get the intel_encoder according to the parameter port and pipe 863 * intel_encoder is saved by the index of pipe 864 * MST & (pipe >= 0): return the av_enc_map[pipe], 865 * when port is matched 866 * MST & (pipe < 0): this is invalid 867 * Non-MST & (pipe >= 0): only pipe = 0 (the first device entry) 868 * will get the right intel_encoder with port matched 869 * Non-MST & (pipe < 0): get the right intel_encoder with port matched 870 */ 871 static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv, 872 int port, int pipe) 873 { 874 struct intel_encoder *encoder; 875 876 /* MST */ 877 if (pipe >= 0) { 878 if (WARN_ON(pipe >= ARRAY_SIZE(dev_priv->av_enc_map))) 879 return NULL; 880 881 encoder = dev_priv->av_enc_map[pipe]; 882 /* 883 * when bootup, audio driver may not know it is 884 * MST or not. So it will poll all the port & pipe 885 * combinations 886 */ 887 if (encoder != NULL && encoder->port == port && 888 encoder->type == INTEL_OUTPUT_DP_MST) 889 return encoder; 890 } 891 892 /* Non-MST */ 893 if (pipe > 0) 894 return NULL; 895 896 for_each_pipe(dev_priv, pipe) { 897 encoder = dev_priv->av_enc_map[pipe]; 898 if (encoder == NULL) 899 continue; 900 901 if (encoder->type == INTEL_OUTPUT_DP_MST) 902 continue; 903 904 if (port == encoder->port) 905 return encoder; 906 } 907 908 return NULL; 909 } 910 911 static int i915_audio_component_sync_audio_rate(struct device *kdev, int port, 912 int pipe, int rate) 913 { 914 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 915 struct i915_audio_component *acomp = dev_priv->audio_component; 916 struct intel_encoder *encoder; 917 struct intel_crtc *crtc; 918 unsigned long cookie; 919 int err = 0; 920 921 if (!HAS_DDI(dev_priv)) 922 return 0; 923 924 cookie = i915_audio_component_get_power(kdev); 925 mutex_lock(&dev_priv->av_mutex); 926 927 /* 1. get the pipe */ 928 encoder = get_saved_enc(dev_priv, port, pipe); 929 if (!encoder || !encoder->base.crtc) { 930 DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port)); 931 err = -ENODEV; 932 goto unlock; 933 } 934 935 crtc = to_intel_crtc(encoder->base.crtc); 936 937 /* port must be valid now, otherwise the pipe will be invalid */ 938 acomp->aud_sample_rate[port] = rate; 939 940 hsw_audio_config_update(encoder, crtc->config); 941 942 unlock: 943 mutex_unlock(&dev_priv->av_mutex); 944 i915_audio_component_put_power(kdev, cookie); 945 return err; 946 } 947 948 static int i915_audio_component_get_eld(struct device *kdev, int port, 949 int pipe, bool *enabled, 950 unsigned char *buf, int max_bytes) 951 { 952 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 953 struct intel_encoder *intel_encoder; 954 const u8 *eld; 955 int ret = -EINVAL; 956 957 mutex_lock(&dev_priv->av_mutex); 958 959 intel_encoder = get_saved_enc(dev_priv, port, pipe); 960 if (!intel_encoder) { 961 DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port)); 962 mutex_unlock(&dev_priv->av_mutex); 963 return ret; 964 } 965 966 ret = 0; 967 *enabled = intel_encoder->audio_connector != NULL; 968 if (*enabled) { 969 eld = intel_encoder->audio_connector->eld; 970 ret = drm_eld_size(eld); 971 memcpy(buf, eld, min(max_bytes, ret)); 972 } 973 974 mutex_unlock(&dev_priv->av_mutex); 975 return ret; 976 } 977 978 static const struct drm_audio_component_ops i915_audio_component_ops = { 979 .owner = THIS_MODULE, 980 .get_power = i915_audio_component_get_power, 981 .put_power = i915_audio_component_put_power, 982 .codec_wake_override = i915_audio_component_codec_wake_override, 983 .get_cdclk_freq = i915_audio_component_get_cdclk_freq, 984 .sync_audio_rate = i915_audio_component_sync_audio_rate, 985 .get_eld = i915_audio_component_get_eld, 986 }; 987 988 static int i915_audio_component_bind(struct device *i915_kdev, 989 struct device *hda_kdev, void *data) 990 { 991 struct i915_audio_component *acomp = data; 992 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); 993 int i; 994 995 if (WARN_ON(acomp->base.ops || acomp->base.dev)) 996 return -EEXIST; 997 998 if (WARN_ON(!device_link_add(hda_kdev, i915_kdev, DL_FLAG_STATELESS))) 999 return -ENOMEM; 1000 1001 drm_modeset_lock_all(&dev_priv->drm); 1002 acomp->base.ops = &i915_audio_component_ops; 1003 acomp->base.dev = i915_kdev; 1004 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); 1005 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) 1006 acomp->aud_sample_rate[i] = 0; 1007 dev_priv->audio_component = acomp; 1008 drm_modeset_unlock_all(&dev_priv->drm); 1009 1010 return 0; 1011 } 1012 1013 static void i915_audio_component_unbind(struct device *i915_kdev, 1014 struct device *hda_kdev, void *data) 1015 { 1016 struct i915_audio_component *acomp = data; 1017 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); 1018 1019 drm_modeset_lock_all(&dev_priv->drm); 1020 acomp->base.ops = NULL; 1021 acomp->base.dev = NULL; 1022 dev_priv->audio_component = NULL; 1023 drm_modeset_unlock_all(&dev_priv->drm); 1024 1025 device_link_remove(hda_kdev, i915_kdev); 1026 } 1027 1028 static const struct component_ops i915_audio_component_bind_ops = { 1029 .bind = i915_audio_component_bind, 1030 .unbind = i915_audio_component_unbind, 1031 }; 1032 1033 /** 1034 * i915_audio_component_init - initialize and register the audio component 1035 * @dev_priv: i915 device instance 1036 * 1037 * This will register with the component framework a child component which 1038 * will bind dynamically to the snd_hda_intel driver's corresponding master 1039 * component when the latter is registered. During binding the child 1040 * initializes an instance of struct i915_audio_component which it receives 1041 * from the master. The master can then start to use the interface defined by 1042 * this struct. Each side can break the binding at any point by deregistering 1043 * its own component after which each side's component unbind callback is 1044 * called. 1045 * 1046 * We ignore any error during registration and continue with reduced 1047 * functionality (i.e. without HDMI audio). 1048 */ 1049 static void i915_audio_component_init(struct drm_i915_private *dev_priv) 1050 { 1051 int ret; 1052 1053 ret = component_add_typed(dev_priv->drm.dev, 1054 &i915_audio_component_bind_ops, 1055 I915_COMPONENT_AUDIO); 1056 if (ret < 0) { 1057 DRM_ERROR("failed to add audio component (%d)\n", ret); 1058 /* continue with reduced functionality */ 1059 return; 1060 } 1061 1062 dev_priv->audio_component_registered = true; 1063 } 1064 1065 /** 1066 * i915_audio_component_cleanup - deregister the audio component 1067 * @dev_priv: i915 device instance 1068 * 1069 * Deregisters the audio component, breaking any existing binding to the 1070 * corresponding snd_hda_intel driver's master component. 1071 */ 1072 static void i915_audio_component_cleanup(struct drm_i915_private *dev_priv) 1073 { 1074 if (!dev_priv->audio_component_registered) 1075 return; 1076 1077 component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops); 1078 dev_priv->audio_component_registered = false; 1079 } 1080 1081 /** 1082 * intel_audio_init() - Initialize the audio driver either using 1083 * component framework or using lpe audio bridge 1084 * @dev_priv: the i915 drm device private data 1085 * 1086 */ 1087 void intel_audio_init(struct drm_i915_private *dev_priv) 1088 { 1089 if (intel_lpe_audio_init(dev_priv) < 0) 1090 i915_audio_component_init(dev_priv); 1091 } 1092 1093 /** 1094 * intel_audio_deinit() - deinitialize the audio driver 1095 * @dev_priv: the i915 drm device private data 1096 * 1097 */ 1098 void intel_audio_deinit(struct drm_i915_private *dev_priv) 1099 { 1100 if ((dev_priv)->lpe_audio.platdev != NULL) 1101 intel_lpe_audio_teardown(dev_priv); 1102 else 1103 i915_audio_component_cleanup(dev_priv); 1104 } 1105