1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/component.h> 25 #include <linux/kernel.h> 26 27 #include <drm/drm_edid.h> 28 #include <drm/i915_component.h> 29 30 #include "i915_drv.h" 31 #include "intel_audio.h" 32 #include "intel_display_types.h" 33 #include "intel_lpe_audio.h" 34 35 /** 36 * DOC: High Definition Audio over HDMI and Display Port 37 * 38 * The graphics and audio drivers together support High Definition Audio over 39 * HDMI and Display Port. The audio programming sequences are divided into audio 40 * codec and controller enable and disable sequences. The graphics driver 41 * handles the audio codec sequences, while the audio driver handles the audio 42 * controller sequences. 43 * 44 * The disable sequences must be performed before disabling the transcoder or 45 * port. The enable sequences may only be performed after enabling the 46 * transcoder and port, and after completed link training. Therefore the audio 47 * enable/disable sequences are part of the modeset sequence. 48 * 49 * The codec and controller sequences could be done either parallel or serial, 50 * but generally the ELDV/PD change in the codec sequence indicates to the audio 51 * driver that the controller sequence should start. Indeed, most of the 52 * co-operation between the graphics and audio drivers is handled via audio 53 * related registers. (The notable exception is the power management, not 54 * covered here.) 55 * 56 * The struct &i915_audio_component is used to interact between the graphics 57 * and audio drivers. The struct &i915_audio_component_ops @ops in it is 58 * defined in graphics driver and called in audio driver. The 59 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver. 60 */ 61 62 /* DP N/M table */ 63 #define LC_810M 810000 64 #define LC_540M 540000 65 #define LC_270M 270000 66 #define LC_162M 162000 67 68 struct dp_aud_n_m { 69 int sample_rate; 70 int clock; 71 u16 m; 72 u16 n; 73 }; 74 75 struct hdmi_aud_ncts { 76 int sample_rate; 77 int clock; 78 int n; 79 int cts; 80 }; 81 82 /* Values according to DP 1.4 Table 2-104 */ 83 static const struct dp_aud_n_m dp_aud_n_m[] = { 84 { 32000, LC_162M, 1024, 10125 }, 85 { 44100, LC_162M, 784, 5625 }, 86 { 48000, LC_162M, 512, 3375 }, 87 { 64000, LC_162M, 2048, 10125 }, 88 { 88200, LC_162M, 1568, 5625 }, 89 { 96000, LC_162M, 1024, 3375 }, 90 { 128000, LC_162M, 4096, 10125 }, 91 { 176400, LC_162M, 3136, 5625 }, 92 { 192000, LC_162M, 2048, 3375 }, 93 { 32000, LC_270M, 1024, 16875 }, 94 { 44100, LC_270M, 784, 9375 }, 95 { 48000, LC_270M, 512, 5625 }, 96 { 64000, LC_270M, 2048, 16875 }, 97 { 88200, LC_270M, 1568, 9375 }, 98 { 96000, LC_270M, 1024, 5625 }, 99 { 128000, LC_270M, 4096, 16875 }, 100 { 176400, LC_270M, 3136, 9375 }, 101 { 192000, LC_270M, 2048, 5625 }, 102 { 32000, LC_540M, 1024, 33750 }, 103 { 44100, LC_540M, 784, 18750 }, 104 { 48000, LC_540M, 512, 11250 }, 105 { 64000, LC_540M, 2048, 33750 }, 106 { 88200, LC_540M, 1568, 18750 }, 107 { 96000, LC_540M, 1024, 11250 }, 108 { 128000, LC_540M, 4096, 33750 }, 109 { 176400, LC_540M, 3136, 18750 }, 110 { 192000, LC_540M, 2048, 11250 }, 111 { 32000, LC_810M, 1024, 50625 }, 112 { 44100, LC_810M, 784, 28125 }, 113 { 48000, LC_810M, 512, 16875 }, 114 { 64000, LC_810M, 2048, 50625 }, 115 { 88200, LC_810M, 1568, 28125 }, 116 { 96000, LC_810M, 1024, 16875 }, 117 { 128000, LC_810M, 4096, 50625 }, 118 { 176400, LC_810M, 3136, 28125 }, 119 { 192000, LC_810M, 2048, 16875 }, 120 }; 121 122 static const struct dp_aud_n_m * 123 audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate) 124 { 125 int i; 126 127 for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) { 128 if (rate == dp_aud_n_m[i].sample_rate && 129 crtc_state->port_clock == dp_aud_n_m[i].clock) 130 return &dp_aud_n_m[i]; 131 } 132 133 return NULL; 134 } 135 136 static const struct { 137 int clock; 138 u32 config; 139 } hdmi_audio_clock[] = { 140 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, 141 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ 142 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, 143 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, 144 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, 145 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, 146 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, 147 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, 148 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, 149 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, 150 }; 151 152 /* HDMI N/CTS table */ 153 #define TMDS_297M 297000 154 #define TMDS_296M 296703 155 #define TMDS_594M 594000 156 #define TMDS_593M 593407 157 158 static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = { 159 { 32000, TMDS_296M, 5824, 421875 }, 160 { 32000, TMDS_297M, 3072, 222750 }, 161 { 32000, TMDS_593M, 5824, 843750 }, 162 { 32000, TMDS_594M, 3072, 445500 }, 163 { 44100, TMDS_296M, 4459, 234375 }, 164 { 44100, TMDS_297M, 4704, 247500 }, 165 { 44100, TMDS_593M, 8918, 937500 }, 166 { 44100, TMDS_594M, 9408, 990000 }, 167 { 88200, TMDS_296M, 8918, 234375 }, 168 { 88200, TMDS_297M, 9408, 247500 }, 169 { 88200, TMDS_593M, 17836, 937500 }, 170 { 88200, TMDS_594M, 18816, 990000 }, 171 { 176400, TMDS_296M, 17836, 234375 }, 172 { 176400, TMDS_297M, 18816, 247500 }, 173 { 176400, TMDS_593M, 35672, 937500 }, 174 { 176400, TMDS_594M, 37632, 990000 }, 175 { 48000, TMDS_296M, 5824, 281250 }, 176 { 48000, TMDS_297M, 5120, 247500 }, 177 { 48000, TMDS_593M, 5824, 562500 }, 178 { 48000, TMDS_594M, 6144, 594000 }, 179 { 96000, TMDS_296M, 11648, 281250 }, 180 { 96000, TMDS_297M, 10240, 247500 }, 181 { 96000, TMDS_593M, 11648, 562500 }, 182 { 96000, TMDS_594M, 12288, 594000 }, 183 { 192000, TMDS_296M, 23296, 281250 }, 184 { 192000, TMDS_297M, 20480, 247500 }, 185 { 192000, TMDS_593M, 23296, 562500 }, 186 { 192000, TMDS_594M, 24576, 594000 }, 187 }; 188 189 /* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/ 190 /* HDMI N/CTS table for 10 bit deep color(30 bpp)*/ 191 #define TMDS_371M 371250 192 #define TMDS_370M 370878 193 194 static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = { 195 { 32000, TMDS_370M, 5824, 527344 }, 196 { 32000, TMDS_371M, 6144, 556875 }, 197 { 44100, TMDS_370M, 8918, 585938 }, 198 { 44100, TMDS_371M, 4704, 309375 }, 199 { 88200, TMDS_370M, 17836, 585938 }, 200 { 88200, TMDS_371M, 9408, 309375 }, 201 { 176400, TMDS_370M, 35672, 585938 }, 202 { 176400, TMDS_371M, 18816, 309375 }, 203 { 48000, TMDS_370M, 11648, 703125 }, 204 { 48000, TMDS_371M, 5120, 309375 }, 205 { 96000, TMDS_370M, 23296, 703125 }, 206 { 96000, TMDS_371M, 10240, 309375 }, 207 { 192000, TMDS_370M, 46592, 703125 }, 208 { 192000, TMDS_371M, 20480, 309375 }, 209 }; 210 211 /* HDMI N/CTS table for 12 bit deep color(36 bpp)*/ 212 #define TMDS_445_5M 445500 213 #define TMDS_445M 445054 214 215 static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = { 216 { 32000, TMDS_445M, 5824, 632813 }, 217 { 32000, TMDS_445_5M, 4096, 445500 }, 218 { 44100, TMDS_445M, 8918, 703125 }, 219 { 44100, TMDS_445_5M, 4704, 371250 }, 220 { 88200, TMDS_445M, 17836, 703125 }, 221 { 88200, TMDS_445_5M, 9408, 371250 }, 222 { 176400, TMDS_445M, 35672, 703125 }, 223 { 176400, TMDS_445_5M, 18816, 371250 }, 224 { 48000, TMDS_445M, 5824, 421875 }, 225 { 48000, TMDS_445_5M, 5120, 371250 }, 226 { 96000, TMDS_445M, 11648, 421875 }, 227 { 96000, TMDS_445_5M, 10240, 371250 }, 228 { 192000, TMDS_445M, 23296, 421875 }, 229 { 192000, TMDS_445_5M, 20480, 371250 }, 230 }; 231 232 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ 233 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state) 234 { 235 const struct drm_display_mode *adjusted_mode = 236 &crtc_state->base.adjusted_mode; 237 int i; 238 239 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { 240 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) 241 break; 242 } 243 244 if (i == ARRAY_SIZE(hdmi_audio_clock)) { 245 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", 246 adjusted_mode->crtc_clock); 247 i = 1; 248 } 249 250 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", 251 hdmi_audio_clock[i].clock, 252 hdmi_audio_clock[i].config); 253 254 return hdmi_audio_clock[i].config; 255 } 256 257 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state, 258 int rate) 259 { 260 const struct hdmi_aud_ncts *hdmi_ncts_table; 261 int i, size; 262 263 if (crtc_state->pipe_bpp == 36) { 264 hdmi_ncts_table = hdmi_aud_ncts_36bpp; 265 size = ARRAY_SIZE(hdmi_aud_ncts_36bpp); 266 } else if (crtc_state->pipe_bpp == 30) { 267 hdmi_ncts_table = hdmi_aud_ncts_30bpp; 268 size = ARRAY_SIZE(hdmi_aud_ncts_30bpp); 269 } else { 270 hdmi_ncts_table = hdmi_aud_ncts_24bpp; 271 size = ARRAY_SIZE(hdmi_aud_ncts_24bpp); 272 } 273 274 for (i = 0; i < size; i++) { 275 if (rate == hdmi_ncts_table[i].sample_rate && 276 crtc_state->port_clock == hdmi_ncts_table[i].clock) { 277 return hdmi_ncts_table[i].n; 278 } 279 } 280 return 0; 281 } 282 283 static bool intel_eld_uptodate(struct drm_connector *connector, 284 i915_reg_t reg_eldv, u32 bits_eldv, 285 i915_reg_t reg_elda, u32 bits_elda, 286 i915_reg_t reg_edid) 287 { 288 struct drm_i915_private *dev_priv = to_i915(connector->dev); 289 const u8 *eld = connector->eld; 290 u32 tmp; 291 int i; 292 293 tmp = I915_READ(reg_eldv); 294 tmp &= bits_eldv; 295 296 if (!tmp) 297 return false; 298 299 tmp = I915_READ(reg_elda); 300 tmp &= ~bits_elda; 301 I915_WRITE(reg_elda, tmp); 302 303 for (i = 0; i < drm_eld_size(eld) / 4; i++) 304 if (I915_READ(reg_edid) != *((const u32 *)eld + i)) 305 return false; 306 307 return true; 308 } 309 310 static void g4x_audio_codec_disable(struct intel_encoder *encoder, 311 const struct intel_crtc_state *old_crtc_state, 312 const struct drm_connector_state *old_conn_state) 313 { 314 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 315 u32 eldv, tmp; 316 317 DRM_DEBUG_KMS("Disable audio codec\n"); 318 319 tmp = I915_READ(G4X_AUD_VID_DID); 320 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) 321 eldv = G4X_ELDV_DEVCL_DEVBLC; 322 else 323 eldv = G4X_ELDV_DEVCTG; 324 325 /* Invalidate ELD */ 326 tmp = I915_READ(G4X_AUD_CNTL_ST); 327 tmp &= ~eldv; 328 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 329 } 330 331 static void g4x_audio_codec_enable(struct intel_encoder *encoder, 332 const struct intel_crtc_state *crtc_state, 333 const struct drm_connector_state *conn_state) 334 { 335 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 336 struct drm_connector *connector = conn_state->connector; 337 const u8 *eld = connector->eld; 338 u32 eldv; 339 u32 tmp; 340 int len, i; 341 342 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", drm_eld_size(eld)); 343 344 tmp = I915_READ(G4X_AUD_VID_DID); 345 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) 346 eldv = G4X_ELDV_DEVCL_DEVBLC; 347 else 348 eldv = G4X_ELDV_DEVCTG; 349 350 if (intel_eld_uptodate(connector, 351 G4X_AUD_CNTL_ST, eldv, 352 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK, 353 G4X_HDMIW_HDMIEDID)) 354 return; 355 356 tmp = I915_READ(G4X_AUD_CNTL_ST); 357 tmp &= ~(eldv | G4X_ELD_ADDR_MASK); 358 len = (tmp >> 9) & 0x1f; /* ELD buffer size */ 359 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 360 361 len = min(drm_eld_size(eld) / 4, len); 362 DRM_DEBUG_DRIVER("ELD size %d\n", len); 363 for (i = 0; i < len; i++) 364 I915_WRITE(G4X_HDMIW_HDMIEDID, *((const u32 *)eld + i)); 365 366 tmp = I915_READ(G4X_AUD_CNTL_ST); 367 tmp |= eldv; 368 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 369 } 370 371 static void 372 hsw_dp_audio_config_update(struct intel_encoder *encoder, 373 const struct intel_crtc_state *crtc_state) 374 { 375 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 376 struct i915_audio_component *acomp = dev_priv->audio_component; 377 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 378 enum port port = encoder->port; 379 const struct dp_aud_n_m *nm; 380 int rate; 381 u32 tmp; 382 383 rate = acomp ? acomp->aud_sample_rate[port] : 0; 384 nm = audio_config_dp_get_n_m(crtc_state, rate); 385 if (nm) 386 DRM_DEBUG_KMS("using Maud %u, Naud %u\n", nm->m, nm->n); 387 else 388 DRM_DEBUG_KMS("using automatic Maud, Naud\n"); 389 390 tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder)); 391 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 392 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 393 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 394 tmp |= AUD_CONFIG_N_VALUE_INDEX; 395 396 if (nm) { 397 tmp &= ~AUD_CONFIG_N_MASK; 398 tmp |= AUD_CONFIG_N(nm->n); 399 tmp |= AUD_CONFIG_N_PROG_ENABLE; 400 } 401 402 I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp); 403 404 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); 405 tmp &= ~AUD_CONFIG_M_MASK; 406 tmp &= ~AUD_M_CTS_M_VALUE_INDEX; 407 tmp &= ~AUD_M_CTS_M_PROG_ENABLE; 408 409 if (nm) { 410 tmp |= nm->m; 411 tmp |= AUD_M_CTS_M_VALUE_INDEX; 412 tmp |= AUD_M_CTS_M_PROG_ENABLE; 413 } 414 415 I915_WRITE(HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 416 } 417 418 static void 419 hsw_hdmi_audio_config_update(struct intel_encoder *encoder, 420 const struct intel_crtc_state *crtc_state) 421 { 422 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 423 struct i915_audio_component *acomp = dev_priv->audio_component; 424 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 425 enum port port = encoder->port; 426 int n, rate; 427 u32 tmp; 428 429 rate = acomp ? acomp->aud_sample_rate[port] : 0; 430 431 tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder)); 432 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 433 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 434 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 435 tmp |= audio_config_hdmi_pixel_clock(crtc_state); 436 437 n = audio_config_hdmi_get_n(crtc_state, rate); 438 if (n != 0) { 439 DRM_DEBUG_KMS("using N %d\n", n); 440 441 tmp &= ~AUD_CONFIG_N_MASK; 442 tmp |= AUD_CONFIG_N(n); 443 tmp |= AUD_CONFIG_N_PROG_ENABLE; 444 } else { 445 DRM_DEBUG_KMS("using automatic N\n"); 446 } 447 448 I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp); 449 450 /* 451 * Let's disable "Enable CTS or M Prog bit" 452 * and let HW calculate the value 453 */ 454 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); 455 tmp &= ~AUD_M_CTS_M_PROG_ENABLE; 456 tmp &= ~AUD_M_CTS_M_VALUE_INDEX; 457 I915_WRITE(HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 458 } 459 460 static void 461 hsw_audio_config_update(struct intel_encoder *encoder, 462 const struct intel_crtc_state *crtc_state) 463 { 464 if (intel_crtc_has_dp_encoder(crtc_state)) 465 hsw_dp_audio_config_update(encoder, crtc_state); 466 else 467 hsw_hdmi_audio_config_update(encoder, crtc_state); 468 } 469 470 static void hsw_audio_codec_disable(struct intel_encoder *encoder, 471 const struct intel_crtc_state *old_crtc_state, 472 const struct drm_connector_state *old_conn_state) 473 { 474 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 475 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 476 u32 tmp; 477 478 DRM_DEBUG_KMS("Disable audio codec on transcoder %s\n", 479 transcoder_name(cpu_transcoder)); 480 481 mutex_lock(&dev_priv->av_mutex); 482 483 /* Disable timestamps */ 484 tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder)); 485 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 486 tmp |= AUD_CONFIG_N_PROG_ENABLE; 487 tmp &= ~AUD_CONFIG_UPPER_N_MASK; 488 tmp &= ~AUD_CONFIG_LOWER_N_MASK; 489 if (intel_crtc_has_dp_encoder(old_crtc_state)) 490 tmp |= AUD_CONFIG_N_VALUE_INDEX; 491 I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp); 492 493 /* Invalidate ELD */ 494 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 495 tmp &= ~AUDIO_ELD_VALID(cpu_transcoder); 496 tmp &= ~AUDIO_OUTPUT_ENABLE(cpu_transcoder); 497 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 498 499 mutex_unlock(&dev_priv->av_mutex); 500 } 501 502 static void hsw_audio_codec_enable(struct intel_encoder *encoder, 503 const struct intel_crtc_state *crtc_state, 504 const struct drm_connector_state *conn_state) 505 { 506 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 507 struct drm_connector *connector = conn_state->connector; 508 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 509 const u8 *eld = connector->eld; 510 u32 tmp; 511 int len, i; 512 513 DRM_DEBUG_KMS("Enable audio codec on transcoder %s, %u bytes ELD\n", 514 transcoder_name(cpu_transcoder), drm_eld_size(eld)); 515 516 mutex_lock(&dev_priv->av_mutex); 517 518 /* Enable audio presence detect, invalidate ELD */ 519 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 520 tmp |= AUDIO_OUTPUT_ENABLE(cpu_transcoder); 521 tmp &= ~AUDIO_ELD_VALID(cpu_transcoder); 522 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 523 524 /* 525 * FIXME: We're supposed to wait for vblank here, but we have vblanks 526 * disabled during the mode set. The proper fix would be to push the 527 * rest of the setup into a vblank work item, queued here, but the 528 * infrastructure is not there yet. 529 */ 530 531 /* Reset ELD write address */ 532 tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(cpu_transcoder)); 533 tmp &= ~IBX_ELD_ADDRESS_MASK; 534 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(cpu_transcoder), tmp); 535 536 /* Up to 84 bytes of hw ELD buffer */ 537 len = min(drm_eld_size(eld), 84); 538 for (i = 0; i < len / 4; i++) 539 I915_WRITE(HSW_AUD_EDID_DATA(cpu_transcoder), *((const u32 *)eld + i)); 540 541 /* ELD valid */ 542 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 543 tmp |= AUDIO_ELD_VALID(cpu_transcoder); 544 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 545 546 /* Enable timestamps */ 547 hsw_audio_config_update(encoder, crtc_state); 548 549 mutex_unlock(&dev_priv->av_mutex); 550 } 551 552 static void ilk_audio_codec_disable(struct intel_encoder *encoder, 553 const struct intel_crtc_state *old_crtc_state, 554 const struct drm_connector_state *old_conn_state) 555 { 556 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 557 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); 558 enum pipe pipe = crtc->pipe; 559 enum port port = encoder->port; 560 u32 tmp, eldv; 561 i915_reg_t aud_config, aud_cntrl_st2; 562 563 DRM_DEBUG_KMS("Disable audio codec on [ENCODER:%d:%s], pipe %c\n", 564 encoder->base.base.id, encoder->base.name, 565 pipe_name(pipe)); 566 567 if (WARN_ON(port == PORT_A)) 568 return; 569 570 if (HAS_PCH_IBX(dev_priv)) { 571 aud_config = IBX_AUD_CFG(pipe); 572 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 573 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 574 aud_config = VLV_AUD_CFG(pipe); 575 aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 576 } else { 577 aud_config = CPT_AUD_CFG(pipe); 578 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 579 } 580 581 /* Disable timestamps */ 582 tmp = I915_READ(aud_config); 583 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 584 tmp |= AUD_CONFIG_N_PROG_ENABLE; 585 tmp &= ~AUD_CONFIG_UPPER_N_MASK; 586 tmp &= ~AUD_CONFIG_LOWER_N_MASK; 587 if (intel_crtc_has_dp_encoder(old_crtc_state)) 588 tmp |= AUD_CONFIG_N_VALUE_INDEX; 589 I915_WRITE(aud_config, tmp); 590 591 eldv = IBX_ELD_VALID(port); 592 593 /* Invalidate ELD */ 594 tmp = I915_READ(aud_cntrl_st2); 595 tmp &= ~eldv; 596 I915_WRITE(aud_cntrl_st2, tmp); 597 } 598 599 static void ilk_audio_codec_enable(struct intel_encoder *encoder, 600 const struct intel_crtc_state *crtc_state, 601 const struct drm_connector_state *conn_state) 602 { 603 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 604 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 605 struct drm_connector *connector = conn_state->connector; 606 enum pipe pipe = crtc->pipe; 607 enum port port = encoder->port; 608 const u8 *eld = connector->eld; 609 u32 tmp, eldv; 610 int len, i; 611 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; 612 613 DRM_DEBUG_KMS("Enable audio codec on [ENCODER:%d:%s], pipe %c, %u bytes ELD\n", 614 encoder->base.base.id, encoder->base.name, 615 pipe_name(pipe), drm_eld_size(eld)); 616 617 if (WARN_ON(port == PORT_A)) 618 return; 619 620 /* 621 * FIXME: We're supposed to wait for vblank here, but we have vblanks 622 * disabled during the mode set. The proper fix would be to push the 623 * rest of the setup into a vblank work item, queued here, but the 624 * infrastructure is not there yet. 625 */ 626 627 if (HAS_PCH_IBX(dev_priv)) { 628 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); 629 aud_config = IBX_AUD_CFG(pipe); 630 aud_cntl_st = IBX_AUD_CNTL_ST(pipe); 631 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 632 } else if (IS_VALLEYVIEW(dev_priv) || 633 IS_CHERRYVIEW(dev_priv)) { 634 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); 635 aud_config = VLV_AUD_CFG(pipe); 636 aud_cntl_st = VLV_AUD_CNTL_ST(pipe); 637 aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 638 } else { 639 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); 640 aud_config = CPT_AUD_CFG(pipe); 641 aud_cntl_st = CPT_AUD_CNTL_ST(pipe); 642 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 643 } 644 645 eldv = IBX_ELD_VALID(port); 646 647 /* Invalidate ELD */ 648 tmp = I915_READ(aud_cntrl_st2); 649 tmp &= ~eldv; 650 I915_WRITE(aud_cntrl_st2, tmp); 651 652 /* Reset ELD write address */ 653 tmp = I915_READ(aud_cntl_st); 654 tmp &= ~IBX_ELD_ADDRESS_MASK; 655 I915_WRITE(aud_cntl_st, tmp); 656 657 /* Up to 84 bytes of hw ELD buffer */ 658 len = min(drm_eld_size(eld), 84); 659 for (i = 0; i < len / 4; i++) 660 I915_WRITE(hdmiw_hdmiedid, *((const u32 *)eld + i)); 661 662 /* ELD valid */ 663 tmp = I915_READ(aud_cntrl_st2); 664 tmp |= eldv; 665 I915_WRITE(aud_cntrl_st2, tmp); 666 667 /* Enable timestamps */ 668 tmp = I915_READ(aud_config); 669 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 670 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 671 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 672 if (intel_crtc_has_dp_encoder(crtc_state)) 673 tmp |= AUD_CONFIG_N_VALUE_INDEX; 674 else 675 tmp |= audio_config_hdmi_pixel_clock(crtc_state); 676 I915_WRITE(aud_config, tmp); 677 } 678 679 /** 680 * intel_audio_codec_enable - Enable the audio codec for HD audio 681 * @encoder: encoder on which to enable audio 682 * @crtc_state: pointer to the current crtc state. 683 * @conn_state: pointer to the current connector state. 684 * 685 * The enable sequences may only be performed after enabling the transcoder and 686 * port, and after completed link training. 687 */ 688 void intel_audio_codec_enable(struct intel_encoder *encoder, 689 const struct intel_crtc_state *crtc_state, 690 const struct drm_connector_state *conn_state) 691 { 692 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 693 struct i915_audio_component *acomp = dev_priv->audio_component; 694 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 695 struct drm_connector *connector = conn_state->connector; 696 const struct drm_display_mode *adjusted_mode = 697 &crtc_state->base.adjusted_mode; 698 enum port port = encoder->port; 699 enum pipe pipe = crtc->pipe; 700 701 /* FIXME precompute the ELD in .compute_config() */ 702 if (!connector->eld[0]) 703 DRM_DEBUG_KMS("Bogus ELD on [CONNECTOR:%d:%s]\n", 704 connector->base.id, connector->name); 705 706 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 707 connector->base.id, 708 connector->name, 709 connector->encoder->base.id, 710 connector->encoder->name); 711 712 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; 713 714 if (dev_priv->display.audio_codec_enable) 715 dev_priv->display.audio_codec_enable(encoder, 716 crtc_state, 717 conn_state); 718 719 mutex_lock(&dev_priv->av_mutex); 720 encoder->audio_connector = connector; 721 722 /* referred in audio callbacks */ 723 dev_priv->av_enc_map[pipe] = encoder; 724 mutex_unlock(&dev_priv->av_mutex); 725 726 if (acomp && acomp->base.audio_ops && 727 acomp->base.audio_ops->pin_eld_notify) { 728 /* audio drivers expect pipe = -1 to indicate Non-MST cases */ 729 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 730 pipe = -1; 731 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 732 (int) port, (int) pipe); 733 } 734 735 intel_lpe_audio_notify(dev_priv, pipe, port, connector->eld, 736 crtc_state->port_clock, 737 intel_crtc_has_dp_encoder(crtc_state)); 738 } 739 740 /** 741 * intel_audio_codec_disable - Disable the audio codec for HD audio 742 * @encoder: encoder on which to disable audio 743 * @old_crtc_state: pointer to the old crtc state. 744 * @old_conn_state: pointer to the old connector state. 745 * 746 * The disable sequences must be performed before disabling the transcoder or 747 * port. 748 */ 749 void intel_audio_codec_disable(struct intel_encoder *encoder, 750 const struct intel_crtc_state *old_crtc_state, 751 const struct drm_connector_state *old_conn_state) 752 { 753 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 754 struct i915_audio_component *acomp = dev_priv->audio_component; 755 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); 756 enum port port = encoder->port; 757 enum pipe pipe = crtc->pipe; 758 759 if (dev_priv->display.audio_codec_disable) 760 dev_priv->display.audio_codec_disable(encoder, 761 old_crtc_state, 762 old_conn_state); 763 764 mutex_lock(&dev_priv->av_mutex); 765 encoder->audio_connector = NULL; 766 dev_priv->av_enc_map[pipe] = NULL; 767 mutex_unlock(&dev_priv->av_mutex); 768 769 if (acomp && acomp->base.audio_ops && 770 acomp->base.audio_ops->pin_eld_notify) { 771 /* audio drivers expect pipe = -1 to indicate Non-MST cases */ 772 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 773 pipe = -1; 774 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 775 (int) port, (int) pipe); 776 } 777 778 intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false); 779 } 780 781 /** 782 * intel_init_audio_hooks - Set up chip specific audio hooks 783 * @dev_priv: device private 784 */ 785 void intel_init_audio_hooks(struct drm_i915_private *dev_priv) 786 { 787 if (IS_G4X(dev_priv)) { 788 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable; 789 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable; 790 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 791 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; 792 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; 793 } else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) { 794 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable; 795 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable; 796 } else if (HAS_PCH_SPLIT(dev_priv)) { 797 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; 798 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; 799 } 800 } 801 802 static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv, 803 bool enable) 804 { 805 struct drm_modeset_acquire_ctx ctx; 806 struct drm_atomic_state *state; 807 int ret; 808 809 drm_modeset_acquire_init(&ctx, 0); 810 state = drm_atomic_state_alloc(&dev_priv->drm); 811 if (WARN_ON(!state)) 812 return; 813 814 state->acquire_ctx = &ctx; 815 816 retry: 817 to_intel_atomic_state(state)->cdclk.force_min_cdclk_changed = true; 818 to_intel_atomic_state(state)->cdclk.force_min_cdclk = 819 enable ? 2 * 96000 : 0; 820 821 /* 822 * Protects dev_priv->cdclk.force_min_cdclk 823 * Need to lock this here in case we have no active pipes 824 * and thus wouldn't lock it during the commit otherwise. 825 */ 826 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 827 &ctx); 828 if (!ret) 829 ret = drm_atomic_commit(state); 830 831 if (ret == -EDEADLK) { 832 drm_atomic_state_clear(state); 833 drm_modeset_backoff(&ctx); 834 goto retry; 835 } 836 837 WARN_ON(ret); 838 839 drm_atomic_state_put(state); 840 841 drm_modeset_drop_locks(&ctx); 842 drm_modeset_acquire_fini(&ctx); 843 } 844 845 static unsigned long i915_audio_component_get_power(struct device *kdev) 846 { 847 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 848 intel_wakeref_t ret; 849 850 /* Catch potential impedance mismatches before they occur! */ 851 BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long)); 852 853 ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); 854 855 if (dev_priv->audio_power_refcount++ == 0) { 856 if (IS_TIGERLAKE(dev_priv) || IS_ICELAKE(dev_priv)) { 857 I915_WRITE(AUD_FREQ_CNTRL, dev_priv->audio_freq_cntrl); 858 DRM_DEBUG_KMS("restored AUD_FREQ_CNTRL to 0x%x\n", 859 dev_priv->audio_freq_cntrl); 860 } 861 862 /* Force CDCLK to 2*BCLK as long as we need audio powered. */ 863 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 864 glk_force_audio_cdclk(dev_priv, true); 865 866 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 867 I915_WRITE(AUD_PIN_BUF_CTL, 868 (I915_READ(AUD_PIN_BUF_CTL) | 869 AUD_PIN_BUF_ENABLE)); 870 } 871 872 return ret; 873 } 874 875 static void i915_audio_component_put_power(struct device *kdev, 876 unsigned long cookie) 877 { 878 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 879 880 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */ 881 if (--dev_priv->audio_power_refcount == 0) 882 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 883 glk_force_audio_cdclk(dev_priv, false); 884 885 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie); 886 } 887 888 static void i915_audio_component_codec_wake_override(struct device *kdev, 889 bool enable) 890 { 891 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 892 unsigned long cookie; 893 u32 tmp; 894 895 if (!IS_GEN(dev_priv, 9)) 896 return; 897 898 cookie = i915_audio_component_get_power(kdev); 899 900 /* 901 * Enable/disable generating the codec wake signal, overriding the 902 * internal logic to generate the codec wake to controller. 903 */ 904 tmp = I915_READ(HSW_AUD_CHICKENBIT); 905 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL; 906 I915_WRITE(HSW_AUD_CHICKENBIT, tmp); 907 usleep_range(1000, 1500); 908 909 if (enable) { 910 tmp = I915_READ(HSW_AUD_CHICKENBIT); 911 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL; 912 I915_WRITE(HSW_AUD_CHICKENBIT, tmp); 913 usleep_range(1000, 1500); 914 } 915 916 i915_audio_component_put_power(kdev, cookie); 917 } 918 919 /* Get CDCLK in kHz */ 920 static int i915_audio_component_get_cdclk_freq(struct device *kdev) 921 { 922 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 923 924 if (WARN_ON_ONCE(!HAS_DDI(dev_priv))) 925 return -ENODEV; 926 927 return dev_priv->cdclk.hw.cdclk; 928 } 929 930 /* 931 * get the intel_encoder according to the parameter port and pipe 932 * intel_encoder is saved by the index of pipe 933 * MST & (pipe >= 0): return the av_enc_map[pipe], 934 * when port is matched 935 * MST & (pipe < 0): this is invalid 936 * Non-MST & (pipe >= 0): only pipe = 0 (the first device entry) 937 * will get the right intel_encoder with port matched 938 * Non-MST & (pipe < 0): get the right intel_encoder with port matched 939 */ 940 static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv, 941 int port, int pipe) 942 { 943 struct intel_encoder *encoder; 944 945 /* MST */ 946 if (pipe >= 0) { 947 if (WARN_ON(pipe >= ARRAY_SIZE(dev_priv->av_enc_map))) 948 return NULL; 949 950 encoder = dev_priv->av_enc_map[pipe]; 951 /* 952 * when bootup, audio driver may not know it is 953 * MST or not. So it will poll all the port & pipe 954 * combinations 955 */ 956 if (encoder != NULL && encoder->port == port && 957 encoder->type == INTEL_OUTPUT_DP_MST) 958 return encoder; 959 } 960 961 /* Non-MST */ 962 if (pipe > 0) 963 return NULL; 964 965 for_each_pipe(dev_priv, pipe) { 966 encoder = dev_priv->av_enc_map[pipe]; 967 if (encoder == NULL) 968 continue; 969 970 if (encoder->type == INTEL_OUTPUT_DP_MST) 971 continue; 972 973 if (port == encoder->port) 974 return encoder; 975 } 976 977 return NULL; 978 } 979 980 static int i915_audio_component_sync_audio_rate(struct device *kdev, int port, 981 int pipe, int rate) 982 { 983 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 984 struct i915_audio_component *acomp = dev_priv->audio_component; 985 struct intel_encoder *encoder; 986 struct intel_crtc *crtc; 987 unsigned long cookie; 988 int err = 0; 989 990 if (!HAS_DDI(dev_priv)) 991 return 0; 992 993 cookie = i915_audio_component_get_power(kdev); 994 mutex_lock(&dev_priv->av_mutex); 995 996 /* 1. get the pipe */ 997 encoder = get_saved_enc(dev_priv, port, pipe); 998 if (!encoder || !encoder->base.crtc) { 999 DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port)); 1000 err = -ENODEV; 1001 goto unlock; 1002 } 1003 1004 crtc = to_intel_crtc(encoder->base.crtc); 1005 1006 /* port must be valid now, otherwise the pipe will be invalid */ 1007 acomp->aud_sample_rate[port] = rate; 1008 1009 hsw_audio_config_update(encoder, crtc->config); 1010 1011 unlock: 1012 mutex_unlock(&dev_priv->av_mutex); 1013 i915_audio_component_put_power(kdev, cookie); 1014 return err; 1015 } 1016 1017 static int i915_audio_component_get_eld(struct device *kdev, int port, 1018 int pipe, bool *enabled, 1019 unsigned char *buf, int max_bytes) 1020 { 1021 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1022 struct intel_encoder *intel_encoder; 1023 const u8 *eld; 1024 int ret = -EINVAL; 1025 1026 mutex_lock(&dev_priv->av_mutex); 1027 1028 intel_encoder = get_saved_enc(dev_priv, port, pipe); 1029 if (!intel_encoder) { 1030 DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port)); 1031 mutex_unlock(&dev_priv->av_mutex); 1032 return ret; 1033 } 1034 1035 ret = 0; 1036 *enabled = intel_encoder->audio_connector != NULL; 1037 if (*enabled) { 1038 eld = intel_encoder->audio_connector->eld; 1039 ret = drm_eld_size(eld); 1040 memcpy(buf, eld, min(max_bytes, ret)); 1041 } 1042 1043 mutex_unlock(&dev_priv->av_mutex); 1044 return ret; 1045 } 1046 1047 static const struct drm_audio_component_ops i915_audio_component_ops = { 1048 .owner = THIS_MODULE, 1049 .get_power = i915_audio_component_get_power, 1050 .put_power = i915_audio_component_put_power, 1051 .codec_wake_override = i915_audio_component_codec_wake_override, 1052 .get_cdclk_freq = i915_audio_component_get_cdclk_freq, 1053 .sync_audio_rate = i915_audio_component_sync_audio_rate, 1054 .get_eld = i915_audio_component_get_eld, 1055 }; 1056 1057 static int i915_audio_component_bind(struct device *i915_kdev, 1058 struct device *hda_kdev, void *data) 1059 { 1060 struct i915_audio_component *acomp = data; 1061 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); 1062 int i; 1063 1064 if (WARN_ON(acomp->base.ops || acomp->base.dev)) 1065 return -EEXIST; 1066 1067 if (WARN_ON(!device_link_add(hda_kdev, i915_kdev, DL_FLAG_STATELESS))) 1068 return -ENOMEM; 1069 1070 drm_modeset_lock_all(&dev_priv->drm); 1071 acomp->base.ops = &i915_audio_component_ops; 1072 acomp->base.dev = i915_kdev; 1073 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); 1074 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) 1075 acomp->aud_sample_rate[i] = 0; 1076 dev_priv->audio_component = acomp; 1077 drm_modeset_unlock_all(&dev_priv->drm); 1078 1079 return 0; 1080 } 1081 1082 static void i915_audio_component_unbind(struct device *i915_kdev, 1083 struct device *hda_kdev, void *data) 1084 { 1085 struct i915_audio_component *acomp = data; 1086 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); 1087 1088 drm_modeset_lock_all(&dev_priv->drm); 1089 acomp->base.ops = NULL; 1090 acomp->base.dev = NULL; 1091 dev_priv->audio_component = NULL; 1092 drm_modeset_unlock_all(&dev_priv->drm); 1093 1094 device_link_remove(hda_kdev, i915_kdev); 1095 } 1096 1097 static const struct component_ops i915_audio_component_bind_ops = { 1098 .bind = i915_audio_component_bind, 1099 .unbind = i915_audio_component_unbind, 1100 }; 1101 1102 /** 1103 * i915_audio_component_init - initialize and register the audio component 1104 * @dev_priv: i915 device instance 1105 * 1106 * This will register with the component framework a child component which 1107 * will bind dynamically to the snd_hda_intel driver's corresponding master 1108 * component when the latter is registered. During binding the child 1109 * initializes an instance of struct i915_audio_component which it receives 1110 * from the master. The master can then start to use the interface defined by 1111 * this struct. Each side can break the binding at any point by deregistering 1112 * its own component after which each side's component unbind callback is 1113 * called. 1114 * 1115 * We ignore any error during registration and continue with reduced 1116 * functionality (i.e. without HDMI audio). 1117 */ 1118 static void i915_audio_component_init(struct drm_i915_private *dev_priv) 1119 { 1120 int ret; 1121 1122 ret = component_add_typed(dev_priv->drm.dev, 1123 &i915_audio_component_bind_ops, 1124 I915_COMPONENT_AUDIO); 1125 if (ret < 0) { 1126 DRM_ERROR("failed to add audio component (%d)\n", ret); 1127 /* continue with reduced functionality */ 1128 return; 1129 } 1130 1131 if (IS_TIGERLAKE(dev_priv) || IS_ICELAKE(dev_priv)) { 1132 dev_priv->audio_freq_cntrl = I915_READ(AUD_FREQ_CNTRL); 1133 DRM_DEBUG_KMS("init value of AUD_FREQ_CNTRL of 0x%x\n", 1134 dev_priv->audio_freq_cntrl); 1135 } 1136 1137 dev_priv->audio_component_registered = true; 1138 } 1139 1140 /** 1141 * i915_audio_component_cleanup - deregister the audio component 1142 * @dev_priv: i915 device instance 1143 * 1144 * Deregisters the audio component, breaking any existing binding to the 1145 * corresponding snd_hda_intel driver's master component. 1146 */ 1147 static void i915_audio_component_cleanup(struct drm_i915_private *dev_priv) 1148 { 1149 if (!dev_priv->audio_component_registered) 1150 return; 1151 1152 component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops); 1153 dev_priv->audio_component_registered = false; 1154 } 1155 1156 /** 1157 * intel_audio_init() - Initialize the audio driver either using 1158 * component framework or using lpe audio bridge 1159 * @dev_priv: the i915 drm device private data 1160 * 1161 */ 1162 void intel_audio_init(struct drm_i915_private *dev_priv) 1163 { 1164 if (intel_lpe_audio_init(dev_priv) < 0) 1165 i915_audio_component_init(dev_priv); 1166 } 1167 1168 /** 1169 * intel_audio_deinit() - deinitialize the audio driver 1170 * @dev_priv: the i915 drm device private data 1171 * 1172 */ 1173 void intel_audio_deinit(struct drm_i915_private *dev_priv) 1174 { 1175 if ((dev_priv)->lpe_audio.platdev != NULL) 1176 intel_lpe_audio_teardown(dev_priv); 1177 else 1178 i915_audio_component_cleanup(dev_priv); 1179 } 1180