1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/component.h> 25 #include <linux/kernel.h> 26 27 #include <drm/drm_edid.h> 28 #include <drm/i915_component.h> 29 30 #include "i915_drv.h" 31 #include "intel_atomic.h" 32 #include "intel_audio.h" 33 #include "intel_cdclk.h" 34 #include "intel_crtc.h" 35 #include "intel_de.h" 36 #include "intel_display_types.h" 37 #include "intel_lpe_audio.h" 38 39 /** 40 * DOC: High Definition Audio over HDMI and Display Port 41 * 42 * The graphics and audio drivers together support High Definition Audio over 43 * HDMI and Display Port. The audio programming sequences are divided into audio 44 * codec and controller enable and disable sequences. The graphics driver 45 * handles the audio codec sequences, while the audio driver handles the audio 46 * controller sequences. 47 * 48 * The disable sequences must be performed before disabling the transcoder or 49 * port. The enable sequences may only be performed after enabling the 50 * transcoder and port, and after completed link training. Therefore the audio 51 * enable/disable sequences are part of the modeset sequence. 52 * 53 * The codec and controller sequences could be done either parallel or serial, 54 * but generally the ELDV/PD change in the codec sequence indicates to the audio 55 * driver that the controller sequence should start. Indeed, most of the 56 * co-operation between the graphics and audio drivers is handled via audio 57 * related registers. (The notable exception is the power management, not 58 * covered here.) 59 * 60 * The struct &i915_audio_component is used to interact between the graphics 61 * and audio drivers. The struct &i915_audio_component_ops @ops in it is 62 * defined in graphics driver and called in audio driver. The 63 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver. 64 */ 65 66 struct intel_audio_funcs { 67 void (*audio_codec_enable)(struct intel_encoder *encoder, 68 const struct intel_crtc_state *crtc_state, 69 const struct drm_connector_state *conn_state); 70 void (*audio_codec_disable)(struct intel_encoder *encoder, 71 const struct intel_crtc_state *old_crtc_state, 72 const struct drm_connector_state *old_conn_state); 73 }; 74 75 /* DP N/M table */ 76 #define LC_810M 810000 77 #define LC_540M 540000 78 #define LC_270M 270000 79 #define LC_162M 162000 80 81 struct dp_aud_n_m { 82 int sample_rate; 83 int clock; 84 u16 m; 85 u16 n; 86 }; 87 88 struct hdmi_aud_ncts { 89 int sample_rate; 90 int clock; 91 int n; 92 int cts; 93 }; 94 95 /* Values according to DP 1.4 Table 2-104 */ 96 static const struct dp_aud_n_m dp_aud_n_m[] = { 97 { 32000, LC_162M, 1024, 10125 }, 98 { 44100, LC_162M, 784, 5625 }, 99 { 48000, LC_162M, 512, 3375 }, 100 { 64000, LC_162M, 2048, 10125 }, 101 { 88200, LC_162M, 1568, 5625 }, 102 { 96000, LC_162M, 1024, 3375 }, 103 { 128000, LC_162M, 4096, 10125 }, 104 { 176400, LC_162M, 3136, 5625 }, 105 { 192000, LC_162M, 2048, 3375 }, 106 { 32000, LC_270M, 1024, 16875 }, 107 { 44100, LC_270M, 784, 9375 }, 108 { 48000, LC_270M, 512, 5625 }, 109 { 64000, LC_270M, 2048, 16875 }, 110 { 88200, LC_270M, 1568, 9375 }, 111 { 96000, LC_270M, 1024, 5625 }, 112 { 128000, LC_270M, 4096, 16875 }, 113 { 176400, LC_270M, 3136, 9375 }, 114 { 192000, LC_270M, 2048, 5625 }, 115 { 32000, LC_540M, 1024, 33750 }, 116 { 44100, LC_540M, 784, 18750 }, 117 { 48000, LC_540M, 512, 11250 }, 118 { 64000, LC_540M, 2048, 33750 }, 119 { 88200, LC_540M, 1568, 18750 }, 120 { 96000, LC_540M, 1024, 11250 }, 121 { 128000, LC_540M, 4096, 33750 }, 122 { 176400, LC_540M, 3136, 18750 }, 123 { 192000, LC_540M, 2048, 11250 }, 124 { 32000, LC_810M, 1024, 50625 }, 125 { 44100, LC_810M, 784, 28125 }, 126 { 48000, LC_810M, 512, 16875 }, 127 { 64000, LC_810M, 2048, 50625 }, 128 { 88200, LC_810M, 1568, 28125 }, 129 { 96000, LC_810M, 1024, 16875 }, 130 { 128000, LC_810M, 4096, 50625 }, 131 { 176400, LC_810M, 3136, 28125 }, 132 { 192000, LC_810M, 2048, 16875 }, 133 }; 134 135 static const struct dp_aud_n_m * 136 audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate) 137 { 138 int i; 139 140 for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) { 141 if (rate == dp_aud_n_m[i].sample_rate && 142 crtc_state->port_clock == dp_aud_n_m[i].clock) 143 return &dp_aud_n_m[i]; 144 } 145 146 return NULL; 147 } 148 149 static const struct { 150 int clock; 151 u32 config; 152 } hdmi_audio_clock[] = { 153 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, 154 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ 155 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, 156 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, 157 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, 158 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, 159 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, 160 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, 161 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, 162 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, 163 { 296703, AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 }, 164 { 297000, AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 }, 165 { 593407, AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 }, 166 { 594000, AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 }, 167 }; 168 169 /* HDMI N/CTS table */ 170 #define TMDS_297M 297000 171 #define TMDS_296M 296703 172 #define TMDS_594M 594000 173 #define TMDS_593M 593407 174 175 static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = { 176 { 32000, TMDS_296M, 5824, 421875 }, 177 { 32000, TMDS_297M, 3072, 222750 }, 178 { 32000, TMDS_593M, 5824, 843750 }, 179 { 32000, TMDS_594M, 3072, 445500 }, 180 { 44100, TMDS_296M, 4459, 234375 }, 181 { 44100, TMDS_297M, 4704, 247500 }, 182 { 44100, TMDS_593M, 8918, 937500 }, 183 { 44100, TMDS_594M, 9408, 990000 }, 184 { 88200, TMDS_296M, 8918, 234375 }, 185 { 88200, TMDS_297M, 9408, 247500 }, 186 { 88200, TMDS_593M, 17836, 937500 }, 187 { 88200, TMDS_594M, 18816, 990000 }, 188 { 176400, TMDS_296M, 17836, 234375 }, 189 { 176400, TMDS_297M, 18816, 247500 }, 190 { 176400, TMDS_593M, 35672, 937500 }, 191 { 176400, TMDS_594M, 37632, 990000 }, 192 { 48000, TMDS_296M, 5824, 281250 }, 193 { 48000, TMDS_297M, 5120, 247500 }, 194 { 48000, TMDS_593M, 5824, 562500 }, 195 { 48000, TMDS_594M, 6144, 594000 }, 196 { 96000, TMDS_296M, 11648, 281250 }, 197 { 96000, TMDS_297M, 10240, 247500 }, 198 { 96000, TMDS_593M, 11648, 562500 }, 199 { 96000, TMDS_594M, 12288, 594000 }, 200 { 192000, TMDS_296M, 23296, 281250 }, 201 { 192000, TMDS_297M, 20480, 247500 }, 202 { 192000, TMDS_593M, 23296, 562500 }, 203 { 192000, TMDS_594M, 24576, 594000 }, 204 }; 205 206 /* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/ 207 /* HDMI N/CTS table for 10 bit deep color(30 bpp)*/ 208 #define TMDS_371M 371250 209 #define TMDS_370M 370878 210 211 static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = { 212 { 32000, TMDS_370M, 5824, 527344 }, 213 { 32000, TMDS_371M, 6144, 556875 }, 214 { 44100, TMDS_370M, 8918, 585938 }, 215 { 44100, TMDS_371M, 4704, 309375 }, 216 { 88200, TMDS_370M, 17836, 585938 }, 217 { 88200, TMDS_371M, 9408, 309375 }, 218 { 176400, TMDS_370M, 35672, 585938 }, 219 { 176400, TMDS_371M, 18816, 309375 }, 220 { 48000, TMDS_370M, 11648, 703125 }, 221 { 48000, TMDS_371M, 5120, 309375 }, 222 { 96000, TMDS_370M, 23296, 703125 }, 223 { 96000, TMDS_371M, 10240, 309375 }, 224 { 192000, TMDS_370M, 46592, 703125 }, 225 { 192000, TMDS_371M, 20480, 309375 }, 226 }; 227 228 /* HDMI N/CTS table for 12 bit deep color(36 bpp)*/ 229 #define TMDS_445_5M 445500 230 #define TMDS_445M 445054 231 232 static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = { 233 { 32000, TMDS_445M, 5824, 632813 }, 234 { 32000, TMDS_445_5M, 4096, 445500 }, 235 { 44100, TMDS_445M, 8918, 703125 }, 236 { 44100, TMDS_445_5M, 4704, 371250 }, 237 { 88200, TMDS_445M, 17836, 703125 }, 238 { 88200, TMDS_445_5M, 9408, 371250 }, 239 { 176400, TMDS_445M, 35672, 703125 }, 240 { 176400, TMDS_445_5M, 18816, 371250 }, 241 { 48000, TMDS_445M, 5824, 421875 }, 242 { 48000, TMDS_445_5M, 5120, 371250 }, 243 { 96000, TMDS_445M, 11648, 421875 }, 244 { 96000, TMDS_445_5M, 10240, 371250 }, 245 { 192000, TMDS_445M, 23296, 421875 }, 246 { 192000, TMDS_445_5M, 20480, 371250 }, 247 }; 248 249 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ 250 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state) 251 { 252 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 253 const struct drm_display_mode *adjusted_mode = 254 &crtc_state->hw.adjusted_mode; 255 int i; 256 257 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { 258 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) 259 break; 260 } 261 262 if (DISPLAY_VER(dev_priv) < 12 && adjusted_mode->crtc_clock > 148500) 263 i = ARRAY_SIZE(hdmi_audio_clock); 264 265 if (i == ARRAY_SIZE(hdmi_audio_clock)) { 266 drm_dbg_kms(&dev_priv->drm, 267 "HDMI audio pixel clock setting for %d not found, falling back to defaults\n", 268 adjusted_mode->crtc_clock); 269 i = 1; 270 } 271 272 drm_dbg_kms(&dev_priv->drm, 273 "Configuring HDMI audio for pixel clock %d (0x%08x)\n", 274 hdmi_audio_clock[i].clock, 275 hdmi_audio_clock[i].config); 276 277 return hdmi_audio_clock[i].config; 278 } 279 280 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state, 281 int rate) 282 { 283 const struct hdmi_aud_ncts *hdmi_ncts_table; 284 int i, size; 285 286 if (crtc_state->pipe_bpp == 36) { 287 hdmi_ncts_table = hdmi_aud_ncts_36bpp; 288 size = ARRAY_SIZE(hdmi_aud_ncts_36bpp); 289 } else if (crtc_state->pipe_bpp == 30) { 290 hdmi_ncts_table = hdmi_aud_ncts_30bpp; 291 size = ARRAY_SIZE(hdmi_aud_ncts_30bpp); 292 } else { 293 hdmi_ncts_table = hdmi_aud_ncts_24bpp; 294 size = ARRAY_SIZE(hdmi_aud_ncts_24bpp); 295 } 296 297 for (i = 0; i < size; i++) { 298 if (rate == hdmi_ncts_table[i].sample_rate && 299 crtc_state->port_clock == hdmi_ncts_table[i].clock) { 300 return hdmi_ncts_table[i].n; 301 } 302 } 303 return 0; 304 } 305 306 static bool intel_eld_uptodate(struct drm_connector *connector, 307 i915_reg_t reg_eldv, u32 bits_eldv, 308 i915_reg_t reg_elda, u32 bits_elda, 309 i915_reg_t reg_edid) 310 { 311 struct drm_i915_private *dev_priv = to_i915(connector->dev); 312 const u8 *eld = connector->eld; 313 u32 tmp; 314 int i; 315 316 tmp = intel_de_read(dev_priv, reg_eldv); 317 tmp &= bits_eldv; 318 319 if (!tmp) 320 return false; 321 322 tmp = intel_de_read(dev_priv, reg_elda); 323 tmp &= ~bits_elda; 324 intel_de_write(dev_priv, reg_elda, tmp); 325 326 for (i = 0; i < drm_eld_size(eld) / 4; i++) 327 if (intel_de_read(dev_priv, reg_edid) != *((const u32 *)eld + i)) 328 return false; 329 330 return true; 331 } 332 333 static void g4x_audio_codec_disable(struct intel_encoder *encoder, 334 const struct intel_crtc_state *old_crtc_state, 335 const struct drm_connector_state *old_conn_state) 336 { 337 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 338 u32 eldv, tmp; 339 340 drm_dbg_kms(&dev_priv->drm, "Disable audio codec\n"); 341 342 tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID); 343 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) 344 eldv = G4X_ELDV_DEVCL_DEVBLC; 345 else 346 eldv = G4X_ELDV_DEVCTG; 347 348 /* Invalidate ELD */ 349 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST); 350 tmp &= ~eldv; 351 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp); 352 } 353 354 static void g4x_audio_codec_enable(struct intel_encoder *encoder, 355 const struct intel_crtc_state *crtc_state, 356 const struct drm_connector_state *conn_state) 357 { 358 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 359 struct drm_connector *connector = conn_state->connector; 360 const u8 *eld = connector->eld; 361 u32 eldv; 362 u32 tmp; 363 int len, i; 364 365 drm_dbg_kms(&dev_priv->drm, "Enable audio codec, %u bytes ELD\n", 366 drm_eld_size(eld)); 367 368 tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID); 369 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) 370 eldv = G4X_ELDV_DEVCL_DEVBLC; 371 else 372 eldv = G4X_ELDV_DEVCTG; 373 374 if (intel_eld_uptodate(connector, 375 G4X_AUD_CNTL_ST, eldv, 376 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK, 377 G4X_HDMIW_HDMIEDID)) 378 return; 379 380 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST); 381 tmp &= ~(eldv | G4X_ELD_ADDR_MASK); 382 len = (tmp >> 9) & 0x1f; /* ELD buffer size */ 383 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp); 384 385 len = min(drm_eld_size(eld) / 4, len); 386 drm_dbg(&dev_priv->drm, "ELD size %d\n", len); 387 for (i = 0; i < len; i++) 388 intel_de_write(dev_priv, G4X_HDMIW_HDMIEDID, 389 *((const u32 *)eld + i)); 390 391 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST); 392 tmp |= eldv; 393 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp); 394 } 395 396 static void 397 hsw_dp_audio_config_update(struct intel_encoder *encoder, 398 const struct intel_crtc_state *crtc_state) 399 { 400 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 401 struct i915_audio_component *acomp = dev_priv->audio.component; 402 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 403 enum port port = encoder->port; 404 const struct dp_aud_n_m *nm; 405 int rate; 406 u32 tmp; 407 408 rate = acomp ? acomp->aud_sample_rate[port] : 0; 409 nm = audio_config_dp_get_n_m(crtc_state, rate); 410 if (nm) 411 drm_dbg_kms(&dev_priv->drm, "using Maud %u, Naud %u\n", nm->m, 412 nm->n); 413 else 414 drm_dbg_kms(&dev_priv->drm, "using automatic Maud, Naud\n"); 415 416 tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder)); 417 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 418 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 419 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 420 tmp |= AUD_CONFIG_N_VALUE_INDEX; 421 422 if (nm) { 423 tmp &= ~AUD_CONFIG_N_MASK; 424 tmp |= AUD_CONFIG_N(nm->n); 425 tmp |= AUD_CONFIG_N_PROG_ENABLE; 426 } 427 428 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp); 429 430 tmp = intel_de_read(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); 431 tmp &= ~AUD_CONFIG_M_MASK; 432 tmp &= ~AUD_M_CTS_M_VALUE_INDEX; 433 tmp &= ~AUD_M_CTS_M_PROG_ENABLE; 434 435 if (nm) { 436 tmp |= nm->m; 437 tmp |= AUD_M_CTS_M_VALUE_INDEX; 438 tmp |= AUD_M_CTS_M_PROG_ENABLE; 439 } 440 441 intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 442 } 443 444 static void 445 hsw_hdmi_audio_config_update(struct intel_encoder *encoder, 446 const struct intel_crtc_state *crtc_state) 447 { 448 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 449 struct i915_audio_component *acomp = dev_priv->audio.component; 450 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 451 enum port port = encoder->port; 452 int n, rate; 453 u32 tmp; 454 455 rate = acomp ? acomp->aud_sample_rate[port] : 0; 456 457 tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder)); 458 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 459 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 460 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 461 tmp |= audio_config_hdmi_pixel_clock(crtc_state); 462 463 n = audio_config_hdmi_get_n(crtc_state, rate); 464 if (n != 0) { 465 drm_dbg_kms(&dev_priv->drm, "using N %d\n", n); 466 467 tmp &= ~AUD_CONFIG_N_MASK; 468 tmp |= AUD_CONFIG_N(n); 469 tmp |= AUD_CONFIG_N_PROG_ENABLE; 470 } else { 471 drm_dbg_kms(&dev_priv->drm, "using automatic N\n"); 472 } 473 474 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp); 475 476 /* 477 * Let's disable "Enable CTS or M Prog bit" 478 * and let HW calculate the value 479 */ 480 tmp = intel_de_read(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); 481 tmp &= ~AUD_M_CTS_M_PROG_ENABLE; 482 tmp &= ~AUD_M_CTS_M_VALUE_INDEX; 483 intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 484 } 485 486 static void 487 hsw_audio_config_update(struct intel_encoder *encoder, 488 const struct intel_crtc_state *crtc_state) 489 { 490 if (intel_crtc_has_dp_encoder(crtc_state)) 491 hsw_dp_audio_config_update(encoder, crtc_state); 492 else 493 hsw_hdmi_audio_config_update(encoder, crtc_state); 494 } 495 496 static void hsw_audio_codec_disable(struct intel_encoder *encoder, 497 const struct intel_crtc_state *old_crtc_state, 498 const struct drm_connector_state *old_conn_state) 499 { 500 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 501 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 502 u32 tmp; 503 504 drm_dbg_kms(&dev_priv->drm, "Disable audio codec on transcoder %s\n", 505 transcoder_name(cpu_transcoder)); 506 507 mutex_lock(&dev_priv->audio.mutex); 508 509 /* Disable timestamps */ 510 tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder)); 511 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 512 tmp |= AUD_CONFIG_N_PROG_ENABLE; 513 tmp &= ~AUD_CONFIG_UPPER_N_MASK; 514 tmp &= ~AUD_CONFIG_LOWER_N_MASK; 515 if (intel_crtc_has_dp_encoder(old_crtc_state)) 516 tmp |= AUD_CONFIG_N_VALUE_INDEX; 517 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp); 518 519 /* Invalidate ELD */ 520 tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD); 521 tmp &= ~AUDIO_ELD_VALID(cpu_transcoder); 522 tmp &= ~AUDIO_OUTPUT_ENABLE(cpu_transcoder); 523 intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp); 524 525 mutex_unlock(&dev_priv->audio.mutex); 526 } 527 528 static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, 529 const struct intel_crtc_state *crtc_state) 530 { 531 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 532 unsigned int link_clks_available, link_clks_required; 533 unsigned int tu_data, tu_line, link_clks_active; 534 unsigned int h_active, h_total, hblank_delta, pixel_clk; 535 unsigned int fec_coeff, cdclk, vdsc_bpp; 536 unsigned int link_clk, lanes; 537 unsigned int hblank_rise; 538 539 h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay; 540 h_total = crtc_state->hw.adjusted_mode.crtc_htotal; 541 pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock; 542 vdsc_bpp = crtc_state->dsc.compressed_bpp; 543 cdclk = i915->cdclk.hw.cdclk; 544 /* fec= 0.972261, using rounding multiplier of 1000000 */ 545 fec_coeff = 972261; 546 link_clk = crtc_state->port_clock; 547 lanes = crtc_state->lane_count; 548 549 drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :" 550 "lanes = %u vdsc_bpp = %u cdclk = %u\n", 551 h_active, link_clk, lanes, vdsc_bpp, cdclk); 552 553 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk)) 554 return 0; 555 556 link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28; 557 link_clks_required = DIV_ROUND_UP(192000 * h_total, 1000 * pixel_clk) * (48 / lanes + 2); 558 559 if (link_clks_available > link_clks_required) 560 hblank_delta = 32; 561 else 562 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), 563 mul_u32_u32(link_clk, cdclk)); 564 565 tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bpp * 8, 1000000), 566 mul_u32_u32(link_clk * lanes, fec_coeff)); 567 tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff), 568 mul_u32_u32(64 * pixel_clk, 1000000)); 569 link_clks_active = (tu_line - 1) * 64 + tu_data; 570 571 hblank_rise = (link_clks_active + 6 * DIV_ROUND_UP(link_clks_active, 250) + 4) * pixel_clk / link_clk; 572 573 return h_active - hblank_rise + hblank_delta; 574 } 575 576 static unsigned int calc_samples_room(const struct intel_crtc_state *crtc_state) 577 { 578 unsigned int h_active, h_total, pixel_clk; 579 unsigned int link_clk, lanes; 580 581 h_active = crtc_state->hw.adjusted_mode.hdisplay; 582 h_total = crtc_state->hw.adjusted_mode.htotal; 583 pixel_clk = crtc_state->hw.adjusted_mode.clock; 584 link_clk = crtc_state->port_clock; 585 lanes = crtc_state->lane_count; 586 587 return ((h_total - h_active) * link_clk - 12 * pixel_clk) / 588 (pixel_clk * (48 / lanes + 2)); 589 } 590 591 static void enable_audio_dsc_wa(struct intel_encoder *encoder, 592 const struct intel_crtc_state *crtc_state) 593 { 594 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 595 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 596 enum pipe pipe = crtc->pipe; 597 unsigned int hblank_early_prog, samples_room; 598 unsigned int val; 599 600 if (DISPLAY_VER(i915) < 11) 601 return; 602 603 val = intel_de_read(i915, AUD_CONFIG_BE); 604 605 if (DISPLAY_VER(i915) == 11) 606 val |= HBLANK_EARLY_ENABLE_ICL(pipe); 607 else if (DISPLAY_VER(i915) >= 12) 608 val |= HBLANK_EARLY_ENABLE_TGL(pipe); 609 610 if (crtc_state->dsc.compression_enable && 611 crtc_state->hw.adjusted_mode.hdisplay >= 3840 && 612 crtc_state->hw.adjusted_mode.vdisplay >= 2160) { 613 /* Get hblank early enable value required */ 614 val &= ~HBLANK_START_COUNT_MASK(pipe); 615 hblank_early_prog = calc_hblank_early_prog(encoder, crtc_state); 616 if (hblank_early_prog < 32) 617 val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_32); 618 else if (hblank_early_prog < 64) 619 val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_64); 620 else if (hblank_early_prog < 96) 621 val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_96); 622 else 623 val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_128); 624 625 /* Get samples room value required */ 626 val &= ~NUMBER_SAMPLES_PER_LINE_MASK(pipe); 627 samples_room = calc_samples_room(crtc_state); 628 if (samples_room < 3) 629 val |= NUMBER_SAMPLES_PER_LINE(pipe, samples_room); 630 else /* Program 0 i.e "All Samples available in buffer" */ 631 val |= NUMBER_SAMPLES_PER_LINE(pipe, 0x0); 632 } 633 634 intel_de_write(i915, AUD_CONFIG_BE, val); 635 } 636 637 #undef ROUNDING_FACTOR 638 639 static void hsw_audio_codec_enable(struct intel_encoder *encoder, 640 const struct intel_crtc_state *crtc_state, 641 const struct drm_connector_state *conn_state) 642 { 643 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 644 struct drm_connector *connector = conn_state->connector; 645 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 646 const u8 *eld = connector->eld; 647 u32 tmp; 648 int len, i; 649 650 drm_dbg_kms(&dev_priv->drm, 651 "Enable audio codec on transcoder %s, %u bytes ELD\n", 652 transcoder_name(cpu_transcoder), drm_eld_size(eld)); 653 654 mutex_lock(&dev_priv->audio.mutex); 655 656 /* Enable Audio WA for 4k DSC usecases */ 657 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP)) 658 enable_audio_dsc_wa(encoder, crtc_state); 659 660 /* Enable audio presence detect, invalidate ELD */ 661 tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD); 662 tmp |= AUDIO_OUTPUT_ENABLE(cpu_transcoder); 663 tmp &= ~AUDIO_ELD_VALID(cpu_transcoder); 664 intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp); 665 666 /* 667 * FIXME: We're supposed to wait for vblank here, but we have vblanks 668 * disabled during the mode set. The proper fix would be to push the 669 * rest of the setup into a vblank work item, queued here, but the 670 * infrastructure is not there yet. 671 */ 672 673 /* Reset ELD write address */ 674 tmp = intel_de_read(dev_priv, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder)); 675 tmp &= ~IBX_ELD_ADDRESS_MASK; 676 intel_de_write(dev_priv, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder), tmp); 677 678 /* Up to 84 bytes of hw ELD buffer */ 679 len = min(drm_eld_size(eld), 84); 680 for (i = 0; i < len / 4; i++) 681 intel_de_write(dev_priv, HSW_AUD_EDID_DATA(cpu_transcoder), 682 *((const u32 *)eld + i)); 683 684 /* ELD valid */ 685 tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD); 686 tmp |= AUDIO_ELD_VALID(cpu_transcoder); 687 intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp); 688 689 /* Enable timestamps */ 690 hsw_audio_config_update(encoder, crtc_state); 691 692 mutex_unlock(&dev_priv->audio.mutex); 693 } 694 695 static void ilk_audio_codec_disable(struct intel_encoder *encoder, 696 const struct intel_crtc_state *old_crtc_state, 697 const struct drm_connector_state *old_conn_state) 698 { 699 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 700 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 701 enum pipe pipe = crtc->pipe; 702 enum port port = encoder->port; 703 u32 tmp, eldv; 704 i915_reg_t aud_config, aud_cntrl_st2; 705 706 drm_dbg_kms(&dev_priv->drm, 707 "Disable audio codec on [ENCODER:%d:%s], pipe %c\n", 708 encoder->base.base.id, encoder->base.name, 709 pipe_name(pipe)); 710 711 if (drm_WARN_ON(&dev_priv->drm, port == PORT_A)) 712 return; 713 714 if (HAS_PCH_IBX(dev_priv)) { 715 aud_config = IBX_AUD_CFG(pipe); 716 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 717 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 718 aud_config = VLV_AUD_CFG(pipe); 719 aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 720 } else { 721 aud_config = CPT_AUD_CFG(pipe); 722 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 723 } 724 725 /* Disable timestamps */ 726 tmp = intel_de_read(dev_priv, aud_config); 727 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 728 tmp |= AUD_CONFIG_N_PROG_ENABLE; 729 tmp &= ~AUD_CONFIG_UPPER_N_MASK; 730 tmp &= ~AUD_CONFIG_LOWER_N_MASK; 731 if (intel_crtc_has_dp_encoder(old_crtc_state)) 732 tmp |= AUD_CONFIG_N_VALUE_INDEX; 733 intel_de_write(dev_priv, aud_config, tmp); 734 735 eldv = IBX_ELD_VALID(port); 736 737 /* Invalidate ELD */ 738 tmp = intel_de_read(dev_priv, aud_cntrl_st2); 739 tmp &= ~eldv; 740 intel_de_write(dev_priv, aud_cntrl_st2, tmp); 741 } 742 743 static void ilk_audio_codec_enable(struct intel_encoder *encoder, 744 const struct intel_crtc_state *crtc_state, 745 const struct drm_connector_state *conn_state) 746 { 747 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 748 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 749 struct drm_connector *connector = conn_state->connector; 750 enum pipe pipe = crtc->pipe; 751 enum port port = encoder->port; 752 const u8 *eld = connector->eld; 753 u32 tmp, eldv; 754 int len, i; 755 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; 756 757 drm_dbg_kms(&dev_priv->drm, 758 "Enable audio codec on [ENCODER:%d:%s], pipe %c, %u bytes ELD\n", 759 encoder->base.base.id, encoder->base.name, 760 pipe_name(pipe), drm_eld_size(eld)); 761 762 if (drm_WARN_ON(&dev_priv->drm, port == PORT_A)) 763 return; 764 765 /* 766 * FIXME: We're supposed to wait for vblank here, but we have vblanks 767 * disabled during the mode set. The proper fix would be to push the 768 * rest of the setup into a vblank work item, queued here, but the 769 * infrastructure is not there yet. 770 */ 771 772 if (HAS_PCH_IBX(dev_priv)) { 773 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); 774 aud_config = IBX_AUD_CFG(pipe); 775 aud_cntl_st = IBX_AUD_CNTL_ST(pipe); 776 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 777 } else if (IS_VALLEYVIEW(dev_priv) || 778 IS_CHERRYVIEW(dev_priv)) { 779 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); 780 aud_config = VLV_AUD_CFG(pipe); 781 aud_cntl_st = VLV_AUD_CNTL_ST(pipe); 782 aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 783 } else { 784 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); 785 aud_config = CPT_AUD_CFG(pipe); 786 aud_cntl_st = CPT_AUD_CNTL_ST(pipe); 787 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 788 } 789 790 eldv = IBX_ELD_VALID(port); 791 792 /* Invalidate ELD */ 793 tmp = intel_de_read(dev_priv, aud_cntrl_st2); 794 tmp &= ~eldv; 795 intel_de_write(dev_priv, aud_cntrl_st2, tmp); 796 797 /* Reset ELD write address */ 798 tmp = intel_de_read(dev_priv, aud_cntl_st); 799 tmp &= ~IBX_ELD_ADDRESS_MASK; 800 intel_de_write(dev_priv, aud_cntl_st, tmp); 801 802 /* Up to 84 bytes of hw ELD buffer */ 803 len = min(drm_eld_size(eld), 84); 804 for (i = 0; i < len / 4; i++) 805 intel_de_write(dev_priv, hdmiw_hdmiedid, 806 *((const u32 *)eld + i)); 807 808 /* ELD valid */ 809 tmp = intel_de_read(dev_priv, aud_cntrl_st2); 810 tmp |= eldv; 811 intel_de_write(dev_priv, aud_cntrl_st2, tmp); 812 813 /* Enable timestamps */ 814 tmp = intel_de_read(dev_priv, aud_config); 815 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 816 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 817 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 818 if (intel_crtc_has_dp_encoder(crtc_state)) 819 tmp |= AUD_CONFIG_N_VALUE_INDEX; 820 else 821 tmp |= audio_config_hdmi_pixel_clock(crtc_state); 822 intel_de_write(dev_priv, aud_config, tmp); 823 } 824 825 /** 826 * intel_audio_codec_enable - Enable the audio codec for HD audio 827 * @encoder: encoder on which to enable audio 828 * @crtc_state: pointer to the current crtc state. 829 * @conn_state: pointer to the current connector state. 830 * 831 * The enable sequences may only be performed after enabling the transcoder and 832 * port, and after completed link training. 833 */ 834 void intel_audio_codec_enable(struct intel_encoder *encoder, 835 const struct intel_crtc_state *crtc_state, 836 const struct drm_connector_state *conn_state) 837 { 838 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 839 struct i915_audio_component *acomp = dev_priv->audio.component; 840 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 841 struct drm_connector *connector = conn_state->connector; 842 const struct drm_display_mode *adjusted_mode = 843 &crtc_state->hw.adjusted_mode; 844 enum port port = encoder->port; 845 enum pipe pipe = crtc->pipe; 846 847 /* FIXME precompute the ELD in .compute_config() */ 848 if (!connector->eld[0]) 849 drm_dbg_kms(&dev_priv->drm, 850 "Bogus ELD on [CONNECTOR:%d:%s]\n", 851 connector->base.id, connector->name); 852 853 drm_dbg(&dev_priv->drm, "ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 854 connector->base.id, 855 connector->name, 856 encoder->base.base.id, 857 encoder->base.name); 858 859 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; 860 861 if (dev_priv->audio.funcs) 862 dev_priv->audio.funcs->audio_codec_enable(encoder, 863 crtc_state, 864 conn_state); 865 866 mutex_lock(&dev_priv->audio.mutex); 867 encoder->audio_connector = connector; 868 869 /* referred in audio callbacks */ 870 dev_priv->audio.encoder_map[pipe] = encoder; 871 mutex_unlock(&dev_priv->audio.mutex); 872 873 if (acomp && acomp->base.audio_ops && 874 acomp->base.audio_ops->pin_eld_notify) { 875 /* audio drivers expect pipe = -1 to indicate Non-MST cases */ 876 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 877 pipe = -1; 878 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 879 (int) port, (int) pipe); 880 } 881 882 intel_lpe_audio_notify(dev_priv, pipe, port, connector->eld, 883 crtc_state->port_clock, 884 intel_crtc_has_dp_encoder(crtc_state)); 885 } 886 887 /** 888 * intel_audio_codec_disable - Disable the audio codec for HD audio 889 * @encoder: encoder on which to disable audio 890 * @old_crtc_state: pointer to the old crtc state. 891 * @old_conn_state: pointer to the old connector state. 892 * 893 * The disable sequences must be performed before disabling the transcoder or 894 * port. 895 */ 896 void intel_audio_codec_disable(struct intel_encoder *encoder, 897 const struct intel_crtc_state *old_crtc_state, 898 const struct drm_connector_state *old_conn_state) 899 { 900 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 901 struct i915_audio_component *acomp = dev_priv->audio.component; 902 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 903 enum port port = encoder->port; 904 enum pipe pipe = crtc->pipe; 905 906 if (dev_priv->audio.funcs) 907 dev_priv->audio.funcs->audio_codec_disable(encoder, 908 old_crtc_state, 909 old_conn_state); 910 911 mutex_lock(&dev_priv->audio.mutex); 912 encoder->audio_connector = NULL; 913 dev_priv->audio.encoder_map[pipe] = NULL; 914 mutex_unlock(&dev_priv->audio.mutex); 915 916 if (acomp && acomp->base.audio_ops && 917 acomp->base.audio_ops->pin_eld_notify) { 918 /* audio drivers expect pipe = -1 to indicate Non-MST cases */ 919 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 920 pipe = -1; 921 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 922 (int) port, (int) pipe); 923 } 924 925 intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false); 926 } 927 928 static const struct intel_audio_funcs g4x_audio_funcs = { 929 .audio_codec_enable = g4x_audio_codec_enable, 930 .audio_codec_disable = g4x_audio_codec_disable, 931 }; 932 933 static const struct intel_audio_funcs ilk_audio_funcs = { 934 .audio_codec_enable = ilk_audio_codec_enable, 935 .audio_codec_disable = ilk_audio_codec_disable, 936 }; 937 938 static const struct intel_audio_funcs hsw_audio_funcs = { 939 .audio_codec_enable = hsw_audio_codec_enable, 940 .audio_codec_disable = hsw_audio_codec_disable, 941 }; 942 943 /** 944 * intel_audio_hooks_init - Set up chip specific audio hooks 945 * @dev_priv: device private 946 */ 947 void intel_audio_hooks_init(struct drm_i915_private *dev_priv) 948 { 949 if (IS_G4X(dev_priv)) { 950 dev_priv->audio.funcs = &g4x_audio_funcs; 951 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 952 dev_priv->audio.funcs = &ilk_audio_funcs; 953 } else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) { 954 dev_priv->audio.funcs = &hsw_audio_funcs; 955 } else if (HAS_PCH_SPLIT(dev_priv)) { 956 dev_priv->audio.funcs = &ilk_audio_funcs; 957 } 958 } 959 960 struct aud_ts_cdclk_m_n { 961 u8 m; 962 u16 n; 963 }; 964 965 void intel_audio_cdclk_change_pre(struct drm_i915_private *i915) 966 { 967 if (DISPLAY_VER(i915) >= 13) 968 intel_de_rmw(i915, AUD_TS_CDCLK_M, AUD_TS_CDCLK_M_EN, 0); 969 } 970 971 static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts) 972 { 973 if (refclk == 24000) 974 aud_ts->m = 12; 975 else 976 aud_ts->m = 15; 977 978 aud_ts->n = cdclk * aud_ts->m / 24000; 979 } 980 981 void intel_audio_cdclk_change_post(struct drm_i915_private *i915) 982 { 983 struct aud_ts_cdclk_m_n aud_ts; 984 985 if (DISPLAY_VER(i915) >= 13) { 986 get_aud_ts_cdclk_m_n(i915->cdclk.hw.ref, i915->cdclk.hw.cdclk, &aud_ts); 987 988 intel_de_write(i915, AUD_TS_CDCLK_N, aud_ts.n); 989 intel_de_write(i915, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN); 990 drm_dbg_kms(&i915->drm, "aud_ts_cdclk set to M=%u, N=%u\n", aud_ts.m, aud_ts.n); 991 } 992 } 993 994 static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state, 995 struct intel_crtc *crtc, 996 bool enable) 997 { 998 struct intel_cdclk_state *cdclk_state; 999 int ret; 1000 1001 /* need to hold at least one crtc lock for the global state */ 1002 ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx); 1003 if (ret) 1004 return ret; 1005 1006 cdclk_state = intel_atomic_get_cdclk_state(state); 1007 if (IS_ERR(cdclk_state)) 1008 return PTR_ERR(cdclk_state); 1009 1010 cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0; 1011 1012 return drm_atomic_commit(&state->base); 1013 } 1014 1015 static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv, 1016 bool enable) 1017 { 1018 struct drm_modeset_acquire_ctx ctx; 1019 struct drm_atomic_state *state; 1020 struct intel_crtc *crtc; 1021 int ret; 1022 1023 crtc = intel_first_crtc(dev_priv); 1024 if (!crtc) 1025 return; 1026 1027 drm_modeset_acquire_init(&ctx, 0); 1028 state = drm_atomic_state_alloc(&dev_priv->drm); 1029 if (drm_WARN_ON(&dev_priv->drm, !state)) 1030 return; 1031 1032 state->acquire_ctx = &ctx; 1033 1034 retry: 1035 ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), crtc, 1036 enable); 1037 if (ret == -EDEADLK) { 1038 drm_atomic_state_clear(state); 1039 drm_modeset_backoff(&ctx); 1040 goto retry; 1041 } 1042 1043 drm_WARN_ON(&dev_priv->drm, ret); 1044 1045 drm_atomic_state_put(state); 1046 1047 drm_modeset_drop_locks(&ctx); 1048 drm_modeset_acquire_fini(&ctx); 1049 } 1050 1051 static unsigned long i915_audio_component_get_power(struct device *kdev) 1052 { 1053 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1054 intel_wakeref_t ret; 1055 1056 /* Catch potential impedance mismatches before they occur! */ 1057 BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long)); 1058 1059 ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO_PLAYBACK); 1060 1061 if (dev_priv->audio.power_refcount++ == 0) { 1062 if (DISPLAY_VER(dev_priv) >= 9) { 1063 intel_de_write(dev_priv, AUD_FREQ_CNTRL, 1064 dev_priv->audio.freq_cntrl); 1065 drm_dbg_kms(&dev_priv->drm, 1066 "restored AUD_FREQ_CNTRL to 0x%x\n", 1067 dev_priv->audio.freq_cntrl); 1068 } 1069 1070 /* Force CDCLK to 2*BCLK as long as we need audio powered. */ 1071 if (IS_GEMINILAKE(dev_priv)) 1072 glk_force_audio_cdclk(dev_priv, true); 1073 1074 if (DISPLAY_VER(dev_priv) >= 10) 1075 intel_de_write(dev_priv, AUD_PIN_BUF_CTL, 1076 (intel_de_read(dev_priv, AUD_PIN_BUF_CTL) | AUD_PIN_BUF_ENABLE)); 1077 } 1078 1079 return ret; 1080 } 1081 1082 static void i915_audio_component_put_power(struct device *kdev, 1083 unsigned long cookie) 1084 { 1085 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1086 1087 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */ 1088 if (--dev_priv->audio.power_refcount == 0) 1089 if (IS_GEMINILAKE(dev_priv)) 1090 glk_force_audio_cdclk(dev_priv, false); 1091 1092 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO_PLAYBACK, cookie); 1093 } 1094 1095 static void i915_audio_component_codec_wake_override(struct device *kdev, 1096 bool enable) 1097 { 1098 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1099 unsigned long cookie; 1100 u32 tmp; 1101 1102 if (DISPLAY_VER(dev_priv) < 9) 1103 return; 1104 1105 cookie = i915_audio_component_get_power(kdev); 1106 1107 /* 1108 * Enable/disable generating the codec wake signal, overriding the 1109 * internal logic to generate the codec wake to controller. 1110 */ 1111 tmp = intel_de_read(dev_priv, HSW_AUD_CHICKENBIT); 1112 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL; 1113 intel_de_write(dev_priv, HSW_AUD_CHICKENBIT, tmp); 1114 usleep_range(1000, 1500); 1115 1116 if (enable) { 1117 tmp = intel_de_read(dev_priv, HSW_AUD_CHICKENBIT); 1118 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL; 1119 intel_de_write(dev_priv, HSW_AUD_CHICKENBIT, tmp); 1120 usleep_range(1000, 1500); 1121 } 1122 1123 i915_audio_component_put_power(kdev, cookie); 1124 } 1125 1126 /* Get CDCLK in kHz */ 1127 static int i915_audio_component_get_cdclk_freq(struct device *kdev) 1128 { 1129 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1130 1131 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DDI(dev_priv))) 1132 return -ENODEV; 1133 1134 return dev_priv->cdclk.hw.cdclk; 1135 } 1136 1137 /* 1138 * get the intel_encoder according to the parameter port and pipe 1139 * intel_encoder is saved by the index of pipe 1140 * MST & (pipe >= 0): return the audio.encoder_map[pipe], 1141 * when port is matched 1142 * MST & (pipe < 0): this is invalid 1143 * Non-MST & (pipe >= 0): only pipe = 0 (the first device entry) 1144 * will get the right intel_encoder with port matched 1145 * Non-MST & (pipe < 0): get the right intel_encoder with port matched 1146 */ 1147 static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv, 1148 int port, int pipe) 1149 { 1150 struct intel_encoder *encoder; 1151 1152 /* MST */ 1153 if (pipe >= 0) { 1154 if (drm_WARN_ON(&dev_priv->drm, 1155 pipe >= ARRAY_SIZE(dev_priv->audio.encoder_map))) 1156 return NULL; 1157 1158 encoder = dev_priv->audio.encoder_map[pipe]; 1159 /* 1160 * when bootup, audio driver may not know it is 1161 * MST or not. So it will poll all the port & pipe 1162 * combinations 1163 */ 1164 if (encoder != NULL && encoder->port == port && 1165 encoder->type == INTEL_OUTPUT_DP_MST) 1166 return encoder; 1167 } 1168 1169 /* Non-MST */ 1170 if (pipe > 0) 1171 return NULL; 1172 1173 for_each_pipe(dev_priv, pipe) { 1174 encoder = dev_priv->audio.encoder_map[pipe]; 1175 if (encoder == NULL) 1176 continue; 1177 1178 if (encoder->type == INTEL_OUTPUT_DP_MST) 1179 continue; 1180 1181 if (port == encoder->port) 1182 return encoder; 1183 } 1184 1185 return NULL; 1186 } 1187 1188 static int i915_audio_component_sync_audio_rate(struct device *kdev, int port, 1189 int pipe, int rate) 1190 { 1191 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1192 struct i915_audio_component *acomp = dev_priv->audio.component; 1193 struct intel_encoder *encoder; 1194 struct intel_crtc *crtc; 1195 unsigned long cookie; 1196 int err = 0; 1197 1198 if (!HAS_DDI(dev_priv)) 1199 return 0; 1200 1201 cookie = i915_audio_component_get_power(kdev); 1202 mutex_lock(&dev_priv->audio.mutex); 1203 1204 /* 1. get the pipe */ 1205 encoder = get_saved_enc(dev_priv, port, pipe); 1206 if (!encoder || !encoder->base.crtc) { 1207 drm_dbg_kms(&dev_priv->drm, "Not valid for port %c\n", 1208 port_name(port)); 1209 err = -ENODEV; 1210 goto unlock; 1211 } 1212 1213 crtc = to_intel_crtc(encoder->base.crtc); 1214 1215 /* port must be valid now, otherwise the pipe will be invalid */ 1216 acomp->aud_sample_rate[port] = rate; 1217 1218 hsw_audio_config_update(encoder, crtc->config); 1219 1220 unlock: 1221 mutex_unlock(&dev_priv->audio.mutex); 1222 i915_audio_component_put_power(kdev, cookie); 1223 return err; 1224 } 1225 1226 static int i915_audio_component_get_eld(struct device *kdev, int port, 1227 int pipe, bool *enabled, 1228 unsigned char *buf, int max_bytes) 1229 { 1230 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1231 struct intel_encoder *intel_encoder; 1232 const u8 *eld; 1233 int ret = -EINVAL; 1234 1235 mutex_lock(&dev_priv->audio.mutex); 1236 1237 intel_encoder = get_saved_enc(dev_priv, port, pipe); 1238 if (!intel_encoder) { 1239 drm_dbg_kms(&dev_priv->drm, "Not valid for port %c\n", 1240 port_name(port)); 1241 mutex_unlock(&dev_priv->audio.mutex); 1242 return ret; 1243 } 1244 1245 ret = 0; 1246 *enabled = intel_encoder->audio_connector != NULL; 1247 if (*enabled) { 1248 eld = intel_encoder->audio_connector->eld; 1249 ret = drm_eld_size(eld); 1250 memcpy(buf, eld, min(max_bytes, ret)); 1251 } 1252 1253 mutex_unlock(&dev_priv->audio.mutex); 1254 return ret; 1255 } 1256 1257 static const struct drm_audio_component_ops i915_audio_component_ops = { 1258 .owner = THIS_MODULE, 1259 .get_power = i915_audio_component_get_power, 1260 .put_power = i915_audio_component_put_power, 1261 .codec_wake_override = i915_audio_component_codec_wake_override, 1262 .get_cdclk_freq = i915_audio_component_get_cdclk_freq, 1263 .sync_audio_rate = i915_audio_component_sync_audio_rate, 1264 .get_eld = i915_audio_component_get_eld, 1265 }; 1266 1267 static int i915_audio_component_bind(struct device *i915_kdev, 1268 struct device *hda_kdev, void *data) 1269 { 1270 struct i915_audio_component *acomp = data; 1271 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); 1272 int i; 1273 1274 if (drm_WARN_ON(&dev_priv->drm, acomp->base.ops || acomp->base.dev)) 1275 return -EEXIST; 1276 1277 if (drm_WARN_ON(&dev_priv->drm, 1278 !device_link_add(hda_kdev, i915_kdev, 1279 DL_FLAG_STATELESS))) 1280 return -ENOMEM; 1281 1282 drm_modeset_lock_all(&dev_priv->drm); 1283 acomp->base.ops = &i915_audio_component_ops; 1284 acomp->base.dev = i915_kdev; 1285 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); 1286 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) 1287 acomp->aud_sample_rate[i] = 0; 1288 dev_priv->audio.component = acomp; 1289 drm_modeset_unlock_all(&dev_priv->drm); 1290 1291 return 0; 1292 } 1293 1294 static void i915_audio_component_unbind(struct device *i915_kdev, 1295 struct device *hda_kdev, void *data) 1296 { 1297 struct i915_audio_component *acomp = data; 1298 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); 1299 1300 drm_modeset_lock_all(&dev_priv->drm); 1301 acomp->base.ops = NULL; 1302 acomp->base.dev = NULL; 1303 dev_priv->audio.component = NULL; 1304 drm_modeset_unlock_all(&dev_priv->drm); 1305 1306 device_link_remove(hda_kdev, i915_kdev); 1307 1308 if (dev_priv->audio.power_refcount) 1309 drm_err(&dev_priv->drm, "audio power refcount %d after unbind\n", 1310 dev_priv->audio.power_refcount); 1311 } 1312 1313 static const struct component_ops i915_audio_component_bind_ops = { 1314 .bind = i915_audio_component_bind, 1315 .unbind = i915_audio_component_unbind, 1316 }; 1317 1318 #define AUD_FREQ_TMODE_SHIFT 14 1319 #define AUD_FREQ_4T 0 1320 #define AUD_FREQ_8T (2 << AUD_FREQ_TMODE_SHIFT) 1321 #define AUD_FREQ_PULLCLKS(x) (((x) & 0x3) << 11) 1322 #define AUD_FREQ_BCLK_96M BIT(4) 1323 1324 #define AUD_FREQ_GEN12 (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(0) | AUD_FREQ_BCLK_96M) 1325 #define AUD_FREQ_TGL_BROKEN (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(2) | AUD_FREQ_BCLK_96M) 1326 1327 /** 1328 * i915_audio_component_init - initialize and register the audio component 1329 * @dev_priv: i915 device instance 1330 * 1331 * This will register with the component framework a child component which 1332 * will bind dynamically to the snd_hda_intel driver's corresponding master 1333 * component when the latter is registered. During binding the child 1334 * initializes an instance of struct i915_audio_component which it receives 1335 * from the master. The master can then start to use the interface defined by 1336 * this struct. Each side can break the binding at any point by deregistering 1337 * its own component after which each side's component unbind callback is 1338 * called. 1339 * 1340 * We ignore any error during registration and continue with reduced 1341 * functionality (i.e. without HDMI audio). 1342 */ 1343 static void i915_audio_component_init(struct drm_i915_private *dev_priv) 1344 { 1345 u32 aud_freq, aud_freq_init; 1346 int ret; 1347 1348 ret = component_add_typed(dev_priv->drm.dev, 1349 &i915_audio_component_bind_ops, 1350 I915_COMPONENT_AUDIO); 1351 if (ret < 0) { 1352 drm_err(&dev_priv->drm, 1353 "failed to add audio component (%d)\n", ret); 1354 /* continue with reduced functionality */ 1355 return; 1356 } 1357 1358 if (DISPLAY_VER(dev_priv) >= 9) { 1359 aud_freq_init = intel_de_read(dev_priv, AUD_FREQ_CNTRL); 1360 1361 if (DISPLAY_VER(dev_priv) >= 12) 1362 aud_freq = AUD_FREQ_GEN12; 1363 else 1364 aud_freq = aud_freq_init; 1365 1366 /* use BIOS provided value for TGL and RKL unless it is a known bad value */ 1367 if ((IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv)) && 1368 aud_freq_init != AUD_FREQ_TGL_BROKEN) 1369 aud_freq = aud_freq_init; 1370 1371 drm_dbg_kms(&dev_priv->drm, "use AUD_FREQ_CNTRL of 0x%x (init value 0x%x)\n", 1372 aud_freq, aud_freq_init); 1373 1374 dev_priv->audio.freq_cntrl = aud_freq; 1375 } 1376 1377 /* init with current cdclk */ 1378 intel_audio_cdclk_change_post(dev_priv); 1379 1380 dev_priv->audio.component_registered = true; 1381 } 1382 1383 /** 1384 * i915_audio_component_cleanup - deregister the audio component 1385 * @dev_priv: i915 device instance 1386 * 1387 * Deregisters the audio component, breaking any existing binding to the 1388 * corresponding snd_hda_intel driver's master component. 1389 */ 1390 static void i915_audio_component_cleanup(struct drm_i915_private *dev_priv) 1391 { 1392 if (!dev_priv->audio.component_registered) 1393 return; 1394 1395 component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops); 1396 dev_priv->audio.component_registered = false; 1397 } 1398 1399 /** 1400 * intel_audio_init() - Initialize the audio driver either using 1401 * component framework or using lpe audio bridge 1402 * @dev_priv: the i915 drm device private data 1403 * 1404 */ 1405 void intel_audio_init(struct drm_i915_private *dev_priv) 1406 { 1407 if (intel_lpe_audio_init(dev_priv) < 0) 1408 i915_audio_component_init(dev_priv); 1409 } 1410 1411 /** 1412 * intel_audio_deinit() - deinitialize the audio driver 1413 * @dev_priv: the i915 drm device private data 1414 * 1415 */ 1416 void intel_audio_deinit(struct drm_i915_private *dev_priv) 1417 { 1418 if ((dev_priv)->audio.lpe.platdev != NULL) 1419 intel_lpe_audio_teardown(dev_priv); 1420 else 1421 i915_audio_component_cleanup(dev_priv); 1422 } 1423