1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/component.h> 25 #include <linux/kernel.h> 26 27 #include <drm/drm_edid.h> 28 #include <drm/i915_component.h> 29 30 #include "i915_drv.h" 31 #include "intel_atomic.h" 32 #include "intel_audio.h" 33 #include "intel_audio_regs.h" 34 #include "intel_cdclk.h" 35 #include "intel_crtc.h" 36 #include "intel_de.h" 37 #include "intel_display_types.h" 38 #include "intel_lpe_audio.h" 39 40 /** 41 * DOC: High Definition Audio over HDMI and Display Port 42 * 43 * The graphics and audio drivers together support High Definition Audio over 44 * HDMI and Display Port. The audio programming sequences are divided into audio 45 * codec and controller enable and disable sequences. The graphics driver 46 * handles the audio codec sequences, while the audio driver handles the audio 47 * controller sequences. 48 * 49 * The disable sequences must be performed before disabling the transcoder or 50 * port. The enable sequences may only be performed after enabling the 51 * transcoder and port, and after completed link training. Therefore the audio 52 * enable/disable sequences are part of the modeset sequence. 53 * 54 * The codec and controller sequences could be done either parallel or serial, 55 * but generally the ELDV/PD change in the codec sequence indicates to the audio 56 * driver that the controller sequence should start. Indeed, most of the 57 * co-operation between the graphics and audio drivers is handled via audio 58 * related registers. (The notable exception is the power management, not 59 * covered here.) 60 * 61 * The struct &i915_audio_component is used to interact between the graphics 62 * and audio drivers. The struct &i915_audio_component_ops @ops in it is 63 * defined in graphics driver and called in audio driver. The 64 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver. 65 */ 66 67 struct intel_audio_funcs { 68 void (*audio_codec_enable)(struct intel_encoder *encoder, 69 const struct intel_crtc_state *crtc_state, 70 const struct drm_connector_state *conn_state); 71 void (*audio_codec_disable)(struct intel_encoder *encoder, 72 const struct intel_crtc_state *old_crtc_state, 73 const struct drm_connector_state *old_conn_state); 74 }; 75 76 /* DP N/M table */ 77 #define LC_810M 810000 78 #define LC_540M 540000 79 #define LC_270M 270000 80 #define LC_162M 162000 81 82 struct dp_aud_n_m { 83 int sample_rate; 84 int clock; 85 u16 m; 86 u16 n; 87 }; 88 89 struct hdmi_aud_ncts { 90 int sample_rate; 91 int clock; 92 int n; 93 int cts; 94 }; 95 96 /* Values according to DP 1.4 Table 2-104 */ 97 static const struct dp_aud_n_m dp_aud_n_m[] = { 98 { 32000, LC_162M, 1024, 10125 }, 99 { 44100, LC_162M, 784, 5625 }, 100 { 48000, LC_162M, 512, 3375 }, 101 { 64000, LC_162M, 2048, 10125 }, 102 { 88200, LC_162M, 1568, 5625 }, 103 { 96000, LC_162M, 1024, 3375 }, 104 { 128000, LC_162M, 4096, 10125 }, 105 { 176400, LC_162M, 3136, 5625 }, 106 { 192000, LC_162M, 2048, 3375 }, 107 { 32000, LC_270M, 1024, 16875 }, 108 { 44100, LC_270M, 784, 9375 }, 109 { 48000, LC_270M, 512, 5625 }, 110 { 64000, LC_270M, 2048, 16875 }, 111 { 88200, LC_270M, 1568, 9375 }, 112 { 96000, LC_270M, 1024, 5625 }, 113 { 128000, LC_270M, 4096, 16875 }, 114 { 176400, LC_270M, 3136, 9375 }, 115 { 192000, LC_270M, 2048, 5625 }, 116 { 32000, LC_540M, 1024, 33750 }, 117 { 44100, LC_540M, 784, 18750 }, 118 { 48000, LC_540M, 512, 11250 }, 119 { 64000, LC_540M, 2048, 33750 }, 120 { 88200, LC_540M, 1568, 18750 }, 121 { 96000, LC_540M, 1024, 11250 }, 122 { 128000, LC_540M, 4096, 33750 }, 123 { 176400, LC_540M, 3136, 18750 }, 124 { 192000, LC_540M, 2048, 11250 }, 125 { 32000, LC_810M, 1024, 50625 }, 126 { 44100, LC_810M, 784, 28125 }, 127 { 48000, LC_810M, 512, 16875 }, 128 { 64000, LC_810M, 2048, 50625 }, 129 { 88200, LC_810M, 1568, 28125 }, 130 { 96000, LC_810M, 1024, 16875 }, 131 { 128000, LC_810M, 4096, 50625 }, 132 { 176400, LC_810M, 3136, 28125 }, 133 { 192000, LC_810M, 2048, 16875 }, 134 }; 135 136 static const struct dp_aud_n_m * 137 audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate) 138 { 139 int i; 140 141 for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) { 142 if (rate == dp_aud_n_m[i].sample_rate && 143 crtc_state->port_clock == dp_aud_n_m[i].clock) 144 return &dp_aud_n_m[i]; 145 } 146 147 return NULL; 148 } 149 150 static const struct { 151 int clock; 152 u32 config; 153 } hdmi_audio_clock[] = { 154 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, 155 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ 156 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, 157 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, 158 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, 159 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, 160 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, 161 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, 162 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, 163 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, 164 { 296703, AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 }, 165 { 297000, AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 }, 166 { 593407, AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 }, 167 { 594000, AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 }, 168 }; 169 170 /* HDMI N/CTS table */ 171 #define TMDS_297M 297000 172 #define TMDS_296M 296703 173 #define TMDS_594M 594000 174 #define TMDS_593M 593407 175 176 static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = { 177 { 32000, TMDS_296M, 5824, 421875 }, 178 { 32000, TMDS_297M, 3072, 222750 }, 179 { 32000, TMDS_593M, 5824, 843750 }, 180 { 32000, TMDS_594M, 3072, 445500 }, 181 { 44100, TMDS_296M, 4459, 234375 }, 182 { 44100, TMDS_297M, 4704, 247500 }, 183 { 44100, TMDS_593M, 8918, 937500 }, 184 { 44100, TMDS_594M, 9408, 990000 }, 185 { 88200, TMDS_296M, 8918, 234375 }, 186 { 88200, TMDS_297M, 9408, 247500 }, 187 { 88200, TMDS_593M, 17836, 937500 }, 188 { 88200, TMDS_594M, 18816, 990000 }, 189 { 176400, TMDS_296M, 17836, 234375 }, 190 { 176400, TMDS_297M, 18816, 247500 }, 191 { 176400, TMDS_593M, 35672, 937500 }, 192 { 176400, TMDS_594M, 37632, 990000 }, 193 { 48000, TMDS_296M, 5824, 281250 }, 194 { 48000, TMDS_297M, 5120, 247500 }, 195 { 48000, TMDS_593M, 5824, 562500 }, 196 { 48000, TMDS_594M, 6144, 594000 }, 197 { 96000, TMDS_296M, 11648, 281250 }, 198 { 96000, TMDS_297M, 10240, 247500 }, 199 { 96000, TMDS_593M, 11648, 562500 }, 200 { 96000, TMDS_594M, 12288, 594000 }, 201 { 192000, TMDS_296M, 23296, 281250 }, 202 { 192000, TMDS_297M, 20480, 247500 }, 203 { 192000, TMDS_593M, 23296, 562500 }, 204 { 192000, TMDS_594M, 24576, 594000 }, 205 }; 206 207 /* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/ 208 /* HDMI N/CTS table for 10 bit deep color(30 bpp)*/ 209 #define TMDS_371M 371250 210 #define TMDS_370M 370878 211 212 static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = { 213 { 32000, TMDS_370M, 5824, 527344 }, 214 { 32000, TMDS_371M, 6144, 556875 }, 215 { 44100, TMDS_370M, 8918, 585938 }, 216 { 44100, TMDS_371M, 4704, 309375 }, 217 { 88200, TMDS_370M, 17836, 585938 }, 218 { 88200, TMDS_371M, 9408, 309375 }, 219 { 176400, TMDS_370M, 35672, 585938 }, 220 { 176400, TMDS_371M, 18816, 309375 }, 221 { 48000, TMDS_370M, 11648, 703125 }, 222 { 48000, TMDS_371M, 5120, 309375 }, 223 { 96000, TMDS_370M, 23296, 703125 }, 224 { 96000, TMDS_371M, 10240, 309375 }, 225 { 192000, TMDS_370M, 46592, 703125 }, 226 { 192000, TMDS_371M, 20480, 309375 }, 227 }; 228 229 /* HDMI N/CTS table for 12 bit deep color(36 bpp)*/ 230 #define TMDS_445_5M 445500 231 #define TMDS_445M 445054 232 233 static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = { 234 { 32000, TMDS_445M, 5824, 632813 }, 235 { 32000, TMDS_445_5M, 4096, 445500 }, 236 { 44100, TMDS_445M, 8918, 703125 }, 237 { 44100, TMDS_445_5M, 4704, 371250 }, 238 { 88200, TMDS_445M, 17836, 703125 }, 239 { 88200, TMDS_445_5M, 9408, 371250 }, 240 { 176400, TMDS_445M, 35672, 703125 }, 241 { 176400, TMDS_445_5M, 18816, 371250 }, 242 { 48000, TMDS_445M, 5824, 421875 }, 243 { 48000, TMDS_445_5M, 5120, 371250 }, 244 { 96000, TMDS_445M, 11648, 421875 }, 245 { 96000, TMDS_445_5M, 10240, 371250 }, 246 { 192000, TMDS_445M, 23296, 421875 }, 247 { 192000, TMDS_445_5M, 20480, 371250 }, 248 }; 249 250 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ 251 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state) 252 { 253 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 254 const struct drm_display_mode *adjusted_mode = 255 &crtc_state->hw.adjusted_mode; 256 int i; 257 258 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { 259 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) 260 break; 261 } 262 263 if (DISPLAY_VER(dev_priv) < 12 && adjusted_mode->crtc_clock > 148500) 264 i = ARRAY_SIZE(hdmi_audio_clock); 265 266 if (i == ARRAY_SIZE(hdmi_audio_clock)) { 267 drm_dbg_kms(&dev_priv->drm, 268 "HDMI audio pixel clock setting for %d not found, falling back to defaults\n", 269 adjusted_mode->crtc_clock); 270 i = 1; 271 } 272 273 drm_dbg_kms(&dev_priv->drm, 274 "Configuring HDMI audio for pixel clock %d (0x%08x)\n", 275 hdmi_audio_clock[i].clock, 276 hdmi_audio_clock[i].config); 277 278 return hdmi_audio_clock[i].config; 279 } 280 281 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state, 282 int rate) 283 { 284 const struct hdmi_aud_ncts *hdmi_ncts_table; 285 int i, size; 286 287 if (crtc_state->pipe_bpp == 36) { 288 hdmi_ncts_table = hdmi_aud_ncts_36bpp; 289 size = ARRAY_SIZE(hdmi_aud_ncts_36bpp); 290 } else if (crtc_state->pipe_bpp == 30) { 291 hdmi_ncts_table = hdmi_aud_ncts_30bpp; 292 size = ARRAY_SIZE(hdmi_aud_ncts_30bpp); 293 } else { 294 hdmi_ncts_table = hdmi_aud_ncts_24bpp; 295 size = ARRAY_SIZE(hdmi_aud_ncts_24bpp); 296 } 297 298 for (i = 0; i < size; i++) { 299 if (rate == hdmi_ncts_table[i].sample_rate && 300 crtc_state->port_clock == hdmi_ncts_table[i].clock) { 301 return hdmi_ncts_table[i].n; 302 } 303 } 304 return 0; 305 } 306 307 static bool intel_eld_uptodate(struct drm_connector *connector, 308 i915_reg_t reg_eldv, u32 bits_eldv, 309 i915_reg_t reg_elda, u32 bits_elda, 310 i915_reg_t reg_edid) 311 { 312 struct drm_i915_private *dev_priv = to_i915(connector->dev); 313 const u8 *eld = connector->eld; 314 u32 tmp; 315 int i; 316 317 tmp = intel_de_read(dev_priv, reg_eldv); 318 tmp &= bits_eldv; 319 320 if (!tmp) 321 return false; 322 323 tmp = intel_de_read(dev_priv, reg_elda); 324 tmp &= ~bits_elda; 325 intel_de_write(dev_priv, reg_elda, tmp); 326 327 for (i = 0; i < drm_eld_size(eld) / 4; i++) 328 if (intel_de_read(dev_priv, reg_edid) != *((const u32 *)eld + i)) 329 return false; 330 331 return true; 332 } 333 334 static void g4x_audio_codec_disable(struct intel_encoder *encoder, 335 const struct intel_crtc_state *old_crtc_state, 336 const struct drm_connector_state *old_conn_state) 337 { 338 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 339 u32 eldv, tmp; 340 341 tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID); 342 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) 343 eldv = G4X_ELDV_DEVCL_DEVBLC; 344 else 345 eldv = G4X_ELDV_DEVCTG; 346 347 /* Invalidate ELD */ 348 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST); 349 tmp &= ~eldv; 350 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp); 351 } 352 353 static void g4x_audio_codec_enable(struct intel_encoder *encoder, 354 const struct intel_crtc_state *crtc_state, 355 const struct drm_connector_state *conn_state) 356 { 357 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 358 struct drm_connector *connector = conn_state->connector; 359 const u8 *eld = connector->eld; 360 u32 eldv; 361 u32 tmp; 362 int len, i; 363 364 tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID); 365 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) 366 eldv = G4X_ELDV_DEVCL_DEVBLC; 367 else 368 eldv = G4X_ELDV_DEVCTG; 369 370 if (intel_eld_uptodate(connector, 371 G4X_AUD_CNTL_ST, eldv, 372 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK, 373 G4X_HDMIW_HDMIEDID)) 374 return; 375 376 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST); 377 tmp &= ~(eldv | G4X_ELD_ADDR_MASK); 378 len = (tmp >> 9) & 0x1f; /* ELD buffer size */ 379 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp); 380 381 len = min(drm_eld_size(eld) / 4, len); 382 for (i = 0; i < len; i++) 383 intel_de_write(dev_priv, G4X_HDMIW_HDMIEDID, 384 *((const u32 *)eld + i)); 385 386 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST); 387 tmp |= eldv; 388 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp); 389 } 390 391 static void 392 hsw_dp_audio_config_update(struct intel_encoder *encoder, 393 const struct intel_crtc_state *crtc_state) 394 { 395 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 396 struct i915_audio_component *acomp = dev_priv->display.audio.component; 397 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 398 enum port port = encoder->port; 399 const struct dp_aud_n_m *nm; 400 int rate; 401 u32 tmp; 402 403 rate = acomp ? acomp->aud_sample_rate[port] : 0; 404 nm = audio_config_dp_get_n_m(crtc_state, rate); 405 if (nm) 406 drm_dbg_kms(&dev_priv->drm, "using Maud %u, Naud %u\n", nm->m, 407 nm->n); 408 else 409 drm_dbg_kms(&dev_priv->drm, "using automatic Maud, Naud\n"); 410 411 tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder)); 412 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 413 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 414 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 415 tmp |= AUD_CONFIG_N_VALUE_INDEX; 416 417 if (nm) { 418 tmp &= ~AUD_CONFIG_N_MASK; 419 tmp |= AUD_CONFIG_N(nm->n); 420 tmp |= AUD_CONFIG_N_PROG_ENABLE; 421 } 422 423 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp); 424 425 tmp = intel_de_read(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); 426 tmp &= ~AUD_CONFIG_M_MASK; 427 tmp &= ~AUD_M_CTS_M_VALUE_INDEX; 428 tmp &= ~AUD_M_CTS_M_PROG_ENABLE; 429 430 if (nm) { 431 tmp |= nm->m; 432 tmp |= AUD_M_CTS_M_VALUE_INDEX; 433 tmp |= AUD_M_CTS_M_PROG_ENABLE; 434 } 435 436 intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 437 } 438 439 static void 440 hsw_hdmi_audio_config_update(struct intel_encoder *encoder, 441 const struct intel_crtc_state *crtc_state) 442 { 443 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 444 struct i915_audio_component *acomp = dev_priv->display.audio.component; 445 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 446 enum port port = encoder->port; 447 int n, rate; 448 u32 tmp; 449 450 rate = acomp ? acomp->aud_sample_rate[port] : 0; 451 452 tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder)); 453 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 454 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 455 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 456 tmp |= audio_config_hdmi_pixel_clock(crtc_state); 457 458 n = audio_config_hdmi_get_n(crtc_state, rate); 459 if (n != 0) { 460 drm_dbg_kms(&dev_priv->drm, "using N %d\n", n); 461 462 tmp &= ~AUD_CONFIG_N_MASK; 463 tmp |= AUD_CONFIG_N(n); 464 tmp |= AUD_CONFIG_N_PROG_ENABLE; 465 } else { 466 drm_dbg_kms(&dev_priv->drm, "using automatic N\n"); 467 } 468 469 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp); 470 471 /* 472 * Let's disable "Enable CTS or M Prog bit" 473 * and let HW calculate the value 474 */ 475 tmp = intel_de_read(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); 476 tmp &= ~AUD_M_CTS_M_PROG_ENABLE; 477 tmp &= ~AUD_M_CTS_M_VALUE_INDEX; 478 intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 479 } 480 481 static void 482 hsw_audio_config_update(struct intel_encoder *encoder, 483 const struct intel_crtc_state *crtc_state) 484 { 485 if (intel_crtc_has_dp_encoder(crtc_state)) 486 hsw_dp_audio_config_update(encoder, crtc_state); 487 else 488 hsw_hdmi_audio_config_update(encoder, crtc_state); 489 } 490 491 static void hsw_audio_codec_disable(struct intel_encoder *encoder, 492 const struct intel_crtc_state *old_crtc_state, 493 const struct drm_connector_state *old_conn_state) 494 { 495 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 496 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 497 u32 tmp; 498 499 mutex_lock(&dev_priv->display.audio.mutex); 500 501 /* Disable timestamps */ 502 tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder)); 503 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 504 tmp |= AUD_CONFIG_N_PROG_ENABLE; 505 tmp &= ~AUD_CONFIG_UPPER_N_MASK; 506 tmp &= ~AUD_CONFIG_LOWER_N_MASK; 507 if (intel_crtc_has_dp_encoder(old_crtc_state)) 508 tmp |= AUD_CONFIG_N_VALUE_INDEX; 509 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp); 510 511 /* Invalidate ELD */ 512 tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD); 513 tmp &= ~AUDIO_ELD_VALID(cpu_transcoder); 514 tmp &= ~AUDIO_OUTPUT_ENABLE(cpu_transcoder); 515 intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp); 516 517 mutex_unlock(&dev_priv->display.audio.mutex); 518 } 519 520 static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, 521 const struct intel_crtc_state *crtc_state) 522 { 523 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 524 unsigned int link_clks_available, link_clks_required; 525 unsigned int tu_data, tu_line, link_clks_active; 526 unsigned int h_active, h_total, hblank_delta, pixel_clk; 527 unsigned int fec_coeff, cdclk, vdsc_bpp; 528 unsigned int link_clk, lanes; 529 unsigned int hblank_rise; 530 531 h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay; 532 h_total = crtc_state->hw.adjusted_mode.crtc_htotal; 533 pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock; 534 vdsc_bpp = crtc_state->dsc.compressed_bpp; 535 cdclk = i915->display.cdclk.hw.cdclk; 536 /* fec= 0.972261, using rounding multiplier of 1000000 */ 537 fec_coeff = 972261; 538 link_clk = crtc_state->port_clock; 539 lanes = crtc_state->lane_count; 540 541 drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :" 542 "lanes = %u vdsc_bpp = %u cdclk = %u\n", 543 h_active, link_clk, lanes, vdsc_bpp, cdclk); 544 545 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk)) 546 return 0; 547 548 link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28; 549 link_clks_required = DIV_ROUND_UP(192000 * h_total, 1000 * pixel_clk) * (48 / lanes + 2); 550 551 if (link_clks_available > link_clks_required) 552 hblank_delta = 32; 553 else 554 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), 555 mul_u32_u32(link_clk, cdclk)); 556 557 tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bpp * 8, 1000000), 558 mul_u32_u32(link_clk * lanes, fec_coeff)); 559 tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff), 560 mul_u32_u32(64 * pixel_clk, 1000000)); 561 link_clks_active = (tu_line - 1) * 64 + tu_data; 562 563 hblank_rise = (link_clks_active + 6 * DIV_ROUND_UP(link_clks_active, 250) + 4) * pixel_clk / link_clk; 564 565 return h_active - hblank_rise + hblank_delta; 566 } 567 568 static unsigned int calc_samples_room(const struct intel_crtc_state *crtc_state) 569 { 570 unsigned int h_active, h_total, pixel_clk; 571 unsigned int link_clk, lanes; 572 573 h_active = crtc_state->hw.adjusted_mode.hdisplay; 574 h_total = crtc_state->hw.adjusted_mode.htotal; 575 pixel_clk = crtc_state->hw.adjusted_mode.clock; 576 link_clk = crtc_state->port_clock; 577 lanes = crtc_state->lane_count; 578 579 return ((h_total - h_active) * link_clk - 12 * pixel_clk) / 580 (pixel_clk * (48 / lanes + 2)); 581 } 582 583 static void enable_audio_dsc_wa(struct intel_encoder *encoder, 584 const struct intel_crtc_state *crtc_state) 585 { 586 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 587 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 588 enum pipe pipe = crtc->pipe; 589 unsigned int hblank_early_prog, samples_room; 590 unsigned int val; 591 592 if (DISPLAY_VER(i915) < 11) 593 return; 594 595 val = intel_de_read(i915, AUD_CONFIG_BE); 596 597 if (DISPLAY_VER(i915) == 11) 598 val |= HBLANK_EARLY_ENABLE_ICL(pipe); 599 else if (DISPLAY_VER(i915) >= 12) 600 val |= HBLANK_EARLY_ENABLE_TGL(pipe); 601 602 if (crtc_state->dsc.compression_enable && 603 crtc_state->hw.adjusted_mode.hdisplay >= 3840 && 604 crtc_state->hw.adjusted_mode.vdisplay >= 2160) { 605 /* Get hblank early enable value required */ 606 val &= ~HBLANK_START_COUNT_MASK(pipe); 607 hblank_early_prog = calc_hblank_early_prog(encoder, crtc_state); 608 if (hblank_early_prog < 32) 609 val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_32); 610 else if (hblank_early_prog < 64) 611 val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_64); 612 else if (hblank_early_prog < 96) 613 val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_96); 614 else 615 val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_128); 616 617 /* Get samples room value required */ 618 val &= ~NUMBER_SAMPLES_PER_LINE_MASK(pipe); 619 samples_room = calc_samples_room(crtc_state); 620 if (samples_room < 3) 621 val |= NUMBER_SAMPLES_PER_LINE(pipe, samples_room); 622 else /* Program 0 i.e "All Samples available in buffer" */ 623 val |= NUMBER_SAMPLES_PER_LINE(pipe, 0x0); 624 } 625 626 intel_de_write(i915, AUD_CONFIG_BE, val); 627 } 628 629 #undef ROUNDING_FACTOR 630 631 static void hsw_audio_codec_enable(struct intel_encoder *encoder, 632 const struct intel_crtc_state *crtc_state, 633 const struct drm_connector_state *conn_state) 634 { 635 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 636 struct drm_connector *connector = conn_state->connector; 637 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 638 const u8 *eld = connector->eld; 639 u32 tmp; 640 int len, i; 641 642 mutex_lock(&dev_priv->display.audio.mutex); 643 644 /* Enable Audio WA for 4k DSC usecases */ 645 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP)) 646 enable_audio_dsc_wa(encoder, crtc_state); 647 648 /* Enable audio presence detect, invalidate ELD */ 649 tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD); 650 tmp |= AUDIO_OUTPUT_ENABLE(cpu_transcoder); 651 tmp &= ~AUDIO_ELD_VALID(cpu_transcoder); 652 intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp); 653 654 /* 655 * FIXME: We're supposed to wait for vblank here, but we have vblanks 656 * disabled during the mode set. The proper fix would be to push the 657 * rest of the setup into a vblank work item, queued here, but the 658 * infrastructure is not there yet. 659 */ 660 661 /* Reset ELD write address */ 662 tmp = intel_de_read(dev_priv, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder)); 663 tmp &= ~IBX_ELD_ADDRESS_MASK; 664 intel_de_write(dev_priv, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder), tmp); 665 666 /* Up to 84 bytes of hw ELD buffer */ 667 len = min(drm_eld_size(eld), 84); 668 for (i = 0; i < len / 4; i++) 669 intel_de_write(dev_priv, HSW_AUD_EDID_DATA(cpu_transcoder), 670 *((const u32 *)eld + i)); 671 672 /* ELD valid */ 673 tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD); 674 tmp |= AUDIO_ELD_VALID(cpu_transcoder); 675 intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp); 676 677 /* Enable timestamps */ 678 hsw_audio_config_update(encoder, crtc_state); 679 680 mutex_unlock(&dev_priv->display.audio.mutex); 681 } 682 683 static void ilk_audio_codec_disable(struct intel_encoder *encoder, 684 const struct intel_crtc_state *old_crtc_state, 685 const struct drm_connector_state *old_conn_state) 686 { 687 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 688 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 689 enum pipe pipe = crtc->pipe; 690 enum port port = encoder->port; 691 u32 tmp, eldv; 692 i915_reg_t aud_config, aud_cntrl_st2; 693 694 if (drm_WARN_ON(&dev_priv->drm, port == PORT_A)) 695 return; 696 697 if (HAS_PCH_IBX(dev_priv)) { 698 aud_config = IBX_AUD_CFG(pipe); 699 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 700 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 701 aud_config = VLV_AUD_CFG(pipe); 702 aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 703 } else { 704 aud_config = CPT_AUD_CFG(pipe); 705 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 706 } 707 708 /* Disable timestamps */ 709 tmp = intel_de_read(dev_priv, aud_config); 710 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 711 tmp |= AUD_CONFIG_N_PROG_ENABLE; 712 tmp &= ~AUD_CONFIG_UPPER_N_MASK; 713 tmp &= ~AUD_CONFIG_LOWER_N_MASK; 714 if (intel_crtc_has_dp_encoder(old_crtc_state)) 715 tmp |= AUD_CONFIG_N_VALUE_INDEX; 716 intel_de_write(dev_priv, aud_config, tmp); 717 718 eldv = IBX_ELD_VALID(port); 719 720 /* Invalidate ELD */ 721 tmp = intel_de_read(dev_priv, aud_cntrl_st2); 722 tmp &= ~eldv; 723 intel_de_write(dev_priv, aud_cntrl_st2, tmp); 724 } 725 726 static void ilk_audio_codec_enable(struct intel_encoder *encoder, 727 const struct intel_crtc_state *crtc_state, 728 const struct drm_connector_state *conn_state) 729 { 730 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 731 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 732 struct drm_connector *connector = conn_state->connector; 733 enum pipe pipe = crtc->pipe; 734 enum port port = encoder->port; 735 const u8 *eld = connector->eld; 736 u32 tmp, eldv; 737 int len, i; 738 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; 739 740 if (drm_WARN_ON(&dev_priv->drm, port == PORT_A)) 741 return; 742 743 /* 744 * FIXME: We're supposed to wait for vblank here, but we have vblanks 745 * disabled during the mode set. The proper fix would be to push the 746 * rest of the setup into a vblank work item, queued here, but the 747 * infrastructure is not there yet. 748 */ 749 750 if (HAS_PCH_IBX(dev_priv)) { 751 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); 752 aud_config = IBX_AUD_CFG(pipe); 753 aud_cntl_st = IBX_AUD_CNTL_ST(pipe); 754 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 755 } else if (IS_VALLEYVIEW(dev_priv) || 756 IS_CHERRYVIEW(dev_priv)) { 757 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); 758 aud_config = VLV_AUD_CFG(pipe); 759 aud_cntl_st = VLV_AUD_CNTL_ST(pipe); 760 aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 761 } else { 762 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); 763 aud_config = CPT_AUD_CFG(pipe); 764 aud_cntl_st = CPT_AUD_CNTL_ST(pipe); 765 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 766 } 767 768 eldv = IBX_ELD_VALID(port); 769 770 /* Invalidate ELD */ 771 tmp = intel_de_read(dev_priv, aud_cntrl_st2); 772 tmp &= ~eldv; 773 intel_de_write(dev_priv, aud_cntrl_st2, tmp); 774 775 /* Reset ELD write address */ 776 tmp = intel_de_read(dev_priv, aud_cntl_st); 777 tmp &= ~IBX_ELD_ADDRESS_MASK; 778 intel_de_write(dev_priv, aud_cntl_st, tmp); 779 780 /* Up to 84 bytes of hw ELD buffer */ 781 len = min(drm_eld_size(eld), 84); 782 for (i = 0; i < len / 4; i++) 783 intel_de_write(dev_priv, hdmiw_hdmiedid, 784 *((const u32 *)eld + i)); 785 786 /* ELD valid */ 787 tmp = intel_de_read(dev_priv, aud_cntrl_st2); 788 tmp |= eldv; 789 intel_de_write(dev_priv, aud_cntrl_st2, tmp); 790 791 /* Enable timestamps */ 792 tmp = intel_de_read(dev_priv, aud_config); 793 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 794 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 795 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 796 if (intel_crtc_has_dp_encoder(crtc_state)) 797 tmp |= AUD_CONFIG_N_VALUE_INDEX; 798 else 799 tmp |= audio_config_hdmi_pixel_clock(crtc_state); 800 intel_de_write(dev_priv, aud_config, tmp); 801 } 802 803 /** 804 * intel_audio_codec_enable - Enable the audio codec for HD audio 805 * @encoder: encoder on which to enable audio 806 * @crtc_state: pointer to the current crtc state. 807 * @conn_state: pointer to the current connector state. 808 * 809 * The enable sequences may only be performed after enabling the transcoder and 810 * port, and after completed link training. 811 */ 812 void intel_audio_codec_enable(struct intel_encoder *encoder, 813 const struct intel_crtc_state *crtc_state, 814 const struct drm_connector_state *conn_state) 815 { 816 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 817 struct i915_audio_component *acomp = dev_priv->display.audio.component; 818 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 819 struct drm_connector *connector = conn_state->connector; 820 const struct drm_display_mode *adjusted_mode = 821 &crtc_state->hw.adjusted_mode; 822 enum port port = encoder->port; 823 enum pipe pipe = crtc->pipe; 824 825 if (!crtc_state->has_audio) 826 return; 827 828 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Enable audio codec on pipe %c, %u bytes ELD\n", 829 connector->base.id, connector->name, 830 encoder->base.base.id, encoder->base.name, 831 pipe_name(pipe), drm_eld_size(connector->eld)); 832 833 /* FIXME precompute the ELD in .compute_config() */ 834 if (!connector->eld[0]) 835 drm_dbg_kms(&dev_priv->drm, 836 "Bogus ELD on [CONNECTOR:%d:%s]\n", 837 connector->base.id, connector->name); 838 839 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; 840 841 if (dev_priv->display.funcs.audio) 842 dev_priv->display.funcs.audio->audio_codec_enable(encoder, 843 crtc_state, 844 conn_state); 845 846 mutex_lock(&dev_priv->display.audio.mutex); 847 encoder->audio_connector = connector; 848 849 /* referred in audio callbacks */ 850 dev_priv->display.audio.encoder_map[pipe] = encoder; 851 mutex_unlock(&dev_priv->display.audio.mutex); 852 853 if (acomp && acomp->base.audio_ops && 854 acomp->base.audio_ops->pin_eld_notify) { 855 /* audio drivers expect pipe = -1 to indicate Non-MST cases */ 856 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 857 pipe = -1; 858 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 859 (int) port, (int) pipe); 860 } 861 862 intel_lpe_audio_notify(dev_priv, pipe, port, connector->eld, 863 crtc_state->port_clock, 864 intel_crtc_has_dp_encoder(crtc_state)); 865 } 866 867 /** 868 * intel_audio_codec_disable - Disable the audio codec for HD audio 869 * @encoder: encoder on which to disable audio 870 * @old_crtc_state: pointer to the old crtc state. 871 * @old_conn_state: pointer to the old connector state. 872 * 873 * The disable sequences must be performed before disabling the transcoder or 874 * port. 875 */ 876 void intel_audio_codec_disable(struct intel_encoder *encoder, 877 const struct intel_crtc_state *old_crtc_state, 878 const struct drm_connector_state *old_conn_state) 879 { 880 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 881 struct i915_audio_component *acomp = dev_priv->display.audio.component; 882 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 883 struct drm_connector *connector = old_conn_state->connector; 884 enum port port = encoder->port; 885 enum pipe pipe = crtc->pipe; 886 887 if (!old_crtc_state->has_audio) 888 return; 889 890 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Disable audio codec on pipe %c\n", 891 connector->base.id, connector->name, 892 encoder->base.base.id, encoder->base.name, pipe_name(pipe)); 893 894 if (dev_priv->display.funcs.audio) 895 dev_priv->display.funcs.audio->audio_codec_disable(encoder, 896 old_crtc_state, 897 old_conn_state); 898 899 mutex_lock(&dev_priv->display.audio.mutex); 900 encoder->audio_connector = NULL; 901 dev_priv->display.audio.encoder_map[pipe] = NULL; 902 mutex_unlock(&dev_priv->display.audio.mutex); 903 904 if (acomp && acomp->base.audio_ops && 905 acomp->base.audio_ops->pin_eld_notify) { 906 /* audio drivers expect pipe = -1 to indicate Non-MST cases */ 907 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 908 pipe = -1; 909 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 910 (int) port, (int) pipe); 911 } 912 913 intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false); 914 } 915 916 static const struct intel_audio_funcs g4x_audio_funcs = { 917 .audio_codec_enable = g4x_audio_codec_enable, 918 .audio_codec_disable = g4x_audio_codec_disable, 919 }; 920 921 static const struct intel_audio_funcs ilk_audio_funcs = { 922 .audio_codec_enable = ilk_audio_codec_enable, 923 .audio_codec_disable = ilk_audio_codec_disable, 924 }; 925 926 static const struct intel_audio_funcs hsw_audio_funcs = { 927 .audio_codec_enable = hsw_audio_codec_enable, 928 .audio_codec_disable = hsw_audio_codec_disable, 929 }; 930 931 /** 932 * intel_audio_hooks_init - Set up chip specific audio hooks 933 * @dev_priv: device private 934 */ 935 void intel_audio_hooks_init(struct drm_i915_private *dev_priv) 936 { 937 if (IS_G4X(dev_priv)) { 938 dev_priv->display.funcs.audio = &g4x_audio_funcs; 939 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 940 dev_priv->display.funcs.audio = &ilk_audio_funcs; 941 } else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) { 942 dev_priv->display.funcs.audio = &hsw_audio_funcs; 943 } else if (HAS_PCH_SPLIT(dev_priv)) { 944 dev_priv->display.funcs.audio = &ilk_audio_funcs; 945 } 946 } 947 948 struct aud_ts_cdclk_m_n { 949 u8 m; 950 u16 n; 951 }; 952 953 void intel_audio_cdclk_change_pre(struct drm_i915_private *i915) 954 { 955 if (DISPLAY_VER(i915) >= 13) 956 intel_de_rmw(i915, AUD_TS_CDCLK_M, AUD_TS_CDCLK_M_EN, 0); 957 } 958 959 static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts) 960 { 961 if (refclk == 24000) 962 aud_ts->m = 12; 963 else 964 aud_ts->m = 15; 965 966 aud_ts->n = cdclk * aud_ts->m / 24000; 967 } 968 969 void intel_audio_cdclk_change_post(struct drm_i915_private *i915) 970 { 971 struct aud_ts_cdclk_m_n aud_ts; 972 973 if (DISPLAY_VER(i915) >= 13) { 974 get_aud_ts_cdclk_m_n(i915->display.cdclk.hw.ref, i915->display.cdclk.hw.cdclk, &aud_ts); 975 976 intel_de_write(i915, AUD_TS_CDCLK_N, aud_ts.n); 977 intel_de_write(i915, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN); 978 drm_dbg_kms(&i915->drm, "aud_ts_cdclk set to M=%u, N=%u\n", aud_ts.m, aud_ts.n); 979 } 980 } 981 982 static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state, 983 struct intel_crtc *crtc, 984 bool enable) 985 { 986 struct intel_cdclk_state *cdclk_state; 987 int ret; 988 989 /* need to hold at least one crtc lock for the global state */ 990 ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx); 991 if (ret) 992 return ret; 993 994 cdclk_state = intel_atomic_get_cdclk_state(state); 995 if (IS_ERR(cdclk_state)) 996 return PTR_ERR(cdclk_state); 997 998 cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0; 999 1000 return drm_atomic_commit(&state->base); 1001 } 1002 1003 static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv, 1004 bool enable) 1005 { 1006 struct drm_modeset_acquire_ctx ctx; 1007 struct drm_atomic_state *state; 1008 struct intel_crtc *crtc; 1009 int ret; 1010 1011 crtc = intel_first_crtc(dev_priv); 1012 if (!crtc) 1013 return; 1014 1015 drm_modeset_acquire_init(&ctx, 0); 1016 state = drm_atomic_state_alloc(&dev_priv->drm); 1017 if (drm_WARN_ON(&dev_priv->drm, !state)) 1018 return; 1019 1020 state->acquire_ctx = &ctx; 1021 1022 retry: 1023 ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), crtc, 1024 enable); 1025 if (ret == -EDEADLK) { 1026 drm_atomic_state_clear(state); 1027 drm_modeset_backoff(&ctx); 1028 goto retry; 1029 } 1030 1031 drm_WARN_ON(&dev_priv->drm, ret); 1032 1033 drm_atomic_state_put(state); 1034 1035 drm_modeset_drop_locks(&ctx); 1036 drm_modeset_acquire_fini(&ctx); 1037 } 1038 1039 static unsigned long i915_audio_component_get_power(struct device *kdev) 1040 { 1041 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1042 intel_wakeref_t ret; 1043 1044 /* Catch potential impedance mismatches before they occur! */ 1045 BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long)); 1046 1047 ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO_PLAYBACK); 1048 1049 if (dev_priv->display.audio.power_refcount++ == 0) { 1050 if (DISPLAY_VER(dev_priv) >= 9) { 1051 intel_de_write(dev_priv, AUD_FREQ_CNTRL, 1052 dev_priv->display.audio.freq_cntrl); 1053 drm_dbg_kms(&dev_priv->drm, 1054 "restored AUD_FREQ_CNTRL to 0x%x\n", 1055 dev_priv->display.audio.freq_cntrl); 1056 } 1057 1058 /* Force CDCLK to 2*BCLK as long as we need audio powered. */ 1059 if (IS_GEMINILAKE(dev_priv)) 1060 glk_force_audio_cdclk(dev_priv, true); 1061 1062 if (DISPLAY_VER(dev_priv) >= 10) 1063 intel_de_write(dev_priv, AUD_PIN_BUF_CTL, 1064 (intel_de_read(dev_priv, AUD_PIN_BUF_CTL) | AUD_PIN_BUF_ENABLE)); 1065 } 1066 1067 return ret; 1068 } 1069 1070 static void i915_audio_component_put_power(struct device *kdev, 1071 unsigned long cookie) 1072 { 1073 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1074 1075 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */ 1076 if (--dev_priv->display.audio.power_refcount == 0) 1077 if (IS_GEMINILAKE(dev_priv)) 1078 glk_force_audio_cdclk(dev_priv, false); 1079 1080 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO_PLAYBACK, cookie); 1081 } 1082 1083 static void i915_audio_component_codec_wake_override(struct device *kdev, 1084 bool enable) 1085 { 1086 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1087 unsigned long cookie; 1088 u32 tmp; 1089 1090 if (DISPLAY_VER(dev_priv) < 9) 1091 return; 1092 1093 cookie = i915_audio_component_get_power(kdev); 1094 1095 /* 1096 * Enable/disable generating the codec wake signal, overriding the 1097 * internal logic to generate the codec wake to controller. 1098 */ 1099 tmp = intel_de_read(dev_priv, HSW_AUD_CHICKENBIT); 1100 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL; 1101 intel_de_write(dev_priv, HSW_AUD_CHICKENBIT, tmp); 1102 usleep_range(1000, 1500); 1103 1104 if (enable) { 1105 tmp = intel_de_read(dev_priv, HSW_AUD_CHICKENBIT); 1106 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL; 1107 intel_de_write(dev_priv, HSW_AUD_CHICKENBIT, tmp); 1108 usleep_range(1000, 1500); 1109 } 1110 1111 i915_audio_component_put_power(kdev, cookie); 1112 } 1113 1114 /* Get CDCLK in kHz */ 1115 static int i915_audio_component_get_cdclk_freq(struct device *kdev) 1116 { 1117 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1118 1119 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DDI(dev_priv))) 1120 return -ENODEV; 1121 1122 return dev_priv->display.cdclk.hw.cdclk; 1123 } 1124 1125 /* 1126 * get the intel_encoder according to the parameter port and pipe 1127 * intel_encoder is saved by the index of pipe 1128 * MST & (pipe >= 0): return the audio.encoder_map[pipe], 1129 * when port is matched 1130 * MST & (pipe < 0): this is invalid 1131 * Non-MST & (pipe >= 0): only pipe = 0 (the first device entry) 1132 * will get the right intel_encoder with port matched 1133 * Non-MST & (pipe < 0): get the right intel_encoder with port matched 1134 */ 1135 static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv, 1136 int port, int pipe) 1137 { 1138 struct intel_encoder *encoder; 1139 1140 /* MST */ 1141 if (pipe >= 0) { 1142 if (drm_WARN_ON(&dev_priv->drm, 1143 pipe >= ARRAY_SIZE(dev_priv->display.audio.encoder_map))) 1144 return NULL; 1145 1146 encoder = dev_priv->display.audio.encoder_map[pipe]; 1147 /* 1148 * when bootup, audio driver may not know it is 1149 * MST or not. So it will poll all the port & pipe 1150 * combinations 1151 */ 1152 if (encoder != NULL && encoder->port == port && 1153 encoder->type == INTEL_OUTPUT_DP_MST) 1154 return encoder; 1155 } 1156 1157 /* Non-MST */ 1158 if (pipe > 0) 1159 return NULL; 1160 1161 for_each_pipe(dev_priv, pipe) { 1162 encoder = dev_priv->display.audio.encoder_map[pipe]; 1163 if (encoder == NULL) 1164 continue; 1165 1166 if (encoder->type == INTEL_OUTPUT_DP_MST) 1167 continue; 1168 1169 if (port == encoder->port) 1170 return encoder; 1171 } 1172 1173 return NULL; 1174 } 1175 1176 static int i915_audio_component_sync_audio_rate(struct device *kdev, int port, 1177 int pipe, int rate) 1178 { 1179 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1180 struct i915_audio_component *acomp = dev_priv->display.audio.component; 1181 struct intel_encoder *encoder; 1182 struct intel_crtc *crtc; 1183 unsigned long cookie; 1184 int err = 0; 1185 1186 if (!HAS_DDI(dev_priv)) 1187 return 0; 1188 1189 cookie = i915_audio_component_get_power(kdev); 1190 mutex_lock(&dev_priv->display.audio.mutex); 1191 1192 /* 1. get the pipe */ 1193 encoder = get_saved_enc(dev_priv, port, pipe); 1194 if (!encoder || !encoder->base.crtc) { 1195 drm_dbg_kms(&dev_priv->drm, "Not valid for port %c\n", 1196 port_name(port)); 1197 err = -ENODEV; 1198 goto unlock; 1199 } 1200 1201 crtc = to_intel_crtc(encoder->base.crtc); 1202 1203 /* port must be valid now, otherwise the pipe will be invalid */ 1204 acomp->aud_sample_rate[port] = rate; 1205 1206 hsw_audio_config_update(encoder, crtc->config); 1207 1208 unlock: 1209 mutex_unlock(&dev_priv->display.audio.mutex); 1210 i915_audio_component_put_power(kdev, cookie); 1211 return err; 1212 } 1213 1214 static int i915_audio_component_get_eld(struct device *kdev, int port, 1215 int pipe, bool *enabled, 1216 unsigned char *buf, int max_bytes) 1217 { 1218 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1219 struct intel_encoder *intel_encoder; 1220 const u8 *eld; 1221 int ret = -EINVAL; 1222 1223 mutex_lock(&dev_priv->display.audio.mutex); 1224 1225 intel_encoder = get_saved_enc(dev_priv, port, pipe); 1226 if (!intel_encoder) { 1227 drm_dbg_kms(&dev_priv->drm, "Not valid for port %c\n", 1228 port_name(port)); 1229 mutex_unlock(&dev_priv->display.audio.mutex); 1230 return ret; 1231 } 1232 1233 ret = 0; 1234 *enabled = intel_encoder->audio_connector != NULL; 1235 if (*enabled) { 1236 eld = intel_encoder->audio_connector->eld; 1237 ret = drm_eld_size(eld); 1238 memcpy(buf, eld, min(max_bytes, ret)); 1239 } 1240 1241 mutex_unlock(&dev_priv->display.audio.mutex); 1242 return ret; 1243 } 1244 1245 static const struct drm_audio_component_ops i915_audio_component_ops = { 1246 .owner = THIS_MODULE, 1247 .get_power = i915_audio_component_get_power, 1248 .put_power = i915_audio_component_put_power, 1249 .codec_wake_override = i915_audio_component_codec_wake_override, 1250 .get_cdclk_freq = i915_audio_component_get_cdclk_freq, 1251 .sync_audio_rate = i915_audio_component_sync_audio_rate, 1252 .get_eld = i915_audio_component_get_eld, 1253 }; 1254 1255 static int i915_audio_component_bind(struct device *i915_kdev, 1256 struct device *hda_kdev, void *data) 1257 { 1258 struct i915_audio_component *acomp = data; 1259 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); 1260 int i; 1261 1262 if (drm_WARN_ON(&dev_priv->drm, acomp->base.ops || acomp->base.dev)) 1263 return -EEXIST; 1264 1265 if (drm_WARN_ON(&dev_priv->drm, 1266 !device_link_add(hda_kdev, i915_kdev, 1267 DL_FLAG_STATELESS))) 1268 return -ENOMEM; 1269 1270 drm_modeset_lock_all(&dev_priv->drm); 1271 acomp->base.ops = &i915_audio_component_ops; 1272 acomp->base.dev = i915_kdev; 1273 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); 1274 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) 1275 acomp->aud_sample_rate[i] = 0; 1276 dev_priv->display.audio.component = acomp; 1277 drm_modeset_unlock_all(&dev_priv->drm); 1278 1279 return 0; 1280 } 1281 1282 static void i915_audio_component_unbind(struct device *i915_kdev, 1283 struct device *hda_kdev, void *data) 1284 { 1285 struct i915_audio_component *acomp = data; 1286 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); 1287 1288 drm_modeset_lock_all(&dev_priv->drm); 1289 acomp->base.ops = NULL; 1290 acomp->base.dev = NULL; 1291 dev_priv->display.audio.component = NULL; 1292 drm_modeset_unlock_all(&dev_priv->drm); 1293 1294 device_link_remove(hda_kdev, i915_kdev); 1295 1296 if (dev_priv->display.audio.power_refcount) 1297 drm_err(&dev_priv->drm, "audio power refcount %d after unbind\n", 1298 dev_priv->display.audio.power_refcount); 1299 } 1300 1301 static const struct component_ops i915_audio_component_bind_ops = { 1302 .bind = i915_audio_component_bind, 1303 .unbind = i915_audio_component_unbind, 1304 }; 1305 1306 #define AUD_FREQ_TMODE_SHIFT 14 1307 #define AUD_FREQ_4T 0 1308 #define AUD_FREQ_8T (2 << AUD_FREQ_TMODE_SHIFT) 1309 #define AUD_FREQ_PULLCLKS(x) (((x) & 0x3) << 11) 1310 #define AUD_FREQ_BCLK_96M BIT(4) 1311 1312 #define AUD_FREQ_GEN12 (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(0) | AUD_FREQ_BCLK_96M) 1313 #define AUD_FREQ_TGL_BROKEN (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(2) | AUD_FREQ_BCLK_96M) 1314 1315 /** 1316 * i915_audio_component_init - initialize and register the audio component 1317 * @dev_priv: i915 device instance 1318 * 1319 * This will register with the component framework a child component which 1320 * will bind dynamically to the snd_hda_intel driver's corresponding master 1321 * component when the latter is registered. During binding the child 1322 * initializes an instance of struct i915_audio_component which it receives 1323 * from the master. The master can then start to use the interface defined by 1324 * this struct. Each side can break the binding at any point by deregistering 1325 * its own component after which each side's component unbind callback is 1326 * called. 1327 * 1328 * We ignore any error during registration and continue with reduced 1329 * functionality (i.e. without HDMI audio). 1330 */ 1331 static void i915_audio_component_init(struct drm_i915_private *dev_priv) 1332 { 1333 u32 aud_freq, aud_freq_init; 1334 int ret; 1335 1336 ret = component_add_typed(dev_priv->drm.dev, 1337 &i915_audio_component_bind_ops, 1338 I915_COMPONENT_AUDIO); 1339 if (ret < 0) { 1340 drm_err(&dev_priv->drm, 1341 "failed to add audio component (%d)\n", ret); 1342 /* continue with reduced functionality */ 1343 return; 1344 } 1345 1346 if (DISPLAY_VER(dev_priv) >= 9) { 1347 aud_freq_init = intel_de_read(dev_priv, AUD_FREQ_CNTRL); 1348 1349 if (DISPLAY_VER(dev_priv) >= 12) 1350 aud_freq = AUD_FREQ_GEN12; 1351 else 1352 aud_freq = aud_freq_init; 1353 1354 /* use BIOS provided value for TGL and RKL unless it is a known bad value */ 1355 if ((IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv)) && 1356 aud_freq_init != AUD_FREQ_TGL_BROKEN) 1357 aud_freq = aud_freq_init; 1358 1359 drm_dbg_kms(&dev_priv->drm, "use AUD_FREQ_CNTRL of 0x%x (init value 0x%x)\n", 1360 aud_freq, aud_freq_init); 1361 1362 dev_priv->display.audio.freq_cntrl = aud_freq; 1363 } 1364 1365 /* init with current cdclk */ 1366 intel_audio_cdclk_change_post(dev_priv); 1367 1368 dev_priv->display.audio.component_registered = true; 1369 } 1370 1371 /** 1372 * i915_audio_component_cleanup - deregister the audio component 1373 * @dev_priv: i915 device instance 1374 * 1375 * Deregisters the audio component, breaking any existing binding to the 1376 * corresponding snd_hda_intel driver's master component. 1377 */ 1378 static void i915_audio_component_cleanup(struct drm_i915_private *dev_priv) 1379 { 1380 if (!dev_priv->display.audio.component_registered) 1381 return; 1382 1383 component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops); 1384 dev_priv->display.audio.component_registered = false; 1385 } 1386 1387 /** 1388 * intel_audio_init() - Initialize the audio driver either using 1389 * component framework or using lpe audio bridge 1390 * @dev_priv: the i915 drm device private data 1391 * 1392 */ 1393 void intel_audio_init(struct drm_i915_private *dev_priv) 1394 { 1395 if (intel_lpe_audio_init(dev_priv) < 0) 1396 i915_audio_component_init(dev_priv); 1397 } 1398 1399 /** 1400 * intel_audio_deinit() - deinitialize the audio driver 1401 * @dev_priv: the i915 drm device private data 1402 * 1403 */ 1404 void intel_audio_deinit(struct drm_i915_private *dev_priv) 1405 { 1406 if (dev_priv->display.audio.lpe.platdev != NULL) 1407 intel_lpe_audio_teardown(dev_priv); 1408 else 1409 i915_audio_component_cleanup(dev_priv); 1410 } 1411