1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/component.h> 25 #include <linux/kernel.h> 26 27 #include <drm/drm_edid.h> 28 #include <drm/i915_component.h> 29 30 #include "i915_drv.h" 31 #include "intel_atomic.h" 32 #include "intel_audio.h" 33 #include "intel_cdclk.h" 34 #include "intel_display_types.h" 35 #include "intel_lpe_audio.h" 36 37 /** 38 * DOC: High Definition Audio over HDMI and Display Port 39 * 40 * The graphics and audio drivers together support High Definition Audio over 41 * HDMI and Display Port. The audio programming sequences are divided into audio 42 * codec and controller enable and disable sequences. The graphics driver 43 * handles the audio codec sequences, while the audio driver handles the audio 44 * controller sequences. 45 * 46 * The disable sequences must be performed before disabling the transcoder or 47 * port. The enable sequences may only be performed after enabling the 48 * transcoder and port, and after completed link training. Therefore the audio 49 * enable/disable sequences are part of the modeset sequence. 50 * 51 * The codec and controller sequences could be done either parallel or serial, 52 * but generally the ELDV/PD change in the codec sequence indicates to the audio 53 * driver that the controller sequence should start. Indeed, most of the 54 * co-operation between the graphics and audio drivers is handled via audio 55 * related registers. (The notable exception is the power management, not 56 * covered here.) 57 * 58 * The struct &i915_audio_component is used to interact between the graphics 59 * and audio drivers. The struct &i915_audio_component_ops @ops in it is 60 * defined in graphics driver and called in audio driver. The 61 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver. 62 */ 63 64 /* DP N/M table */ 65 #define LC_810M 810000 66 #define LC_540M 540000 67 #define LC_270M 270000 68 #define LC_162M 162000 69 70 struct dp_aud_n_m { 71 int sample_rate; 72 int clock; 73 u16 m; 74 u16 n; 75 }; 76 77 struct hdmi_aud_ncts { 78 int sample_rate; 79 int clock; 80 int n; 81 int cts; 82 }; 83 84 /* Values according to DP 1.4 Table 2-104 */ 85 static const struct dp_aud_n_m dp_aud_n_m[] = { 86 { 32000, LC_162M, 1024, 10125 }, 87 { 44100, LC_162M, 784, 5625 }, 88 { 48000, LC_162M, 512, 3375 }, 89 { 64000, LC_162M, 2048, 10125 }, 90 { 88200, LC_162M, 1568, 5625 }, 91 { 96000, LC_162M, 1024, 3375 }, 92 { 128000, LC_162M, 4096, 10125 }, 93 { 176400, LC_162M, 3136, 5625 }, 94 { 192000, LC_162M, 2048, 3375 }, 95 { 32000, LC_270M, 1024, 16875 }, 96 { 44100, LC_270M, 784, 9375 }, 97 { 48000, LC_270M, 512, 5625 }, 98 { 64000, LC_270M, 2048, 16875 }, 99 { 88200, LC_270M, 1568, 9375 }, 100 { 96000, LC_270M, 1024, 5625 }, 101 { 128000, LC_270M, 4096, 16875 }, 102 { 176400, LC_270M, 3136, 9375 }, 103 { 192000, LC_270M, 2048, 5625 }, 104 { 32000, LC_540M, 1024, 33750 }, 105 { 44100, LC_540M, 784, 18750 }, 106 { 48000, LC_540M, 512, 11250 }, 107 { 64000, LC_540M, 2048, 33750 }, 108 { 88200, LC_540M, 1568, 18750 }, 109 { 96000, LC_540M, 1024, 11250 }, 110 { 128000, LC_540M, 4096, 33750 }, 111 { 176400, LC_540M, 3136, 18750 }, 112 { 192000, LC_540M, 2048, 11250 }, 113 { 32000, LC_810M, 1024, 50625 }, 114 { 44100, LC_810M, 784, 28125 }, 115 { 48000, LC_810M, 512, 16875 }, 116 { 64000, LC_810M, 2048, 50625 }, 117 { 88200, LC_810M, 1568, 28125 }, 118 { 96000, LC_810M, 1024, 16875 }, 119 { 128000, LC_810M, 4096, 50625 }, 120 { 176400, LC_810M, 3136, 28125 }, 121 { 192000, LC_810M, 2048, 16875 }, 122 }; 123 124 static const struct dp_aud_n_m * 125 audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate) 126 { 127 int i; 128 129 for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) { 130 if (rate == dp_aud_n_m[i].sample_rate && 131 crtc_state->port_clock == dp_aud_n_m[i].clock) 132 return &dp_aud_n_m[i]; 133 } 134 135 return NULL; 136 } 137 138 static const struct { 139 int clock; 140 u32 config; 141 } hdmi_audio_clock[] = { 142 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, 143 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ 144 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, 145 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, 146 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, 147 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, 148 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, 149 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, 150 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, 151 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, 152 }; 153 154 /* HDMI N/CTS table */ 155 #define TMDS_297M 297000 156 #define TMDS_296M 296703 157 #define TMDS_594M 594000 158 #define TMDS_593M 593407 159 160 static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = { 161 { 32000, TMDS_296M, 5824, 421875 }, 162 { 32000, TMDS_297M, 3072, 222750 }, 163 { 32000, TMDS_593M, 5824, 843750 }, 164 { 32000, TMDS_594M, 3072, 445500 }, 165 { 44100, TMDS_296M, 4459, 234375 }, 166 { 44100, TMDS_297M, 4704, 247500 }, 167 { 44100, TMDS_593M, 8918, 937500 }, 168 { 44100, TMDS_594M, 9408, 990000 }, 169 { 88200, TMDS_296M, 8918, 234375 }, 170 { 88200, TMDS_297M, 9408, 247500 }, 171 { 88200, TMDS_593M, 17836, 937500 }, 172 { 88200, TMDS_594M, 18816, 990000 }, 173 { 176400, TMDS_296M, 17836, 234375 }, 174 { 176400, TMDS_297M, 18816, 247500 }, 175 { 176400, TMDS_593M, 35672, 937500 }, 176 { 176400, TMDS_594M, 37632, 990000 }, 177 { 48000, TMDS_296M, 5824, 281250 }, 178 { 48000, TMDS_297M, 5120, 247500 }, 179 { 48000, TMDS_593M, 5824, 562500 }, 180 { 48000, TMDS_594M, 6144, 594000 }, 181 { 96000, TMDS_296M, 11648, 281250 }, 182 { 96000, TMDS_297M, 10240, 247500 }, 183 { 96000, TMDS_593M, 11648, 562500 }, 184 { 96000, TMDS_594M, 12288, 594000 }, 185 { 192000, TMDS_296M, 23296, 281250 }, 186 { 192000, TMDS_297M, 20480, 247500 }, 187 { 192000, TMDS_593M, 23296, 562500 }, 188 { 192000, TMDS_594M, 24576, 594000 }, 189 }; 190 191 /* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/ 192 /* HDMI N/CTS table for 10 bit deep color(30 bpp)*/ 193 #define TMDS_371M 371250 194 #define TMDS_370M 370878 195 196 static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = { 197 { 32000, TMDS_370M, 5824, 527344 }, 198 { 32000, TMDS_371M, 6144, 556875 }, 199 { 44100, TMDS_370M, 8918, 585938 }, 200 { 44100, TMDS_371M, 4704, 309375 }, 201 { 88200, TMDS_370M, 17836, 585938 }, 202 { 88200, TMDS_371M, 9408, 309375 }, 203 { 176400, TMDS_370M, 35672, 585938 }, 204 { 176400, TMDS_371M, 18816, 309375 }, 205 { 48000, TMDS_370M, 11648, 703125 }, 206 { 48000, TMDS_371M, 5120, 309375 }, 207 { 96000, TMDS_370M, 23296, 703125 }, 208 { 96000, TMDS_371M, 10240, 309375 }, 209 { 192000, TMDS_370M, 46592, 703125 }, 210 { 192000, TMDS_371M, 20480, 309375 }, 211 }; 212 213 /* HDMI N/CTS table for 12 bit deep color(36 bpp)*/ 214 #define TMDS_445_5M 445500 215 #define TMDS_445M 445054 216 217 static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = { 218 { 32000, TMDS_445M, 5824, 632813 }, 219 { 32000, TMDS_445_5M, 4096, 445500 }, 220 { 44100, TMDS_445M, 8918, 703125 }, 221 { 44100, TMDS_445_5M, 4704, 371250 }, 222 { 88200, TMDS_445M, 17836, 703125 }, 223 { 88200, TMDS_445_5M, 9408, 371250 }, 224 { 176400, TMDS_445M, 35672, 703125 }, 225 { 176400, TMDS_445_5M, 18816, 371250 }, 226 { 48000, TMDS_445M, 5824, 421875 }, 227 { 48000, TMDS_445_5M, 5120, 371250 }, 228 { 96000, TMDS_445M, 11648, 421875 }, 229 { 96000, TMDS_445_5M, 10240, 371250 }, 230 { 192000, TMDS_445M, 23296, 421875 }, 231 { 192000, TMDS_445_5M, 20480, 371250 }, 232 }; 233 234 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ 235 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state) 236 { 237 const struct drm_display_mode *adjusted_mode = 238 &crtc_state->hw.adjusted_mode; 239 int i; 240 241 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { 242 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) 243 break; 244 } 245 246 if (i == ARRAY_SIZE(hdmi_audio_clock)) { 247 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", 248 adjusted_mode->crtc_clock); 249 i = 1; 250 } 251 252 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", 253 hdmi_audio_clock[i].clock, 254 hdmi_audio_clock[i].config); 255 256 return hdmi_audio_clock[i].config; 257 } 258 259 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state, 260 int rate) 261 { 262 const struct hdmi_aud_ncts *hdmi_ncts_table; 263 int i, size; 264 265 if (crtc_state->pipe_bpp == 36) { 266 hdmi_ncts_table = hdmi_aud_ncts_36bpp; 267 size = ARRAY_SIZE(hdmi_aud_ncts_36bpp); 268 } else if (crtc_state->pipe_bpp == 30) { 269 hdmi_ncts_table = hdmi_aud_ncts_30bpp; 270 size = ARRAY_SIZE(hdmi_aud_ncts_30bpp); 271 } else { 272 hdmi_ncts_table = hdmi_aud_ncts_24bpp; 273 size = ARRAY_SIZE(hdmi_aud_ncts_24bpp); 274 } 275 276 for (i = 0; i < size; i++) { 277 if (rate == hdmi_ncts_table[i].sample_rate && 278 crtc_state->port_clock == hdmi_ncts_table[i].clock) { 279 return hdmi_ncts_table[i].n; 280 } 281 } 282 return 0; 283 } 284 285 static bool intel_eld_uptodate(struct drm_connector *connector, 286 i915_reg_t reg_eldv, u32 bits_eldv, 287 i915_reg_t reg_elda, u32 bits_elda, 288 i915_reg_t reg_edid) 289 { 290 struct drm_i915_private *dev_priv = to_i915(connector->dev); 291 const u8 *eld = connector->eld; 292 u32 tmp; 293 int i; 294 295 tmp = intel_de_read(dev_priv, reg_eldv); 296 tmp &= bits_eldv; 297 298 if (!tmp) 299 return false; 300 301 tmp = intel_de_read(dev_priv, reg_elda); 302 tmp &= ~bits_elda; 303 intel_de_write(dev_priv, reg_elda, tmp); 304 305 for (i = 0; i < drm_eld_size(eld) / 4; i++) 306 if (intel_de_read(dev_priv, reg_edid) != *((const u32 *)eld + i)) 307 return false; 308 309 return true; 310 } 311 312 static void g4x_audio_codec_disable(struct intel_encoder *encoder, 313 const struct intel_crtc_state *old_crtc_state, 314 const struct drm_connector_state *old_conn_state) 315 { 316 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 317 u32 eldv, tmp; 318 319 drm_dbg_kms(&dev_priv->drm, "Disable audio codec\n"); 320 321 tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID); 322 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) 323 eldv = G4X_ELDV_DEVCL_DEVBLC; 324 else 325 eldv = G4X_ELDV_DEVCTG; 326 327 /* Invalidate ELD */ 328 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST); 329 tmp &= ~eldv; 330 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp); 331 } 332 333 static void g4x_audio_codec_enable(struct intel_encoder *encoder, 334 const struct intel_crtc_state *crtc_state, 335 const struct drm_connector_state *conn_state) 336 { 337 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 338 struct drm_connector *connector = conn_state->connector; 339 const u8 *eld = connector->eld; 340 u32 eldv; 341 u32 tmp; 342 int len, i; 343 344 drm_dbg_kms(&dev_priv->drm, "Enable audio codec, %u bytes ELD\n", 345 drm_eld_size(eld)); 346 347 tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID); 348 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) 349 eldv = G4X_ELDV_DEVCL_DEVBLC; 350 else 351 eldv = G4X_ELDV_DEVCTG; 352 353 if (intel_eld_uptodate(connector, 354 G4X_AUD_CNTL_ST, eldv, 355 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK, 356 G4X_HDMIW_HDMIEDID)) 357 return; 358 359 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST); 360 tmp &= ~(eldv | G4X_ELD_ADDR_MASK); 361 len = (tmp >> 9) & 0x1f; /* ELD buffer size */ 362 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp); 363 364 len = min(drm_eld_size(eld) / 4, len); 365 drm_dbg(&dev_priv->drm, "ELD size %d\n", len); 366 for (i = 0; i < len; i++) 367 intel_de_write(dev_priv, G4X_HDMIW_HDMIEDID, 368 *((const u32 *)eld + i)); 369 370 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST); 371 tmp |= eldv; 372 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp); 373 } 374 375 static void 376 hsw_dp_audio_config_update(struct intel_encoder *encoder, 377 const struct intel_crtc_state *crtc_state) 378 { 379 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 380 struct i915_audio_component *acomp = dev_priv->audio_component; 381 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 382 enum port port = encoder->port; 383 const struct dp_aud_n_m *nm; 384 int rate; 385 u32 tmp; 386 387 rate = acomp ? acomp->aud_sample_rate[port] : 0; 388 nm = audio_config_dp_get_n_m(crtc_state, rate); 389 if (nm) 390 drm_dbg_kms(&dev_priv->drm, "using Maud %u, Naud %u\n", nm->m, 391 nm->n); 392 else 393 drm_dbg_kms(&dev_priv->drm, "using automatic Maud, Naud\n"); 394 395 tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder)); 396 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 397 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 398 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 399 tmp |= AUD_CONFIG_N_VALUE_INDEX; 400 401 if (nm) { 402 tmp &= ~AUD_CONFIG_N_MASK; 403 tmp |= AUD_CONFIG_N(nm->n); 404 tmp |= AUD_CONFIG_N_PROG_ENABLE; 405 } 406 407 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp); 408 409 tmp = intel_de_read(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); 410 tmp &= ~AUD_CONFIG_M_MASK; 411 tmp &= ~AUD_M_CTS_M_VALUE_INDEX; 412 tmp &= ~AUD_M_CTS_M_PROG_ENABLE; 413 414 if (nm) { 415 tmp |= nm->m; 416 tmp |= AUD_M_CTS_M_VALUE_INDEX; 417 tmp |= AUD_M_CTS_M_PROG_ENABLE; 418 } 419 420 intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 421 } 422 423 static void 424 hsw_hdmi_audio_config_update(struct intel_encoder *encoder, 425 const struct intel_crtc_state *crtc_state) 426 { 427 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 428 struct i915_audio_component *acomp = dev_priv->audio_component; 429 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 430 enum port port = encoder->port; 431 int n, rate; 432 u32 tmp; 433 434 rate = acomp ? acomp->aud_sample_rate[port] : 0; 435 436 tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder)); 437 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 438 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 439 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 440 tmp |= audio_config_hdmi_pixel_clock(crtc_state); 441 442 n = audio_config_hdmi_get_n(crtc_state, rate); 443 if (n != 0) { 444 drm_dbg_kms(&dev_priv->drm, "using N %d\n", n); 445 446 tmp &= ~AUD_CONFIG_N_MASK; 447 tmp |= AUD_CONFIG_N(n); 448 tmp |= AUD_CONFIG_N_PROG_ENABLE; 449 } else { 450 drm_dbg_kms(&dev_priv->drm, "using automatic N\n"); 451 } 452 453 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp); 454 455 /* 456 * Let's disable "Enable CTS or M Prog bit" 457 * and let HW calculate the value 458 */ 459 tmp = intel_de_read(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); 460 tmp &= ~AUD_M_CTS_M_PROG_ENABLE; 461 tmp &= ~AUD_M_CTS_M_VALUE_INDEX; 462 intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 463 } 464 465 static void 466 hsw_audio_config_update(struct intel_encoder *encoder, 467 const struct intel_crtc_state *crtc_state) 468 { 469 if (intel_crtc_has_dp_encoder(crtc_state)) 470 hsw_dp_audio_config_update(encoder, crtc_state); 471 else 472 hsw_hdmi_audio_config_update(encoder, crtc_state); 473 } 474 475 static void hsw_audio_codec_disable(struct intel_encoder *encoder, 476 const struct intel_crtc_state *old_crtc_state, 477 const struct drm_connector_state *old_conn_state) 478 { 479 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 480 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 481 u32 tmp; 482 483 drm_dbg_kms(&dev_priv->drm, "Disable audio codec on transcoder %s\n", 484 transcoder_name(cpu_transcoder)); 485 486 mutex_lock(&dev_priv->av_mutex); 487 488 /* Disable timestamps */ 489 tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder)); 490 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 491 tmp |= AUD_CONFIG_N_PROG_ENABLE; 492 tmp &= ~AUD_CONFIG_UPPER_N_MASK; 493 tmp &= ~AUD_CONFIG_LOWER_N_MASK; 494 if (intel_crtc_has_dp_encoder(old_crtc_state)) 495 tmp |= AUD_CONFIG_N_VALUE_INDEX; 496 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp); 497 498 /* Invalidate ELD */ 499 tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD); 500 tmp &= ~AUDIO_ELD_VALID(cpu_transcoder); 501 tmp &= ~AUDIO_OUTPUT_ENABLE(cpu_transcoder); 502 intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp); 503 504 mutex_unlock(&dev_priv->av_mutex); 505 } 506 507 static void hsw_audio_codec_enable(struct intel_encoder *encoder, 508 const struct intel_crtc_state *crtc_state, 509 const struct drm_connector_state *conn_state) 510 { 511 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 512 struct drm_connector *connector = conn_state->connector; 513 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 514 const u8 *eld = connector->eld; 515 u32 tmp; 516 int len, i; 517 518 drm_dbg_kms(&dev_priv->drm, 519 "Enable audio codec on transcoder %s, %u bytes ELD\n", 520 transcoder_name(cpu_transcoder), drm_eld_size(eld)); 521 522 mutex_lock(&dev_priv->av_mutex); 523 524 /* Enable audio presence detect, invalidate ELD */ 525 tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD); 526 tmp |= AUDIO_OUTPUT_ENABLE(cpu_transcoder); 527 tmp &= ~AUDIO_ELD_VALID(cpu_transcoder); 528 intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp); 529 530 /* 531 * FIXME: We're supposed to wait for vblank here, but we have vblanks 532 * disabled during the mode set. The proper fix would be to push the 533 * rest of the setup into a vblank work item, queued here, but the 534 * infrastructure is not there yet. 535 */ 536 537 /* Reset ELD write address */ 538 tmp = intel_de_read(dev_priv, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder)); 539 tmp &= ~IBX_ELD_ADDRESS_MASK; 540 intel_de_write(dev_priv, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder), tmp); 541 542 /* Up to 84 bytes of hw ELD buffer */ 543 len = min(drm_eld_size(eld), 84); 544 for (i = 0; i < len / 4; i++) 545 intel_de_write(dev_priv, HSW_AUD_EDID_DATA(cpu_transcoder), 546 *((const u32 *)eld + i)); 547 548 /* ELD valid */ 549 tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD); 550 tmp |= AUDIO_ELD_VALID(cpu_transcoder); 551 intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp); 552 553 /* Enable timestamps */ 554 hsw_audio_config_update(encoder, crtc_state); 555 556 mutex_unlock(&dev_priv->av_mutex); 557 } 558 559 static void ilk_audio_codec_disable(struct intel_encoder *encoder, 560 const struct intel_crtc_state *old_crtc_state, 561 const struct drm_connector_state *old_conn_state) 562 { 563 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 564 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 565 enum pipe pipe = crtc->pipe; 566 enum port port = encoder->port; 567 u32 tmp, eldv; 568 i915_reg_t aud_config, aud_cntrl_st2; 569 570 drm_dbg_kms(&dev_priv->drm, 571 "Disable audio codec on [ENCODER:%d:%s], pipe %c\n", 572 encoder->base.base.id, encoder->base.name, 573 pipe_name(pipe)); 574 575 if (drm_WARN_ON(&dev_priv->drm, port == PORT_A)) 576 return; 577 578 if (HAS_PCH_IBX(dev_priv)) { 579 aud_config = IBX_AUD_CFG(pipe); 580 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 581 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 582 aud_config = VLV_AUD_CFG(pipe); 583 aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 584 } else { 585 aud_config = CPT_AUD_CFG(pipe); 586 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 587 } 588 589 /* Disable timestamps */ 590 tmp = intel_de_read(dev_priv, aud_config); 591 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 592 tmp |= AUD_CONFIG_N_PROG_ENABLE; 593 tmp &= ~AUD_CONFIG_UPPER_N_MASK; 594 tmp &= ~AUD_CONFIG_LOWER_N_MASK; 595 if (intel_crtc_has_dp_encoder(old_crtc_state)) 596 tmp |= AUD_CONFIG_N_VALUE_INDEX; 597 intel_de_write(dev_priv, aud_config, tmp); 598 599 eldv = IBX_ELD_VALID(port); 600 601 /* Invalidate ELD */ 602 tmp = intel_de_read(dev_priv, aud_cntrl_st2); 603 tmp &= ~eldv; 604 intel_de_write(dev_priv, aud_cntrl_st2, tmp); 605 } 606 607 static void ilk_audio_codec_enable(struct intel_encoder *encoder, 608 const struct intel_crtc_state *crtc_state, 609 const struct drm_connector_state *conn_state) 610 { 611 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 612 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 613 struct drm_connector *connector = conn_state->connector; 614 enum pipe pipe = crtc->pipe; 615 enum port port = encoder->port; 616 const u8 *eld = connector->eld; 617 u32 tmp, eldv; 618 int len, i; 619 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; 620 621 drm_dbg_kms(&dev_priv->drm, 622 "Enable audio codec on [ENCODER:%d:%s], pipe %c, %u bytes ELD\n", 623 encoder->base.base.id, encoder->base.name, 624 pipe_name(pipe), drm_eld_size(eld)); 625 626 if (drm_WARN_ON(&dev_priv->drm, port == PORT_A)) 627 return; 628 629 /* 630 * FIXME: We're supposed to wait for vblank here, but we have vblanks 631 * disabled during the mode set. The proper fix would be to push the 632 * rest of the setup into a vblank work item, queued here, but the 633 * infrastructure is not there yet. 634 */ 635 636 if (HAS_PCH_IBX(dev_priv)) { 637 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); 638 aud_config = IBX_AUD_CFG(pipe); 639 aud_cntl_st = IBX_AUD_CNTL_ST(pipe); 640 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 641 } else if (IS_VALLEYVIEW(dev_priv) || 642 IS_CHERRYVIEW(dev_priv)) { 643 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); 644 aud_config = VLV_AUD_CFG(pipe); 645 aud_cntl_st = VLV_AUD_CNTL_ST(pipe); 646 aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 647 } else { 648 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); 649 aud_config = CPT_AUD_CFG(pipe); 650 aud_cntl_st = CPT_AUD_CNTL_ST(pipe); 651 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 652 } 653 654 eldv = IBX_ELD_VALID(port); 655 656 /* Invalidate ELD */ 657 tmp = intel_de_read(dev_priv, aud_cntrl_st2); 658 tmp &= ~eldv; 659 intel_de_write(dev_priv, aud_cntrl_st2, tmp); 660 661 /* Reset ELD write address */ 662 tmp = intel_de_read(dev_priv, aud_cntl_st); 663 tmp &= ~IBX_ELD_ADDRESS_MASK; 664 intel_de_write(dev_priv, aud_cntl_st, tmp); 665 666 /* Up to 84 bytes of hw ELD buffer */ 667 len = min(drm_eld_size(eld), 84); 668 for (i = 0; i < len / 4; i++) 669 intel_de_write(dev_priv, hdmiw_hdmiedid, 670 *((const u32 *)eld + i)); 671 672 /* ELD valid */ 673 tmp = intel_de_read(dev_priv, aud_cntrl_st2); 674 tmp |= eldv; 675 intel_de_write(dev_priv, aud_cntrl_st2, tmp); 676 677 /* Enable timestamps */ 678 tmp = intel_de_read(dev_priv, aud_config); 679 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 680 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 681 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 682 if (intel_crtc_has_dp_encoder(crtc_state)) 683 tmp |= AUD_CONFIG_N_VALUE_INDEX; 684 else 685 tmp |= audio_config_hdmi_pixel_clock(crtc_state); 686 intel_de_write(dev_priv, aud_config, tmp); 687 } 688 689 /** 690 * intel_audio_codec_enable - Enable the audio codec for HD audio 691 * @encoder: encoder on which to enable audio 692 * @crtc_state: pointer to the current crtc state. 693 * @conn_state: pointer to the current connector state. 694 * 695 * The enable sequences may only be performed after enabling the transcoder and 696 * port, and after completed link training. 697 */ 698 void intel_audio_codec_enable(struct intel_encoder *encoder, 699 const struct intel_crtc_state *crtc_state, 700 const struct drm_connector_state *conn_state) 701 { 702 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 703 struct i915_audio_component *acomp = dev_priv->audio_component; 704 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 705 struct drm_connector *connector = conn_state->connector; 706 const struct drm_display_mode *adjusted_mode = 707 &crtc_state->hw.adjusted_mode; 708 enum port port = encoder->port; 709 enum pipe pipe = crtc->pipe; 710 711 /* FIXME precompute the ELD in .compute_config() */ 712 if (!connector->eld[0]) 713 drm_dbg_kms(&dev_priv->drm, 714 "Bogus ELD on [CONNECTOR:%d:%s]\n", 715 connector->base.id, connector->name); 716 717 drm_dbg(&dev_priv->drm, "ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 718 connector->base.id, 719 connector->name, 720 encoder->base.base.id, 721 encoder->base.name); 722 723 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; 724 725 if (dev_priv->display.audio_codec_enable) 726 dev_priv->display.audio_codec_enable(encoder, 727 crtc_state, 728 conn_state); 729 730 mutex_lock(&dev_priv->av_mutex); 731 encoder->audio_connector = connector; 732 733 /* referred in audio callbacks */ 734 dev_priv->av_enc_map[pipe] = encoder; 735 mutex_unlock(&dev_priv->av_mutex); 736 737 if (acomp && acomp->base.audio_ops && 738 acomp->base.audio_ops->pin_eld_notify) { 739 /* audio drivers expect pipe = -1 to indicate Non-MST cases */ 740 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 741 pipe = -1; 742 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 743 (int) port, (int) pipe); 744 } 745 746 intel_lpe_audio_notify(dev_priv, pipe, port, connector->eld, 747 crtc_state->port_clock, 748 intel_crtc_has_dp_encoder(crtc_state)); 749 } 750 751 /** 752 * intel_audio_codec_disable - Disable the audio codec for HD audio 753 * @encoder: encoder on which to disable audio 754 * @old_crtc_state: pointer to the old crtc state. 755 * @old_conn_state: pointer to the old connector state. 756 * 757 * The disable sequences must be performed before disabling the transcoder or 758 * port. 759 */ 760 void intel_audio_codec_disable(struct intel_encoder *encoder, 761 const struct intel_crtc_state *old_crtc_state, 762 const struct drm_connector_state *old_conn_state) 763 { 764 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 765 struct i915_audio_component *acomp = dev_priv->audio_component; 766 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 767 enum port port = encoder->port; 768 enum pipe pipe = crtc->pipe; 769 770 if (dev_priv->display.audio_codec_disable) 771 dev_priv->display.audio_codec_disable(encoder, 772 old_crtc_state, 773 old_conn_state); 774 775 mutex_lock(&dev_priv->av_mutex); 776 encoder->audio_connector = NULL; 777 dev_priv->av_enc_map[pipe] = NULL; 778 mutex_unlock(&dev_priv->av_mutex); 779 780 if (acomp && acomp->base.audio_ops && 781 acomp->base.audio_ops->pin_eld_notify) { 782 /* audio drivers expect pipe = -1 to indicate Non-MST cases */ 783 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 784 pipe = -1; 785 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 786 (int) port, (int) pipe); 787 } 788 789 intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false); 790 } 791 792 /** 793 * intel_init_audio_hooks - Set up chip specific audio hooks 794 * @dev_priv: device private 795 */ 796 void intel_init_audio_hooks(struct drm_i915_private *dev_priv) 797 { 798 if (IS_G4X(dev_priv)) { 799 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable; 800 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable; 801 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 802 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; 803 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; 804 } else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) { 805 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable; 806 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable; 807 } else if (HAS_PCH_SPLIT(dev_priv)) { 808 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; 809 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; 810 } 811 } 812 813 static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state, 814 struct intel_crtc *crtc, 815 bool enable) 816 { 817 struct intel_cdclk_state *cdclk_state; 818 int ret; 819 820 /* need to hold at least one crtc lock for the global state */ 821 ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx); 822 if (ret) 823 return ret; 824 825 cdclk_state = intel_atomic_get_cdclk_state(state); 826 if (IS_ERR(cdclk_state)) 827 return PTR_ERR(cdclk_state); 828 829 cdclk_state->force_min_cdclk_changed = true; 830 cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0; 831 832 ret = intel_atomic_lock_global_state(&cdclk_state->base); 833 if (ret) 834 return ret; 835 836 return drm_atomic_commit(&state->base); 837 } 838 839 static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv, 840 bool enable) 841 { 842 struct drm_modeset_acquire_ctx ctx; 843 struct drm_atomic_state *state; 844 struct intel_crtc *crtc; 845 int ret; 846 847 crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A); 848 if (!crtc) 849 return; 850 851 drm_modeset_acquire_init(&ctx, 0); 852 state = drm_atomic_state_alloc(&dev_priv->drm); 853 if (drm_WARN_ON(&dev_priv->drm, !state)) 854 return; 855 856 state->acquire_ctx = &ctx; 857 858 retry: 859 ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), crtc, 860 enable); 861 if (ret == -EDEADLK) { 862 drm_atomic_state_clear(state); 863 drm_modeset_backoff(&ctx); 864 goto retry; 865 } 866 867 drm_WARN_ON(&dev_priv->drm, ret); 868 869 drm_atomic_state_put(state); 870 871 drm_modeset_drop_locks(&ctx); 872 drm_modeset_acquire_fini(&ctx); 873 } 874 875 static unsigned long i915_audio_component_get_power(struct device *kdev) 876 { 877 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 878 intel_wakeref_t ret; 879 880 /* Catch potential impedance mismatches before they occur! */ 881 BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long)); 882 883 ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); 884 885 if (dev_priv->audio_power_refcount++ == 0) { 886 if (IS_TIGERLAKE(dev_priv) || IS_ICELAKE(dev_priv)) { 887 intel_de_write(dev_priv, AUD_FREQ_CNTRL, 888 dev_priv->audio_freq_cntrl); 889 drm_dbg_kms(&dev_priv->drm, 890 "restored AUD_FREQ_CNTRL to 0x%x\n", 891 dev_priv->audio_freq_cntrl); 892 } 893 894 /* Force CDCLK to 2*BCLK as long as we need audio powered. */ 895 if (IS_GEMINILAKE(dev_priv)) 896 glk_force_audio_cdclk(dev_priv, true); 897 898 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 899 intel_de_write(dev_priv, AUD_PIN_BUF_CTL, 900 (intel_de_read(dev_priv, AUD_PIN_BUF_CTL) | AUD_PIN_BUF_ENABLE)); 901 } 902 903 return ret; 904 } 905 906 static void i915_audio_component_put_power(struct device *kdev, 907 unsigned long cookie) 908 { 909 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 910 911 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */ 912 if (--dev_priv->audio_power_refcount == 0) 913 if (IS_GEMINILAKE(dev_priv)) 914 glk_force_audio_cdclk(dev_priv, false); 915 916 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie); 917 } 918 919 static void i915_audio_component_codec_wake_override(struct device *kdev, 920 bool enable) 921 { 922 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 923 unsigned long cookie; 924 u32 tmp; 925 926 if (!IS_GEN(dev_priv, 9)) 927 return; 928 929 cookie = i915_audio_component_get_power(kdev); 930 931 /* 932 * Enable/disable generating the codec wake signal, overriding the 933 * internal logic to generate the codec wake to controller. 934 */ 935 tmp = intel_de_read(dev_priv, HSW_AUD_CHICKENBIT); 936 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL; 937 intel_de_write(dev_priv, HSW_AUD_CHICKENBIT, tmp); 938 usleep_range(1000, 1500); 939 940 if (enable) { 941 tmp = intel_de_read(dev_priv, HSW_AUD_CHICKENBIT); 942 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL; 943 intel_de_write(dev_priv, HSW_AUD_CHICKENBIT, tmp); 944 usleep_range(1000, 1500); 945 } 946 947 i915_audio_component_put_power(kdev, cookie); 948 } 949 950 /* Get CDCLK in kHz */ 951 static int i915_audio_component_get_cdclk_freq(struct device *kdev) 952 { 953 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 954 955 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DDI(dev_priv))) 956 return -ENODEV; 957 958 return dev_priv->cdclk.hw.cdclk; 959 } 960 961 /* 962 * get the intel_encoder according to the parameter port and pipe 963 * intel_encoder is saved by the index of pipe 964 * MST & (pipe >= 0): return the av_enc_map[pipe], 965 * when port is matched 966 * MST & (pipe < 0): this is invalid 967 * Non-MST & (pipe >= 0): only pipe = 0 (the first device entry) 968 * will get the right intel_encoder with port matched 969 * Non-MST & (pipe < 0): get the right intel_encoder with port matched 970 */ 971 static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv, 972 int port, int pipe) 973 { 974 struct intel_encoder *encoder; 975 976 /* MST */ 977 if (pipe >= 0) { 978 if (drm_WARN_ON(&dev_priv->drm, 979 pipe >= ARRAY_SIZE(dev_priv->av_enc_map))) 980 return NULL; 981 982 encoder = dev_priv->av_enc_map[pipe]; 983 /* 984 * when bootup, audio driver may not know it is 985 * MST or not. So it will poll all the port & pipe 986 * combinations 987 */ 988 if (encoder != NULL && encoder->port == port && 989 encoder->type == INTEL_OUTPUT_DP_MST) 990 return encoder; 991 } 992 993 /* Non-MST */ 994 if (pipe > 0) 995 return NULL; 996 997 for_each_pipe(dev_priv, pipe) { 998 encoder = dev_priv->av_enc_map[pipe]; 999 if (encoder == NULL) 1000 continue; 1001 1002 if (encoder->type == INTEL_OUTPUT_DP_MST) 1003 continue; 1004 1005 if (port == encoder->port) 1006 return encoder; 1007 } 1008 1009 return NULL; 1010 } 1011 1012 static int i915_audio_component_sync_audio_rate(struct device *kdev, int port, 1013 int pipe, int rate) 1014 { 1015 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1016 struct i915_audio_component *acomp = dev_priv->audio_component; 1017 struct intel_encoder *encoder; 1018 struct intel_crtc *crtc; 1019 unsigned long cookie; 1020 int err = 0; 1021 1022 if (!HAS_DDI(dev_priv)) 1023 return 0; 1024 1025 cookie = i915_audio_component_get_power(kdev); 1026 mutex_lock(&dev_priv->av_mutex); 1027 1028 /* 1. get the pipe */ 1029 encoder = get_saved_enc(dev_priv, port, pipe); 1030 if (!encoder || !encoder->base.crtc) { 1031 drm_dbg_kms(&dev_priv->drm, "Not valid for port %c\n", 1032 port_name(port)); 1033 err = -ENODEV; 1034 goto unlock; 1035 } 1036 1037 crtc = to_intel_crtc(encoder->base.crtc); 1038 1039 /* port must be valid now, otherwise the pipe will be invalid */ 1040 acomp->aud_sample_rate[port] = rate; 1041 1042 hsw_audio_config_update(encoder, crtc->config); 1043 1044 unlock: 1045 mutex_unlock(&dev_priv->av_mutex); 1046 i915_audio_component_put_power(kdev, cookie); 1047 return err; 1048 } 1049 1050 static int i915_audio_component_get_eld(struct device *kdev, int port, 1051 int pipe, bool *enabled, 1052 unsigned char *buf, int max_bytes) 1053 { 1054 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1055 struct intel_encoder *intel_encoder; 1056 const u8 *eld; 1057 int ret = -EINVAL; 1058 1059 mutex_lock(&dev_priv->av_mutex); 1060 1061 intel_encoder = get_saved_enc(dev_priv, port, pipe); 1062 if (!intel_encoder) { 1063 drm_dbg_kms(&dev_priv->drm, "Not valid for port %c\n", 1064 port_name(port)); 1065 mutex_unlock(&dev_priv->av_mutex); 1066 return ret; 1067 } 1068 1069 ret = 0; 1070 *enabled = intel_encoder->audio_connector != NULL; 1071 if (*enabled) { 1072 eld = intel_encoder->audio_connector->eld; 1073 ret = drm_eld_size(eld); 1074 memcpy(buf, eld, min(max_bytes, ret)); 1075 } 1076 1077 mutex_unlock(&dev_priv->av_mutex); 1078 return ret; 1079 } 1080 1081 static const struct drm_audio_component_ops i915_audio_component_ops = { 1082 .owner = THIS_MODULE, 1083 .get_power = i915_audio_component_get_power, 1084 .put_power = i915_audio_component_put_power, 1085 .codec_wake_override = i915_audio_component_codec_wake_override, 1086 .get_cdclk_freq = i915_audio_component_get_cdclk_freq, 1087 .sync_audio_rate = i915_audio_component_sync_audio_rate, 1088 .get_eld = i915_audio_component_get_eld, 1089 }; 1090 1091 static int i915_audio_component_bind(struct device *i915_kdev, 1092 struct device *hda_kdev, void *data) 1093 { 1094 struct i915_audio_component *acomp = data; 1095 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); 1096 int i; 1097 1098 if (drm_WARN_ON(&dev_priv->drm, acomp->base.ops || acomp->base.dev)) 1099 return -EEXIST; 1100 1101 if (drm_WARN_ON(&dev_priv->drm, 1102 !device_link_add(hda_kdev, i915_kdev, 1103 DL_FLAG_STATELESS))) 1104 return -ENOMEM; 1105 1106 drm_modeset_lock_all(&dev_priv->drm); 1107 acomp->base.ops = &i915_audio_component_ops; 1108 acomp->base.dev = i915_kdev; 1109 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); 1110 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) 1111 acomp->aud_sample_rate[i] = 0; 1112 dev_priv->audio_component = acomp; 1113 drm_modeset_unlock_all(&dev_priv->drm); 1114 1115 return 0; 1116 } 1117 1118 static void i915_audio_component_unbind(struct device *i915_kdev, 1119 struct device *hda_kdev, void *data) 1120 { 1121 struct i915_audio_component *acomp = data; 1122 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); 1123 1124 drm_modeset_lock_all(&dev_priv->drm); 1125 acomp->base.ops = NULL; 1126 acomp->base.dev = NULL; 1127 dev_priv->audio_component = NULL; 1128 drm_modeset_unlock_all(&dev_priv->drm); 1129 1130 device_link_remove(hda_kdev, i915_kdev); 1131 } 1132 1133 static const struct component_ops i915_audio_component_bind_ops = { 1134 .bind = i915_audio_component_bind, 1135 .unbind = i915_audio_component_unbind, 1136 }; 1137 1138 /** 1139 * i915_audio_component_init - initialize and register the audio component 1140 * @dev_priv: i915 device instance 1141 * 1142 * This will register with the component framework a child component which 1143 * will bind dynamically to the snd_hda_intel driver's corresponding master 1144 * component when the latter is registered. During binding the child 1145 * initializes an instance of struct i915_audio_component which it receives 1146 * from the master. The master can then start to use the interface defined by 1147 * this struct. Each side can break the binding at any point by deregistering 1148 * its own component after which each side's component unbind callback is 1149 * called. 1150 * 1151 * We ignore any error during registration and continue with reduced 1152 * functionality (i.e. without HDMI audio). 1153 */ 1154 static void i915_audio_component_init(struct drm_i915_private *dev_priv) 1155 { 1156 int ret; 1157 1158 ret = component_add_typed(dev_priv->drm.dev, 1159 &i915_audio_component_bind_ops, 1160 I915_COMPONENT_AUDIO); 1161 if (ret < 0) { 1162 drm_err(&dev_priv->drm, 1163 "failed to add audio component (%d)\n", ret); 1164 /* continue with reduced functionality */ 1165 return; 1166 } 1167 1168 if (IS_TIGERLAKE(dev_priv) || IS_ICELAKE(dev_priv)) { 1169 dev_priv->audio_freq_cntrl = intel_de_read(dev_priv, 1170 AUD_FREQ_CNTRL); 1171 drm_dbg_kms(&dev_priv->drm, 1172 "init value of AUD_FREQ_CNTRL of 0x%x\n", 1173 dev_priv->audio_freq_cntrl); 1174 } 1175 1176 dev_priv->audio_component_registered = true; 1177 } 1178 1179 /** 1180 * i915_audio_component_cleanup - deregister the audio component 1181 * @dev_priv: i915 device instance 1182 * 1183 * Deregisters the audio component, breaking any existing binding to the 1184 * corresponding snd_hda_intel driver's master component. 1185 */ 1186 static void i915_audio_component_cleanup(struct drm_i915_private *dev_priv) 1187 { 1188 if (!dev_priv->audio_component_registered) 1189 return; 1190 1191 component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops); 1192 dev_priv->audio_component_registered = false; 1193 } 1194 1195 /** 1196 * intel_audio_init() - Initialize the audio driver either using 1197 * component framework or using lpe audio bridge 1198 * @dev_priv: the i915 drm device private data 1199 * 1200 */ 1201 void intel_audio_init(struct drm_i915_private *dev_priv) 1202 { 1203 if (intel_lpe_audio_init(dev_priv) < 0) 1204 i915_audio_component_init(dev_priv); 1205 } 1206 1207 /** 1208 * intel_audio_deinit() - deinitialize the audio driver 1209 * @dev_priv: the i915 drm device private data 1210 * 1211 */ 1212 void intel_audio_deinit(struct drm_i915_private *dev_priv) 1213 { 1214 if ((dev_priv)->lpe_audio.platdev != NULL) 1215 intel_lpe_audio_teardown(dev_priv); 1216 else 1217 i915_audio_component_cleanup(dev_priv); 1218 } 1219