1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/component.h> 25 #include <linux/kernel.h> 26 27 #include <drm/drm_edid.h> 28 #include <drm/i915_component.h> 29 30 #include "i915_drv.h" 31 #include "intel_atomic.h" 32 #include "intel_audio.h" 33 #include "intel_display_types.h" 34 #include "intel_lpe_audio.h" 35 36 /** 37 * DOC: High Definition Audio over HDMI and Display Port 38 * 39 * The graphics and audio drivers together support High Definition Audio over 40 * HDMI and Display Port. The audio programming sequences are divided into audio 41 * codec and controller enable and disable sequences. The graphics driver 42 * handles the audio codec sequences, while the audio driver handles the audio 43 * controller sequences. 44 * 45 * The disable sequences must be performed before disabling the transcoder or 46 * port. The enable sequences may only be performed after enabling the 47 * transcoder and port, and after completed link training. Therefore the audio 48 * enable/disable sequences are part of the modeset sequence. 49 * 50 * The codec and controller sequences could be done either parallel or serial, 51 * but generally the ELDV/PD change in the codec sequence indicates to the audio 52 * driver that the controller sequence should start. Indeed, most of the 53 * co-operation between the graphics and audio drivers is handled via audio 54 * related registers. (The notable exception is the power management, not 55 * covered here.) 56 * 57 * The struct &i915_audio_component is used to interact between the graphics 58 * and audio drivers. The struct &i915_audio_component_ops @ops in it is 59 * defined in graphics driver and called in audio driver. The 60 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver. 61 */ 62 63 /* DP N/M table */ 64 #define LC_810M 810000 65 #define LC_540M 540000 66 #define LC_270M 270000 67 #define LC_162M 162000 68 69 struct dp_aud_n_m { 70 int sample_rate; 71 int clock; 72 u16 m; 73 u16 n; 74 }; 75 76 struct hdmi_aud_ncts { 77 int sample_rate; 78 int clock; 79 int n; 80 int cts; 81 }; 82 83 /* Values according to DP 1.4 Table 2-104 */ 84 static const struct dp_aud_n_m dp_aud_n_m[] = { 85 { 32000, LC_162M, 1024, 10125 }, 86 { 44100, LC_162M, 784, 5625 }, 87 { 48000, LC_162M, 512, 3375 }, 88 { 64000, LC_162M, 2048, 10125 }, 89 { 88200, LC_162M, 1568, 5625 }, 90 { 96000, LC_162M, 1024, 3375 }, 91 { 128000, LC_162M, 4096, 10125 }, 92 { 176400, LC_162M, 3136, 5625 }, 93 { 192000, LC_162M, 2048, 3375 }, 94 { 32000, LC_270M, 1024, 16875 }, 95 { 44100, LC_270M, 784, 9375 }, 96 { 48000, LC_270M, 512, 5625 }, 97 { 64000, LC_270M, 2048, 16875 }, 98 { 88200, LC_270M, 1568, 9375 }, 99 { 96000, LC_270M, 1024, 5625 }, 100 { 128000, LC_270M, 4096, 16875 }, 101 { 176400, LC_270M, 3136, 9375 }, 102 { 192000, LC_270M, 2048, 5625 }, 103 { 32000, LC_540M, 1024, 33750 }, 104 { 44100, LC_540M, 784, 18750 }, 105 { 48000, LC_540M, 512, 11250 }, 106 { 64000, LC_540M, 2048, 33750 }, 107 { 88200, LC_540M, 1568, 18750 }, 108 { 96000, LC_540M, 1024, 11250 }, 109 { 128000, LC_540M, 4096, 33750 }, 110 { 176400, LC_540M, 3136, 18750 }, 111 { 192000, LC_540M, 2048, 11250 }, 112 { 32000, LC_810M, 1024, 50625 }, 113 { 44100, LC_810M, 784, 28125 }, 114 { 48000, LC_810M, 512, 16875 }, 115 { 64000, LC_810M, 2048, 50625 }, 116 { 88200, LC_810M, 1568, 28125 }, 117 { 96000, LC_810M, 1024, 16875 }, 118 { 128000, LC_810M, 4096, 50625 }, 119 { 176400, LC_810M, 3136, 28125 }, 120 { 192000, LC_810M, 2048, 16875 }, 121 }; 122 123 static const struct dp_aud_n_m * 124 audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate) 125 { 126 int i; 127 128 for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) { 129 if (rate == dp_aud_n_m[i].sample_rate && 130 crtc_state->port_clock == dp_aud_n_m[i].clock) 131 return &dp_aud_n_m[i]; 132 } 133 134 return NULL; 135 } 136 137 static const struct { 138 int clock; 139 u32 config; 140 } hdmi_audio_clock[] = { 141 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, 142 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ 143 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, 144 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, 145 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, 146 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, 147 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, 148 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, 149 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, 150 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, 151 }; 152 153 /* HDMI N/CTS table */ 154 #define TMDS_297M 297000 155 #define TMDS_296M 296703 156 #define TMDS_594M 594000 157 #define TMDS_593M 593407 158 159 static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = { 160 { 32000, TMDS_296M, 5824, 421875 }, 161 { 32000, TMDS_297M, 3072, 222750 }, 162 { 32000, TMDS_593M, 5824, 843750 }, 163 { 32000, TMDS_594M, 3072, 445500 }, 164 { 44100, TMDS_296M, 4459, 234375 }, 165 { 44100, TMDS_297M, 4704, 247500 }, 166 { 44100, TMDS_593M, 8918, 937500 }, 167 { 44100, TMDS_594M, 9408, 990000 }, 168 { 88200, TMDS_296M, 8918, 234375 }, 169 { 88200, TMDS_297M, 9408, 247500 }, 170 { 88200, TMDS_593M, 17836, 937500 }, 171 { 88200, TMDS_594M, 18816, 990000 }, 172 { 176400, TMDS_296M, 17836, 234375 }, 173 { 176400, TMDS_297M, 18816, 247500 }, 174 { 176400, TMDS_593M, 35672, 937500 }, 175 { 176400, TMDS_594M, 37632, 990000 }, 176 { 48000, TMDS_296M, 5824, 281250 }, 177 { 48000, TMDS_297M, 5120, 247500 }, 178 { 48000, TMDS_593M, 5824, 562500 }, 179 { 48000, TMDS_594M, 6144, 594000 }, 180 { 96000, TMDS_296M, 11648, 281250 }, 181 { 96000, TMDS_297M, 10240, 247500 }, 182 { 96000, TMDS_593M, 11648, 562500 }, 183 { 96000, TMDS_594M, 12288, 594000 }, 184 { 192000, TMDS_296M, 23296, 281250 }, 185 { 192000, TMDS_297M, 20480, 247500 }, 186 { 192000, TMDS_593M, 23296, 562500 }, 187 { 192000, TMDS_594M, 24576, 594000 }, 188 }; 189 190 /* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/ 191 /* HDMI N/CTS table for 10 bit deep color(30 bpp)*/ 192 #define TMDS_371M 371250 193 #define TMDS_370M 370878 194 195 static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = { 196 { 32000, TMDS_370M, 5824, 527344 }, 197 { 32000, TMDS_371M, 6144, 556875 }, 198 { 44100, TMDS_370M, 8918, 585938 }, 199 { 44100, TMDS_371M, 4704, 309375 }, 200 { 88200, TMDS_370M, 17836, 585938 }, 201 { 88200, TMDS_371M, 9408, 309375 }, 202 { 176400, TMDS_370M, 35672, 585938 }, 203 { 176400, TMDS_371M, 18816, 309375 }, 204 { 48000, TMDS_370M, 11648, 703125 }, 205 { 48000, TMDS_371M, 5120, 309375 }, 206 { 96000, TMDS_370M, 23296, 703125 }, 207 { 96000, TMDS_371M, 10240, 309375 }, 208 { 192000, TMDS_370M, 46592, 703125 }, 209 { 192000, TMDS_371M, 20480, 309375 }, 210 }; 211 212 /* HDMI N/CTS table for 12 bit deep color(36 bpp)*/ 213 #define TMDS_445_5M 445500 214 #define TMDS_445M 445054 215 216 static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = { 217 { 32000, TMDS_445M, 5824, 632813 }, 218 { 32000, TMDS_445_5M, 4096, 445500 }, 219 { 44100, TMDS_445M, 8918, 703125 }, 220 { 44100, TMDS_445_5M, 4704, 371250 }, 221 { 88200, TMDS_445M, 17836, 703125 }, 222 { 88200, TMDS_445_5M, 9408, 371250 }, 223 { 176400, TMDS_445M, 35672, 703125 }, 224 { 176400, TMDS_445_5M, 18816, 371250 }, 225 { 48000, TMDS_445M, 5824, 421875 }, 226 { 48000, TMDS_445_5M, 5120, 371250 }, 227 { 96000, TMDS_445M, 11648, 421875 }, 228 { 96000, TMDS_445_5M, 10240, 371250 }, 229 { 192000, TMDS_445M, 23296, 421875 }, 230 { 192000, TMDS_445_5M, 20480, 371250 }, 231 }; 232 233 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ 234 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state) 235 { 236 const struct drm_display_mode *adjusted_mode = 237 &crtc_state->base.adjusted_mode; 238 int i; 239 240 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { 241 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) 242 break; 243 } 244 245 if (i == ARRAY_SIZE(hdmi_audio_clock)) { 246 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", 247 adjusted_mode->crtc_clock); 248 i = 1; 249 } 250 251 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", 252 hdmi_audio_clock[i].clock, 253 hdmi_audio_clock[i].config); 254 255 return hdmi_audio_clock[i].config; 256 } 257 258 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state, 259 int rate) 260 { 261 const struct hdmi_aud_ncts *hdmi_ncts_table; 262 int i, size; 263 264 if (crtc_state->pipe_bpp == 36) { 265 hdmi_ncts_table = hdmi_aud_ncts_36bpp; 266 size = ARRAY_SIZE(hdmi_aud_ncts_36bpp); 267 } else if (crtc_state->pipe_bpp == 30) { 268 hdmi_ncts_table = hdmi_aud_ncts_30bpp; 269 size = ARRAY_SIZE(hdmi_aud_ncts_30bpp); 270 } else { 271 hdmi_ncts_table = hdmi_aud_ncts_24bpp; 272 size = ARRAY_SIZE(hdmi_aud_ncts_24bpp); 273 } 274 275 for (i = 0; i < size; i++) { 276 if (rate == hdmi_ncts_table[i].sample_rate && 277 crtc_state->port_clock == hdmi_ncts_table[i].clock) { 278 return hdmi_ncts_table[i].n; 279 } 280 } 281 return 0; 282 } 283 284 static bool intel_eld_uptodate(struct drm_connector *connector, 285 i915_reg_t reg_eldv, u32 bits_eldv, 286 i915_reg_t reg_elda, u32 bits_elda, 287 i915_reg_t reg_edid) 288 { 289 struct drm_i915_private *dev_priv = to_i915(connector->dev); 290 const u8 *eld = connector->eld; 291 u32 tmp; 292 int i; 293 294 tmp = I915_READ(reg_eldv); 295 tmp &= bits_eldv; 296 297 if (!tmp) 298 return false; 299 300 tmp = I915_READ(reg_elda); 301 tmp &= ~bits_elda; 302 I915_WRITE(reg_elda, tmp); 303 304 for (i = 0; i < drm_eld_size(eld) / 4; i++) 305 if (I915_READ(reg_edid) != *((const u32 *)eld + i)) 306 return false; 307 308 return true; 309 } 310 311 static void g4x_audio_codec_disable(struct intel_encoder *encoder, 312 const struct intel_crtc_state *old_crtc_state, 313 const struct drm_connector_state *old_conn_state) 314 { 315 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 316 u32 eldv, tmp; 317 318 DRM_DEBUG_KMS("Disable audio codec\n"); 319 320 tmp = I915_READ(G4X_AUD_VID_DID); 321 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) 322 eldv = G4X_ELDV_DEVCL_DEVBLC; 323 else 324 eldv = G4X_ELDV_DEVCTG; 325 326 /* Invalidate ELD */ 327 tmp = I915_READ(G4X_AUD_CNTL_ST); 328 tmp &= ~eldv; 329 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 330 } 331 332 static void g4x_audio_codec_enable(struct intel_encoder *encoder, 333 const struct intel_crtc_state *crtc_state, 334 const struct drm_connector_state *conn_state) 335 { 336 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 337 struct drm_connector *connector = conn_state->connector; 338 const u8 *eld = connector->eld; 339 u32 eldv; 340 u32 tmp; 341 int len, i; 342 343 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", drm_eld_size(eld)); 344 345 tmp = I915_READ(G4X_AUD_VID_DID); 346 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) 347 eldv = G4X_ELDV_DEVCL_DEVBLC; 348 else 349 eldv = G4X_ELDV_DEVCTG; 350 351 if (intel_eld_uptodate(connector, 352 G4X_AUD_CNTL_ST, eldv, 353 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK, 354 G4X_HDMIW_HDMIEDID)) 355 return; 356 357 tmp = I915_READ(G4X_AUD_CNTL_ST); 358 tmp &= ~(eldv | G4X_ELD_ADDR_MASK); 359 len = (tmp >> 9) & 0x1f; /* ELD buffer size */ 360 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 361 362 len = min(drm_eld_size(eld) / 4, len); 363 DRM_DEBUG_DRIVER("ELD size %d\n", len); 364 for (i = 0; i < len; i++) 365 I915_WRITE(G4X_HDMIW_HDMIEDID, *((const u32 *)eld + i)); 366 367 tmp = I915_READ(G4X_AUD_CNTL_ST); 368 tmp |= eldv; 369 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 370 } 371 372 static void 373 hsw_dp_audio_config_update(struct intel_encoder *encoder, 374 const struct intel_crtc_state *crtc_state) 375 { 376 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 377 struct i915_audio_component *acomp = dev_priv->audio_component; 378 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 379 enum port port = encoder->port; 380 const struct dp_aud_n_m *nm; 381 int rate; 382 u32 tmp; 383 384 rate = acomp ? acomp->aud_sample_rate[port] : 0; 385 nm = audio_config_dp_get_n_m(crtc_state, rate); 386 if (nm) 387 DRM_DEBUG_KMS("using Maud %u, Naud %u\n", nm->m, nm->n); 388 else 389 DRM_DEBUG_KMS("using automatic Maud, Naud\n"); 390 391 tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder)); 392 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 393 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 394 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 395 tmp |= AUD_CONFIG_N_VALUE_INDEX; 396 397 if (nm) { 398 tmp &= ~AUD_CONFIG_N_MASK; 399 tmp |= AUD_CONFIG_N(nm->n); 400 tmp |= AUD_CONFIG_N_PROG_ENABLE; 401 } 402 403 I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp); 404 405 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); 406 tmp &= ~AUD_CONFIG_M_MASK; 407 tmp &= ~AUD_M_CTS_M_VALUE_INDEX; 408 tmp &= ~AUD_M_CTS_M_PROG_ENABLE; 409 410 if (nm) { 411 tmp |= nm->m; 412 tmp |= AUD_M_CTS_M_VALUE_INDEX; 413 tmp |= AUD_M_CTS_M_PROG_ENABLE; 414 } 415 416 I915_WRITE(HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 417 } 418 419 static void 420 hsw_hdmi_audio_config_update(struct intel_encoder *encoder, 421 const struct intel_crtc_state *crtc_state) 422 { 423 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 424 struct i915_audio_component *acomp = dev_priv->audio_component; 425 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 426 enum port port = encoder->port; 427 int n, rate; 428 u32 tmp; 429 430 rate = acomp ? acomp->aud_sample_rate[port] : 0; 431 432 tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder)); 433 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 434 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 435 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 436 tmp |= audio_config_hdmi_pixel_clock(crtc_state); 437 438 n = audio_config_hdmi_get_n(crtc_state, rate); 439 if (n != 0) { 440 DRM_DEBUG_KMS("using N %d\n", n); 441 442 tmp &= ~AUD_CONFIG_N_MASK; 443 tmp |= AUD_CONFIG_N(n); 444 tmp |= AUD_CONFIG_N_PROG_ENABLE; 445 } else { 446 DRM_DEBUG_KMS("using automatic N\n"); 447 } 448 449 I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp); 450 451 /* 452 * Let's disable "Enable CTS or M Prog bit" 453 * and let HW calculate the value 454 */ 455 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); 456 tmp &= ~AUD_M_CTS_M_PROG_ENABLE; 457 tmp &= ~AUD_M_CTS_M_VALUE_INDEX; 458 I915_WRITE(HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 459 } 460 461 static void 462 hsw_audio_config_update(struct intel_encoder *encoder, 463 const struct intel_crtc_state *crtc_state) 464 { 465 if (intel_crtc_has_dp_encoder(crtc_state)) 466 hsw_dp_audio_config_update(encoder, crtc_state); 467 else 468 hsw_hdmi_audio_config_update(encoder, crtc_state); 469 } 470 471 static void hsw_audio_codec_disable(struct intel_encoder *encoder, 472 const struct intel_crtc_state *old_crtc_state, 473 const struct drm_connector_state *old_conn_state) 474 { 475 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 476 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 477 u32 tmp; 478 479 DRM_DEBUG_KMS("Disable audio codec on transcoder %s\n", 480 transcoder_name(cpu_transcoder)); 481 482 mutex_lock(&dev_priv->av_mutex); 483 484 /* Disable timestamps */ 485 tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder)); 486 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 487 tmp |= AUD_CONFIG_N_PROG_ENABLE; 488 tmp &= ~AUD_CONFIG_UPPER_N_MASK; 489 tmp &= ~AUD_CONFIG_LOWER_N_MASK; 490 if (intel_crtc_has_dp_encoder(old_crtc_state)) 491 tmp |= AUD_CONFIG_N_VALUE_INDEX; 492 I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp); 493 494 /* Invalidate ELD */ 495 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 496 tmp &= ~AUDIO_ELD_VALID(cpu_transcoder); 497 tmp &= ~AUDIO_OUTPUT_ENABLE(cpu_transcoder); 498 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 499 500 mutex_unlock(&dev_priv->av_mutex); 501 } 502 503 static void hsw_audio_codec_enable(struct intel_encoder *encoder, 504 const struct intel_crtc_state *crtc_state, 505 const struct drm_connector_state *conn_state) 506 { 507 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 508 struct drm_connector *connector = conn_state->connector; 509 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 510 const u8 *eld = connector->eld; 511 u32 tmp; 512 int len, i; 513 514 DRM_DEBUG_KMS("Enable audio codec on transcoder %s, %u bytes ELD\n", 515 transcoder_name(cpu_transcoder), drm_eld_size(eld)); 516 517 mutex_lock(&dev_priv->av_mutex); 518 519 /* Enable audio presence detect, invalidate ELD */ 520 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 521 tmp |= AUDIO_OUTPUT_ENABLE(cpu_transcoder); 522 tmp &= ~AUDIO_ELD_VALID(cpu_transcoder); 523 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 524 525 /* 526 * FIXME: We're supposed to wait for vblank here, but we have vblanks 527 * disabled during the mode set. The proper fix would be to push the 528 * rest of the setup into a vblank work item, queued here, but the 529 * infrastructure is not there yet. 530 */ 531 532 /* Reset ELD write address */ 533 tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(cpu_transcoder)); 534 tmp &= ~IBX_ELD_ADDRESS_MASK; 535 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(cpu_transcoder), tmp); 536 537 /* Up to 84 bytes of hw ELD buffer */ 538 len = min(drm_eld_size(eld), 84); 539 for (i = 0; i < len / 4; i++) 540 I915_WRITE(HSW_AUD_EDID_DATA(cpu_transcoder), *((const u32 *)eld + i)); 541 542 /* ELD valid */ 543 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 544 tmp |= AUDIO_ELD_VALID(cpu_transcoder); 545 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 546 547 /* Enable timestamps */ 548 hsw_audio_config_update(encoder, crtc_state); 549 550 mutex_unlock(&dev_priv->av_mutex); 551 } 552 553 static void ilk_audio_codec_disable(struct intel_encoder *encoder, 554 const struct intel_crtc_state *old_crtc_state, 555 const struct drm_connector_state *old_conn_state) 556 { 557 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 558 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); 559 enum pipe pipe = crtc->pipe; 560 enum port port = encoder->port; 561 u32 tmp, eldv; 562 i915_reg_t aud_config, aud_cntrl_st2; 563 564 DRM_DEBUG_KMS("Disable audio codec on [ENCODER:%d:%s], pipe %c\n", 565 encoder->base.base.id, encoder->base.name, 566 pipe_name(pipe)); 567 568 if (WARN_ON(port == PORT_A)) 569 return; 570 571 if (HAS_PCH_IBX(dev_priv)) { 572 aud_config = IBX_AUD_CFG(pipe); 573 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 574 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 575 aud_config = VLV_AUD_CFG(pipe); 576 aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 577 } else { 578 aud_config = CPT_AUD_CFG(pipe); 579 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 580 } 581 582 /* Disable timestamps */ 583 tmp = I915_READ(aud_config); 584 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 585 tmp |= AUD_CONFIG_N_PROG_ENABLE; 586 tmp &= ~AUD_CONFIG_UPPER_N_MASK; 587 tmp &= ~AUD_CONFIG_LOWER_N_MASK; 588 if (intel_crtc_has_dp_encoder(old_crtc_state)) 589 tmp |= AUD_CONFIG_N_VALUE_INDEX; 590 I915_WRITE(aud_config, tmp); 591 592 eldv = IBX_ELD_VALID(port); 593 594 /* Invalidate ELD */ 595 tmp = I915_READ(aud_cntrl_st2); 596 tmp &= ~eldv; 597 I915_WRITE(aud_cntrl_st2, tmp); 598 } 599 600 static void ilk_audio_codec_enable(struct intel_encoder *encoder, 601 const struct intel_crtc_state *crtc_state, 602 const struct drm_connector_state *conn_state) 603 { 604 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 605 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 606 struct drm_connector *connector = conn_state->connector; 607 enum pipe pipe = crtc->pipe; 608 enum port port = encoder->port; 609 const u8 *eld = connector->eld; 610 u32 tmp, eldv; 611 int len, i; 612 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; 613 614 DRM_DEBUG_KMS("Enable audio codec on [ENCODER:%d:%s], pipe %c, %u bytes ELD\n", 615 encoder->base.base.id, encoder->base.name, 616 pipe_name(pipe), drm_eld_size(eld)); 617 618 if (WARN_ON(port == PORT_A)) 619 return; 620 621 /* 622 * FIXME: We're supposed to wait for vblank here, but we have vblanks 623 * disabled during the mode set. The proper fix would be to push the 624 * rest of the setup into a vblank work item, queued here, but the 625 * infrastructure is not there yet. 626 */ 627 628 if (HAS_PCH_IBX(dev_priv)) { 629 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); 630 aud_config = IBX_AUD_CFG(pipe); 631 aud_cntl_st = IBX_AUD_CNTL_ST(pipe); 632 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 633 } else if (IS_VALLEYVIEW(dev_priv) || 634 IS_CHERRYVIEW(dev_priv)) { 635 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); 636 aud_config = VLV_AUD_CFG(pipe); 637 aud_cntl_st = VLV_AUD_CNTL_ST(pipe); 638 aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 639 } else { 640 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); 641 aud_config = CPT_AUD_CFG(pipe); 642 aud_cntl_st = CPT_AUD_CNTL_ST(pipe); 643 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 644 } 645 646 eldv = IBX_ELD_VALID(port); 647 648 /* Invalidate ELD */ 649 tmp = I915_READ(aud_cntrl_st2); 650 tmp &= ~eldv; 651 I915_WRITE(aud_cntrl_st2, tmp); 652 653 /* Reset ELD write address */ 654 tmp = I915_READ(aud_cntl_st); 655 tmp &= ~IBX_ELD_ADDRESS_MASK; 656 I915_WRITE(aud_cntl_st, tmp); 657 658 /* Up to 84 bytes of hw ELD buffer */ 659 len = min(drm_eld_size(eld), 84); 660 for (i = 0; i < len / 4; i++) 661 I915_WRITE(hdmiw_hdmiedid, *((const u32 *)eld + i)); 662 663 /* ELD valid */ 664 tmp = I915_READ(aud_cntrl_st2); 665 tmp |= eldv; 666 I915_WRITE(aud_cntrl_st2, tmp); 667 668 /* Enable timestamps */ 669 tmp = I915_READ(aud_config); 670 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 671 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 672 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 673 if (intel_crtc_has_dp_encoder(crtc_state)) 674 tmp |= AUD_CONFIG_N_VALUE_INDEX; 675 else 676 tmp |= audio_config_hdmi_pixel_clock(crtc_state); 677 I915_WRITE(aud_config, tmp); 678 } 679 680 /** 681 * intel_audio_codec_enable - Enable the audio codec for HD audio 682 * @encoder: encoder on which to enable audio 683 * @crtc_state: pointer to the current crtc state. 684 * @conn_state: pointer to the current connector state. 685 * 686 * The enable sequences may only be performed after enabling the transcoder and 687 * port, and after completed link training. 688 */ 689 void intel_audio_codec_enable(struct intel_encoder *encoder, 690 const struct intel_crtc_state *crtc_state, 691 const struct drm_connector_state *conn_state) 692 { 693 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 694 struct i915_audio_component *acomp = dev_priv->audio_component; 695 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 696 struct drm_connector *connector = conn_state->connector; 697 const struct drm_display_mode *adjusted_mode = 698 &crtc_state->base.adjusted_mode; 699 enum port port = encoder->port; 700 enum pipe pipe = crtc->pipe; 701 702 /* FIXME precompute the ELD in .compute_config() */ 703 if (!connector->eld[0]) 704 DRM_DEBUG_KMS("Bogus ELD on [CONNECTOR:%d:%s]\n", 705 connector->base.id, connector->name); 706 707 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 708 connector->base.id, 709 connector->name, 710 connector->encoder->base.id, 711 connector->encoder->name); 712 713 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; 714 715 if (dev_priv->display.audio_codec_enable) 716 dev_priv->display.audio_codec_enable(encoder, 717 crtc_state, 718 conn_state); 719 720 mutex_lock(&dev_priv->av_mutex); 721 encoder->audio_connector = connector; 722 723 /* referred in audio callbacks */ 724 dev_priv->av_enc_map[pipe] = encoder; 725 mutex_unlock(&dev_priv->av_mutex); 726 727 if (acomp && acomp->base.audio_ops && 728 acomp->base.audio_ops->pin_eld_notify) { 729 /* audio drivers expect pipe = -1 to indicate Non-MST cases */ 730 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 731 pipe = -1; 732 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 733 (int) port, (int) pipe); 734 } 735 736 intel_lpe_audio_notify(dev_priv, pipe, port, connector->eld, 737 crtc_state->port_clock, 738 intel_crtc_has_dp_encoder(crtc_state)); 739 } 740 741 /** 742 * intel_audio_codec_disable - Disable the audio codec for HD audio 743 * @encoder: encoder on which to disable audio 744 * @old_crtc_state: pointer to the old crtc state. 745 * @old_conn_state: pointer to the old connector state. 746 * 747 * The disable sequences must be performed before disabling the transcoder or 748 * port. 749 */ 750 void intel_audio_codec_disable(struct intel_encoder *encoder, 751 const struct intel_crtc_state *old_crtc_state, 752 const struct drm_connector_state *old_conn_state) 753 { 754 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 755 struct i915_audio_component *acomp = dev_priv->audio_component; 756 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); 757 enum port port = encoder->port; 758 enum pipe pipe = crtc->pipe; 759 760 if (dev_priv->display.audio_codec_disable) 761 dev_priv->display.audio_codec_disable(encoder, 762 old_crtc_state, 763 old_conn_state); 764 765 mutex_lock(&dev_priv->av_mutex); 766 encoder->audio_connector = NULL; 767 dev_priv->av_enc_map[pipe] = NULL; 768 mutex_unlock(&dev_priv->av_mutex); 769 770 if (acomp && acomp->base.audio_ops && 771 acomp->base.audio_ops->pin_eld_notify) { 772 /* audio drivers expect pipe = -1 to indicate Non-MST cases */ 773 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 774 pipe = -1; 775 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 776 (int) port, (int) pipe); 777 } 778 779 intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false); 780 } 781 782 /** 783 * intel_init_audio_hooks - Set up chip specific audio hooks 784 * @dev_priv: device private 785 */ 786 void intel_init_audio_hooks(struct drm_i915_private *dev_priv) 787 { 788 if (IS_G4X(dev_priv)) { 789 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable; 790 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable; 791 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 792 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; 793 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; 794 } else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) { 795 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable; 796 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable; 797 } else if (HAS_PCH_SPLIT(dev_priv)) { 798 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; 799 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; 800 } 801 } 802 803 static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv, 804 bool enable) 805 { 806 struct drm_modeset_acquire_ctx ctx; 807 struct drm_atomic_state *state; 808 int ret; 809 810 drm_modeset_acquire_init(&ctx, 0); 811 state = drm_atomic_state_alloc(&dev_priv->drm); 812 if (WARN_ON(!state)) 813 return; 814 815 state->acquire_ctx = &ctx; 816 817 retry: 818 to_intel_atomic_state(state)->cdclk.force_min_cdclk_changed = true; 819 to_intel_atomic_state(state)->cdclk.force_min_cdclk = 820 enable ? 2 * 96000 : 0; 821 822 /* Protects dev_priv->cdclk.force_min_cdclk */ 823 ret = intel_atomic_lock_global_state(to_intel_atomic_state(state)); 824 if (!ret) 825 ret = drm_atomic_commit(state); 826 827 if (ret == -EDEADLK) { 828 drm_atomic_state_clear(state); 829 drm_modeset_backoff(&ctx); 830 goto retry; 831 } 832 833 WARN_ON(ret); 834 835 drm_atomic_state_put(state); 836 837 drm_modeset_drop_locks(&ctx); 838 drm_modeset_acquire_fini(&ctx); 839 } 840 841 static unsigned long i915_audio_component_get_power(struct device *kdev) 842 { 843 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 844 intel_wakeref_t ret; 845 846 /* Catch potential impedance mismatches before they occur! */ 847 BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long)); 848 849 ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); 850 851 if (dev_priv->audio_power_refcount++ == 0) { 852 if (IS_TIGERLAKE(dev_priv) || IS_ICELAKE(dev_priv)) { 853 I915_WRITE(AUD_FREQ_CNTRL, dev_priv->audio_freq_cntrl); 854 DRM_DEBUG_KMS("restored AUD_FREQ_CNTRL to 0x%x\n", 855 dev_priv->audio_freq_cntrl); 856 } 857 858 /* Force CDCLK to 2*BCLK as long as we need audio powered. */ 859 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 860 glk_force_audio_cdclk(dev_priv, true); 861 862 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 863 I915_WRITE(AUD_PIN_BUF_CTL, 864 (I915_READ(AUD_PIN_BUF_CTL) | 865 AUD_PIN_BUF_ENABLE)); 866 } 867 868 return ret; 869 } 870 871 static void i915_audio_component_put_power(struct device *kdev, 872 unsigned long cookie) 873 { 874 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 875 876 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */ 877 if (--dev_priv->audio_power_refcount == 0) 878 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 879 glk_force_audio_cdclk(dev_priv, false); 880 881 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie); 882 } 883 884 static void i915_audio_component_codec_wake_override(struct device *kdev, 885 bool enable) 886 { 887 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 888 unsigned long cookie; 889 u32 tmp; 890 891 if (!IS_GEN(dev_priv, 9)) 892 return; 893 894 cookie = i915_audio_component_get_power(kdev); 895 896 /* 897 * Enable/disable generating the codec wake signal, overriding the 898 * internal logic to generate the codec wake to controller. 899 */ 900 tmp = I915_READ(HSW_AUD_CHICKENBIT); 901 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL; 902 I915_WRITE(HSW_AUD_CHICKENBIT, tmp); 903 usleep_range(1000, 1500); 904 905 if (enable) { 906 tmp = I915_READ(HSW_AUD_CHICKENBIT); 907 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL; 908 I915_WRITE(HSW_AUD_CHICKENBIT, tmp); 909 usleep_range(1000, 1500); 910 } 911 912 i915_audio_component_put_power(kdev, cookie); 913 } 914 915 /* Get CDCLK in kHz */ 916 static int i915_audio_component_get_cdclk_freq(struct device *kdev) 917 { 918 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 919 920 if (WARN_ON_ONCE(!HAS_DDI(dev_priv))) 921 return -ENODEV; 922 923 return dev_priv->cdclk.hw.cdclk; 924 } 925 926 /* 927 * get the intel_encoder according to the parameter port and pipe 928 * intel_encoder is saved by the index of pipe 929 * MST & (pipe >= 0): return the av_enc_map[pipe], 930 * when port is matched 931 * MST & (pipe < 0): this is invalid 932 * Non-MST & (pipe >= 0): only pipe = 0 (the first device entry) 933 * will get the right intel_encoder with port matched 934 * Non-MST & (pipe < 0): get the right intel_encoder with port matched 935 */ 936 static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv, 937 int port, int pipe) 938 { 939 struct intel_encoder *encoder; 940 941 /* MST */ 942 if (pipe >= 0) { 943 if (WARN_ON(pipe >= ARRAY_SIZE(dev_priv->av_enc_map))) 944 return NULL; 945 946 encoder = dev_priv->av_enc_map[pipe]; 947 /* 948 * when bootup, audio driver may not know it is 949 * MST or not. So it will poll all the port & pipe 950 * combinations 951 */ 952 if (encoder != NULL && encoder->port == port && 953 encoder->type == INTEL_OUTPUT_DP_MST) 954 return encoder; 955 } 956 957 /* Non-MST */ 958 if (pipe > 0) 959 return NULL; 960 961 for_each_pipe(dev_priv, pipe) { 962 encoder = dev_priv->av_enc_map[pipe]; 963 if (encoder == NULL) 964 continue; 965 966 if (encoder->type == INTEL_OUTPUT_DP_MST) 967 continue; 968 969 if (port == encoder->port) 970 return encoder; 971 } 972 973 return NULL; 974 } 975 976 static int i915_audio_component_sync_audio_rate(struct device *kdev, int port, 977 int pipe, int rate) 978 { 979 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 980 struct i915_audio_component *acomp = dev_priv->audio_component; 981 struct intel_encoder *encoder; 982 struct intel_crtc *crtc; 983 unsigned long cookie; 984 int err = 0; 985 986 if (!HAS_DDI(dev_priv)) 987 return 0; 988 989 cookie = i915_audio_component_get_power(kdev); 990 mutex_lock(&dev_priv->av_mutex); 991 992 /* 1. get the pipe */ 993 encoder = get_saved_enc(dev_priv, port, pipe); 994 if (!encoder || !encoder->base.crtc) { 995 DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port)); 996 err = -ENODEV; 997 goto unlock; 998 } 999 1000 crtc = to_intel_crtc(encoder->base.crtc); 1001 1002 /* port must be valid now, otherwise the pipe will be invalid */ 1003 acomp->aud_sample_rate[port] = rate; 1004 1005 hsw_audio_config_update(encoder, crtc->config); 1006 1007 unlock: 1008 mutex_unlock(&dev_priv->av_mutex); 1009 i915_audio_component_put_power(kdev, cookie); 1010 return err; 1011 } 1012 1013 static int i915_audio_component_get_eld(struct device *kdev, int port, 1014 int pipe, bool *enabled, 1015 unsigned char *buf, int max_bytes) 1016 { 1017 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1018 struct intel_encoder *intel_encoder; 1019 const u8 *eld; 1020 int ret = -EINVAL; 1021 1022 mutex_lock(&dev_priv->av_mutex); 1023 1024 intel_encoder = get_saved_enc(dev_priv, port, pipe); 1025 if (!intel_encoder) { 1026 DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port)); 1027 mutex_unlock(&dev_priv->av_mutex); 1028 return ret; 1029 } 1030 1031 ret = 0; 1032 *enabled = intel_encoder->audio_connector != NULL; 1033 if (*enabled) { 1034 eld = intel_encoder->audio_connector->eld; 1035 ret = drm_eld_size(eld); 1036 memcpy(buf, eld, min(max_bytes, ret)); 1037 } 1038 1039 mutex_unlock(&dev_priv->av_mutex); 1040 return ret; 1041 } 1042 1043 static const struct drm_audio_component_ops i915_audio_component_ops = { 1044 .owner = THIS_MODULE, 1045 .get_power = i915_audio_component_get_power, 1046 .put_power = i915_audio_component_put_power, 1047 .codec_wake_override = i915_audio_component_codec_wake_override, 1048 .get_cdclk_freq = i915_audio_component_get_cdclk_freq, 1049 .sync_audio_rate = i915_audio_component_sync_audio_rate, 1050 .get_eld = i915_audio_component_get_eld, 1051 }; 1052 1053 static int i915_audio_component_bind(struct device *i915_kdev, 1054 struct device *hda_kdev, void *data) 1055 { 1056 struct i915_audio_component *acomp = data; 1057 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); 1058 int i; 1059 1060 if (WARN_ON(acomp->base.ops || acomp->base.dev)) 1061 return -EEXIST; 1062 1063 if (WARN_ON(!device_link_add(hda_kdev, i915_kdev, DL_FLAG_STATELESS))) 1064 return -ENOMEM; 1065 1066 drm_modeset_lock_all(&dev_priv->drm); 1067 acomp->base.ops = &i915_audio_component_ops; 1068 acomp->base.dev = i915_kdev; 1069 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); 1070 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) 1071 acomp->aud_sample_rate[i] = 0; 1072 dev_priv->audio_component = acomp; 1073 drm_modeset_unlock_all(&dev_priv->drm); 1074 1075 return 0; 1076 } 1077 1078 static void i915_audio_component_unbind(struct device *i915_kdev, 1079 struct device *hda_kdev, void *data) 1080 { 1081 struct i915_audio_component *acomp = data; 1082 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); 1083 1084 drm_modeset_lock_all(&dev_priv->drm); 1085 acomp->base.ops = NULL; 1086 acomp->base.dev = NULL; 1087 dev_priv->audio_component = NULL; 1088 drm_modeset_unlock_all(&dev_priv->drm); 1089 1090 device_link_remove(hda_kdev, i915_kdev); 1091 } 1092 1093 static const struct component_ops i915_audio_component_bind_ops = { 1094 .bind = i915_audio_component_bind, 1095 .unbind = i915_audio_component_unbind, 1096 }; 1097 1098 /** 1099 * i915_audio_component_init - initialize and register the audio component 1100 * @dev_priv: i915 device instance 1101 * 1102 * This will register with the component framework a child component which 1103 * will bind dynamically to the snd_hda_intel driver's corresponding master 1104 * component when the latter is registered. During binding the child 1105 * initializes an instance of struct i915_audio_component which it receives 1106 * from the master. The master can then start to use the interface defined by 1107 * this struct. Each side can break the binding at any point by deregistering 1108 * its own component after which each side's component unbind callback is 1109 * called. 1110 * 1111 * We ignore any error during registration and continue with reduced 1112 * functionality (i.e. without HDMI audio). 1113 */ 1114 static void i915_audio_component_init(struct drm_i915_private *dev_priv) 1115 { 1116 int ret; 1117 1118 ret = component_add_typed(dev_priv->drm.dev, 1119 &i915_audio_component_bind_ops, 1120 I915_COMPONENT_AUDIO); 1121 if (ret < 0) { 1122 DRM_ERROR("failed to add audio component (%d)\n", ret); 1123 /* continue with reduced functionality */ 1124 return; 1125 } 1126 1127 if (IS_TIGERLAKE(dev_priv) || IS_ICELAKE(dev_priv)) { 1128 dev_priv->audio_freq_cntrl = I915_READ(AUD_FREQ_CNTRL); 1129 DRM_DEBUG_KMS("init value of AUD_FREQ_CNTRL of 0x%x\n", 1130 dev_priv->audio_freq_cntrl); 1131 } 1132 1133 dev_priv->audio_component_registered = true; 1134 } 1135 1136 /** 1137 * i915_audio_component_cleanup - deregister the audio component 1138 * @dev_priv: i915 device instance 1139 * 1140 * Deregisters the audio component, breaking any existing binding to the 1141 * corresponding snd_hda_intel driver's master component. 1142 */ 1143 static void i915_audio_component_cleanup(struct drm_i915_private *dev_priv) 1144 { 1145 if (!dev_priv->audio_component_registered) 1146 return; 1147 1148 component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops); 1149 dev_priv->audio_component_registered = false; 1150 } 1151 1152 /** 1153 * intel_audio_init() - Initialize the audio driver either using 1154 * component framework or using lpe audio bridge 1155 * @dev_priv: the i915 drm device private data 1156 * 1157 */ 1158 void intel_audio_init(struct drm_i915_private *dev_priv) 1159 { 1160 if (intel_lpe_audio_init(dev_priv) < 0) 1161 i915_audio_component_init(dev_priv); 1162 } 1163 1164 /** 1165 * intel_audio_deinit() - deinitialize the audio driver 1166 * @dev_priv: the i915 drm device private data 1167 * 1168 */ 1169 void intel_audio_deinit(struct drm_i915_private *dev_priv) 1170 { 1171 if ((dev_priv)->lpe_audio.platdev != NULL) 1172 intel_lpe_audio_teardown(dev_priv); 1173 else 1174 i915_audio_component_cleanup(dev_priv); 1175 } 1176