1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 /** 25 * DOC: atomic plane helpers 26 * 27 * The functions here are used by the atomic plane helper functions to 28 * implement legacy plane updates (i.e., drm_plane->update_plane() and 29 * drm_plane->disable_plane()). This allows plane updates to use the 30 * atomic state infrastructure and perform plane updates as separate 31 * prepare/check/commit/cleanup steps. 32 */ 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_fourcc.h> 36 #include <drm/drm_plane_helper.h> 37 38 #include "i915_trace.h" 39 #include "intel_atomic_plane.h" 40 #include "intel_cdclk.h" 41 #include "intel_display_types.h" 42 #include "intel_pm.h" 43 #include "intel_sprite.h" 44 45 static void intel_plane_state_reset(struct intel_plane_state *plane_state, 46 struct intel_plane *plane) 47 { 48 memset(plane_state, 0, sizeof(*plane_state)); 49 50 __drm_atomic_helper_plane_state_reset(&plane_state->uapi, &plane->base); 51 52 plane_state->scaler_id = -1; 53 } 54 55 struct intel_plane *intel_plane_alloc(void) 56 { 57 struct intel_plane_state *plane_state; 58 struct intel_plane *plane; 59 60 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 61 if (!plane) 62 return ERR_PTR(-ENOMEM); 63 64 plane_state = kzalloc(sizeof(*plane_state), GFP_KERNEL); 65 if (!plane_state) { 66 kfree(plane); 67 return ERR_PTR(-ENOMEM); 68 } 69 70 intel_plane_state_reset(plane_state, plane); 71 72 plane->base.state = &plane_state->uapi; 73 74 return plane; 75 } 76 77 void intel_plane_free(struct intel_plane *plane) 78 { 79 intel_plane_destroy_state(&plane->base, plane->base.state); 80 kfree(plane); 81 } 82 83 /** 84 * intel_plane_duplicate_state - duplicate plane state 85 * @plane: drm plane 86 * 87 * Allocates and returns a copy of the plane state (both common and 88 * Intel-specific) for the specified plane. 89 * 90 * Returns: The newly allocated plane state, or NULL on failure. 91 */ 92 struct drm_plane_state * 93 intel_plane_duplicate_state(struct drm_plane *plane) 94 { 95 struct intel_plane_state *intel_state; 96 97 intel_state = to_intel_plane_state(plane->state); 98 intel_state = kmemdup(intel_state, sizeof(*intel_state), GFP_KERNEL); 99 100 if (!intel_state) 101 return NULL; 102 103 __drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi); 104 105 intel_state->vma = NULL; 106 intel_state->flags = 0; 107 108 /* add reference to fb */ 109 if (intel_state->hw.fb) 110 drm_framebuffer_get(intel_state->hw.fb); 111 112 return &intel_state->uapi; 113 } 114 115 /** 116 * intel_plane_destroy_state - destroy plane state 117 * @plane: drm plane 118 * @state: state object to destroy 119 * 120 * Destroys the plane state (both common and Intel-specific) for the 121 * specified plane. 122 */ 123 void 124 intel_plane_destroy_state(struct drm_plane *plane, 125 struct drm_plane_state *state) 126 { 127 struct intel_plane_state *plane_state = to_intel_plane_state(state); 128 drm_WARN_ON(plane->dev, plane_state->vma); 129 130 __drm_atomic_helper_plane_destroy_state(&plane_state->uapi); 131 if (plane_state->hw.fb) 132 drm_framebuffer_put(plane_state->hw.fb); 133 kfree(plane_state); 134 } 135 136 unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state, 137 const struct intel_plane_state *plane_state) 138 { 139 unsigned int src_w, src_h, dst_w, dst_h; 140 unsigned int pixel_rate = crtc_state->pixel_rate; 141 142 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 143 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 144 dst_w = drm_rect_width(&plane_state->uapi.dst); 145 dst_h = drm_rect_height(&plane_state->uapi.dst); 146 147 /* Downscaling limits the maximum pixel rate */ 148 dst_w = min(src_w, dst_w); 149 dst_h = min(src_h, dst_h); 150 151 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, src_w * src_h), 152 dst_w * dst_h); 153 } 154 155 unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state, 156 const struct intel_plane_state *plane_state) 157 { 158 const struct drm_framebuffer *fb = plane_state->hw.fb; 159 unsigned int cpp; 160 unsigned int pixel_rate; 161 162 if (!plane_state->uapi.visible) 163 return 0; 164 165 pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); 166 167 cpp = fb->format->cpp[0]; 168 169 /* 170 * Based on HSD#:1408715493 171 * NV12 cpp == 4, P010 cpp == 8 172 * 173 * FIXME what is the logic behind this? 174 */ 175 if (fb->format->is_yuv && fb->format->num_planes > 1) 176 cpp *= 4; 177 178 return pixel_rate * cpp; 179 } 180 181 int intel_plane_calc_min_cdclk(struct intel_atomic_state *state, 182 struct intel_plane *plane, 183 bool *need_cdclk_calc) 184 { 185 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 186 const struct intel_plane_state *plane_state = 187 intel_atomic_get_new_plane_state(state, plane); 188 struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc); 189 const struct intel_cdclk_state *cdclk_state; 190 const struct intel_crtc_state *old_crtc_state; 191 struct intel_crtc_state *new_crtc_state; 192 193 if (!plane_state->uapi.visible || !plane->min_cdclk) 194 return 0; 195 196 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 197 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 198 199 new_crtc_state->min_cdclk[plane->id] = 200 plane->min_cdclk(new_crtc_state, plane_state); 201 202 /* 203 * No need to check against the cdclk state if 204 * the min cdclk for the plane doesn't increase. 205 * 206 * Ie. we only ever increase the cdclk due to plane 207 * requirements. This can reduce back and forth 208 * display blinking due to constant cdclk changes. 209 */ 210 if (new_crtc_state->min_cdclk[plane->id] <= 211 old_crtc_state->min_cdclk[plane->id]) 212 return 0; 213 214 cdclk_state = intel_atomic_get_cdclk_state(state); 215 if (IS_ERR(cdclk_state)) 216 return PTR_ERR(cdclk_state); 217 218 /* 219 * No need to recalculate the cdclk state if 220 * the min cdclk for the pipe doesn't increase. 221 * 222 * Ie. we only ever increase the cdclk due to plane 223 * requirements. This can reduce back and forth 224 * display blinking due to constant cdclk changes. 225 */ 226 if (new_crtc_state->min_cdclk[plane->id] <= 227 cdclk_state->min_cdclk[crtc->pipe]) 228 return 0; 229 230 drm_dbg_kms(&dev_priv->drm, 231 "[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n", 232 plane->base.base.id, plane->base.name, 233 new_crtc_state->min_cdclk[plane->id], 234 crtc->base.base.id, crtc->base.name, 235 cdclk_state->min_cdclk[crtc->pipe]); 236 *need_cdclk_calc = true; 237 238 return 0; 239 } 240 241 static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state) 242 { 243 if (plane_state->hw.fb) 244 drm_framebuffer_put(plane_state->hw.fb); 245 246 memset(&plane_state->hw, 0, sizeof(plane_state->hw)); 247 } 248 249 void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state, 250 const struct intel_plane_state *from_plane_state) 251 { 252 intel_plane_clear_hw_state(plane_state); 253 254 plane_state->hw.crtc = from_plane_state->uapi.crtc; 255 plane_state->hw.fb = from_plane_state->uapi.fb; 256 if (plane_state->hw.fb) 257 drm_framebuffer_get(plane_state->hw.fb); 258 259 plane_state->hw.alpha = from_plane_state->uapi.alpha; 260 plane_state->hw.pixel_blend_mode = 261 from_plane_state->uapi.pixel_blend_mode; 262 plane_state->hw.rotation = from_plane_state->uapi.rotation; 263 plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding; 264 plane_state->hw.color_range = from_plane_state->uapi.color_range; 265 plane_state->hw.scaling_filter = from_plane_state->uapi.scaling_filter; 266 } 267 268 void intel_plane_set_invisible(struct intel_crtc_state *crtc_state, 269 struct intel_plane_state *plane_state) 270 { 271 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 272 273 crtc_state->active_planes &= ~BIT(plane->id); 274 crtc_state->nv12_planes &= ~BIT(plane->id); 275 crtc_state->c8_planes &= ~BIT(plane->id); 276 crtc_state->data_rate[plane->id] = 0; 277 crtc_state->min_cdclk[plane->id] = 0; 278 279 plane_state->uapi.visible = false; 280 } 281 282 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state, 283 struct intel_crtc_state *new_crtc_state, 284 const struct intel_plane_state *old_plane_state, 285 struct intel_plane_state *new_plane_state) 286 { 287 struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane); 288 const struct drm_framebuffer *fb = new_plane_state->hw.fb; 289 int ret; 290 291 intel_plane_set_invisible(new_crtc_state, new_plane_state); 292 293 if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc) 294 return 0; 295 296 ret = plane->check_plane(new_crtc_state, new_plane_state); 297 if (ret) 298 return ret; 299 300 /* FIXME pre-g4x don't work like this */ 301 if (new_plane_state->uapi.visible) 302 new_crtc_state->active_planes |= BIT(plane->id); 303 304 if (new_plane_state->uapi.visible && 305 intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) 306 new_crtc_state->nv12_planes |= BIT(plane->id); 307 308 if (new_plane_state->uapi.visible && 309 fb->format->format == DRM_FORMAT_C8) 310 new_crtc_state->c8_planes |= BIT(plane->id); 311 312 if (new_plane_state->uapi.visible || old_plane_state->uapi.visible) 313 new_crtc_state->update_planes |= BIT(plane->id); 314 315 new_crtc_state->data_rate[plane->id] = 316 intel_plane_data_rate(new_crtc_state, new_plane_state); 317 318 return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state, 319 old_plane_state, new_plane_state); 320 } 321 322 static struct intel_crtc * 323 get_crtc_from_states(const struct intel_plane_state *old_plane_state, 324 const struct intel_plane_state *new_plane_state) 325 { 326 if (new_plane_state->uapi.crtc) 327 return to_intel_crtc(new_plane_state->uapi.crtc); 328 329 if (old_plane_state->uapi.crtc) 330 return to_intel_crtc(old_plane_state->uapi.crtc); 331 332 return NULL; 333 } 334 335 int intel_plane_atomic_check(struct intel_atomic_state *state, 336 struct intel_plane *plane) 337 { 338 struct intel_plane_state *new_plane_state = 339 intel_atomic_get_new_plane_state(state, plane); 340 const struct intel_plane_state *old_plane_state = 341 intel_atomic_get_old_plane_state(state, plane); 342 struct intel_crtc *crtc = 343 get_crtc_from_states(old_plane_state, new_plane_state); 344 const struct intel_crtc_state *old_crtc_state; 345 struct intel_crtc_state *new_crtc_state; 346 347 intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state); 348 new_plane_state->uapi.visible = false; 349 if (!crtc) 350 return 0; 351 352 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 353 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 354 355 return intel_plane_atomic_check_with_state(old_crtc_state, 356 new_crtc_state, 357 old_plane_state, 358 new_plane_state); 359 } 360 361 static struct intel_plane * 362 skl_next_plane_to_commit(struct intel_atomic_state *state, 363 struct intel_crtc *crtc, 364 struct skl_ddb_entry entries_y[I915_MAX_PLANES], 365 struct skl_ddb_entry entries_uv[I915_MAX_PLANES], 366 unsigned int *update_mask) 367 { 368 struct intel_crtc_state *crtc_state = 369 intel_atomic_get_new_crtc_state(state, crtc); 370 struct intel_plane_state *plane_state; 371 struct intel_plane *plane; 372 int i; 373 374 if (*update_mask == 0) 375 return NULL; 376 377 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 378 enum plane_id plane_id = plane->id; 379 380 if (crtc->pipe != plane->pipe || 381 !(*update_mask & BIT(plane_id))) 382 continue; 383 384 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id], 385 entries_y, 386 I915_MAX_PLANES, plane_id) || 387 skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_uv[plane_id], 388 entries_uv, 389 I915_MAX_PLANES, plane_id)) 390 continue; 391 392 *update_mask &= ~BIT(plane_id); 393 entries_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id]; 394 entries_uv[plane_id] = crtc_state->wm.skl.plane_ddb_uv[plane_id]; 395 396 return plane; 397 } 398 399 /* should never happen */ 400 drm_WARN_ON(state->base.dev, 1); 401 402 return NULL; 403 } 404 405 void intel_update_plane(struct intel_plane *plane, 406 const struct intel_crtc_state *crtc_state, 407 const struct intel_plane_state *plane_state) 408 { 409 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 410 411 trace_intel_update_plane(&plane->base, crtc); 412 413 if (crtc_state->uapi.async_flip && plane->async_flip) 414 plane->async_flip(plane, crtc_state, plane_state); 415 else 416 plane->update_plane(plane, crtc_state, plane_state); 417 } 418 419 void intel_disable_plane(struct intel_plane *plane, 420 const struct intel_crtc_state *crtc_state) 421 { 422 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 423 424 trace_intel_disable_plane(&plane->base, crtc); 425 plane->disable_plane(plane, crtc_state); 426 } 427 428 void skl_update_planes_on_crtc(struct intel_atomic_state *state, 429 struct intel_crtc *crtc) 430 { 431 struct intel_crtc_state *old_crtc_state = 432 intel_atomic_get_old_crtc_state(state, crtc); 433 struct intel_crtc_state *new_crtc_state = 434 intel_atomic_get_new_crtc_state(state, crtc); 435 struct skl_ddb_entry entries_y[I915_MAX_PLANES]; 436 struct skl_ddb_entry entries_uv[I915_MAX_PLANES]; 437 u32 update_mask = new_crtc_state->update_planes; 438 struct intel_plane *plane; 439 440 memcpy(entries_y, old_crtc_state->wm.skl.plane_ddb_y, 441 sizeof(old_crtc_state->wm.skl.plane_ddb_y)); 442 memcpy(entries_uv, old_crtc_state->wm.skl.plane_ddb_uv, 443 sizeof(old_crtc_state->wm.skl.plane_ddb_uv)); 444 445 while ((plane = skl_next_plane_to_commit(state, crtc, 446 entries_y, entries_uv, 447 &update_mask))) { 448 struct intel_plane_state *new_plane_state = 449 intel_atomic_get_new_plane_state(state, plane); 450 451 if (new_plane_state->uapi.visible || 452 new_plane_state->planar_slave) { 453 intel_update_plane(plane, new_crtc_state, new_plane_state); 454 } else { 455 intel_disable_plane(plane, new_crtc_state); 456 } 457 } 458 } 459 460 void i9xx_update_planes_on_crtc(struct intel_atomic_state *state, 461 struct intel_crtc *crtc) 462 { 463 struct intel_crtc_state *new_crtc_state = 464 intel_atomic_get_new_crtc_state(state, crtc); 465 u32 update_mask = new_crtc_state->update_planes; 466 struct intel_plane_state *new_plane_state; 467 struct intel_plane *plane; 468 int i; 469 470 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) { 471 if (crtc->pipe != plane->pipe || 472 !(update_mask & BIT(plane->id))) 473 continue; 474 475 if (new_plane_state->uapi.visible) 476 intel_update_plane(plane, new_crtc_state, new_plane_state); 477 else 478 intel_disable_plane(plane, new_crtc_state); 479 } 480 } 481 482 const struct drm_plane_helper_funcs intel_plane_helper_funcs = { 483 .prepare_fb = intel_prepare_plane_fb, 484 .cleanup_fb = intel_cleanup_plane_fb, 485 }; 486