1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 /** 25 * DOC: atomic plane helpers 26 * 27 * The functions here are used by the atomic plane helper functions to 28 * implement legacy plane updates (i.e., drm_plane->update_plane() and 29 * drm_plane->disable_plane()). This allows plane updates to use the 30 * atomic state infrastructure and perform plane updates as separate 31 * prepare/check/commit/cleanup steps. 32 */ 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_fourcc.h> 36 #include <drm/drm_plane_helper.h> 37 38 #include "gt/intel_rps.h" 39 40 #include "intel_atomic_plane.h" 41 #include "intel_cdclk.h" 42 #include "intel_display_trace.h" 43 #include "intel_display_types.h" 44 #include "intel_fb.h" 45 #include "intel_fb_pin.h" 46 #include "intel_pm.h" 47 #include "intel_sprite.h" 48 49 static void intel_plane_state_reset(struct intel_plane_state *plane_state, 50 struct intel_plane *plane) 51 { 52 memset(plane_state, 0, sizeof(*plane_state)); 53 54 __drm_atomic_helper_plane_state_reset(&plane_state->uapi, &plane->base); 55 56 plane_state->scaler_id = -1; 57 } 58 59 struct intel_plane *intel_plane_alloc(void) 60 { 61 struct intel_plane_state *plane_state; 62 struct intel_plane *plane; 63 64 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 65 if (!plane) 66 return ERR_PTR(-ENOMEM); 67 68 plane_state = kzalloc(sizeof(*plane_state), GFP_KERNEL); 69 if (!plane_state) { 70 kfree(plane); 71 return ERR_PTR(-ENOMEM); 72 } 73 74 intel_plane_state_reset(plane_state, plane); 75 76 plane->base.state = &plane_state->uapi; 77 78 return plane; 79 } 80 81 void intel_plane_free(struct intel_plane *plane) 82 { 83 intel_plane_destroy_state(&plane->base, plane->base.state); 84 kfree(plane); 85 } 86 87 /** 88 * intel_plane_duplicate_state - duplicate plane state 89 * @plane: drm plane 90 * 91 * Allocates and returns a copy of the plane state (both common and 92 * Intel-specific) for the specified plane. 93 * 94 * Returns: The newly allocated plane state, or NULL on failure. 95 */ 96 struct drm_plane_state * 97 intel_plane_duplicate_state(struct drm_plane *plane) 98 { 99 struct intel_plane_state *intel_state; 100 101 intel_state = to_intel_plane_state(plane->state); 102 intel_state = kmemdup(intel_state, sizeof(*intel_state), GFP_KERNEL); 103 104 if (!intel_state) 105 return NULL; 106 107 __drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi); 108 109 intel_state->ggtt_vma = NULL; 110 intel_state->dpt_vma = NULL; 111 intel_state->flags = 0; 112 intel_state->do_async_flip = false; 113 114 /* add reference to fb */ 115 if (intel_state->hw.fb) 116 drm_framebuffer_get(intel_state->hw.fb); 117 118 return &intel_state->uapi; 119 } 120 121 /** 122 * intel_plane_destroy_state - destroy plane state 123 * @plane: drm plane 124 * @state: state object to destroy 125 * 126 * Destroys the plane state (both common and Intel-specific) for the 127 * specified plane. 128 */ 129 void 130 intel_plane_destroy_state(struct drm_plane *plane, 131 struct drm_plane_state *state) 132 { 133 struct intel_plane_state *plane_state = to_intel_plane_state(state); 134 135 drm_WARN_ON(plane->dev, plane_state->ggtt_vma); 136 drm_WARN_ON(plane->dev, plane_state->dpt_vma); 137 138 __drm_atomic_helper_plane_destroy_state(&plane_state->uapi); 139 if (plane_state->hw.fb) 140 drm_framebuffer_put(plane_state->hw.fb); 141 kfree(plane_state); 142 } 143 144 unsigned int intel_adjusted_rate(const struct drm_rect *src, 145 const struct drm_rect *dst, 146 unsigned int rate) 147 { 148 unsigned int src_w, src_h, dst_w, dst_h; 149 150 src_w = drm_rect_width(src) >> 16; 151 src_h = drm_rect_height(src) >> 16; 152 dst_w = drm_rect_width(dst); 153 dst_h = drm_rect_height(dst); 154 155 /* Downscaling limits the maximum pixel rate */ 156 dst_w = min(src_w, dst_w); 157 dst_h = min(src_h, dst_h); 158 159 return DIV_ROUND_UP_ULL(mul_u32_u32(rate, src_w * src_h), 160 dst_w * dst_h); 161 } 162 163 unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state, 164 const struct intel_plane_state *plane_state) 165 { 166 /* 167 * Note we don't check for plane visibility here as 168 * we want to use this when calculating the cursor 169 * watermarks even if the cursor is fully offscreen. 170 * That depends on the src/dst rectangles being 171 * correctly populated whenever the watermark code 172 * considers the cursor to be visible, whether or not 173 * it is actually visible. 174 * 175 * See: intel_wm_plane_visible() and intel_check_cursor() 176 */ 177 178 return intel_adjusted_rate(&plane_state->uapi.src, 179 &plane_state->uapi.dst, 180 crtc_state->pixel_rate); 181 } 182 183 unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state, 184 const struct intel_plane_state *plane_state) 185 { 186 const struct drm_framebuffer *fb = plane_state->hw.fb; 187 unsigned int cpp; 188 unsigned int pixel_rate; 189 190 if (!plane_state->uapi.visible) 191 return 0; 192 193 pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); 194 195 cpp = fb->format->cpp[0]; 196 197 /* 198 * Based on HSD#:1408715493 199 * NV12 cpp == 4, P010 cpp == 8 200 * 201 * FIXME what is the logic behind this? 202 */ 203 if (fb->format->is_yuv && fb->format->num_planes > 1) 204 cpp *= 4; 205 206 return pixel_rate * cpp; 207 } 208 209 int intel_plane_calc_min_cdclk(struct intel_atomic_state *state, 210 struct intel_plane *plane, 211 bool *need_cdclk_calc) 212 { 213 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 214 const struct intel_plane_state *plane_state = 215 intel_atomic_get_new_plane_state(state, plane); 216 struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc); 217 const struct intel_cdclk_state *cdclk_state; 218 const struct intel_crtc_state *old_crtc_state; 219 struct intel_crtc_state *new_crtc_state; 220 221 if (!plane_state->uapi.visible || !plane->min_cdclk) 222 return 0; 223 224 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 225 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 226 227 new_crtc_state->min_cdclk[plane->id] = 228 plane->min_cdclk(new_crtc_state, plane_state); 229 230 /* 231 * No need to check against the cdclk state if 232 * the min cdclk for the plane doesn't increase. 233 * 234 * Ie. we only ever increase the cdclk due to plane 235 * requirements. This can reduce back and forth 236 * display blinking due to constant cdclk changes. 237 */ 238 if (new_crtc_state->min_cdclk[plane->id] <= 239 old_crtc_state->min_cdclk[plane->id]) 240 return 0; 241 242 cdclk_state = intel_atomic_get_cdclk_state(state); 243 if (IS_ERR(cdclk_state)) 244 return PTR_ERR(cdclk_state); 245 246 /* 247 * No need to recalculate the cdclk state if 248 * the min cdclk for the pipe doesn't increase. 249 * 250 * Ie. we only ever increase the cdclk due to plane 251 * requirements. This can reduce back and forth 252 * display blinking due to constant cdclk changes. 253 */ 254 if (new_crtc_state->min_cdclk[plane->id] <= 255 cdclk_state->min_cdclk[crtc->pipe]) 256 return 0; 257 258 drm_dbg_kms(&dev_priv->drm, 259 "[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n", 260 plane->base.base.id, plane->base.name, 261 new_crtc_state->min_cdclk[plane->id], 262 crtc->base.base.id, crtc->base.name, 263 cdclk_state->min_cdclk[crtc->pipe]); 264 *need_cdclk_calc = true; 265 266 return 0; 267 } 268 269 static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state) 270 { 271 if (plane_state->hw.fb) 272 drm_framebuffer_put(plane_state->hw.fb); 273 274 memset(&plane_state->hw, 0, sizeof(plane_state->hw)); 275 } 276 277 void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state, 278 const struct intel_plane_state *from_plane_state, 279 struct intel_crtc *crtc) 280 { 281 intel_plane_clear_hw_state(plane_state); 282 283 /* 284 * For the bigjoiner slave uapi.crtc will point at 285 * the master crtc. So we explicitly assign the right 286 * slave crtc to hw.crtc. uapi.crtc!=NULL simply indicates 287 * the plane is logically enabled on the uapi level. 288 */ 289 plane_state->hw.crtc = from_plane_state->uapi.crtc ? &crtc->base : NULL; 290 291 plane_state->hw.fb = from_plane_state->uapi.fb; 292 if (plane_state->hw.fb) 293 drm_framebuffer_get(plane_state->hw.fb); 294 295 plane_state->hw.alpha = from_plane_state->uapi.alpha; 296 plane_state->hw.pixel_blend_mode = 297 from_plane_state->uapi.pixel_blend_mode; 298 plane_state->hw.rotation = from_plane_state->uapi.rotation; 299 plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding; 300 plane_state->hw.color_range = from_plane_state->uapi.color_range; 301 plane_state->hw.scaling_filter = from_plane_state->uapi.scaling_filter; 302 303 plane_state->uapi.src = drm_plane_state_src(&from_plane_state->uapi); 304 plane_state->uapi.dst = drm_plane_state_dest(&from_plane_state->uapi); 305 } 306 307 void intel_plane_copy_hw_state(struct intel_plane_state *plane_state, 308 const struct intel_plane_state *from_plane_state) 309 { 310 intel_plane_clear_hw_state(plane_state); 311 312 memcpy(&plane_state->hw, &from_plane_state->hw, 313 sizeof(plane_state->hw)); 314 315 if (plane_state->hw.fb) 316 drm_framebuffer_get(plane_state->hw.fb); 317 } 318 319 void intel_plane_set_invisible(struct intel_crtc_state *crtc_state, 320 struct intel_plane_state *plane_state) 321 { 322 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 323 324 crtc_state->active_planes &= ~BIT(plane->id); 325 crtc_state->nv12_planes &= ~BIT(plane->id); 326 crtc_state->c8_planes &= ~BIT(plane->id); 327 crtc_state->data_rate[plane->id] = 0; 328 crtc_state->min_cdclk[plane->id] = 0; 329 330 plane_state->uapi.visible = false; 331 } 332 333 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state, 334 struct intel_crtc_state *new_crtc_state, 335 const struct intel_plane_state *old_plane_state, 336 struct intel_plane_state *new_plane_state) 337 { 338 struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane); 339 const struct drm_framebuffer *fb = new_plane_state->hw.fb; 340 int ret; 341 342 intel_plane_set_invisible(new_crtc_state, new_plane_state); 343 new_crtc_state->enabled_planes &= ~BIT(plane->id); 344 345 if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc) 346 return 0; 347 348 ret = plane->check_plane(new_crtc_state, new_plane_state); 349 if (ret) 350 return ret; 351 352 if (fb) 353 new_crtc_state->enabled_planes |= BIT(plane->id); 354 355 /* FIXME pre-g4x don't work like this */ 356 if (new_plane_state->uapi.visible) 357 new_crtc_state->active_planes |= BIT(plane->id); 358 359 if (new_plane_state->uapi.visible && 360 intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) 361 new_crtc_state->nv12_planes |= BIT(plane->id); 362 363 if (new_plane_state->uapi.visible && 364 fb->format->format == DRM_FORMAT_C8) 365 new_crtc_state->c8_planes |= BIT(plane->id); 366 367 if (new_plane_state->uapi.visible || old_plane_state->uapi.visible) 368 new_crtc_state->update_planes |= BIT(plane->id); 369 370 new_crtc_state->data_rate[plane->id] = 371 intel_plane_data_rate(new_crtc_state, new_plane_state); 372 373 return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state, 374 old_plane_state, new_plane_state); 375 } 376 377 static struct intel_plane * 378 intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id) 379 { 380 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 381 struct intel_plane *plane; 382 383 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 384 if (plane->id == plane_id) 385 return plane; 386 } 387 388 return NULL; 389 } 390 391 int intel_plane_atomic_check(struct intel_atomic_state *state, 392 struct intel_plane *plane) 393 { 394 struct drm_i915_private *i915 = to_i915(state->base.dev); 395 struct intel_plane_state *new_plane_state = 396 intel_atomic_get_new_plane_state(state, plane); 397 const struct intel_plane_state *old_plane_state = 398 intel_atomic_get_old_plane_state(state, plane); 399 const struct intel_plane_state *new_master_plane_state; 400 struct intel_crtc *crtc = intel_crtc_for_pipe(i915, plane->pipe); 401 const struct intel_crtc_state *old_crtc_state = 402 intel_atomic_get_old_crtc_state(state, crtc); 403 struct intel_crtc_state *new_crtc_state = 404 intel_atomic_get_new_crtc_state(state, crtc); 405 406 if (new_crtc_state && new_crtc_state->bigjoiner_slave) { 407 struct intel_plane *master_plane = 408 intel_crtc_get_plane(new_crtc_state->bigjoiner_linked_crtc, 409 plane->id); 410 411 new_master_plane_state = 412 intel_atomic_get_new_plane_state(state, master_plane); 413 } else { 414 new_master_plane_state = new_plane_state; 415 } 416 417 intel_plane_copy_uapi_to_hw_state(new_plane_state, 418 new_master_plane_state, 419 crtc); 420 421 new_plane_state->uapi.visible = false; 422 if (!new_crtc_state) 423 return 0; 424 425 return intel_plane_atomic_check_with_state(old_crtc_state, 426 new_crtc_state, 427 old_plane_state, 428 new_plane_state); 429 } 430 431 static struct intel_plane * 432 skl_next_plane_to_commit(struct intel_atomic_state *state, 433 struct intel_crtc *crtc, 434 struct skl_ddb_entry entries_y[I915_MAX_PLANES], 435 struct skl_ddb_entry entries_uv[I915_MAX_PLANES], 436 unsigned int *update_mask) 437 { 438 struct intel_crtc_state *crtc_state = 439 intel_atomic_get_new_crtc_state(state, crtc); 440 struct intel_plane_state *plane_state; 441 struct intel_plane *plane; 442 int i; 443 444 if (*update_mask == 0) 445 return NULL; 446 447 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 448 enum plane_id plane_id = plane->id; 449 450 if (crtc->pipe != plane->pipe || 451 !(*update_mask & BIT(plane_id))) 452 continue; 453 454 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id], 455 entries_y, 456 I915_MAX_PLANES, plane_id) || 457 skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_uv[plane_id], 458 entries_uv, 459 I915_MAX_PLANES, plane_id)) 460 continue; 461 462 *update_mask &= ~BIT(plane_id); 463 entries_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id]; 464 entries_uv[plane_id] = crtc_state->wm.skl.plane_ddb_uv[plane_id]; 465 466 return plane; 467 } 468 469 /* should never happen */ 470 drm_WARN_ON(state->base.dev, 1); 471 472 return NULL; 473 } 474 475 void intel_plane_update_noarm(struct intel_plane *plane, 476 const struct intel_crtc_state *crtc_state, 477 const struct intel_plane_state *plane_state) 478 { 479 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 480 481 trace_intel_plane_update_noarm(&plane->base, crtc); 482 483 if (plane->update_noarm) 484 plane->update_noarm(plane, crtc_state, plane_state); 485 } 486 487 void intel_plane_update_arm(struct intel_plane *plane, 488 const struct intel_crtc_state *crtc_state, 489 const struct intel_plane_state *plane_state) 490 { 491 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 492 493 trace_intel_plane_update_arm(&plane->base, crtc); 494 495 if (plane_state->do_async_flip) 496 plane->async_flip(plane, crtc_state, plane_state, true); 497 else 498 plane->update_arm(plane, crtc_state, plane_state); 499 } 500 501 void intel_plane_disable_arm(struct intel_plane *plane, 502 const struct intel_crtc_state *crtc_state) 503 { 504 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 505 506 trace_intel_plane_disable_arm(&plane->base, crtc); 507 plane->disable_arm(plane, crtc_state); 508 } 509 510 void intel_update_planes_on_crtc(struct intel_atomic_state *state, 511 struct intel_crtc *crtc) 512 { 513 struct intel_crtc_state *new_crtc_state = 514 intel_atomic_get_new_crtc_state(state, crtc); 515 u32 update_mask = new_crtc_state->update_planes; 516 struct intel_plane_state *new_plane_state; 517 struct intel_plane *plane; 518 int i; 519 520 if (new_crtc_state->uapi.async_flip) 521 return; 522 523 /* 524 * Since we only write non-arming registers here, 525 * the order does not matter even for skl+. 526 */ 527 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) { 528 if (crtc->pipe != plane->pipe || 529 !(update_mask & BIT(plane->id))) 530 continue; 531 532 /* TODO: for mailbox updates this should be skipped */ 533 if (new_plane_state->uapi.visible || 534 new_plane_state->planar_slave) 535 intel_plane_update_noarm(plane, new_crtc_state, new_plane_state); 536 } 537 } 538 539 void skl_arm_planes_on_crtc(struct intel_atomic_state *state, 540 struct intel_crtc *crtc) 541 { 542 struct intel_crtc_state *old_crtc_state = 543 intel_atomic_get_old_crtc_state(state, crtc); 544 struct intel_crtc_state *new_crtc_state = 545 intel_atomic_get_new_crtc_state(state, crtc); 546 struct skl_ddb_entry entries_y[I915_MAX_PLANES]; 547 struct skl_ddb_entry entries_uv[I915_MAX_PLANES]; 548 u32 update_mask = new_crtc_state->update_planes; 549 struct intel_plane *plane; 550 551 memcpy(entries_y, old_crtc_state->wm.skl.plane_ddb_y, 552 sizeof(old_crtc_state->wm.skl.plane_ddb_y)); 553 memcpy(entries_uv, old_crtc_state->wm.skl.plane_ddb_uv, 554 sizeof(old_crtc_state->wm.skl.plane_ddb_uv)); 555 556 while ((plane = skl_next_plane_to_commit(state, crtc, 557 entries_y, entries_uv, 558 &update_mask))) { 559 struct intel_plane_state *new_plane_state = 560 intel_atomic_get_new_plane_state(state, plane); 561 562 /* 563 * TODO: for mailbox updates intel_plane_update_noarm() 564 * would have to be called here as well. 565 */ 566 if (new_plane_state->uapi.visible || 567 new_plane_state->planar_slave) 568 intel_plane_update_arm(plane, new_crtc_state, new_plane_state); 569 else 570 intel_plane_disable_arm(plane, new_crtc_state); 571 } 572 } 573 574 void i9xx_arm_planes_on_crtc(struct intel_atomic_state *state, 575 struct intel_crtc *crtc) 576 { 577 struct intel_crtc_state *new_crtc_state = 578 intel_atomic_get_new_crtc_state(state, crtc); 579 u32 update_mask = new_crtc_state->update_planes; 580 struct intel_plane_state *new_plane_state; 581 struct intel_plane *plane; 582 int i; 583 584 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) { 585 if (crtc->pipe != plane->pipe || 586 !(update_mask & BIT(plane->id))) 587 continue; 588 589 /* 590 * TODO: for mailbox updates intel_plane_update_noarm() 591 * would have to be called here as well. 592 */ 593 if (new_plane_state->uapi.visible) 594 intel_plane_update_arm(plane, new_crtc_state, new_plane_state); 595 else 596 intel_plane_disable_arm(plane, new_crtc_state); 597 } 598 } 599 600 int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state, 601 struct intel_crtc_state *crtc_state, 602 int min_scale, int max_scale, 603 bool can_position) 604 { 605 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 606 struct drm_framebuffer *fb = plane_state->hw.fb; 607 struct drm_rect *src = &plane_state->uapi.src; 608 struct drm_rect *dst = &plane_state->uapi.dst; 609 unsigned int rotation = plane_state->hw.rotation; 610 struct drm_rect clip = {}; 611 int hscale, vscale; 612 613 if (!fb) { 614 plane_state->uapi.visible = false; 615 return 0; 616 } 617 618 drm_rect_rotate(src, fb->width << 16, fb->height << 16, rotation); 619 620 /* Check scaling */ 621 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale); 622 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale); 623 if (hscale < 0 || vscale < 0) { 624 drm_dbg_kms(&i915->drm, "Invalid scaling of plane\n"); 625 drm_rect_debug_print("src: ", src, true); 626 drm_rect_debug_print("dst: ", dst, false); 627 return -ERANGE; 628 } 629 630 if (crtc_state->hw.enable) { 631 clip.x2 = crtc_state->pipe_src_w; 632 clip.y2 = crtc_state->pipe_src_h; 633 } 634 635 /* right side of the image is on the slave crtc, adjust dst to match */ 636 if (crtc_state->bigjoiner_slave) 637 drm_rect_translate(dst, -crtc_state->pipe_src_w, 0); 638 639 /* 640 * FIXME: This might need further adjustment for seamless scaling 641 * with phase information, for the 2p2 and 2p1 scenarios. 642 */ 643 plane_state->uapi.visible = drm_rect_clip_scaled(src, dst, &clip); 644 645 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, rotation); 646 647 if (!can_position && plane_state->uapi.visible && 648 !drm_rect_equals(dst, &clip)) { 649 drm_dbg_kms(&i915->drm, "Plane must cover entire CRTC\n"); 650 drm_rect_debug_print("dst: ", dst, false); 651 drm_rect_debug_print("clip: ", &clip, false); 652 return -EINVAL; 653 } 654 655 return 0; 656 } 657 658 struct wait_rps_boost { 659 struct wait_queue_entry wait; 660 661 struct drm_crtc *crtc; 662 struct i915_request *request; 663 }; 664 665 static int do_rps_boost(struct wait_queue_entry *_wait, 666 unsigned mode, int sync, void *key) 667 { 668 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait); 669 struct i915_request *rq = wait->request; 670 671 /* 672 * If we missed the vblank, but the request is already running it 673 * is reasonable to assume that it will complete before the next 674 * vblank without our intervention, so leave RPS alone. 675 */ 676 if (!i915_request_started(rq)) 677 intel_rps_boost(rq); 678 i915_request_put(rq); 679 680 drm_crtc_vblank_put(wait->crtc); 681 682 list_del(&wait->wait.entry); 683 kfree(wait); 684 return 1; 685 } 686 687 static void add_rps_boost_after_vblank(struct drm_crtc *crtc, 688 struct dma_fence *fence) 689 { 690 struct wait_rps_boost *wait; 691 692 if (!dma_fence_is_i915(fence)) 693 return; 694 695 if (DISPLAY_VER(to_i915(crtc->dev)) < 6) 696 return; 697 698 if (drm_crtc_vblank_get(crtc)) 699 return; 700 701 wait = kmalloc(sizeof(*wait), GFP_KERNEL); 702 if (!wait) { 703 drm_crtc_vblank_put(crtc); 704 return; 705 } 706 707 wait->request = to_request(dma_fence_get(fence)); 708 wait->crtc = crtc; 709 710 wait->wait.func = do_rps_boost; 711 wait->wait.flags = 0; 712 713 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait); 714 } 715 716 /** 717 * intel_prepare_plane_fb - Prepare fb for usage on plane 718 * @_plane: drm plane to prepare for 719 * @_new_plane_state: the plane state being prepared 720 * 721 * Prepares a framebuffer for usage on a display plane. Generally this 722 * involves pinning the underlying object and updating the frontbuffer tracking 723 * bits. Some older platforms need special physical address handling for 724 * cursor planes. 725 * 726 * Returns 0 on success, negative error code on failure. 727 */ 728 static int 729 intel_prepare_plane_fb(struct drm_plane *_plane, 730 struct drm_plane_state *_new_plane_state) 731 { 732 struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY }; 733 struct intel_plane *plane = to_intel_plane(_plane); 734 struct intel_plane_state *new_plane_state = 735 to_intel_plane_state(_new_plane_state); 736 struct intel_atomic_state *state = 737 to_intel_atomic_state(new_plane_state->uapi.state); 738 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 739 const struct intel_plane_state *old_plane_state = 740 intel_atomic_get_old_plane_state(state, plane); 741 struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb); 742 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb); 743 int ret; 744 745 if (old_obj) { 746 const struct intel_crtc_state *crtc_state = 747 intel_atomic_get_new_crtc_state(state, 748 to_intel_crtc(old_plane_state->hw.crtc)); 749 750 /* Big Hammer, we also need to ensure that any pending 751 * MI_WAIT_FOR_EVENT inside a user batch buffer on the 752 * current scanout is retired before unpinning the old 753 * framebuffer. Note that we rely on userspace rendering 754 * into the buffer attached to the pipe they are waiting 755 * on. If not, userspace generates a GPU hang with IPEHR 756 * point to the MI_WAIT_FOR_EVENT. 757 * 758 * This should only fail upon a hung GPU, in which case we 759 * can safely continue. 760 */ 761 if (intel_crtc_needs_modeset(crtc_state)) { 762 ret = i915_sw_fence_await_reservation(&state->commit_ready, 763 old_obj->base.resv, NULL, 764 false, 0, 765 GFP_KERNEL); 766 if (ret < 0) 767 return ret; 768 } 769 } 770 771 if (new_plane_state->uapi.fence) { /* explicit fencing */ 772 i915_gem_fence_wait_priority(new_plane_state->uapi.fence, 773 &attr); 774 ret = i915_sw_fence_await_dma_fence(&state->commit_ready, 775 new_plane_state->uapi.fence, 776 i915_fence_timeout(dev_priv), 777 GFP_KERNEL); 778 if (ret < 0) 779 return ret; 780 } 781 782 if (!obj) 783 return 0; 784 785 786 ret = intel_plane_pin_fb(new_plane_state); 787 if (ret) 788 return ret; 789 790 i915_gem_object_wait_priority(obj, 0, &attr); 791 792 if (!new_plane_state->uapi.fence) { /* implicit fencing */ 793 struct dma_resv_iter cursor; 794 struct dma_fence *fence; 795 796 ret = i915_sw_fence_await_reservation(&state->commit_ready, 797 obj->base.resv, NULL, 798 false, 799 i915_fence_timeout(dev_priv), 800 GFP_KERNEL); 801 if (ret < 0) 802 goto unpin_fb; 803 804 dma_resv_iter_begin(&cursor, obj->base.resv, false); 805 dma_resv_for_each_fence_unlocked(&cursor, fence) { 806 add_rps_boost_after_vblank(new_plane_state->hw.crtc, 807 fence); 808 } 809 dma_resv_iter_end(&cursor); 810 } else { 811 add_rps_boost_after_vblank(new_plane_state->hw.crtc, 812 new_plane_state->uapi.fence); 813 } 814 815 /* 816 * We declare pageflips to be interactive and so merit a small bias 817 * towards upclocking to deliver the frame on time. By only changing 818 * the RPS thresholds to sample more regularly and aim for higher 819 * clocks we can hopefully deliver low power workloads (like kodi) 820 * that are not quite steady state without resorting to forcing 821 * maximum clocks following a vblank miss (see do_rps_boost()). 822 */ 823 if (!state->rps_interactive) { 824 intel_rps_mark_interactive(&to_gt(dev_priv)->rps, true); 825 state->rps_interactive = true; 826 } 827 828 return 0; 829 830 unpin_fb: 831 intel_plane_unpin_fb(new_plane_state); 832 833 return ret; 834 } 835 836 /** 837 * intel_cleanup_plane_fb - Cleans up an fb after plane use 838 * @plane: drm plane to clean up for 839 * @_old_plane_state: the state from the previous modeset 840 * 841 * Cleans up a framebuffer that has just been removed from a plane. 842 */ 843 static void 844 intel_cleanup_plane_fb(struct drm_plane *plane, 845 struct drm_plane_state *_old_plane_state) 846 { 847 struct intel_plane_state *old_plane_state = 848 to_intel_plane_state(_old_plane_state); 849 struct intel_atomic_state *state = 850 to_intel_atomic_state(old_plane_state->uapi.state); 851 struct drm_i915_private *dev_priv = to_i915(plane->dev); 852 struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb); 853 854 if (!obj) 855 return; 856 857 if (state->rps_interactive) { 858 intel_rps_mark_interactive(&to_gt(dev_priv)->rps, false); 859 state->rps_interactive = false; 860 } 861 862 /* Should only be called after a successful intel_prepare_plane_fb()! */ 863 intel_plane_unpin_fb(old_plane_state); 864 } 865 866 static const struct drm_plane_helper_funcs intel_plane_helper_funcs = { 867 .prepare_fb = intel_prepare_plane_fb, 868 .cleanup_fb = intel_cleanup_plane_fb, 869 }; 870 871 void intel_plane_helper_add(struct intel_plane *plane) 872 { 873 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); 874 } 875