1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 /** 25 * DOC: atomic plane helpers 26 * 27 * The functions here are used by the atomic plane helper functions to 28 * implement legacy plane updates (i.e., drm_plane->update_plane() and 29 * drm_plane->disable_plane()). This allows plane updates to use the 30 * atomic state infrastructure and perform plane updates as separate 31 * prepare/check/commit/cleanup steps. 32 */ 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_fourcc.h> 36 #include <drm/drm_plane_helper.h> 37 38 #include "i915_trace.h" 39 #include "intel_atomic_plane.h" 40 #include "intel_cdclk.h" 41 #include "intel_display_types.h" 42 #include "intel_pm.h" 43 #include "intel_sprite.h" 44 45 static void intel_plane_state_reset(struct intel_plane_state *plane_state, 46 struct intel_plane *plane) 47 { 48 memset(plane_state, 0, sizeof(*plane_state)); 49 50 __drm_atomic_helper_plane_state_reset(&plane_state->uapi, &plane->base); 51 52 plane_state->scaler_id = -1; 53 } 54 55 struct intel_plane *intel_plane_alloc(void) 56 { 57 struct intel_plane_state *plane_state; 58 struct intel_plane *plane; 59 60 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 61 if (!plane) 62 return ERR_PTR(-ENOMEM); 63 64 plane_state = kzalloc(sizeof(*plane_state), GFP_KERNEL); 65 if (!plane_state) { 66 kfree(plane); 67 return ERR_PTR(-ENOMEM); 68 } 69 70 intel_plane_state_reset(plane_state, plane); 71 72 plane->base.state = &plane_state->uapi; 73 74 return plane; 75 } 76 77 void intel_plane_free(struct intel_plane *plane) 78 { 79 intel_plane_destroy_state(&plane->base, plane->base.state); 80 kfree(plane); 81 } 82 83 /** 84 * intel_plane_duplicate_state - duplicate plane state 85 * @plane: drm plane 86 * 87 * Allocates and returns a copy of the plane state (both common and 88 * Intel-specific) for the specified plane. 89 * 90 * Returns: The newly allocated plane state, or NULL on failure. 91 */ 92 struct drm_plane_state * 93 intel_plane_duplicate_state(struct drm_plane *plane) 94 { 95 struct intel_plane_state *intel_state; 96 97 intel_state = to_intel_plane_state(plane->state); 98 intel_state = kmemdup(intel_state, sizeof(*intel_state), GFP_KERNEL); 99 100 if (!intel_state) 101 return NULL; 102 103 __drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi); 104 105 intel_state->vma = NULL; 106 intel_state->flags = 0; 107 108 /* add reference to fb */ 109 if (intel_state->hw.fb) 110 drm_framebuffer_get(intel_state->hw.fb); 111 112 return &intel_state->uapi; 113 } 114 115 /** 116 * intel_plane_destroy_state - destroy plane state 117 * @plane: drm plane 118 * @state: state object to destroy 119 * 120 * Destroys the plane state (both common and Intel-specific) for the 121 * specified plane. 122 */ 123 void 124 intel_plane_destroy_state(struct drm_plane *plane, 125 struct drm_plane_state *state) 126 { 127 struct intel_plane_state *plane_state = to_intel_plane_state(state); 128 drm_WARN_ON(plane->dev, plane_state->vma); 129 130 __drm_atomic_helper_plane_destroy_state(&plane_state->uapi); 131 if (plane_state->hw.fb) 132 drm_framebuffer_put(plane_state->hw.fb); 133 kfree(plane_state); 134 } 135 136 unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state, 137 const struct intel_plane_state *plane_state) 138 { 139 unsigned int src_w, src_h, dst_w, dst_h; 140 unsigned int pixel_rate = crtc_state->pixel_rate; 141 142 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 143 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 144 dst_w = drm_rect_width(&plane_state->uapi.dst); 145 dst_h = drm_rect_height(&plane_state->uapi.dst); 146 147 /* Downscaling limits the maximum pixel rate */ 148 dst_w = min(src_w, dst_w); 149 dst_h = min(src_h, dst_h); 150 151 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, src_w * src_h), 152 dst_w * dst_h); 153 } 154 155 unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state, 156 const struct intel_plane_state *plane_state) 157 { 158 const struct drm_framebuffer *fb = plane_state->hw.fb; 159 unsigned int cpp; 160 unsigned int pixel_rate; 161 162 if (!plane_state->uapi.visible) 163 return 0; 164 165 pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); 166 167 cpp = fb->format->cpp[0]; 168 169 /* 170 * Based on HSD#:1408715493 171 * NV12 cpp == 4, P010 cpp == 8 172 * 173 * FIXME what is the logic behind this? 174 */ 175 if (fb->format->is_yuv && fb->format->num_planes > 1) 176 cpp *= 4; 177 178 return pixel_rate * cpp; 179 } 180 181 int intel_plane_calc_min_cdclk(struct intel_atomic_state *state, 182 struct intel_plane *plane, 183 bool *need_cdclk_calc) 184 { 185 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 186 const struct intel_plane_state *plane_state = 187 intel_atomic_get_new_plane_state(state, plane); 188 struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc); 189 const struct intel_cdclk_state *cdclk_state; 190 const struct intel_crtc_state *old_crtc_state; 191 struct intel_crtc_state *new_crtc_state; 192 193 if (!plane_state->uapi.visible || !plane->min_cdclk) 194 return 0; 195 196 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 197 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 198 199 new_crtc_state->min_cdclk[plane->id] = 200 plane->min_cdclk(new_crtc_state, plane_state); 201 202 /* 203 * No need to check against the cdclk state if 204 * the min cdclk for the plane doesn't increase. 205 * 206 * Ie. we only ever increase the cdclk due to plane 207 * requirements. This can reduce back and forth 208 * display blinking due to constant cdclk changes. 209 */ 210 if (new_crtc_state->min_cdclk[plane->id] <= 211 old_crtc_state->min_cdclk[plane->id]) 212 return 0; 213 214 cdclk_state = intel_atomic_get_cdclk_state(state); 215 if (IS_ERR(cdclk_state)) 216 return PTR_ERR(cdclk_state); 217 218 /* 219 * No need to recalculate the cdclk state if 220 * the min cdclk for the pipe doesn't increase. 221 * 222 * Ie. we only ever increase the cdclk due to plane 223 * requirements. This can reduce back and forth 224 * display blinking due to constant cdclk changes. 225 */ 226 if (new_crtc_state->min_cdclk[plane->id] <= 227 cdclk_state->min_cdclk[crtc->pipe]) 228 return 0; 229 230 drm_dbg_kms(&dev_priv->drm, 231 "[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n", 232 plane->base.base.id, plane->base.name, 233 new_crtc_state->min_cdclk[plane->id], 234 crtc->base.base.id, crtc->base.name, 235 cdclk_state->min_cdclk[crtc->pipe]); 236 *need_cdclk_calc = true; 237 238 return 0; 239 } 240 241 static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state) 242 { 243 if (plane_state->hw.fb) 244 drm_framebuffer_put(plane_state->hw.fb); 245 246 memset(&plane_state->hw, 0, sizeof(plane_state->hw)); 247 } 248 249 void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state, 250 const struct intel_plane_state *from_plane_state, 251 struct intel_crtc *crtc) 252 { 253 intel_plane_clear_hw_state(plane_state); 254 255 /* 256 * For the bigjoiner slave uapi.crtc will point at 257 * the master crtc. So we explicitly assign the right 258 * slave crtc to hw.crtc. uapi.crtc!=NULL simply indicates 259 * the plane is logically enabled on the uapi level. 260 */ 261 plane_state->hw.crtc = from_plane_state->uapi.crtc ? &crtc->base : NULL; 262 263 plane_state->hw.fb = from_plane_state->uapi.fb; 264 if (plane_state->hw.fb) 265 drm_framebuffer_get(plane_state->hw.fb); 266 267 plane_state->hw.alpha = from_plane_state->uapi.alpha; 268 plane_state->hw.pixel_blend_mode = 269 from_plane_state->uapi.pixel_blend_mode; 270 plane_state->hw.rotation = from_plane_state->uapi.rotation; 271 plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding; 272 plane_state->hw.color_range = from_plane_state->uapi.color_range; 273 plane_state->hw.scaling_filter = from_plane_state->uapi.scaling_filter; 274 275 plane_state->uapi.src = drm_plane_state_src(&from_plane_state->uapi); 276 plane_state->uapi.dst = drm_plane_state_dest(&from_plane_state->uapi); 277 } 278 279 void intel_plane_copy_hw_state(struct intel_plane_state *plane_state, 280 const struct intel_plane_state *from_plane_state) 281 { 282 intel_plane_clear_hw_state(plane_state); 283 284 memcpy(&plane_state->hw, &from_plane_state->hw, 285 sizeof(plane_state->hw)); 286 287 if (plane_state->hw.fb) 288 drm_framebuffer_get(plane_state->hw.fb); 289 } 290 291 void intel_plane_set_invisible(struct intel_crtc_state *crtc_state, 292 struct intel_plane_state *plane_state) 293 { 294 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 295 296 crtc_state->active_planes &= ~BIT(plane->id); 297 crtc_state->nv12_planes &= ~BIT(plane->id); 298 crtc_state->c8_planes &= ~BIT(plane->id); 299 crtc_state->data_rate[plane->id] = 0; 300 crtc_state->min_cdclk[plane->id] = 0; 301 302 plane_state->uapi.visible = false; 303 } 304 305 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state, 306 struct intel_crtc_state *new_crtc_state, 307 const struct intel_plane_state *old_plane_state, 308 struct intel_plane_state *new_plane_state) 309 { 310 struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane); 311 const struct drm_framebuffer *fb = new_plane_state->hw.fb; 312 int ret; 313 314 intel_plane_set_invisible(new_crtc_state, new_plane_state); 315 new_crtc_state->enabled_planes &= ~BIT(plane->id); 316 317 if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc) 318 return 0; 319 320 new_crtc_state->enabled_planes |= BIT(plane->id); 321 322 ret = plane->check_plane(new_crtc_state, new_plane_state); 323 if (ret) 324 return ret; 325 326 /* FIXME pre-g4x don't work like this */ 327 if (new_plane_state->uapi.visible) 328 new_crtc_state->active_planes |= BIT(plane->id); 329 330 if (new_plane_state->uapi.visible && 331 intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) 332 new_crtc_state->nv12_planes |= BIT(plane->id); 333 334 if (new_plane_state->uapi.visible && 335 fb->format->format == DRM_FORMAT_C8) 336 new_crtc_state->c8_planes |= BIT(plane->id); 337 338 if (new_plane_state->uapi.visible || old_plane_state->uapi.visible) 339 new_crtc_state->update_planes |= BIT(plane->id); 340 341 new_crtc_state->data_rate[plane->id] = 342 intel_plane_data_rate(new_crtc_state, new_plane_state); 343 344 return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state, 345 old_plane_state, new_plane_state); 346 } 347 348 static struct intel_plane * 349 intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id) 350 { 351 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 352 struct intel_plane *plane; 353 354 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 355 if (plane->id == plane_id) 356 return plane; 357 } 358 359 return NULL; 360 } 361 362 int intel_plane_atomic_check(struct intel_atomic_state *state, 363 struct intel_plane *plane) 364 { 365 struct drm_i915_private *i915 = to_i915(state->base.dev); 366 struct intel_plane_state *new_plane_state = 367 intel_atomic_get_new_plane_state(state, plane); 368 const struct intel_plane_state *old_plane_state = 369 intel_atomic_get_old_plane_state(state, plane); 370 const struct intel_plane_state *new_master_plane_state; 371 struct intel_crtc *crtc = intel_get_crtc_for_pipe(i915, plane->pipe); 372 const struct intel_crtc_state *old_crtc_state = 373 intel_atomic_get_old_crtc_state(state, crtc); 374 struct intel_crtc_state *new_crtc_state = 375 intel_atomic_get_new_crtc_state(state, crtc); 376 377 if (new_crtc_state && new_crtc_state->bigjoiner_slave) { 378 struct intel_plane *master_plane = 379 intel_crtc_get_plane(new_crtc_state->bigjoiner_linked_crtc, 380 plane->id); 381 382 new_master_plane_state = 383 intel_atomic_get_new_plane_state(state, master_plane); 384 } else { 385 new_master_plane_state = new_plane_state; 386 } 387 388 intel_plane_copy_uapi_to_hw_state(new_plane_state, 389 new_master_plane_state, 390 crtc); 391 392 new_plane_state->uapi.visible = false; 393 if (!new_crtc_state) 394 return 0; 395 396 return intel_plane_atomic_check_with_state(old_crtc_state, 397 new_crtc_state, 398 old_plane_state, 399 new_plane_state); 400 } 401 402 static struct intel_plane * 403 skl_next_plane_to_commit(struct intel_atomic_state *state, 404 struct intel_crtc *crtc, 405 struct skl_ddb_entry entries_y[I915_MAX_PLANES], 406 struct skl_ddb_entry entries_uv[I915_MAX_PLANES], 407 unsigned int *update_mask) 408 { 409 struct intel_crtc_state *crtc_state = 410 intel_atomic_get_new_crtc_state(state, crtc); 411 struct intel_plane_state *plane_state; 412 struct intel_plane *plane; 413 int i; 414 415 if (*update_mask == 0) 416 return NULL; 417 418 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 419 enum plane_id plane_id = plane->id; 420 421 if (crtc->pipe != plane->pipe || 422 !(*update_mask & BIT(plane_id))) 423 continue; 424 425 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id], 426 entries_y, 427 I915_MAX_PLANES, plane_id) || 428 skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_uv[plane_id], 429 entries_uv, 430 I915_MAX_PLANES, plane_id)) 431 continue; 432 433 *update_mask &= ~BIT(plane_id); 434 entries_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id]; 435 entries_uv[plane_id] = crtc_state->wm.skl.plane_ddb_uv[plane_id]; 436 437 return plane; 438 } 439 440 /* should never happen */ 441 drm_WARN_ON(state->base.dev, 1); 442 443 return NULL; 444 } 445 446 void intel_update_plane(struct intel_plane *plane, 447 const struct intel_crtc_state *crtc_state, 448 const struct intel_plane_state *plane_state) 449 { 450 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 451 452 trace_intel_update_plane(&plane->base, crtc); 453 454 if (crtc_state->uapi.async_flip && plane->async_flip) 455 plane->async_flip(plane, crtc_state, plane_state, true); 456 else 457 plane->update_plane(plane, crtc_state, plane_state); 458 } 459 460 void intel_disable_plane(struct intel_plane *plane, 461 const struct intel_crtc_state *crtc_state) 462 { 463 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 464 465 trace_intel_disable_plane(&plane->base, crtc); 466 plane->disable_plane(plane, crtc_state); 467 } 468 469 void skl_update_planes_on_crtc(struct intel_atomic_state *state, 470 struct intel_crtc *crtc) 471 { 472 struct intel_crtc_state *old_crtc_state = 473 intel_atomic_get_old_crtc_state(state, crtc); 474 struct intel_crtc_state *new_crtc_state = 475 intel_atomic_get_new_crtc_state(state, crtc); 476 struct skl_ddb_entry entries_y[I915_MAX_PLANES]; 477 struct skl_ddb_entry entries_uv[I915_MAX_PLANES]; 478 u32 update_mask = new_crtc_state->update_planes; 479 struct intel_plane *plane; 480 481 memcpy(entries_y, old_crtc_state->wm.skl.plane_ddb_y, 482 sizeof(old_crtc_state->wm.skl.plane_ddb_y)); 483 memcpy(entries_uv, old_crtc_state->wm.skl.plane_ddb_uv, 484 sizeof(old_crtc_state->wm.skl.plane_ddb_uv)); 485 486 while ((plane = skl_next_plane_to_commit(state, crtc, 487 entries_y, entries_uv, 488 &update_mask))) { 489 struct intel_plane_state *new_plane_state = 490 intel_atomic_get_new_plane_state(state, plane); 491 492 if (new_plane_state->uapi.visible || 493 new_plane_state->planar_slave) { 494 intel_update_plane(plane, new_crtc_state, new_plane_state); 495 } else { 496 intel_disable_plane(plane, new_crtc_state); 497 } 498 } 499 } 500 501 void i9xx_update_planes_on_crtc(struct intel_atomic_state *state, 502 struct intel_crtc *crtc) 503 { 504 struct intel_crtc_state *new_crtc_state = 505 intel_atomic_get_new_crtc_state(state, crtc); 506 u32 update_mask = new_crtc_state->update_planes; 507 struct intel_plane_state *new_plane_state; 508 struct intel_plane *plane; 509 int i; 510 511 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) { 512 if (crtc->pipe != plane->pipe || 513 !(update_mask & BIT(plane->id))) 514 continue; 515 516 if (new_plane_state->uapi.visible) 517 intel_update_plane(plane, new_crtc_state, new_plane_state); 518 else 519 intel_disable_plane(plane, new_crtc_state); 520 } 521 } 522 523 int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state, 524 struct intel_crtc_state *crtc_state, 525 int min_scale, int max_scale, 526 bool can_position) 527 { 528 struct drm_framebuffer *fb = plane_state->hw.fb; 529 struct drm_rect *src = &plane_state->uapi.src; 530 struct drm_rect *dst = &plane_state->uapi.dst; 531 unsigned int rotation = plane_state->hw.rotation; 532 struct drm_rect clip = {}; 533 int hscale, vscale; 534 535 if (!fb) { 536 plane_state->uapi.visible = false; 537 return 0; 538 } 539 540 drm_rect_rotate(src, fb->width << 16, fb->height << 16, rotation); 541 542 /* Check scaling */ 543 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale); 544 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale); 545 if (hscale < 0 || vscale < 0) { 546 DRM_DEBUG_KMS("Invalid scaling of plane\n"); 547 drm_rect_debug_print("src: ", src, true); 548 drm_rect_debug_print("dst: ", dst, false); 549 return -ERANGE; 550 } 551 552 if (crtc_state->hw.enable) { 553 clip.x2 = crtc_state->pipe_src_w; 554 clip.y2 = crtc_state->pipe_src_h; 555 } 556 557 /* right side of the image is on the slave crtc, adjust dst to match */ 558 if (crtc_state->bigjoiner_slave) 559 drm_rect_translate(dst, -crtc_state->pipe_src_w, 0); 560 561 /* 562 * FIXME: This might need further adjustment for seamless scaling 563 * with phase information, for the 2p2 and 2p1 scenarios. 564 */ 565 plane_state->uapi.visible = drm_rect_clip_scaled(src, dst, &clip); 566 567 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, rotation); 568 569 if (!can_position && plane_state->uapi.visible && 570 !drm_rect_equals(dst, &clip)) { 571 DRM_DEBUG_KMS("Plane must cover entire CRTC\n"); 572 drm_rect_debug_print("dst: ", dst, false); 573 drm_rect_debug_print("clip: ", &clip, false); 574 return -EINVAL; 575 } 576 577 return 0; 578 } 579 580 const struct drm_plane_helper_funcs intel_plane_helper_funcs = { 581 .prepare_fb = intel_prepare_plane_fb, 582 .cleanup_fb = intel_cleanup_plane_fb, 583 }; 584